Commit `fc0789f8e7`

Jacob Young <jacobly0@users.noreply.github.com>

2022-12-24 01:00:20

behavior: disable tests that trigger an llvm 15 bug and assertion

``` LLVM Emit Object... zig: llvm/include/llvm/ADT/APInt.h:840: void llvm::APInt::lshrInPlace(unsigned int): Assertion `ShiftAmt <= BitWidth && "Invalid shift amount"' failed. Aborted ``` Tracked by #13782

master

1 parent c9e3524

Changed files (2)

test

behavior

bugs

12169.zig

bitcast.zig

@@ -7,6 +7,12 @@ test {
     if (builtin.zig_backend == .stage2_x86) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
+
+    if (comptime builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.endian() == .Big) {
+        // https://github.com/ziglang/zig/issues/13782
+        return error.SkipZigTest;
+    }
+
     const a = @Vector(2, bool){ true, true };
     const b = @Vector(1, bool){true};
     try std.testing.expect(@reduce(.And, a));

@@ -334,6 +334,11 @@ test "comptime @bitCast packed struct to int and back" {
     if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
     if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
 
+    if (comptime builtin.zig_backend == .stage2_llvm and builtin.cpu.arch.endian() == .Big) {
+        // https://github.com/ziglang/zig/issues/13782
+        return error.SkipZigTest;
+    }
+
     const S = packed struct {
         void: void = {},
         uint: u8 = 13,

Commit fc0789f8e7

Commit `fc0789f8e7`