Commit ee72f06f47
Changed files (8)
lib
std
src
lib/std/builtin/assembly.zig
@@ -2197,6 +2197,321 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {
msa_map: bool = false,
msa_unmap: bool = false,
},
+ .alpha => packed struct {
+ /// Whether the inline assembly code may perform stores to memory
+ /// addresses other than those derived from input pointer provenance.
+ memory: bool = false,
+
+ r0: bool = false,
+ r1: bool = false,
+ r2: bool = false,
+ r3: bool = false,
+ r4: bool = false,
+ r5: bool = false,
+ r6: bool = false,
+ r7: bool = false,
+ r8: bool = false,
+ r9: bool = false,
+ r10: bool = false,
+ r11: bool = false,
+ r12: bool = false,
+ r13: bool = false,
+ r14: bool = false,
+ r15: bool = false,
+ r16: bool = false,
+ r17: bool = false,
+ r18: bool = false,
+ r19: bool = false,
+ r20: bool = false,
+ r21: bool = false,
+ r22: bool = false,
+ r23: bool = false,
+ r24: bool = false,
+ r25: bool = false,
+ r26: bool = false,
+ r27: bool = false,
+ r28: bool = false,
+ r29: bool = false,
+ r30: bool = false,
+
+ f0: bool = false,
+ f1: bool = false,
+ f2: bool = false,
+ f3: bool = false,
+ f4: bool = false,
+ f5: bool = false,
+ f6: bool = false,
+ f7: bool = false,
+ f8: bool = false,
+ f9: bool = false,
+ f10: bool = false,
+ f11: bool = false,
+ f12: bool = false,
+ f13: bool = false,
+ f14: bool = false,
+ f15: bool = false,
+ f16: bool = false,
+ f17: bool = false,
+ f18: bool = false,
+ f19: bool = false,
+ f20: bool = false,
+ f21: bool = false,
+ f22: bool = false,
+ f23: bool = false,
+ f24: bool = false,
+ f25: bool = false,
+ f26: bool = false,
+ f27: bool = false,
+ f28: bool = false,
+ f29: bool = false,
+ f30: bool = false,
+ },
+ .hppa, .hppa64 => packed struct {
+ /// Whether the inline assembly code may perform stores to memory
+ /// addresses other than those derived from input pointer provenance.
+ memory: bool = false,
+
+ sar: bool = false,
+
+ r1: bool = false,
+ r2: bool = false,
+ r3: bool = false,
+ r4: bool = false,
+ r5: bool = false,
+ r6: bool = false,
+ r7: bool = false,
+ r8: bool = false,
+ r9: bool = false,
+ r10: bool = false,
+ r11: bool = false,
+ r12: bool = false,
+ r13: bool = false,
+ r14: bool = false,
+ r15: bool = false,
+ r16: bool = false,
+ r17: bool = false,
+ r18: bool = false,
+ r19: bool = false,
+ r20: bool = false,
+ r21: bool = false,
+ r22: bool = false,
+ r23: bool = false,
+ r24: bool = false,
+ r25: bool = false,
+ r26: bool = false,
+ r27: bool = false,
+ r28: bool = false,
+ r29: bool = false,
+ r30: bool = false,
+ r31: bool = false,
+
+ fr4: bool = false,
+ fr5: bool = false,
+ fr6: bool = false,
+ fr7: bool = false,
+ fr8: bool = false,
+ fr9: bool = false,
+ fr10: bool = false,
+ fr11: bool = false,
+ fr12: bool = false,
+ fr13: bool = false,
+ fr14: bool = false,
+ fr15: bool = false,
+ fr16: bool = false,
+ fr17: bool = false,
+ fr18: bool = false,
+ fr19: bool = false,
+ fr20: bool = false,
+ fr21: bool = false,
+ fr22: bool = false,
+ fr23: bool = false,
+ fr24: bool = false,
+ fr25: bool = false,
+ fr26: bool = false,
+ fr27: bool = false,
+ fr28: bool = false,
+ fr29: bool = false,
+ fr30: bool = false,
+ fr31: bool = false,
+
+ fr4r: bool = false,
+ fr5r: bool = false,
+ fr6r: bool = false,
+ fr7r: bool = false,
+ fr8r: bool = false,
+ fr9r: bool = false,
+ fr10r: bool = false,
+ fr11r: bool = false,
+ fr12r: bool = false,
+ fr13r: bool = false,
+ fr14r: bool = false,
+ fr15r: bool = false,
+ fr16r: bool = false,
+ fr17r: bool = false,
+ fr18r: bool = false,
+ fr19r: bool = false,
+ fr20r: bool = false,
+ fr21r: bool = false,
+ fr22r: bool = false,
+ fr23r: bool = false,
+ fr24r: bool = false,
+ fr25r: bool = false,
+ fr26r: bool = false,
+ fr27r: bool = false,
+ fr28r: bool = false,
+ fr29r: bool = false,
+ fr30r: bool = false,
+ fr31r: bool = false,
+ },
+ .microblaze, .microblazeel => packed struct {
+ /// Whether the inline assembly code may perform stores to memory
+ /// addresses other than those derived from input pointer provenance.
+ memory: bool = false,
+
+ rmsr: bool = false,
+
+ r1: bool = false,
+ r2: bool = false,
+ r3: bool = false,
+ r4: bool = false,
+ r5: bool = false,
+ r6: bool = false,
+ r7: bool = false,
+ r8: bool = false,
+ r9: bool = false,
+ r10: bool = false,
+ r11: bool = false,
+ r12: bool = false,
+ r13: bool = false,
+ r14: bool = false,
+ r15: bool = false,
+ r16: bool = false,
+ r17: bool = false,
+ r18: bool = false,
+ r19: bool = false,
+ r20: bool = false,
+ r21: bool = false,
+ r22: bool = false,
+ r23: bool = false,
+ r24: bool = false,
+ r25: bool = false,
+ r26: bool = false,
+ r27: bool = false,
+ r28: bool = false,
+ r29: bool = false,
+ r30: bool = false,
+ r31: bool = false,
+ },
+ .sh, .sheb => packed struct {
+ /// Whether the inline assembly code may perform stores to memory
+ /// addresses other than those derived from input pointer provenance.
+ memory: bool = false,
+
+ sr: bool = false,
+ gbr: bool = false,
+ pr: bool = false,
+
+ r0: bool = false,
+ r1: bool = false,
+ r2: bool = false,
+ r3: bool = false,
+ r4: bool = false,
+ r5: bool = false,
+ r6: bool = false,
+ r7: bool = false,
+ r8: bool = false,
+ r9: bool = false,
+ r10: bool = false,
+ r11: bool = false,
+ r12: bool = false,
+ r13: bool = false,
+ r14: bool = false,
+ r15: bool = false,
+
+ mach: bool = false,
+ macl: bool = false,
+
+ fr0: bool = false,
+ fr1: bool = false,
+ fr2: bool = false,
+ fr3: bool = false,
+ fr4: bool = false,
+ fr5: bool = false,
+ fr6: bool = false,
+ fr7: bool = false,
+ fr8: bool = false,
+ fr9: bool = false,
+ fr10: bool = false,
+ fr11: bool = false,
+ fr12: bool = false,
+ fr13: bool = false,
+ fr14: bool = false,
+ fr15: bool = false,
+
+ dr0: bool = false,
+ dr2: bool = false,
+ dr4: bool = false,
+ dr6: bool = false,
+ dr8: bool = false,
+ dr10: bool = false,
+ dr12: bool = false,
+ dr14: bool = false,
+
+ fv0: bool = false,
+ fv4: bool = false,
+ fv8: bool = false,
+ fv12: bool = false,
+
+ xf0: bool = false,
+ xf1: bool = false,
+ xf2: bool = false,
+ xf3: bool = false,
+ xf4: bool = false,
+ xf5: bool = false,
+ xf6: bool = false,
+ xf7: bool = false,
+ xf8: bool = false,
+ xf9: bool = false,
+ xf10: bool = false,
+ xf11: bool = false,
+ xf12: bool = false,
+ xf13: bool = false,
+ xf14: bool = false,
+ xf15: bool = false,
+
+ xd0: bool = false,
+ xd2: bool = false,
+ xd4: bool = false,
+ xd6: bool = false,
+ xd8: bool = false,
+ xd10: bool = false,
+ xd12: bool = false,
+ xd14: bool = false,
+
+ xmtrx: bool = false,
+
+ fpul: bool = false,
+ fpscr: bool = false,
+
+ ms: bool = false,
+ me: bool = false,
+
+ rs: bool = false,
+ re: bool = false,
+
+ a0: bool = false,
+ a0g: bool = false,
+ a1: bool = false,
+ a1g: bool = false,
+ m0: bool = false,
+ m1: bool = false,
+ x0: bool = false,
+ x1: bool = false,
+ y0: bool = false,
+ y1: bool = false,
+
+ dsr: bool = false,
+ },
else => packed struct {
/// Whether the inline assembly code may perform stores to memory
/// addresses other than those derived from input pointer provenance.
lib/std/builtin.zig
@@ -229,6 +229,9 @@ pub const CallingConvention = union(enum(u8)) {
aarch64_vfabi: CommonOptions,
aarch64_vfabi_sve: CommonOptions,
+ /// The standard `alpha` calling convention.
+ alpha_osf: CommonOptions,
+
// Calling convetions for the `arm`, `armeb`, `thumb`, and `thumbeb` architectures.
/// ARM Architecture Procedure Call Standard
arm_aapcs: CommonOptions,
@@ -296,6 +299,12 @@ pub const CallingConvention = union(enum(u8)) {
hexagon_sysv: CommonOptions,
hexagon_sysv_hvx: CommonOptions,
+ /// The standard `hppa` calling convention.
+ hppa_elf: CommonOptions,
+
+ /// The standard `hppa64` calling convention.
+ hppa64_elf: CommonOptions,
+
/// The standard `lanai` calling convention.
lanai_sysv: CommonOptions,
@@ -311,6 +320,9 @@ pub const CallingConvention = union(enum(u8)) {
m68k_rtd: CommonOptions,
m68k_interrupt: CommonOptions,
+ /// The standard `microblaze`/`microblazeel` calling convention.
+ microblaze_std: CommonOptions,
+
/// The standard `msp430` calling convention.
msp430_eabi: CommonOptions,
@@ -324,6 +336,10 @@ pub const CallingConvention = union(enum(u8)) {
s390x_sysv: CommonOptions,
s390x_sysv_vx: CommonOptions,
+ // Calling conventions for the `sh`/`sheb` architecture.
+ sh_gnu: CommonOptions,
+ sh_renesas: CommonOptions,
+
/// The standard `ve` calling convention.
ve_sysv: CommonOptions,
@@ -858,6 +874,13 @@ pub const VaListAarch64 = extern struct {
__vr_offs: c_int,
};
+/// This data structure is used by the Zig language code generation and
+/// therefore must be kept in sync with the compiler implementation.
+pub const VaListAlpha = extern struct {
+ __base: *anyopaque,
+ __offset: c_int,
+};
+
/// This data structure is used by the Zig language code generation and
/// therefore must be kept in sync with the compiler implementation.
pub const VaListArm = extern struct {
@@ -891,6 +914,16 @@ pub const VaListS390x = extern struct {
__overflow_area_pointer: *anyopaque,
};
+/// This data structure is used by the Zig language code generation and
+/// therefore must be kept in sync with the compiler implementation.
+pub const VaListSh = extern struct {
+ __va_next_o: *anyopaque,
+ __va_next_o_limit: *anyopaque,
+ __va_next_fp: *anyopaque,
+ __va_next_fp_limit: *anyopaque,
+ __va_next_stack: *anyopaque,
+};
+
/// This data structure is used by the Zig language code generation and
/// therefore must be kept in sync with the compiler implementation.
pub const VaListX86_64 = extern struct {
@@ -925,10 +958,14 @@ pub const VaList = switch (builtin.cpu.arch) {
.bpfel,
.bpfeb,
.csky,
+ .hppa,
+ .hppa64,
.lanai,
.loongarch32,
.loongarch64,
.m68k,
+ .microblaze,
+ .microblazeel,
.mips,
.mipsel,
.mips64,
@@ -953,6 +990,7 @@ pub const VaList = switch (builtin.cpu.arch) {
.stage2_llvm => @compileError("disabled due to miscompilations"),
},
},
+ .alpha => VaListAlpha,
.arm, .armeb, .thumb, .thumbeb => VaListArm,
.hexagon => if (builtin.target.abi.isMusl()) VaListHexagon else *u8,
.powerpc, .powerpcle => switch (builtin.os.tag) {
@@ -960,6 +998,7 @@ pub const VaList = switch (builtin.cpu.arch) {
else => VaListPowerPc,
},
.s390x => VaListS390x,
+ .sh, .sheb => VaListSh, // This is wrong for `sh_renesas`: https://github.com/ziglang/zig/issues/24692#issuecomment-3150779829
.x86_64 => switch (builtin.os.tag) {
.uefi, .windows => switch (builtin.zig_backend) {
else => *u8,
lib/std/Target.zig
@@ -733,6 +733,7 @@ pub const Os = struct {
};
pub const aarch64 = @import("Target/aarch64.zig");
+pub const alpha = @import("Target/generic.zig");
pub const amdgcn = @import("Target/amdgcn.zig");
pub const arc = @import("Target/arc.zig");
pub const arm = @import("Target/arm.zig");
@@ -740,10 +741,12 @@ pub const avr = @import("Target/avr.zig");
pub const bpf = @import("Target/bpf.zig");
pub const csky = @import("Target/csky.zig");
pub const hexagon = @import("Target/hexagon.zig");
+pub const hppa = @import("Target/generic.zig");
pub const kalimba = @import("Target/generic.zig");
pub const lanai = @import("Target/lanai.zig");
pub const loongarch = @import("Target/loongarch.zig");
pub const m68k = @import("Target/m68k.zig");
+pub const microblaze = @import("Target/generic.zig");
pub const mips = @import("Target/mips.zig");
pub const msp430 = @import("Target/msp430.zig");
pub const nvptx = @import("Target/nvptx.zig");
@@ -752,6 +755,7 @@ pub const powerpc = @import("Target/powerpc.zig");
pub const propeller = @import("Target/propeller.zig");
pub const riscv = @import("Target/riscv.zig");
pub const s390x = @import("Target/s390x.zig");
+pub const sh = @import("Target/generic.zig");
pub const sparc = @import("Target/sparc.zig");
pub const spirv = @import("Target/spirv.zig");
pub const ve = @import("Target/ve.zig");
@@ -826,10 +830,13 @@ pub const Abi = enum {
.arm,
.armeb,
.csky,
+ .hppa,
.mips,
.mipsel,
.powerpc,
.powerpcle,
+ .sh,
+ .sheb,
.thumb,
.thumbeb,
=> .eabi,
@@ -864,6 +871,10 @@ pub const Abi = enum {
=> .gnu,
.csky,
=> .gnueabi,
+ .hppa,
+ .sh,
+ .sheb,
+ => .gnueabihf,
// No glibc or musl support.
.xtensa,
@@ -1064,6 +1075,7 @@ pub const ObjectFormat = enum {
pub fn toElfMachine(target: *const Target) std.elf.EM {
return switch (target.cpu.arch) {
.aarch64, .aarch64_be => .AARCH64,
+ .alpha => .ALPHA,
.amdgcn => .AMDGPU,
.arc, .arceb => .ARC_COMPACT,
.arm, .armeb, .thumb, .thumbeb => .ARM,
@@ -1071,10 +1083,12 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
.bpfeb, .bpfel => .BPF,
.csky => .CSKY,
.hexagon => .QDSP6,
+ .hppa, .hppa64 => .PARISC,
.kalimba => .CSR_KALIMBA,
.lanai => .LANAI,
.loongarch32, .loongarch64 => .LOONGARCH,
.m68k => .@"68K",
+ .microblaze, .microblazeel => .MICROBLAZE,
.mips, .mips64, .mipsel, .mips64el => .MIPS,
.msp430 => .MSP430,
.or1k => .OR1K,
@@ -1083,6 +1097,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
.propeller => .PROPELLER,
.riscv32, .riscv32be, .riscv64, .riscv64be => .RISCV,
.s390x => .S390,
+ .sh, .sheb => .SH,
.sparc => if (target.cpu.has(.sparc, .v9)) .SPARC32PLUS else .SPARC,
.sparc64 => .SPARCV9,
.ve => .VE,
@@ -1103,6 +1118,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
return switch (target.cpu.arch) {
+ .alpha => .ALPHA64,
.arm => .ARM,
.thumb => .ARMNT,
.aarch64 => .ARM64,
@@ -1114,6 +1130,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
.powerpcle => .POWERPC,
.riscv32 => .RISCV32,
.riscv64 => .RISCV64,
+ .sh => .SH3,
.x86 => .I386,
.x86_64 => .AMD64,
@@ -1127,9 +1144,13 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
.bpfel,
.csky,
.hexagon,
+ .hppa,
+ .hppa64,
.kalimba,
.lanai,
.m68k,
+ .microblaze,
+ .microblazeel,
.mips64,
.msp430,
.nvptx,
@@ -1142,6 +1163,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
.riscv32be,
.riscv64be,
.s390x,
+ .sheb,
.sparc,
.sparc64,
.spirv32,
@@ -1323,6 +1345,7 @@ pub const Cpu = struct {
pub const Arch = enum {
aarch64,
aarch64_be,
+ alpha,
amdgcn,
arc,
arceb,
@@ -1333,11 +1356,15 @@ pub const Cpu = struct {
bpfel,
csky,
hexagon,
+ hppa,
+ hppa64,
kalimba,
lanai,
loongarch32,
loongarch64,
m68k,
+ microblaze,
+ microblazeel,
mips,
mipsel,
mips64,
@@ -1356,6 +1383,8 @@ pub const Cpu = struct {
riscv64,
riscv64be,
s390x,
+ sh,
+ sheb,
sparc,
sparc64,
spirv32,
@@ -1393,18 +1422,21 @@ pub const Cpu = struct {
/// For a given family tag, it is guaranteed that an `std.Target.<tag>` namespace exists
/// containing CPU model and feature data.
pub const Family = enum {
+ aarch64,
+ alpha,
amdgcn,
arc,
arm,
- aarch64,
avr,
bpf,
csky,
hexagon,
+ hppa,
kalimba,
lanai,
loongarch,
m68k,
+ microblaze,
mips,
msp430,
nvptx,
@@ -1413,6 +1445,7 @@ pub const Cpu = struct {
propeller,
riscv,
s390x,
+ sh,
sparc,
spirv,
ve,
@@ -1425,6 +1458,7 @@ pub const Cpu = struct {
pub inline fn family(arch: Arch) Family {
return switch (arch) {
.aarch64, .aarch64_be => .aarch64,
+ .alpha => .alpha,
.amdgcn => .amdgcn,
.arc, .arceb => .arc,
.arm, .armeb, .thumb, .thumbeb => .arm,
@@ -1432,10 +1466,12 @@ pub const Cpu = struct {
.bpfeb, .bpfel => .bpf,
.csky => .csky,
.hexagon => .hexagon,
+ .hppa, .hppa64 => .hppa,
.kalimba => .kalimba,
.lanai => .lanai,
.loongarch32, .loongarch64 => .loongarch,
.m68k => .m68k,
+ .microblaze, .microblazeel => .microblaze,
.mips, .mipsel, .mips64, .mips64el => .mips,
.msp430 => .msp430,
.or1k => .or1k,
@@ -1444,6 +1480,7 @@ pub const Cpu = struct {
.propeller => .propeller,
.riscv32, .riscv32be, .riscv64, .riscv64be => .riscv,
.s390x => .s390x,
+ .sh, .sheb => .sh,
.sparc, .sparc64 => .sparc,
.spirv32, .spirv64 => .spirv,
.ve => .ve,
@@ -1490,6 +1527,13 @@ pub const Cpu = struct {
};
}
+ pub inline fn isHppa(arch: Arch) bool {
+ return switch (arch) {
+ .hppa, .hppa64 => true,
+ else => false,
+ };
+ }
+
pub inline fn isWasm(arch: Arch) bool {
return switch (arch) {
.wasm32, .wasm64 => true,
@@ -1522,6 +1566,13 @@ pub const Cpu = struct {
};
}
+ pub inline fn isMicroblaze(arch: Arch) bool {
+ return switch (arch) {
+ .microblaze, .microblazeel => true,
+ else => false,
+ };
+ }
+
pub inline fn isMIPS(arch: Arch) bool {
return arch.isMIPS32() or arch.isMIPS64();
}
@@ -1572,6 +1623,13 @@ pub const Cpu = struct {
};
}
+ pub inline fn isSh(arch: Arch) bool {
+ return switch (arch) {
+ .sh, .sheb => true,
+ else => false,
+ };
+ }
+
pub inline fn isBpf(arch: Arch) bool {
return switch (arch) {
.bpfel, .bpfeb => true,
@@ -1605,6 +1663,7 @@ pub const Cpu = struct {
pub fn endian(arch: Arch) std.builtin.Endian {
return switch (arch) {
.aarch64,
+ .alpha,
.arm,
.arc,
.avr,
@@ -1614,6 +1673,7 @@ pub const Cpu = struct {
.kalimba,
.loongarch32,
.loongarch64,
+ .microblazeel,
.mipsel,
.mips64el,
.msp430,
@@ -1622,6 +1682,7 @@ pub const Cpu = struct {
.propeller,
.riscv32,
.riscv64,
+ .sh,
.thumb,
.ve,
.wasm32,
@@ -1636,8 +1697,11 @@ pub const Cpu = struct {
.arceb,
.armeb,
.bpfeb,
+ .hppa,
+ .hppa64,
.lanai,
.m68k,
+ .microblaze,
.mips,
.mips64,
.or1k,
@@ -1646,6 +1710,7 @@ pub const Cpu = struct {
.riscv32be,
.riscv64be,
.s390x,
+ .sheb,
.thumbeb,
.sparc,
.sparc64,
@@ -1748,6 +1813,9 @@ pub const Cpu = struct {
.aarch64_vfabi_sve,
=> &.{ .aarch64, .aarch64_be },
+ .alpha_osf,
+ => &.{.alpha},
+
.arm_aapcs,
.arm_aapcs_vfp,
.arm_interrupt,
@@ -1813,6 +1881,12 @@ pub const Cpu = struct {
.hexagon_sysv_hvx,
=> &.{.hexagon},
+ .hppa_elf,
+ => &.{.hppa},
+
+ .hppa64_elf,
+ => &.{.hppa64},
+
.lanai_sysv,
=> &.{.lanai},
@@ -1828,6 +1902,9 @@ pub const Cpu = struct {
.m68k_interrupt,
=> &.{.m68k},
+ .microblaze_std,
+ => &.{ .microblaze, .microblazeel },
+
.msp430_eabi,
=> &.{.msp430},
@@ -1841,6 +1918,10 @@ pub const Cpu = struct {
.s390x_sysv_vx,
=> &.{.s390x},
+ .sh_gnu,
+ .sh_renesas,
+ => &.{ .sh, .sheb },
+
.ve_sysv,
=> &.{.ve},
@@ -2384,6 +2465,8 @@ pub const DynamicLinker = struct {
.aarch64_be,
.hexagon,
.m68k,
+ .microblaze,
+ .microblazeel,
.powerpc64,
.powerpc64le,
.s390x,
@@ -2419,6 +2502,17 @@ pub const DynamicLinker = struct {
else => return none,
}}),
+ .sh,
+ .sheb,
+ => |arch| initFmt("/lib/ld-musl-{t}{s}.so.1", .{
+ arch,
+ switch (abi) {
+ .musleabi => "-nofpu",
+ .musleabihf => "",
+ else => return none,
+ },
+ }),
+
.riscv32,
.riscv64,
=> |arch| if (abi == .musl) initFmt("/lib/ld-musl-{s}{s}.so.1", .{
@@ -2432,6 +2526,7 @@ pub const DynamicLinker = struct {
}) else none,
.x86 => if (abi == .musl) init("/lib/ld-musl-i386.so.1") else none,
+
.x86_64 => initFmt("/lib/ld-musl-{s}.so.1", .{switch (abi) {
.musl => "x86_64",
.muslx32 => "x32",
@@ -2475,7 +2570,10 @@ pub const DynamicLinker = struct {
else => return none,
}}),
+ .hppa,
.m68k,
+ .microblaze,
+ .microblazeel,
.xtensa,
.xtensaeb,
=> if (abi == .gnu) init("/lib/ld.so.1") else none,
@@ -2531,10 +2629,22 @@ pub const DynamicLinker = struct {
.s390x => if (abi == .gnu) init("/lib/ld64.so.1") else none,
- .sparc => if (abi == .gnu) init("/lib/ld-linux.so.2") else none,
+ .sh,
+ .sheb,
+ => switch (abi) {
+ .gnueabi,
+ .gnueabihf,
+ => init("/lib/ld-linux.so.2"),
+ else => none,
+ },
+
+ .alpha,
+ .sparc,
+ .x86,
+ => if (abi == .gnu) init("/lib/ld-linux.so.2") else none,
+
.sparc64 => if (abi == .gnu) init("/lib64/ld-linux.so.2") else none,
- .x86 => if (abi == .gnu) init("/lib/ld-linux.so.2") else none,
.x86_64 => switch (abi) {
.gnu => init("/lib64/ld-linux-x86-64.so.2"),
.gnux32 => init("/libx32/ld-linux-x32.so.2"),
@@ -2712,10 +2822,13 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
.armeb,
.csky,
.hexagon,
+ .hppa,
.kalimba,
.lanai,
.loongarch32,
.m68k,
+ .microblaze,
+ .microblazeel,
.mips,
.mipsel,
.nvptx,
@@ -2725,6 +2838,8 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
.propeller,
.riscv32,
.riscv32be,
+ .sh,
+ .sheb,
.sparc,
.spirv32,
.thumb,
@@ -2738,9 +2853,11 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
.aarch64,
.aarch64_be,
+ .alpha,
.amdgcn,
.bpfeb,
.bpfel,
+ .hppa64,
.loongarch64,
.mips64,
.mips64el,
@@ -2772,17 +2889,20 @@ pub fn stackAlignment(target: *const Target) u16 {
=> return 4,
.arm,
.armeb,
- .thumb,
- .thumbeb,
+ .hppa,
.lanai,
.mips,
.mipsel,
.sparc,
+ .thumb,
+ .thumbeb,
=> return 8,
.aarch64,
.aarch64_be,
+ .alpha,
.bpfeb,
.bpfel,
+ .hppa64,
.loongarch32,
.loongarch64,
.mips64,
@@ -2950,6 +3070,7 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) u16 {
else => return 128,
},
+ .alpha,
.riscv32,
.riscv32be,
.riscv64,
@@ -3059,6 +3180,7 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) u16 {
},
},
+ .alpha,
.riscv32,
.riscv32be,
.riscv64,
@@ -3251,8 +3373,12 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
.arceb,
.csky,
.kalimba,
+ .microblaze,
+ .microblazeel,
.or1k,
.propeller,
+ .sh,
+ .sheb,
.x86,
.xcore,
.xtensa,
@@ -3265,6 +3391,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
.bpfeb,
.bpfel,
.hexagon,
+ .hppa,
.lanai,
.m68k,
.mips,
@@ -3279,6 +3406,8 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
.aarch64,
.aarch64_be,
+ .alpha,
+ .hppa64,
.loongarch32,
.loongarch64,
.mips64,
@@ -3351,8 +3480,12 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
.arceb,
.csky,
.kalimba,
+ .microblaze,
+ .microblazeel,
.or1k,
.propeller,
+ .sh,
+ .sheb,
.xcore,
.xtensa,
.xtensaeb,
@@ -3364,6 +3497,7 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
.bpfeb,
.bpfel,
.hexagon,
+ .hppa,
.lanai,
.m68k,
.mips,
@@ -3379,6 +3513,8 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
.aarch64,
.aarch64_be,
+ .alpha,
+ .hppa64,
.loongarch32,
.loongarch64,
.mips64,
@@ -3416,14 +3552,19 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
.arceb,
.csky,
.kalimba,
+ .microblaze,
+ .microblazeel,
.or1k,
.propeller,
+ .sh,
+ .sheb,
.xcore,
=> 4,
.arm,
.armeb,
.hexagon,
+ .hppa,
.lanai,
.loongarch32,
.m68k,
@@ -3444,9 +3585,11 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
.aarch64,
.aarch64_be,
+ .alpha,
.amdgcn,
.bpfel,
.bpfeb,
+ .hppa64,
.loongarch64,
.mips64,
.mips64el,
@@ -3483,6 +3626,7 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
.windows => .{ .aarch64_aapcs_win = .{} },
else => .{ .aarch64_aapcs = .{} },
},
+ .alpha => .{ .alpha_osf = .{} },
.arm, .armeb, .thumb, .thumbeb => switch (target.abi.float()) {
.soft => .{ .arm_aapcs = .{} },
.hard => .{ .arm_aapcs_vfp = .{} },
@@ -3511,6 +3655,8 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
.bpfel, .bpfeb => .{ .bpf_std = .{} },
.csky => .{ .csky_sysv = .{} },
.hexagon => .{ .hexagon_sysv = .{} },
+ .hppa => .{ .hppa_elf = .{} },
+ .hppa64 => .{ .hppa64_elf = .{} },
.kalimba => null,
.lanai => .{ .lanai_sysv = .{} },
.loongarch64 => .{ .loongarch64_lp64 = .{} },
@@ -3519,10 +3665,12 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
.{ .m68k_gnu = .{} }
else
.{ .m68k_sysv = .{} },
+ .microblaze, .microblazeel => .{ .microblaze_std = .{} },
.msp430 => .{ .msp430_eabi = .{} },
.or1k => .{ .or1k_sysv = .{} },
.propeller => .{ .propeller_sysv = .{} },
.s390x => .{ .s390x_sysv = .{} },
+ .sh, .sheb => .{ .sh_gnu = .{} },
.ve => .{ .ve_sysv = .{} },
.xcore => .{ .xcore_xs1 = .{} },
.xtensa, .xtensaeb => .{ .xtensa_windowed = .{} },
src/codegen/c.zig
@@ -8106,6 +8106,8 @@ fn toCallingConvention(cc: std.builtin.CallingConvention, zcu: *Zcu) ?[]const u8
inline else => |m| "interrupt(\"" ++ @tagName(m) ++ "\")",
},
+ .sh_renesas => "renesas",
+
.m68k_rtd => "m68k_rtd",
.avr_interrupt,
src/codegen/llvm.zig
@@ -106,10 +106,17 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8
.wasm64 => "wasm64",
.ve => "ve",
+ .alpha,
.arceb,
+ .hppa,
+ .hppa64,
.kalimba,
+ .microblaze,
+ .microblazeel,
.or1k,
.propeller,
+ .sh,
+ .sheb,
.xtensaeb,
=> unreachable, // Gated by hasLlvmSupport().
};
@@ -475,10 +482,17 @@ pub fn dataLayout(target: *const std.Target) []const u8 {
.loongarch64 => "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128",
.xtensa => "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32",
+ .alpha,
.arceb,
+ .hppa,
+ .hppa64,
.kalimba,
+ .microblaze,
+ .microblazeel,
.or1k,
.propeller,
+ .sh,
+ .sheb,
.xtensaeb,
=> unreachable, // Gated by hasLlvmSupport().
};
@@ -11908,6 +11922,8 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s
.aarch64_aapcs,
.aarch64_aapcs_darwin,
.aarch64_aapcs_win,
+ .alpha_osf,
+ .microblaze_std,
.mips64_n64,
.mips64_n32,
.mips_o32,
@@ -11930,6 +11946,8 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s
.csky_sysv,
.hexagon_sysv,
.hexagon_sysv_hvx,
+ .hppa_elf,
+ .hppa64_elf,
.lanai_sysv,
.loongarch64_lp64,
.loongarch32_ilp32,
@@ -11940,6 +11958,8 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s
.propeller_sysv,
.s390x_sysv,
.s390x_sysv_vx,
+ .sh_gnu,
+ .sh_renesas,
.ve_sysv,
.xcore_xs1,
.xcore_xs2,
@@ -13111,10 +13131,17 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
},
// LLVM does does not have a backend for these.
+ .alpha,
.arceb,
+ .hppa,
+ .hppa64,
.kalimba,
+ .microblaze,
+ .microblazeel,
.or1k,
.propeller,
+ .sh,
+ .sheb,
.xtensaeb,
=> unreachable,
}
src/link/Dwarf.zig
@@ -3905,6 +3905,8 @@ fn updateLazyType(
.m68k_rtd => .LLVM_M68kRTD,
+ .sh_renesas => .GNU_renesas_sh,
+
.amdgcn_kernel => .LLVM_OpenCLKernel,
.nvptx_kernel,
.spirv_kernel,
src/Sema.zig
@@ -9043,8 +9043,10 @@ const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention
.aarch64_aapcs_win,
.aarch64_vfabi,
.aarch64_vfabi_sve,
+ .alpha_osf,
.arm_aapcs,
.arm_aapcs_vfp,
+ .microblaze_std,
.mips64_n64,
.mips64_n32,
.mips_o32,
@@ -9068,6 +9070,8 @@ const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention
.csky_sysv,
.hexagon_sysv,
.hexagon_sysv_hvx,
+ .hppa_elf,
+ .hppa64_elf,
.lanai_sysv,
.loongarch64_lp64,
.loongarch32_ilp32,
@@ -9078,6 +9082,8 @@ const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention
.or1k_sysv,
.s390x_sysv,
.s390x_sysv_vx,
+ .sh_gnu,
+ .sh_renesas,
.ve_sysv,
.xcore_xs1,
.xcore_xs2,
src/target.zig
@@ -216,10 +216,17 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)
=> false,
// No LLVM backend exists.
+ .alpha,
.arceb,
+ .hppa,
+ .hppa64,
.kalimba,
+ .microblaze,
+ .microblazeel,
.or1k,
.propeller,
+ .sh,
+ .sheb,
.xtensaeb,
=> false,
};
@@ -709,19 +716,26 @@ pub fn minFunctionAlignment(target: *const std.Target) Alignment {
.csky,
.m68k,
.msp430,
+ .sh,
+ .sheb,
.s390x,
.xcore,
=> .@"2",
+ .aarch64,
+ .aarch64_be,
+ .alpha,
.arc,
.arceb,
.arm,
.armeb,
- .aarch64,
- .aarch64_be,
.hexagon,
+ .hppa,
+ .hppa64,
.lanai,
.loongarch32,
.loongarch64,
+ .microblaze,
+ .microblazeel,
.mips,
.mipsel,
.powerpc,
@@ -733,8 +747,8 @@ pub fn minFunctionAlignment(target: *const std.Target) Alignment {
.xtensa,
.xtensaeb,
=> .@"4",
- .bpfel,
.bpfeb,
+ .bpfel,
.mips64,
.mips64el,
=> .@"8",