Commit ece70e08a0

David Rubin <daviru007@icloud.com>
2024-03-29 15:30:04
riscv: pass optionals by register_pair for resolveCallingConventionValues
1 parent 26ce82d
Changed files (2)
src
arch
src/arch/riscv64/abi.zig
@@ -94,10 +94,6 @@ pub fn classifyType(ty: Type, mod: *Module) Class {
 /// There are a maximum of 8 possible return slots. Returned values are in
 /// the beginning of the array; unused slots are filled with .none.
 pub fn classifySystemV(ty: Type, mod: *Module) [8]Class {
-    const memory_class = [_]Class{
-        .memory, .none, .none, .none,
-        .none,   .none, .none, .none,
-    };
     var result = [1]Class{.none} ** 8;
     switch (ty.zigTypeTag(mod)) {
         .Pointer => switch (ty.ptrSize(mod)) {
@@ -113,10 +109,11 @@ pub fn classifySystemV(ty: Type, mod: *Module) [8]Class {
         },
         .Optional => {
             if (ty.isPtrLikeOptional(mod)) {
-                result[0] = .integer;
                 return result;
             }
-            return memory_class;
+            result[0] = .integer;
+            result[1] = .integer;
+            return result;
         },
         else => return result,
     }
src/arch/riscv64/CodeGen.zig
@@ -830,7 +830,7 @@ fn splitType(self: *Self, ty: Type) ![2]Type {
             else => break,
         };
     } else if (parts[0].abiSize(mod) + parts[1].abiSize(mod) == ty.abiSize(mod)) return parts;
-    return std.debug.panic("TODO implement splitType for {}", .{ty.fmt(mod)});
+    return self.fail("TODO implement splitType for {}", .{ty.fmt(mod)});
 }
 
 fn symbolIndex(self: *Self) !u32 {
@@ -3152,11 +3152,6 @@ fn genCopy(self: *Self, ty: Type, dst_mcv: MCValue, src_mcv: MCValue) !void {
             };
             defer if (src_info) |info| self.register_manager.unlockReg(info.addr_lock);
 
-            switch (ty.zigTypeTag(mod)) {
-                .Optional => return,
-                else => {},
-            }
-
             var part_disp: i32 = 0;
             for (dst_regs, try self.splitType(ty), 0..) |dst_reg, dst_ty, part_i| {
                 try self.genSetReg(dst_ty, dst_reg, switch (src_mcv) {
@@ -3554,8 +3549,6 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, src_mcv: MCValue) InnerError!
                     },
                 },
             });
-
-            unreachable;
         },
         .air_ref => |ref| try self.genSetReg(ty, reg, try self.resolveInst(ref)),
         .indirect => |reg_off| {