Commit e73ae94b36
Changed files (4)
src
arch
src/arch/riscv64/abi.zig
@@ -5,13 +5,11 @@ const RegisterManagerFn = @import("../../register_manager.zig").RegisterManager;
const Type = @import("../../type.zig").Type;
const InternPool = @import("../../InternPool.zig");
const Zcu = @import("../../Zcu.zig");
-/// Deprecated.
-const Module = Zcu;
const assert = std.debug.assert;
pub const Class = enum { memory, byval, integer, double_integer, fields };
-pub fn classifyType(ty: Type, mod: *Module) Class {
+pub fn classifyType(ty: Type, mod: *Zcu) Class {
const target = mod.getTarget();
std.debug.assert(ty.hasRuntimeBitsIgnoreComptime(mod));
@@ -99,7 +97,7 @@ pub const SystemClass = enum { integer, float, memory, none };
/// There are a maximum of 8 possible return slots. Returned values are in
/// the beginning of the array; unused slots are filled with .none.
-pub fn classifySystem(ty: Type, zcu: *Module) [8]SystemClass {
+pub fn classifySystem(ty: Type, zcu: *Zcu) [8]SystemClass {
var result = [1]SystemClass{.none} ** 8;
const memory_class = [_]SystemClass{
.memory, .none, .none, .none,
@@ -202,7 +200,7 @@ fn classifyStruct(
result: *[8]Class,
byte_offset: *u64,
loaded_struct: InternPool.LoadedStructType,
- zcu: *Module,
+ zcu: *Zcu,
) void {
const ip = &zcu.intern_pool;
var field_it = loaded_struct.iterateRuntimeOrder(ip);
src/arch/riscv64/bits.zig
@@ -5,8 +5,6 @@ const testing = std.testing;
const Target = std.Target;
const Zcu = @import("../../Zcu.zig");
-/// Deprecated.
-const Module = Zcu;
const Encoding = @import("Encoding.zig");
const Mir = @import("Mir.zig");
const abi = @import("abi.zig");
@@ -202,7 +200,7 @@ pub const Register = enum(u8) {
return @as(u8, reg.id());
}
- pub fn bitSize(reg: Register, zcu: *const Module) u32 {
+ pub fn bitSize(reg: Register, zcu: *const Zcu) u32 {
const features = zcu.getTarget().cpu.features;
return switch (@intFromEnum(reg)) {
src/arch/riscv64/CodeGen.zig
@@ -11,12 +11,10 @@ const Type = @import("../../type.zig").Type;
const Value = @import("../../Value.zig");
const link = @import("../../link.zig");
const Zcu = @import("../../Zcu.zig");
-/// Deprecated.
-const Module = Zcu;
const Package = @import("../../Package.zig");
const InternPool = @import("../../InternPool.zig");
const Compilation = @import("../../Compilation.zig");
-const ErrorMsg = Module.ErrorMsg;
+const ErrorMsg = Zcu.ErrorMsg;
const Target = std.Target;
const Allocator = mem.Allocator;
const trace = @import("../../tracy.zig").trace;
@@ -61,7 +59,7 @@ args: []MCValue,
ret_mcv: InstTracking,
fn_type: Type,
arg_index: usize,
-src_loc: Module.SrcLoc,
+src_loc: Zcu.SrcLoc,
/// MIR Instructions
mir_instructions: std.MultiArrayList(Mir.Inst) = .{},
@@ -543,13 +541,13 @@ const FrameAlloc = struct {
.ref_count = 0,
};
}
- fn initType(ty: Type, zcu: *Module) FrameAlloc {
+ fn initType(ty: Type, zcu: *Zcu) FrameAlloc {
return init(.{
.size = ty.abiSize(zcu),
.alignment = ty.abiAlignment(zcu),
});
}
- fn initSpill(ty: Type, zcu: *Module) FrameAlloc {
+ fn initSpill(ty: Type, zcu: *Zcu) FrameAlloc {
const abi_size = ty.abiSize(zcu);
const spill_size = if (abi_size < 8)
math.ceilPowerOfTwoAssert(u64, abi_size)
@@ -698,7 +696,7 @@ const CallView = enum(u1) {
pub fn generate(
bin_file: *link.File,
- src_loc: Module.SrcLoc,
+ src_loc: Zcu.SrcLoc,
func_index: InternPool.Index,
air: Air,
liveness: Liveness,
@@ -922,7 +920,7 @@ fn fmtWipMir(func: *Func, inst: Mir.Inst.Index) std.fmt.Formatter(formatWipMir)
}
const FormatDeclData = struct {
- mod: *Module,
+ mod: *Zcu,
decl_index: InternPool.DeclIndex,
};
fn formatDecl(
@@ -6636,7 +6634,7 @@ fn hasFeature(func: *Func, feature: Target.riscv.Feature) bool {
return Target.riscv.featureSetHas(func.target.cpu.features, feature);
}
-pub fn errUnionPayloadOffset(payload_ty: Type, zcu: *Module) u64 {
+pub fn errUnionPayloadOffset(payload_ty: Type, zcu: *Zcu) u64 {
if (!payload_ty.hasRuntimeBitsIgnoreComptime(zcu)) return 0;
const payload_align = payload_ty.abiAlignment(zcu);
const error_align = Type.anyerror.abiAlignment(zcu);
@@ -6647,7 +6645,7 @@ pub fn errUnionPayloadOffset(payload_ty: Type, zcu: *Module) u64 {
}
}
-pub fn errUnionErrorOffset(payload_ty: Type, zcu: *Module) u64 {
+pub fn errUnionErrorOffset(payload_ty: Type, zcu: *Zcu) u64 {
if (!payload_ty.hasRuntimeBitsIgnoreComptime(zcu)) return 0;
const payload_align = payload_ty.abiAlignment(zcu);
const error_align = Type.anyerror.abiAlignment(zcu);
src/arch/riscv64/Lower.zig
@@ -8,7 +8,7 @@ allocator: Allocator,
mir: Mir,
cc: std.builtin.CallingConvention,
err_msg: ?*ErrorMsg = null,
-src_loc: Module.SrcLoc,
+src_loc: Zcu.SrcLoc,
result_insts_len: u8 = undefined,
result_relocs_len: u8 = undefined,
result_insts: [
@@ -520,10 +520,8 @@ const log = std.log.scoped(.lower);
const Air = @import("../../Air.zig");
const Allocator = std.mem.Allocator;
-const ErrorMsg = Module.ErrorMsg;
+const ErrorMsg = Zcu.ErrorMsg;
const Mir = @import("Mir.zig");
const Zcu = @import("../../Zcu.zig");
-/// Deprecated.
-const Module = Zcu;
const Instruction = encoder.Instruction;
const Immediate = bits.Immediate;