Commit c9d1db7e8e
Changed files (2)
src
arch
x86_64
test
behavior
src/arch/x86_64/CodeGen.zig
@@ -472,10 +472,14 @@ fn gen(self: *Self) InnerError!void {
.regs = 0,
.disp = mem.alignForwardGeneric(u32, self.next_stack_offset, 8),
};
+ var disp = data.disp + 8;
inline for (callee_preserved_regs) |reg, i| {
if (self.register_manager.isRegAllocated(reg)) {
if (reg.to64() == .rdi) {
for (self.ret_backpatches.items) |inst| {
+ log.debug(".rdi was spilled, backpatching with mov from stack at offset {}", .{
+ -@intCast(i32, disp),
+ });
const ops = Mir.Ops.decode(self.mir_instructions.items(.ops)[inst]);
self.mir_instructions.set(inst, Mir.Inst{
.tag = .mov,
@@ -484,12 +488,13 @@ fn gen(self: *Self) InnerError!void {
.reg2 = .rbp,
.flags = 0b01,
}).encode(),
- .data = .{ .imm = @bitCast(u32, -@intCast(i32, self.max_end_stack + 8)) },
+ .data = .{ .imm = @bitCast(u32, -@intCast(i32, disp)) },
});
}
}
data.regs |= 1 << @intCast(u5, i);
self.max_end_stack += 8;
+ disp += 8;
}
}
break :blk try self.addExtra(data);
test/behavior/cast.zig
@@ -19,7 +19,7 @@ test "integer literal to pointer cast" {
test "peer type resolution: ?T and T" {
if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest;
- if (builtin.zig_backend == .stage2_x86_64 or builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
+ if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest;
try expect(peerTypeTAndOptionalT(true, false).? == 0);
try expect(peerTypeTAndOptionalT(false, false).? == 3);