Commit c641fb8f05

William Sengir <william@sengir.com>
2022-03-26 23:40:31
stage2: fix {add,sub,mul}_with_overflow vectorization in LLVM backend
master
1 parent 5b03d55
Changed files (1)
src
codegen
llvm.zig
src/codegen/llvm.zig
@@ -5604,8 +5604,9 @@ pub const FuncGen = struct {
         const rhs = try self.resolveInst(extra.rhs);
 
         const lhs_ty = self.air.typeOf(extra.lhs);
+        const scalar_ty = lhs_ty.scalarType();
 
-        const intrinsic_name = if (lhs_ty.isSignedInt()) signed_intrinsic else unsigned_intrinsic;
+        const intrinsic_name = if (scalar_ty.isSignedInt()) signed_intrinsic else unsigned_intrinsic;
 
         const llvm_lhs_ty = try self.dg.llvmType(lhs_ty);