Commit c131e50ea7
Changed files (51)
lib
std
target
cpu
feature
src-self-hosted
lib/std/target/cpu/AArch64Cpu.zig
@@ -1,480 +0,0 @@
-const feature = @import("std").target.feature;
-const CpuInfo = @import("std").target.cpu.CpuInfo;
-
-pub const AArch64Cpu = enum {
- AppleLatest,
- CortexA35,
- CortexA53,
- CortexA55,
- CortexA57,
- CortexA65,
- CortexA65ae,
- CortexA72,
- CortexA73,
- CortexA75,
- CortexA76,
- CortexA76ae,
- Cyclone,
- ExynosM1,
- ExynosM2,
- ExynosM3,
- ExynosM4,
- ExynosM5,
- Falkor,
- Generic,
- Kryo,
- NeoverseE1,
- NeoverseN1,
- Saphira,
- Thunderx,
- Thunderx2t99,
- Thunderxt81,
- Thunderxt83,
- Thunderxt88,
- Tsv110,
-
- const FeatureType = feature.AArch64Feature;
-
- pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
- return cpu_infos[@enumToInt(self)];
- }
-
- pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
- CpuInfo(@This(), FeatureType).create(.AppleLatest, "apple-latest", &[_]FeatureType {
- .ArithBccFusion,
- .ArithCbzFusion,
- .ZczFp,
- .AlternateSextloadCvtF32Pattern,
- .DisableLatencySchedHeuristic,
- .Perfmon,
- .ZczGp,
- .ZczFpWorkaround,
- .Zcm,
- .FpArmv8,
- .FuseCryptoEor,
- .FuseAes,
- .Cyclone,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA35, "cortex-a35", &[_]FeatureType {
- .Perfmon,
- .FpArmv8,
- .Crc,
- .A35,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA53, "cortex-a53", &[_]FeatureType {
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .CustomCheapAsMove,
- .BalanceFpOps,
- .UseAa,
- .FpArmv8,
- .FuseAes,
- .A53,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA55, "cortex-a55", &[_]FeatureType {
- .Lse,
- .Vh,
- .Rdm,
- .Perfmon,
- .Pan,
- .Dotprod,
- .Crc,
- .Lor,
- .Uaops,
- .Ras,
- .Rcpc,
- .Ccpp,
- .FpArmv8,
- .FuseAes,
- .A55,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA57, "cortex-a57", &[_]FeatureType {
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .PredictableSelectExpensive,
- .CustomCheapAsMove,
- .BalanceFpOps,
- .FuseLiterals,
- .FpArmv8,
- .FuseAes,
- .A57,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA65, "cortex-a65", &[_]FeatureType {
- .Lse,
- .Vh,
- .Rdm,
- .Pan,
- .Dotprod,
- .Crc,
- .Ssbs,
- .Lor,
- .Uaops,
- .Ras,
- .Rcpc,
- .Ccpp,
- .FpArmv8,
- .A65,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA65ae, "cortex-a65ae", &[_]FeatureType {
- .Lse,
- .Vh,
- .Rdm,
- .Pan,
- .Dotprod,
- .Crc,
- .Ssbs,
- .Lor,
- .Uaops,
- .Ras,
- .Rcpc,
- .Ccpp,
- .FpArmv8,
- .A65,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA72, "cortex-a72", &[_]FeatureType {
- .Perfmon,
- .FpArmv8,
- .Crc,
- .FuseAes,
- .A72,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA73, "cortex-a73", &[_]FeatureType {
- .Perfmon,
- .FpArmv8,
- .Crc,
- .FuseAes,
- .A73,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA75, "cortex-a75", &[_]FeatureType {
- .Lse,
- .Vh,
- .Rdm,
- .Perfmon,
- .Pan,
- .Dotprod,
- .Crc,
- .Lor,
- .Uaops,
- .Ras,
- .Rcpc,
- .Ccpp,
- .FpArmv8,
- .FuseAes,
- .A75,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA76, "cortex-a76", &[_]FeatureType {
- .Lse,
- .Vh,
- .Rdm,
- .Pan,
- .Dotprod,
- .Crc,
- .Ssbs,
- .Lor,
- .Uaops,
- .Ras,
- .Rcpc,
- .Ccpp,
- .FpArmv8,
- .A76,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA76ae, "cortex-a76ae", &[_]FeatureType {
- .Lse,
- .Vh,
- .Rdm,
- .Pan,
- .Dotprod,
- .Crc,
- .Ssbs,
- .Lor,
- .Uaops,
- .Ras,
- .Rcpc,
- .Ccpp,
- .FpArmv8,
- .A76,
- }),
- CpuInfo(@This(), FeatureType).create(.Cyclone, "cyclone", &[_]FeatureType {
- .ArithBccFusion,
- .ArithCbzFusion,
- .ZczFp,
- .AlternateSextloadCvtF32Pattern,
- .DisableLatencySchedHeuristic,
- .Perfmon,
- .ZczGp,
- .ZczFpWorkaround,
- .Zcm,
- .FpArmv8,
- .FuseCryptoEor,
- .FuseAes,
- .Cyclone,
- }),
- CpuInfo(@This(), FeatureType).create(.ExynosM1, "exynos-m1", &[_]FeatureType {
- .ZczFp,
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .UseReciprocalSquareRoot,
- .CustomCheapAsMove,
- .Force32bitJumpTables,
- .SlowMisaligned128store,
- .FpArmv8,
- .SlowPaired128,
- .FuseAes,
- .Exynosm1,
- }),
- CpuInfo(@This(), FeatureType).create(.ExynosM2, "exynos-m2", &[_]FeatureType {
- .ZczFp,
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .CustomCheapAsMove,
- .Force32bitJumpTables,
- .SlowMisaligned128store,
- .FpArmv8,
- .SlowPaired128,
- .FuseAes,
- .Exynosm2,
- }),
- CpuInfo(@This(), FeatureType).create(.ExynosM3, "exynos-m3", &[_]FeatureType {
- .FuseCsel,
- .ZczFp,
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .PredictableSelectExpensive,
- .CustomCheapAsMove,
- .Force32bitJumpTables,
- .FuseLiterals,
- .FuseAddress,
- .LslFast,
- .FpArmv8,
- .FuseAes,
- .Exynosm3,
- }),
- CpuInfo(@This(), FeatureType).create(.ExynosM4, "exynos-m4", &[_]FeatureType {
- .ArithBccFusion,
- .Vh,
- .ArithCbzFusion,
- .ZczFp,
- .Rdm,
- .UsePostraScheduler,
- .Ras,
- .Force32bitJumpTables,
- .Ccpp,
- .FuseCsel,
- .Pan,
- .Uaops,
- .FuseLiterals,
- .LslFast,
- .Lse,
- .Perfmon,
- .Dotprod,
- .Lor,
- .FuseArithLogic,
- .Crc,
- .CustomCheapAsMove,
- .FuseAddress,
- .ZczGp,
- .FpArmv8,
- .FuseAes,
- .Exynosm4,
- }),
- CpuInfo(@This(), FeatureType).create(.ExynosM5, "exynos-m5", &[_]FeatureType {
- .ArithBccFusion,
- .Vh,
- .ArithCbzFusion,
- .ZczFp,
- .Rdm,
- .UsePostraScheduler,
- .Ras,
- .Force32bitJumpTables,
- .Ccpp,
- .FuseCsel,
- .Pan,
- .Uaops,
- .FuseLiterals,
- .LslFast,
- .Lse,
- .Perfmon,
- .Dotprod,
- .Lor,
- .FuseArithLogic,
- .Crc,
- .CustomCheapAsMove,
- .FuseAddress,
- .ZczGp,
- .FpArmv8,
- .FuseAes,
- .Exynosm4,
- }),
- CpuInfo(@This(), FeatureType).create(.Falkor, "falkor", &[_]FeatureType {
- .ZczFp,
- .Rdm,
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .PredictableSelectExpensive,
- .CustomCheapAsMove,
- .ZczGp,
- .FpArmv8,
- .SlowStrqroStore,
- .LslFast,
- .Falkor,
- }),
- CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
- .Trbe,
- .Ete,
- .FpArmv8,
- .FuseAes,
- .Neon,
- .Perfmon,
- .UsePostraScheduler,
- }),
- CpuInfo(@This(), FeatureType).create(.Kryo, "kryo", &[_]FeatureType {
- .ZczFp,
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .PredictableSelectExpensive,
- .CustomCheapAsMove,
- .ZczGp,
- .FpArmv8,
- .LslFast,
- .Kryo,
- }),
- CpuInfo(@This(), FeatureType).create(.NeoverseE1, "neoverse-e1", &[_]FeatureType {
- .Lse,
- .Vh,
- .Rdm,
- .Pan,
- .Dotprod,
- .Crc,
- .Ssbs,
- .Lor,
- .Uaops,
- .Ras,
- .Rcpc,
- .Ccpp,
- .FpArmv8,
- .Neoversee1,
- }),
- CpuInfo(@This(), FeatureType).create(.NeoverseN1, "neoverse-n1", &[_]FeatureType {
- .Lse,
- .Spe,
- .Vh,
- .Rdm,
- .Pan,
- .Dotprod,
- .Crc,
- .Ssbs,
- .Lor,
- .Uaops,
- .Ras,
- .Rcpc,
- .Ccpp,
- .FpArmv8,
- .Neoversen1,
- }),
- CpuInfo(@This(), FeatureType).create(.Saphira, "saphira", &[_]FeatureType {
- .Spe,
- .Vh,
- .ZczFp,
- .Rdm,
- .UsePostraScheduler,
- .Dit,
- .Am,
- .Ras,
- .Rcpc,
- .Sel2,
- .Ccpp,
- .Pa,
- .Pan,
- .Uaops,
- .Tracev84,
- .Mpam,
- .LslFast,
- .Lse,
- .Nv,
- .Perfmon,
- .Dotprod,
- .TlbRmi,
- .Lor,
- .Ccidx,
- .PredictableSelectExpensive,
- .Crc,
- .CustomCheapAsMove,
- .Fmi,
- .ZczGp,
- .FpArmv8,
- .Saphira,
- }),
- CpuInfo(@This(), FeatureType).create(.Thunderx, "thunderx", &[_]FeatureType {
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .FpArmv8,
- .PredictableSelectExpensive,
- .Thunderx,
- }),
- CpuInfo(@This(), FeatureType).create(.Thunderx2t99, "thunderx2t99", &[_]FeatureType {
- .Lse,
- .ArithBccFusion,
- .Vh,
- .Rdm,
- .UsePostraScheduler,
- .Crc,
- .Lor,
- .Pan,
- .AggressiveFma,
- .FpArmv8,
- .PredictableSelectExpensive,
- .Thunderx2t99,
- }),
- CpuInfo(@This(), FeatureType).create(.Thunderxt81, "thunderxt81", &[_]FeatureType {
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .FpArmv8,
- .PredictableSelectExpensive,
- .Thunderxt81,
- }),
- CpuInfo(@This(), FeatureType).create(.Thunderxt83, "thunderxt83", &[_]FeatureType {
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .FpArmv8,
- .PredictableSelectExpensive,
- .Thunderxt83,
- }),
- CpuInfo(@This(), FeatureType).create(.Thunderxt88, "thunderxt88", &[_]FeatureType {
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .FpArmv8,
- .PredictableSelectExpensive,
- .Thunderxt88,
- }),
- CpuInfo(@This(), FeatureType).create(.Tsv110, "tsv110", &[_]FeatureType {
- .Lse,
- .Spe,
- .Vh,
- .Rdm,
- .Perfmon,
- .UsePostraScheduler,
- .Pan,
- .Dotprod,
- .Crc,
- .Lor,
- .Uaops,
- .CustomCheapAsMove,
- .Ras,
- .Ccpp,
- .FpArmv8,
- .FuseAes,
- .Tsv110,
- }),
- };
-};
lib/std/target/cpu/AmdGpuCpu.zig
@@ -1,1060 +0,0 @@
-const feature = @import("std").target.feature;
-const CpuInfo = @import("std").target.cpu.CpuInfo;
-
-pub const AmdGpuCpu = enum {
- Bonaire,
- Carrizo,
- Fiji,
- Generic,
- GenericHsa,
- Gfx1010,
- Gfx1011,
- Gfx1012,
- Gfx600,
- Gfx601,
- Gfx700,
- Gfx701,
- Gfx702,
- Gfx703,
- Gfx704,
- Gfx801,
- Gfx802,
- Gfx803,
- Gfx810,
- Gfx900,
- Gfx902,
- Gfx904,
- Gfx906,
- Gfx908,
- Gfx909,
- Hainan,
- Hawaii,
- Iceland,
- Kabini,
- Kaveri,
- Mullins,
- Oland,
- Pitcairn,
- Polaris10,
- Polaris11,
- Stoney,
- Tahiti,
- Tonga,
- Verde,
-
- const FeatureType = feature.AmdGpuFeature;
-
- pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
- return cpu_infos[@enumToInt(self)];
- }
-
- pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
- CpuInfo(@This(), FeatureType).create(.Bonaire, "bonaire", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .Ldsbankcount32,
- .Movrel,
- .Gfx7Gfx8Gfx9Insts,
- .Fp64,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Localmemorysize65536,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .MimgR128,
- .SeaIslands,
- }),
- CpuInfo(@This(), FeatureType).create(.Carrizo, "carrizo", &[_]FeatureType {
- .CodeObjectV3,
- .FastFmaf,
- .Ldsbankcount32,
- .UnpackedD16Vmem,
- .IntClampInsts,
- .SdwaMav,
- .Movrel,
- .SMemrealtime,
- .Gcn3Encoding,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .ScalarStores,
- .Gfx7Gfx8Gfx9Insts,
- .Dpp,
- .Localmemorysize65536,
- .BitInsts16,
- .VgprIndexMode,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .MimgR128,
- .SdwaOutModsVopc,
- .Fp64,
- .VolcanicIslands,
- .Xnack,
- .HalfRate64Ops,
- }),
- CpuInfo(@This(), FeatureType).create(.Fiji, "fiji", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .Ldsbankcount32,
- .UnpackedD16Vmem,
- .IntClampInsts,
- .SdwaMav,
- .Movrel,
- .SMemrealtime,
- .Gcn3Encoding,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .ScalarStores,
- .Gfx7Gfx8Gfx9Insts,
- .Dpp,
- .Localmemorysize65536,
- .BitInsts16,
- .VgprIndexMode,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .MimgR128,
- .SdwaOutModsVopc,
- .Fp64,
- .VolcanicIslands,
- }),
- CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
- .Wavefrontsize64,
- }),
- CpuInfo(@This(), FeatureType).create(.GenericHsa, "generic-hsa", &[_]FeatureType {
- .FlatAddressSpace,
- .Wavefrontsize64,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx1010, "gfx1010", &[_]FeatureType {
- .CodeObjectV3,
- .DlInsts,
- .NoXnackSupport,
- .FlatSegmentOffsetBug,
- .Vscnt,
- .ApertureRegs,
- .Gfx10Insts,
- .IntClampInsts,
- .PkFmacF16Inst,
- .SdwaOmod,
- .SdwaScalar,
- .AddNoCarryInsts,
- .Movrel,
- .SMemrealtime,
- .NoSdstCmpx,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .NoSramEccSupport,
- .SdwaSdst,
- .FlatInstOffsets,
- .RegisterBanking,
- .Dpp,
- .Localmemorysize65536,
- .Vop3p,
- .BitInsts16,
- .Dpp8,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .Gfx9Insts,
- .FmaMixInsts,
- .MimgR128,
- .Vop3Literal,
- .FlatGlobalInsts,
- .FlatScratchInsts,
- .Fp64,
- .FastFmaf,
- .NoDataDepHazard,
- .Gfx10,
- .InstFwdPrefetchBug,
- .Ldsbankcount32,
- .LdsBranchVmemWarHazard,
- .LdsMisalignedBug,
- .NsaEncoding,
- .NsaToVmemBug,
- .Offset3fBug,
- .SmemToVectorWriteHazard,
- .ScalarAtomics,
- .ScalarFlatScratchInsts,
- .ScalarStores,
- .VmemToScalarWriteHazard,
- .VcmpxExecWarHazard,
- .VcmpxPermlaneHazard,
- .Wavefrontsize32,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx1011, "gfx1011", &[_]FeatureType {
- .CodeObjectV3,
- .DlInsts,
- .NoXnackSupport,
- .Dot1Insts,
- .Dot2Insts,
- .Dot5Insts,
- .Dot6Insts,
- .FlatSegmentOffsetBug,
- .Vscnt,
- .ApertureRegs,
- .Gfx10Insts,
- .IntClampInsts,
- .PkFmacF16Inst,
- .SdwaOmod,
- .SdwaScalar,
- .AddNoCarryInsts,
- .Movrel,
- .SMemrealtime,
- .NoSdstCmpx,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .NoSramEccSupport,
- .SdwaSdst,
- .FlatInstOffsets,
- .RegisterBanking,
- .Dpp,
- .Localmemorysize65536,
- .Vop3p,
- .BitInsts16,
- .Dpp8,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .Gfx9Insts,
- .FmaMixInsts,
- .MimgR128,
- .Vop3Literal,
- .FlatGlobalInsts,
- .FlatScratchInsts,
- .Fp64,
- .FastFmaf,
- .NoDataDepHazard,
- .Gfx10,
- .InstFwdPrefetchBug,
- .Ldsbankcount32,
- .LdsBranchVmemWarHazard,
- .NsaEncoding,
- .NsaToVmemBug,
- .Offset3fBug,
- .SmemToVectorWriteHazard,
- .ScalarAtomics,
- .ScalarFlatScratchInsts,
- .ScalarStores,
- .VmemToScalarWriteHazard,
- .VcmpxExecWarHazard,
- .VcmpxPermlaneHazard,
- .Wavefrontsize32,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx1012, "gfx1012", &[_]FeatureType {
- .CodeObjectV3,
- .DlInsts,
- .NoXnackSupport,
- .Dot1Insts,
- .Dot2Insts,
- .Dot5Insts,
- .Dot6Insts,
- .FlatSegmentOffsetBug,
- .Vscnt,
- .ApertureRegs,
- .Gfx10Insts,
- .IntClampInsts,
- .PkFmacF16Inst,
- .SdwaOmod,
- .SdwaScalar,
- .AddNoCarryInsts,
- .Movrel,
- .SMemrealtime,
- .NoSdstCmpx,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .NoSramEccSupport,
- .SdwaSdst,
- .FlatInstOffsets,
- .RegisterBanking,
- .Dpp,
- .Localmemorysize65536,
- .Vop3p,
- .BitInsts16,
- .Dpp8,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .Gfx9Insts,
- .FmaMixInsts,
- .MimgR128,
- .Vop3Literal,
- .FlatGlobalInsts,
- .FlatScratchInsts,
- .Fp64,
- .FastFmaf,
- .NoDataDepHazard,
- .Gfx10,
- .InstFwdPrefetchBug,
- .Ldsbankcount32,
- .LdsBranchVmemWarHazard,
- .LdsMisalignedBug,
- .NsaEncoding,
- .NsaToVmemBug,
- .Offset3fBug,
- .SmemToVectorWriteHazard,
- .ScalarAtomics,
- .ScalarFlatScratchInsts,
- .ScalarStores,
- .VmemToScalarWriteHazard,
- .VcmpxExecWarHazard,
- .VcmpxPermlaneHazard,
- .Wavefrontsize32,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx600, "gfx600", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .FastFmaf,
- .Ldsbankcount32,
- .Movrel,
- .MimgR128,
- .Fp64,
- .TrigReducedRange,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .Localmemorysize32768,
- .SouthernIslands,
- .HalfRate64Ops,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx601, "gfx601", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .Ldsbankcount32,
- .Movrel,
- .MimgR128,
- .Fp64,
- .TrigReducedRange,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .Localmemorysize32768,
- .SouthernIslands,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx700, "gfx700", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .Ldsbankcount32,
- .Movrel,
- .Gfx7Gfx8Gfx9Insts,
- .Fp64,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Localmemorysize65536,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .MimgR128,
- .SeaIslands,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx701, "gfx701", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .FastFmaf,
- .Ldsbankcount32,
- .Movrel,
- .Gfx7Gfx8Gfx9Insts,
- .Fp64,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Localmemorysize65536,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .MimgR128,
- .SeaIslands,
- .HalfRate64Ops,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx702, "gfx702", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .FastFmaf,
- .Ldsbankcount16,
- .Movrel,
- .Gfx7Gfx8Gfx9Insts,
- .Fp64,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Localmemorysize65536,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .MimgR128,
- .SeaIslands,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx703, "gfx703", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .Ldsbankcount16,
- .Movrel,
- .Gfx7Gfx8Gfx9Insts,
- .Fp64,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Localmemorysize65536,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .MimgR128,
- .SeaIslands,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx704, "gfx704", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .Ldsbankcount32,
- .Movrel,
- .Gfx7Gfx8Gfx9Insts,
- .Fp64,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Localmemorysize65536,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .MimgR128,
- .SeaIslands,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx801, "gfx801", &[_]FeatureType {
- .CodeObjectV3,
- .FastFmaf,
- .Ldsbankcount32,
- .UnpackedD16Vmem,
- .IntClampInsts,
- .SdwaMav,
- .Movrel,
- .SMemrealtime,
- .Gcn3Encoding,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .ScalarStores,
- .Gfx7Gfx8Gfx9Insts,
- .Dpp,
- .Localmemorysize65536,
- .BitInsts16,
- .VgprIndexMode,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .MimgR128,
- .SdwaOutModsVopc,
- .Fp64,
- .VolcanicIslands,
- .Xnack,
- .HalfRate64Ops,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx802, "gfx802", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .Ldsbankcount32,
- .SgprInitBug,
- .UnpackedD16Vmem,
- .IntClampInsts,
- .SdwaMav,
- .Movrel,
- .SMemrealtime,
- .Gcn3Encoding,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .ScalarStores,
- .Gfx7Gfx8Gfx9Insts,
- .Dpp,
- .Localmemorysize65536,
- .BitInsts16,
- .VgprIndexMode,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .MimgR128,
- .SdwaOutModsVopc,
- .Fp64,
- .VolcanicIslands,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx803, "gfx803", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .Ldsbankcount32,
- .UnpackedD16Vmem,
- .IntClampInsts,
- .SdwaMav,
- .Movrel,
- .SMemrealtime,
- .Gcn3Encoding,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .ScalarStores,
- .Gfx7Gfx8Gfx9Insts,
- .Dpp,
- .Localmemorysize65536,
- .BitInsts16,
- .VgprIndexMode,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .MimgR128,
- .SdwaOutModsVopc,
- .Fp64,
- .VolcanicIslands,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx810, "gfx810", &[_]FeatureType {
- .CodeObjectV3,
- .Ldsbankcount16,
- .IntClampInsts,
- .SdwaMav,
- .Movrel,
- .SMemrealtime,
- .Gcn3Encoding,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .ScalarStores,
- .Gfx7Gfx8Gfx9Insts,
- .Dpp,
- .Localmemorysize65536,
- .BitInsts16,
- .VgprIndexMode,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .MimgR128,
- .SdwaOutModsVopc,
- .Fp64,
- .VolcanicIslands,
- .Xnack,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx900, "gfx900", &[_]FeatureType {
- .CodeObjectV3,
- .NoSramEccSupport,
- .NoXnackSupport,
- .ApertureRegs,
- .IntClampInsts,
- .SdwaOmod,
- .SdwaScalar,
- .AddNoCarryInsts,
- .ScalarAtomics,
- .SMemrealtime,
- .Gcn3Encoding,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .Wavefrontsize64,
- .SdwaSdst,
- .FlatInstOffsets,
- .ScalarStores,
- .Gfx7Gfx8Gfx9Insts,
- .R128A16,
- .Dpp,
- .Localmemorysize65536,
- .Vop3p,
- .BitInsts16,
- .VgprIndexMode,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .Gfx9Insts,
- .ScalarFlatScratchInsts,
- .FlatGlobalInsts,
- .FlatScratchInsts,
- .Fp64,
- .FastFmaf,
- .Gfx9,
- .Ldsbankcount32,
- .MadMixInsts,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx902, "gfx902", &[_]FeatureType {
- .CodeObjectV3,
- .NoSramEccSupport,
- .ApertureRegs,
- .IntClampInsts,
- .SdwaOmod,
- .SdwaScalar,
- .AddNoCarryInsts,
- .ScalarAtomics,
- .SMemrealtime,
- .Gcn3Encoding,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .Wavefrontsize64,
- .SdwaSdst,
- .FlatInstOffsets,
- .ScalarStores,
- .Gfx7Gfx8Gfx9Insts,
- .R128A16,
- .Dpp,
- .Localmemorysize65536,
- .Vop3p,
- .BitInsts16,
- .VgprIndexMode,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .Gfx9Insts,
- .ScalarFlatScratchInsts,
- .FlatGlobalInsts,
- .FlatScratchInsts,
- .Fp64,
- .FastFmaf,
- .Gfx9,
- .Ldsbankcount32,
- .MadMixInsts,
- .Xnack,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx904, "gfx904", &[_]FeatureType {
- .CodeObjectV3,
- .NoSramEccSupport,
- .NoXnackSupport,
- .FmaMixInsts,
- .ApertureRegs,
- .IntClampInsts,
- .SdwaOmod,
- .SdwaScalar,
- .AddNoCarryInsts,
- .ScalarAtomics,
- .SMemrealtime,
- .Gcn3Encoding,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .Wavefrontsize64,
- .SdwaSdst,
- .FlatInstOffsets,
- .ScalarStores,
- .Gfx7Gfx8Gfx9Insts,
- .R128A16,
- .Dpp,
- .Localmemorysize65536,
- .Vop3p,
- .BitInsts16,
- .VgprIndexMode,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .Gfx9Insts,
- .ScalarFlatScratchInsts,
- .FlatGlobalInsts,
- .FlatScratchInsts,
- .Fp64,
- .FastFmaf,
- .Gfx9,
- .Ldsbankcount32,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx906, "gfx906", &[_]FeatureType {
- .CodeObjectV3,
- .DlInsts,
- .NoXnackSupport,
- .Dot1Insts,
- .Dot2Insts,
- .FmaMixInsts,
- .ApertureRegs,
- .IntClampInsts,
- .SdwaOmod,
- .SdwaScalar,
- .AddNoCarryInsts,
- .ScalarAtomics,
- .SMemrealtime,
- .Gcn3Encoding,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .Wavefrontsize64,
- .SdwaSdst,
- .FlatInstOffsets,
- .ScalarStores,
- .Gfx7Gfx8Gfx9Insts,
- .R128A16,
- .Dpp,
- .Localmemorysize65536,
- .Vop3p,
- .BitInsts16,
- .VgprIndexMode,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .Gfx9Insts,
- .ScalarFlatScratchInsts,
- .FlatGlobalInsts,
- .FlatScratchInsts,
- .Fp64,
- .FastFmaf,
- .Gfx9,
- .Ldsbankcount32,
- .HalfRate64Ops,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx908, "gfx908", &[_]FeatureType {
- .AtomicFaddInsts,
- .CodeObjectV3,
- .DlInsts,
- .Dot1Insts,
- .Dot2Insts,
- .Dot3Insts,
- .Dot4Insts,
- .Dot5Insts,
- .Dot6Insts,
- .FmaMixInsts,
- .ApertureRegs,
- .IntClampInsts,
- .SdwaOmod,
- .SdwaScalar,
- .AddNoCarryInsts,
- .ScalarAtomics,
- .SMemrealtime,
- .Gcn3Encoding,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .Wavefrontsize64,
- .SdwaSdst,
- .FlatInstOffsets,
- .ScalarStores,
- .Gfx7Gfx8Gfx9Insts,
- .R128A16,
- .Dpp,
- .Localmemorysize65536,
- .Vop3p,
- .BitInsts16,
- .VgprIndexMode,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .Gfx9Insts,
- .ScalarFlatScratchInsts,
- .FlatGlobalInsts,
- .FlatScratchInsts,
- .Fp64,
- .FastFmaf,
- .Gfx9,
- .Ldsbankcount32,
- .MaiInsts,
- .MfmaInlineLiteralBug,
- .PkFmacF16Inst,
- .SramEcc,
- .HalfRate64Ops,
- }),
- CpuInfo(@This(), FeatureType).create(.Gfx909, "gfx909", &[_]FeatureType {
- .CodeObjectV3,
- .ApertureRegs,
- .IntClampInsts,
- .SdwaOmod,
- .SdwaScalar,
- .AddNoCarryInsts,
- .ScalarAtomics,
- .SMemrealtime,
- .Gcn3Encoding,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .Wavefrontsize64,
- .SdwaSdst,
- .FlatInstOffsets,
- .ScalarStores,
- .Gfx7Gfx8Gfx9Insts,
- .R128A16,
- .Dpp,
- .Localmemorysize65536,
- .Vop3p,
- .BitInsts16,
- .VgprIndexMode,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .Gfx9Insts,
- .ScalarFlatScratchInsts,
- .FlatGlobalInsts,
- .FlatScratchInsts,
- .Fp64,
- .FastFmaf,
- .Gfx9,
- .Ldsbankcount32,
- .MadMixInsts,
- .Xnack,
- }),
- CpuInfo(@This(), FeatureType).create(.Hainan, "hainan", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .Ldsbankcount32,
- .Movrel,
- .MimgR128,
- .Fp64,
- .TrigReducedRange,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .Localmemorysize32768,
- .SouthernIslands,
- }),
- CpuInfo(@This(), FeatureType).create(.Hawaii, "hawaii", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .FastFmaf,
- .Ldsbankcount32,
- .Movrel,
- .Gfx7Gfx8Gfx9Insts,
- .Fp64,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Localmemorysize65536,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .MimgR128,
- .SeaIslands,
- .HalfRate64Ops,
- }),
- CpuInfo(@This(), FeatureType).create(.Iceland, "iceland", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .Ldsbankcount32,
- .SgprInitBug,
- .UnpackedD16Vmem,
- .IntClampInsts,
- .SdwaMav,
- .Movrel,
- .SMemrealtime,
- .Gcn3Encoding,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .ScalarStores,
- .Gfx7Gfx8Gfx9Insts,
- .Dpp,
- .Localmemorysize65536,
- .BitInsts16,
- .VgprIndexMode,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .MimgR128,
- .SdwaOutModsVopc,
- .Fp64,
- .VolcanicIslands,
- }),
- CpuInfo(@This(), FeatureType).create(.Kabini, "kabini", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .Ldsbankcount16,
- .Movrel,
- .Gfx7Gfx8Gfx9Insts,
- .Fp64,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Localmemorysize65536,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .MimgR128,
- .SeaIslands,
- }),
- CpuInfo(@This(), FeatureType).create(.Kaveri, "kaveri", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .Ldsbankcount32,
- .Movrel,
- .Gfx7Gfx8Gfx9Insts,
- .Fp64,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Localmemorysize65536,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .MimgR128,
- .SeaIslands,
- }),
- CpuInfo(@This(), FeatureType).create(.Mullins, "mullins", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .Ldsbankcount16,
- .Movrel,
- .Gfx7Gfx8Gfx9Insts,
- .Fp64,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Localmemorysize65536,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .MimgR128,
- .SeaIslands,
- }),
- CpuInfo(@This(), FeatureType).create(.Oland, "oland", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .Ldsbankcount32,
- .Movrel,
- .MimgR128,
- .Fp64,
- .TrigReducedRange,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .Localmemorysize32768,
- .SouthernIslands,
- }),
- CpuInfo(@This(), FeatureType).create(.Pitcairn, "pitcairn", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .Ldsbankcount32,
- .Movrel,
- .MimgR128,
- .Fp64,
- .TrigReducedRange,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .Localmemorysize32768,
- .SouthernIslands,
- }),
- CpuInfo(@This(), FeatureType).create(.Polaris10, "polaris10", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .Ldsbankcount32,
- .UnpackedD16Vmem,
- .IntClampInsts,
- .SdwaMav,
- .Movrel,
- .SMemrealtime,
- .Gcn3Encoding,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .ScalarStores,
- .Gfx7Gfx8Gfx9Insts,
- .Dpp,
- .Localmemorysize65536,
- .BitInsts16,
- .VgprIndexMode,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .MimgR128,
- .SdwaOutModsVopc,
- .Fp64,
- .VolcanicIslands,
- }),
- CpuInfo(@This(), FeatureType).create(.Polaris11, "polaris11", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .Ldsbankcount32,
- .UnpackedD16Vmem,
- .IntClampInsts,
- .SdwaMav,
- .Movrel,
- .SMemrealtime,
- .Gcn3Encoding,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .ScalarStores,
- .Gfx7Gfx8Gfx9Insts,
- .Dpp,
- .Localmemorysize65536,
- .BitInsts16,
- .VgprIndexMode,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .MimgR128,
- .SdwaOutModsVopc,
- .Fp64,
- .VolcanicIslands,
- }),
- CpuInfo(@This(), FeatureType).create(.Stoney, "stoney", &[_]FeatureType {
- .CodeObjectV3,
- .Ldsbankcount16,
- .IntClampInsts,
- .SdwaMav,
- .Movrel,
- .SMemrealtime,
- .Gcn3Encoding,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .ScalarStores,
- .Gfx7Gfx8Gfx9Insts,
- .Dpp,
- .Localmemorysize65536,
- .BitInsts16,
- .VgprIndexMode,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .MimgR128,
- .SdwaOutModsVopc,
- .Fp64,
- .VolcanicIslands,
- .Xnack,
- }),
- CpuInfo(@This(), FeatureType).create(.Tahiti, "tahiti", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .FastFmaf,
- .Ldsbankcount32,
- .Movrel,
- .MimgR128,
- .Fp64,
- .TrigReducedRange,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .Localmemorysize32768,
- .SouthernIslands,
- .HalfRate64Ops,
- }),
- CpuInfo(@This(), FeatureType).create(.Tonga, "tonga", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .Ldsbankcount32,
- .SgprInitBug,
- .UnpackedD16Vmem,
- .IntClampInsts,
- .SdwaMav,
- .Movrel,
- .SMemrealtime,
- .Gcn3Encoding,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .ScalarStores,
- .Gfx7Gfx8Gfx9Insts,
- .Dpp,
- .Localmemorysize65536,
- .BitInsts16,
- .VgprIndexMode,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .MimgR128,
- .SdwaOutModsVopc,
- .Fp64,
- .VolcanicIslands,
- }),
- CpuInfo(@This(), FeatureType).create(.Verde, "verde", &[_]FeatureType {
- .CodeObjectV3,
- .NoXnackSupport,
- .Ldsbankcount32,
- .Movrel,
- .MimgR128,
- .Fp64,
- .TrigReducedRange,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .Localmemorysize32768,
- .SouthernIslands,
- }),
- };
-};
lib/std/target/cpu/ArmCpu.zig
@@ -1,1230 +0,0 @@
-const feature = @import("std").target.feature;
-const CpuInfo = @import("std").target.cpu.CpuInfo;
-
-pub const ArmCpu = enum {
- Arm1020e,
- Arm1020t,
- Arm1022e,
- Arm10e,
- Arm10tdmi,
- Arm1136jS,
- Arm1136jfS,
- Arm1156t2S,
- Arm1156t2fS,
- Arm1176jS,
- Arm1176jzS,
- Arm1176jzfS,
- Arm710t,
- Arm720t,
- Arm7tdmi,
- Arm7tdmiS,
- Arm8,
- Arm810,
- Arm9,
- Arm920,
- Arm920t,
- Arm922t,
- Arm926ejS,
- Arm940t,
- Arm946eS,
- Arm966eS,
- Arm968eS,
- Arm9e,
- Arm9tdmi,
- CortexA12,
- CortexA15,
- CortexA17,
- CortexA32,
- CortexA35,
- CortexA5,
- CortexA53,
- CortexA55,
- CortexA57,
- CortexA7,
- CortexA72,
- CortexA73,
- CortexA75,
- CortexA76,
- CortexA76ae,
- CortexA8,
- CortexA9,
- CortexM0,
- CortexM0plus,
- CortexM1,
- CortexM23,
- CortexM3,
- CortexM33,
- CortexM35p,
- CortexM4,
- CortexM7,
- CortexR4,
- CortexR4f,
- CortexR5,
- CortexR52,
- CortexR7,
- CortexR8,
- Cyclone,
- Ep9312,
- ExynosM1,
- ExynosM2,
- ExynosM3,
- ExynosM4,
- ExynosM5,
- Generic,
- Iwmmxt,
- Krait,
- Kryo,
- Mpcore,
- Mpcorenovfp,
- NeoverseN1,
- Sc000,
- Sc300,
- Strongarm,
- Strongarm110,
- Strongarm1100,
- Strongarm1110,
- Swift,
- Xscale,
-
- const FeatureType = feature.ArmFeature;
-
- pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
- return cpu_infos[@enumToInt(self)];
- }
-
- pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
- CpuInfo(@This(), FeatureType).create(.Arm1020e, "arm1020e", &[_]FeatureType {
- .V4t,
- .Armv5te,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm1020t, "arm1020t", &[_]FeatureType {
- .V4t,
- .Armv5t,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm1022e, "arm1022e", &[_]FeatureType {
- .V4t,
- .Armv5te,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm10e, "arm10e", &[_]FeatureType {
- .V4t,
- .Armv5te,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm10tdmi, "arm10tdmi", &[_]FeatureType {
- .V4t,
- .Armv5t,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm1136jS, "arm1136j-s", &[_]FeatureType {
- .V4t,
- .Dsp,
- .Armv6,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm1136jfS, "arm1136jf-s", &[_]FeatureType {
- .V4t,
- .Dsp,
- .Armv6,
- .Slowfpvmlx,
- .Fpregs,
- .Vfp2,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm1156t2S, "arm1156t2-s", &[_]FeatureType {
- .V4t,
- .Thumb2,
- .Dsp,
- .Armv6t2,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm1156t2fS, "arm1156t2f-s", &[_]FeatureType {
- .V4t,
- .Thumb2,
- .Dsp,
- .Armv6t2,
- .Slowfpvmlx,
- .Fpregs,
- .Vfp2,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm1176jS, "arm1176j-s", &[_]FeatureType {
- .V4t,
- .Trustzone,
- .Armv6kz,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm1176jzS, "arm1176jz-s", &[_]FeatureType {
- .V4t,
- .Trustzone,
- .Armv6kz,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm1176jzfS, "arm1176jzf-s", &[_]FeatureType {
- .V4t,
- .Trustzone,
- .Armv6kz,
- .Slowfpvmlx,
- .Fpregs,
- .Vfp2,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm710t, "arm710t", &[_]FeatureType {
- .V4t,
- .Armv4t,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm720t, "arm720t", &[_]FeatureType {
- .V4t,
- .Armv4t,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm7tdmi, "arm7tdmi", &[_]FeatureType {
- .V4t,
- .Armv4t,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm7tdmiS, "arm7tdmi-s", &[_]FeatureType {
- .V4t,
- .Armv4t,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm8, "arm8", &[_]FeatureType {
- .Armv4,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm810, "arm810", &[_]FeatureType {
- .Armv4,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm9, "arm9", &[_]FeatureType {
- .V4t,
- .Armv4t,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm920, "arm920", &[_]FeatureType {
- .V4t,
- .Armv4t,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm920t, "arm920t", &[_]FeatureType {
- .V4t,
- .Armv4t,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm922t, "arm922t", &[_]FeatureType {
- .V4t,
- .Armv4t,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm926ejS, "arm926ej-s", &[_]FeatureType {
- .V4t,
- .Armv5te,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm940t, "arm940t", &[_]FeatureType {
- .V4t,
- .Armv4t,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm946eS, "arm946e-s", &[_]FeatureType {
- .V4t,
- .Armv5te,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm966eS, "arm966e-s", &[_]FeatureType {
- .V4t,
- .Armv5te,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm968eS, "arm968e-s", &[_]FeatureType {
- .V4t,
- .Armv5te,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm9e, "arm9e", &[_]FeatureType {
- .V4t,
- .Armv5te,
- }),
- CpuInfo(@This(), FeatureType).create(.Arm9tdmi, "arm9tdmi", &[_]FeatureType {
- .V4t,
- .Armv4t,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA12, "cortex-a12", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .D32,
- .Fpregs,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Aclass,
- .Armv7A,
- .AvoidPartialCpsr,
- .RetAddrStack,
- .Mp,
- .Trustzone,
- .Fp16,
- .Vfp4,
- .VmlxForwarding,
- .HwdivArm,
- .Hwdiv,
- .Virtualization,
- .A12,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA15, "cortex-a15", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .D32,
- .Fpregs,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Aclass,
- .Armv7A,
- .AvoidPartialCpsr,
- .VldnAlign,
- .DontWidenVmovs,
- .RetAddrStack,
- .Mp,
- .MuxedUnits,
- .SplatVfpNeon,
- .Trustzone,
- .Fp16,
- .Vfp4,
- .HwdivArm,
- .Hwdiv,
- .Virtualization,
- .A15,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA17, "cortex-a17", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .D32,
- .Fpregs,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Aclass,
- .Armv7A,
- .AvoidPartialCpsr,
- .RetAddrStack,
- .Mp,
- .Trustzone,
- .Fp16,
- .Vfp4,
- .VmlxForwarding,
- .HwdivArm,
- .Hwdiv,
- .Virtualization,
- .A17,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA32, "cortex-a32", &[_]FeatureType {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- .Armv8A,
- .Crypto,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA35, "cortex-a35", &[_]FeatureType {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- .Armv8A,
- .Crypto,
- .A35,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA5, "cortex-a5", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .D32,
- .Fpregs,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Aclass,
- .Armv7A,
- .RetAddrStack,
- .Slowfpvmlx,
- .Mp,
- .SlowFpBrcc,
- .Trustzone,
- .Fp16,
- .Vfp4,
- .VmlxForwarding,
- .A5,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA53, "cortex-a53", &[_]FeatureType {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- .Armv8A,
- .Crypto,
- .Fpao,
- .A53,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA55, "cortex-a55", &[_]FeatureType {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .Ras,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- .Armv82A,
- .Dotprod,
- .A55,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA57, "cortex-a57", &[_]FeatureType {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- .Armv8A,
- .AvoidPartialCpsr,
- .CheapPredicableCpsr,
- .Crypto,
- .Fpao,
- .A57,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA7, "cortex-a7", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .D32,
- .Fpregs,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Aclass,
- .Armv7A,
- .RetAddrStack,
- .Slowfpvmlx,
- .VmlxHazards,
- .Mp,
- .SlowFpBrcc,
- .Trustzone,
- .Fp16,
- .Vfp4,
- .VmlxForwarding,
- .HwdivArm,
- .Hwdiv,
- .Virtualization,
- .A7,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA72, "cortex-a72", &[_]FeatureType {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- .Armv8A,
- .Crypto,
- .A72,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA73, "cortex-a73", &[_]FeatureType {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- .Armv8A,
- .Crypto,
- .A73,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA75, "cortex-a75", &[_]FeatureType {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .Ras,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- .Armv82A,
- .Dotprod,
- .A75,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA76, "cortex-a76", &[_]FeatureType {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .Ras,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- .Armv82A,
- .Crypto,
- .Dotprod,
- .Fullfp16,
- .A76,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA76ae, "cortex-a76ae", &[_]FeatureType {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .Ras,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- .Armv82A,
- .Crypto,
- .Dotprod,
- .Fullfp16,
- .A76,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA8, "cortex-a8", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .D32,
- .Fpregs,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Aclass,
- .Armv7A,
- .RetAddrStack,
- .Slowfpvmlx,
- .VmlxHazards,
- .NonpipelinedVfp,
- .SlowFpBrcc,
- .Trustzone,
- .VmlxForwarding,
- .A8,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexA9, "cortex-a9", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .D32,
- .Fpregs,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Aclass,
- .Armv7A,
- .AvoidPartialCpsr,
- .VldnAlign,
- .ExpandFpMlx,
- .Fp16,
- .RetAddrStack,
- .VmlxHazards,
- .Mp,
- .MuxedUnits,
- .NeonFpmovs,
- .PreferVmovsr,
- .Trustzone,
- .VmlxForwarding,
- .A9,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexM0, "cortex-m0", &[_]FeatureType {
- .V4t,
- .ThumbMode,
- .Db,
- .StrictAlign,
- .Mclass,
- .Noarm,
- .Armv6M,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexM0plus, "cortex-m0plus", &[_]FeatureType {
- .V4t,
- .ThumbMode,
- .Db,
- .StrictAlign,
- .Mclass,
- .Noarm,
- .Armv6M,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexM1, "cortex-m1", &[_]FeatureType {
- .V4t,
- .ThumbMode,
- .Db,
- .StrictAlign,
- .Mclass,
- .Noarm,
- .Armv6M,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexM23, "cortex-m23", &[_]FeatureType {
- .V4t,
- .ThumbMode,
- .Msecext8,
- .V7clrex,
- .Db,
- .StrictAlign,
- .Mclass,
- .Noarm,
- .AcquireRelease,
- .Hwdiv,
- .Armv8Mbase,
- .NoMovt,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexM3, "cortex-m3", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .ThumbMode,
- .V7clrex,
- .Thumb2,
- .Db,
- .Mclass,
- .Noarm,
- .Hwdiv,
- .Armv7M,
- .NoBranchPredictor,
- .LoopAlign,
- .UseAa,
- .UseMisched,
- .M3,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexM33, "cortex-m33", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .ThumbMode,
- .Msecext8,
- .V7clrex,
- .Thumb2,
- .Db,
- .Mclass,
- .Noarm,
- .AcquireRelease,
- .Hwdiv,
- .Armv8Mmain,
- .Dsp,
- .Fpregs,
- .Fp16,
- .FpArmv8d16sp,
- .NoBranchPredictor,
- .Slowfpvmlx,
- .LoopAlign,
- .UseAa,
- .UseMisched,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexM35p, "cortex-m35p", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .ThumbMode,
- .Msecext8,
- .V7clrex,
- .Thumb2,
- .Db,
- .Mclass,
- .Noarm,
- .AcquireRelease,
- .Hwdiv,
- .Armv8Mmain,
- .Dsp,
- .Fpregs,
- .Fp16,
- .FpArmv8d16sp,
- .NoBranchPredictor,
- .Slowfpvmlx,
- .LoopAlign,
- .UseAa,
- .UseMisched,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexM4, "cortex-m4", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .ThumbMode,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Mclass,
- .Noarm,
- .Hwdiv,
- .Armv7eM,
- .NoBranchPredictor,
- .Slowfpvmlx,
- .LoopAlign,
- .UseAa,
- .UseMisched,
- .Fpregs,
- .Fp16,
- .Vfp4d16sp,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexM7, "cortex-m7", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .ThumbMode,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Mclass,
- .Noarm,
- .Hwdiv,
- .Armv7eM,
- .Fpregs,
- .Fp16,
- .FpArmv8d16,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexR4, "cortex-r4", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Hwdiv,
- .Rclass,
- .Armv7R,
- .AvoidPartialCpsr,
- .RetAddrStack,
- .R4,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexR4f, "cortex-r4f", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Hwdiv,
- .Rclass,
- .Armv7R,
- .AvoidPartialCpsr,
- .RetAddrStack,
- .Slowfpvmlx,
- .SlowFpBrcc,
- .Fpregs,
- .Vfp3d16,
- .R4,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexR5, "cortex-r5", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Hwdiv,
- .Rclass,
- .Armv7R,
- .AvoidPartialCpsr,
- .HwdivArm,
- .RetAddrStack,
- .Slowfpvmlx,
- .SlowFpBrcc,
- .Fpregs,
- .Vfp3d16,
- .R5,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexR52, "cortex-r52", &[_]FeatureType {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Crc,
- .Fpregs,
- .Mp,
- .Dfb,
- .Dsp,
- .Fp16,
- .V4t,
- .Db,
- .V7clrex,
- .Thumb2,
- .AcquireRelease,
- .Hwdiv,
- .Rclass,
- .Armv8R,
- .Fpao,
- .UseAa,
- .UseMisched,
- .R52,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexR7, "cortex-r7", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Hwdiv,
- .Rclass,
- .Armv7R,
- .AvoidPartialCpsr,
- .Fp16,
- .HwdivArm,
- .RetAddrStack,
- .Slowfpvmlx,
- .Mp,
- .SlowFpBrcc,
- .Fpregs,
- .Vfp3d16,
- .R7,
- }),
- CpuInfo(@This(), FeatureType).create(.CortexR8, "cortex-r8", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Hwdiv,
- .Rclass,
- .Armv7R,
- .AvoidPartialCpsr,
- .Fp16,
- .HwdivArm,
- .RetAddrStack,
- .Slowfpvmlx,
- .Mp,
- .SlowFpBrcc,
- .Fpregs,
- .Vfp3d16,
- }),
- CpuInfo(@This(), FeatureType).create(.Cyclone, "cyclone", &[_]FeatureType {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- .Armv8A,
- .AvoidMovsShop,
- .AvoidPartialCpsr,
- .Crypto,
- .RetAddrStack,
- .Slowfpvmlx,
- .Neonfp,
- .DisablePostraScheduler,
- .UseMisched,
- .Vfp4,
- .Zcz,
- .Swift,
- }),
- CpuInfo(@This(), FeatureType).create(.Ep9312, "ep9312", &[_]FeatureType {
- .V4t,
- .Armv4t,
- }),
- CpuInfo(@This(), FeatureType).create(.ExynosM1, "exynos-m1", &[_]FeatureType {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- .Armv8A,
- .RetAddrStack,
- .SlowVgetlni32,
- .WideStrideVfp,
- .SlowVdup32,
- .SlowFpBrcc,
- .ProfUnpr,
- .DontWidenVmovs,
- .Zcz,
- .FuseAes,
- .Slowfpvmlx,
- .UseAa,
- .FuseLiterals,
- .ExpandFpMlx,
- .Exynos,
- }),
- CpuInfo(@This(), FeatureType).create(.ExynosM2, "exynos-m2", &[_]FeatureType {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- .Armv8A,
- .RetAddrStack,
- .SlowVgetlni32,
- .WideStrideVfp,
- .SlowVdup32,
- .SlowFpBrcc,
- .ProfUnpr,
- .DontWidenVmovs,
- .Zcz,
- .FuseAes,
- .Slowfpvmlx,
- .UseAa,
- .FuseLiterals,
- .ExpandFpMlx,
- .Exynos,
- }),
- CpuInfo(@This(), FeatureType).create(.ExynosM3, "exynos-m3", &[_]FeatureType {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- .Armv8A,
- .RetAddrStack,
- .SlowVgetlni32,
- .WideStrideVfp,
- .SlowVdup32,
- .SlowFpBrcc,
- .ProfUnpr,
- .DontWidenVmovs,
- .Zcz,
- .FuseAes,
- .Slowfpvmlx,
- .UseAa,
- .FuseLiterals,
- .ExpandFpMlx,
- .Exynos,
- }),
- CpuInfo(@This(), FeatureType).create(.ExynosM4, "exynos-m4", &[_]FeatureType {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .Ras,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- .Armv82A,
- .Dotprod,
- .Fullfp16,
- .RetAddrStack,
- .SlowVgetlni32,
- .WideStrideVfp,
- .SlowVdup32,
- .SlowFpBrcc,
- .ProfUnpr,
- .DontWidenVmovs,
- .Zcz,
- .FuseAes,
- .Slowfpvmlx,
- .UseAa,
- .FuseLiterals,
- .ExpandFpMlx,
- .Exynos,
- }),
- CpuInfo(@This(), FeatureType).create(.ExynosM5, "exynos-m5", &[_]FeatureType {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .Ras,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- .Armv82A,
- .Dotprod,
- .Fullfp16,
- .RetAddrStack,
- .SlowVgetlni32,
- .WideStrideVfp,
- .SlowVdup32,
- .SlowFpBrcc,
- .ProfUnpr,
- .DontWidenVmovs,
- .Zcz,
- .FuseAes,
- .Slowfpvmlx,
- .UseAa,
- .FuseLiterals,
- .ExpandFpMlx,
- .Exynos,
- }),
- CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.Iwmmxt, "iwmmxt", &[_]FeatureType {
- .V4t,
- .Armv5te,
- }),
- CpuInfo(@This(), FeatureType).create(.Krait, "krait", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .D32,
- .Fpregs,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Aclass,
- .Armv7A,
- .AvoidPartialCpsr,
- .VldnAlign,
- .Fp16,
- .HwdivArm,
- .Hwdiv,
- .RetAddrStack,
- .MuxedUnits,
- .Vfp4,
- .VmlxForwarding,
- .Krait,
- }),
- CpuInfo(@This(), FeatureType).create(.Kryo, "kryo", &[_]FeatureType {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- .Armv8A,
- .Crypto,
- .Kryo,
- }),
- CpuInfo(@This(), FeatureType).create(.Mpcore, "mpcore", &[_]FeatureType {
- .V4t,
- .Armv6k,
- .Slowfpvmlx,
- .Fpregs,
- .Vfp2,
- }),
- CpuInfo(@This(), FeatureType).create(.Mpcorenovfp, "mpcorenovfp", &[_]FeatureType {
- .V4t,
- .Armv6k,
- }),
- CpuInfo(@This(), FeatureType).create(.NeoverseN1, "neoverse-n1", &[_]FeatureType {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .Ras,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- .Armv82A,
- .Crypto,
- .Dotprod,
- }),
- CpuInfo(@This(), FeatureType).create(.Sc000, "sc000", &[_]FeatureType {
- .V4t,
- .ThumbMode,
- .Db,
- .StrictAlign,
- .Mclass,
- .Noarm,
- .Armv6M,
- }),
- CpuInfo(@This(), FeatureType).create(.Sc300, "sc300", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .ThumbMode,
- .V7clrex,
- .Thumb2,
- .Db,
- .Mclass,
- .Noarm,
- .Hwdiv,
- .Armv7M,
- .NoBranchPredictor,
- .UseAa,
- .UseMisched,
- .M3,
- }),
- CpuInfo(@This(), FeatureType).create(.Strongarm, "strongarm", &[_]FeatureType {
- .Armv4,
- }),
- CpuInfo(@This(), FeatureType).create(.Strongarm110, "strongarm110", &[_]FeatureType {
- .Armv4,
- }),
- CpuInfo(@This(), FeatureType).create(.Strongarm1100, "strongarm1100", &[_]FeatureType {
- .Armv4,
- }),
- CpuInfo(@This(), FeatureType).create(.Strongarm1110, "strongarm1110", &[_]FeatureType {
- .Armv4,
- }),
- CpuInfo(@This(), FeatureType).create(.Swift, "swift", &[_]FeatureType {
- .Perfmon,
- .V4t,
- .D32,
- .Fpregs,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Aclass,
- .Armv7A,
- .AvoidMovsShop,
- .AvoidPartialCpsr,
- .HwdivArm,
- .Hwdiv,
- .RetAddrStack,
- .Slowfpvmlx,
- .VmlxHazards,
- .Mp,
- .Neonfp,
- .DisablePostraScheduler,
- .PreferIshst,
- .ProfUnpr,
- .SlowLoadDSubreg,
- .SlowOddReg,
- .SlowVdup32,
- .SlowVgetlni32,
- .UseMisched,
- .WideStrideVfp,
- .Fp16,
- .Vfp4,
- .Swift,
- }),
- CpuInfo(@This(), FeatureType).create(.Xscale, "xscale", &[_]FeatureType {
- .V4t,
- .Armv5te,
- }),
- };
-};
lib/std/target/cpu/AvrCpu.zig
@@ -1,3863 +0,0 @@
-const feature = @import("std").target.feature;
-const CpuInfo = @import("std").target.cpu.CpuInfo;
-
-pub const AvrCpu = enum {
- At43usb320,
- At43usb355,
- At76c711,
- At86rf401,
- At90c8534,
- At90can128,
- At90can32,
- At90can64,
- At90pwm1,
- At90pwm161,
- At90pwm2,
- At90pwm216,
- At90pwm2b,
- At90pwm3,
- At90pwm316,
- At90pwm3b,
- At90pwm81,
- At90s1200,
- At90s2313,
- At90s2323,
- At90s2333,
- At90s2343,
- At90s4414,
- At90s4433,
- At90s4434,
- At90s8515,
- At90s8535,
- At90scr100,
- At90usb1286,
- At90usb1287,
- At90usb162,
- At90usb646,
- At90usb647,
- At90usb82,
- At94k,
- Ata5272,
- Ata5505,
- Ata5790,
- Ata5795,
- Ata6285,
- Ata6286,
- Ata6289,
- Atmega103,
- Atmega128,
- Atmega1280,
- Atmega1281,
- Atmega1284,
- Atmega1284p,
- Atmega1284rfr2,
- Atmega128a,
- Atmega128rfa1,
- Atmega128rfr2,
- Atmega16,
- Atmega161,
- Atmega162,
- Atmega163,
- Atmega164a,
- Atmega164p,
- Atmega164pa,
- Atmega165,
- Atmega165a,
- Atmega165p,
- Atmega165pa,
- Atmega168,
- Atmega168a,
- Atmega168p,
- Atmega168pa,
- Atmega169,
- Atmega169a,
- Atmega169p,
- Atmega169pa,
- Atmega16a,
- Atmega16hva,
- Atmega16hva2,
- Atmega16hvb,
- Atmega16hvbrevb,
- Atmega16m1,
- Atmega16u2,
- Atmega16u4,
- Atmega2560,
- Atmega2561,
- Atmega2564rfr2,
- Atmega256rfr2,
- Atmega32,
- Atmega323,
- Atmega324a,
- Atmega324p,
- Atmega324pa,
- Atmega325,
- Atmega3250,
- Atmega3250a,
- Atmega3250p,
- Atmega3250pa,
- Atmega325a,
- Atmega325p,
- Atmega325pa,
- Atmega328,
- Atmega328p,
- Atmega329,
- Atmega3290,
- Atmega3290a,
- Atmega3290p,
- Atmega3290pa,
- Atmega329a,
- Atmega329p,
- Atmega329pa,
- Atmega32a,
- Atmega32c1,
- Atmega32hvb,
- Atmega32hvbrevb,
- Atmega32m1,
- Atmega32u2,
- Atmega32u4,
- Atmega32u6,
- Atmega406,
- Atmega48,
- Atmega48a,
- Atmega48p,
- Atmega48pa,
- Atmega64,
- Atmega640,
- Atmega644,
- Atmega644a,
- Atmega644p,
- Atmega644pa,
- Atmega644rfr2,
- Atmega645,
- Atmega6450,
- Atmega6450a,
- Atmega6450p,
- Atmega645a,
- Atmega645p,
- Atmega649,
- Atmega6490,
- Atmega6490a,
- Atmega6490p,
- Atmega649a,
- Atmega649p,
- Atmega64a,
- Atmega64c1,
- Atmega64hve,
- Atmega64m1,
- Atmega64rfr2,
- Atmega8,
- Atmega8515,
- Atmega8535,
- Atmega88,
- Atmega88a,
- Atmega88p,
- Atmega88pa,
- Atmega8a,
- Atmega8hva,
- Atmega8u2,
- Attiny10,
- Attiny102,
- Attiny104,
- Attiny11,
- Attiny12,
- Attiny13,
- Attiny13a,
- Attiny15,
- Attiny1634,
- Attiny167,
- Attiny20,
- Attiny22,
- Attiny2313,
- Attiny2313a,
- Attiny24,
- Attiny24a,
- Attiny25,
- Attiny26,
- Attiny261,
- Attiny261a,
- Attiny28,
- Attiny4,
- Attiny40,
- Attiny4313,
- Attiny43u,
- Attiny44,
- Attiny44a,
- Attiny45,
- Attiny461,
- Attiny461a,
- Attiny48,
- Attiny5,
- Attiny828,
- Attiny84,
- Attiny84a,
- Attiny85,
- Attiny861,
- Attiny861a,
- Attiny87,
- Attiny88,
- Attiny9,
- Atxmega128a1,
- Atxmega128a1u,
- Atxmega128a3,
- Atxmega128a3u,
- Atxmega128a4u,
- Atxmega128b1,
- Atxmega128b3,
- Atxmega128c3,
- Atxmega128d3,
- Atxmega128d4,
- Atxmega16a4,
- Atxmega16a4u,
- Atxmega16c4,
- Atxmega16d4,
- Atxmega16e5,
- Atxmega192a3,
- Atxmega192a3u,
- Atxmega192c3,
- Atxmega192d3,
- Atxmega256a3,
- Atxmega256a3b,
- Atxmega256a3bu,
- Atxmega256a3u,
- Atxmega256c3,
- Atxmega256d3,
- Atxmega32a4,
- Atxmega32a4u,
- Atxmega32c4,
- Atxmega32d4,
- Atxmega32e5,
- Atxmega32x1,
- Atxmega384c3,
- Atxmega384d3,
- Atxmega64a1,
- Atxmega64a1u,
- Atxmega64a3,
- Atxmega64a3u,
- Atxmega64a4u,
- Atxmega64b1,
- Atxmega64b3,
- Atxmega64c3,
- Atxmega64d3,
- Atxmega64d4,
- Atxmega8e5,
- Avr1,
- Avr2,
- Avr25,
- Avr3,
- Avr31,
- Avr35,
- Avr4,
- Avr5,
- Avr51,
- Avr6,
- Avrtiny,
- Avrxmega1,
- Avrxmega2,
- Avrxmega3,
- Avrxmega4,
- Avrxmega5,
- Avrxmega6,
- Avrxmega7,
- M3000,
-
- const FeatureType = feature.AvrFeature;
-
- pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
- return cpu_infos[@enumToInt(self)];
- }
-
- pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
- CpuInfo(@This(), FeatureType).create(.At43usb320, "at43usb320", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Ijmpcall,
- .Avr31,
- }),
- CpuInfo(@This(), FeatureType).create(.At43usb355, "at43usb355", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Ijmpcall,
- .Avr3,
- }),
- CpuInfo(@This(), FeatureType).create(.At76c711, "at76c711", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Ijmpcall,
- .Avr3,
- }),
- CpuInfo(@This(), FeatureType).create(.At86rf401, "at86rf401", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Ijmpcall,
- .Avr2,
- .Lpmx,
- .Movw,
- }),
- CpuInfo(@This(), FeatureType).create(.At90c8534, "at90c8534", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Ijmpcall,
- .Avr2,
- }),
- CpuInfo(@This(), FeatureType).create(.At90can128, "at90can128", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr51,
- }),
- CpuInfo(@This(), FeatureType).create(.At90can32, "at90can32", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.At90can64, "at90can64", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.At90pwm1, "at90pwm1", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.At90pwm161, "at90pwm161", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.At90pwm2, "at90pwm2", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.At90pwm216, "at90pwm216", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.At90pwm2b, "at90pwm2b", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.At90pwm3, "at90pwm3", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.At90pwm316, "at90pwm316", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.At90pwm3b, "at90pwm3b", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.At90pwm81, "at90pwm81", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.At90s1200, "at90s1200", &[_]FeatureType {
- .Avr0,
- }),
- CpuInfo(@This(), FeatureType).create(.At90s2313, "at90s2313", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Ijmpcall,
- .Avr2,
- }),
- CpuInfo(@This(), FeatureType).create(.At90s2323, "at90s2323", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Ijmpcall,
- .Avr2,
- }),
- CpuInfo(@This(), FeatureType).create(.At90s2333, "at90s2333", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Ijmpcall,
- .Avr2,
- }),
- CpuInfo(@This(), FeatureType).create(.At90s2343, "at90s2343", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Ijmpcall,
- .Avr2,
- }),
- CpuInfo(@This(), FeatureType).create(.At90s4414, "at90s4414", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Ijmpcall,
- .Avr2,
- }),
- CpuInfo(@This(), FeatureType).create(.At90s4433, "at90s4433", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Ijmpcall,
- .Avr2,
- }),
- CpuInfo(@This(), FeatureType).create(.At90s4434, "at90s4434", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Ijmpcall,
- .Avr2,
- }),
- CpuInfo(@This(), FeatureType).create(.At90s8515, "at90s8515", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Ijmpcall,
- .Avr2,
- }),
- CpuInfo(@This(), FeatureType).create(.At90s8535, "at90s8535", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Ijmpcall,
- .Avr2,
- }),
- CpuInfo(@This(), FeatureType).create(.At90scr100, "at90scr100", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.At90usb1286, "at90usb1286", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr51,
- }),
- CpuInfo(@This(), FeatureType).create(.At90usb1287, "at90usb1287", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr51,
- }),
- CpuInfo(@This(), FeatureType).create(.At90usb162, "at90usb162", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr35,
- }),
- CpuInfo(@This(), FeatureType).create(.At90usb646, "at90usb646", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.At90usb647, "at90usb647", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.At90usb82, "at90usb82", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr35,
- }),
- CpuInfo(@This(), FeatureType).create(.At94k, "at94k", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Ijmpcall,
- .Avr3,
- .Lpmx,
- .Movw,
- .Mul,
- }),
- CpuInfo(@This(), FeatureType).create(.Ata5272, "ata5272", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Ata5505, "ata5505", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr35,
- }),
- CpuInfo(@This(), FeatureType).create(.Ata5790, "ata5790", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Ata5795, "ata5795", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Ata6285, "ata6285", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.Ata6286, "ata6286", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.Ata6289, "ata6289", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega103, "atmega103", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Ijmpcall,
- .Avr31,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega128, "atmega128", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr51,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega1280, "atmega1280", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr51,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega1281, "atmega1281", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr51,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega1284, "atmega1284", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr51,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega1284p, "atmega1284p", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr51,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega1284rfr2, "atmega1284rfr2", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr51,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega128a, "atmega128a", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr51,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega128rfa1, "atmega128rfa1", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr51,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega128rfr2, "atmega128rfr2", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr51,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega16, "atmega16", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega161, "atmega161", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Ijmpcall,
- .Avr3,
- .Lpmx,
- .Movw,
- .Mul,
- .Spm,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega162, "atmega162", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega163, "atmega163", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Ijmpcall,
- .Avr3,
- .Lpmx,
- .Movw,
- .Mul,
- .Spm,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega164a, "atmega164a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega164p, "atmega164p", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega164pa, "atmega164pa", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega165, "atmega165", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega165a, "atmega165a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega165p, "atmega165p", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega165pa, "atmega165pa", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega168, "atmega168", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega168a, "atmega168a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega168p, "atmega168p", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega168pa, "atmega168pa", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega169, "atmega169", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega169a, "atmega169a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega169p, "atmega169p", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega169pa, "atmega169pa", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega16a, "atmega16a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega16hva, "atmega16hva", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega16hva2, "atmega16hva2", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega16hvb, "atmega16hvb", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega16hvbrevb, "atmega16hvbrevb", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega16m1, "atmega16m1", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega16u2, "atmega16u2", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr35,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega16u4, "atmega16u4", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega2560, "atmega2560", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr6,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega2561, "atmega2561", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr6,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega2564rfr2, "atmega2564rfr2", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr6,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega256rfr2, "atmega256rfr2", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr6,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega32, "atmega32", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega323, "atmega323", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega324a, "atmega324a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega324p, "atmega324p", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega324pa, "atmega324pa", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega325, "atmega325", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega3250, "atmega3250", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega3250a, "atmega3250a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega3250p, "atmega3250p", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega3250pa, "atmega3250pa", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega325a, "atmega325a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega325p, "atmega325p", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega325pa, "atmega325pa", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega328, "atmega328", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega328p, "atmega328p", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega329, "atmega329", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega3290, "atmega3290", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega3290a, "atmega3290a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega3290p, "atmega3290p", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega3290pa, "atmega3290pa", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega329a, "atmega329a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega329p, "atmega329p", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega329pa, "atmega329pa", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega32a, "atmega32a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega32c1, "atmega32c1", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega32hvb, "atmega32hvb", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega32hvbrevb, "atmega32hvbrevb", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega32m1, "atmega32m1", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega32u2, "atmega32u2", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr35,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega32u4, "atmega32u4", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega32u6, "atmega32u6", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega406, "atmega406", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega48, "atmega48", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega48a, "atmega48a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega48p, "atmega48p", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega48pa, "atmega48pa", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega64, "atmega64", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega640, "atmega640", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega644, "atmega644", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega644a, "atmega644a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega644p, "atmega644p", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega644pa, "atmega644pa", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega644rfr2, "atmega644rfr2", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega645, "atmega645", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega6450, "atmega6450", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega6450a, "atmega6450a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega6450p, "atmega6450p", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega645a, "atmega645a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega645p, "atmega645p", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega649, "atmega649", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega6490, "atmega6490", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega6490a, "atmega6490a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega6490p, "atmega6490p", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega649a, "atmega649a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega649p, "atmega649p", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega64a, "atmega64a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega64c1, "atmega64c1", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega64hve, "atmega64hve", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega64m1, "atmega64m1", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega64rfr2, "atmega64rfr2", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega8, "atmega8", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega8515, "atmega8515", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Ijmpcall,
- .Avr2,
- .Lpmx,
- .Movw,
- .Mul,
- .Spm,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega8535, "atmega8535", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Ijmpcall,
- .Avr2,
- .Lpmx,
- .Movw,
- .Mul,
- .Spm,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega88, "atmega88", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega88a, "atmega88a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega88p, "atmega88p", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega88pa, "atmega88pa", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega8a, "atmega8a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega8hva, "atmega8hva", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.Atmega8u2, "atmega8u2", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr35,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny10, "attiny10", &[_]FeatureType {
- .Avr0,
- .Sram,
- .Break,
- .Tinyencoding,
- .Avrtiny,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny102, "attiny102", &[_]FeatureType {
- .Avr0,
- .Sram,
- .Break,
- .Tinyencoding,
- .Avrtiny,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny104, "attiny104", &[_]FeatureType {
- .Avr0,
- .Sram,
- .Break,
- .Tinyencoding,
- .Avrtiny,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny11, "attiny11", &[_]FeatureType {
- .Avr0,
- .Lpm,
- .Avr1,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny12, "attiny12", &[_]FeatureType {
- .Avr0,
- .Lpm,
- .Avr1,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny13, "attiny13", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny13a, "attiny13a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny15, "attiny15", &[_]FeatureType {
- .Avr0,
- .Lpm,
- .Avr1,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny1634, "attiny1634", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr35,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny167, "attiny167", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr35,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny20, "attiny20", &[_]FeatureType {
- .Avr0,
- .Sram,
- .Break,
- .Tinyencoding,
- .Avrtiny,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny22, "attiny22", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Ijmpcall,
- .Avr2,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny2313, "attiny2313", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny2313a, "attiny2313a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny24, "attiny24", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny24a, "attiny24a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny25, "attiny25", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny26, "attiny26", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Ijmpcall,
- .Avr2,
- .Lpmx,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny261, "attiny261", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny261a, "attiny261a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny28, "attiny28", &[_]FeatureType {
- .Avr0,
- .Lpm,
- .Avr1,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny4, "attiny4", &[_]FeatureType {
- .Avr0,
- .Sram,
- .Break,
- .Tinyencoding,
- .Avrtiny,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny40, "attiny40", &[_]FeatureType {
- .Avr0,
- .Sram,
- .Break,
- .Tinyencoding,
- .Avrtiny,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny4313, "attiny4313", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny43u, "attiny43u", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny44, "attiny44", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny44a, "attiny44a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny45, "attiny45", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny461, "attiny461", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny461a, "attiny461a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny48, "attiny48", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny5, "attiny5", &[_]FeatureType {
- .Avr0,
- .Sram,
- .Break,
- .Tinyencoding,
- .Avrtiny,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny828, "attiny828", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny84, "attiny84", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny84a, "attiny84a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny85, "attiny85", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny861, "attiny861", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny861a, "attiny861a", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny87, "attiny87", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny88, "attiny88", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Attiny9, "attiny9", &[_]FeatureType {
- .Avr0,
- .Sram,
- .Break,
- .Tinyencoding,
- .Avrtiny,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega128a1, "atxmega128a1", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega128a1u, "atxmega128a1u", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega128a3, "atxmega128a3", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega128a3u, "atxmega128a3u", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega128a4u, "atxmega128a4u", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega128b1, "atxmega128b1", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega128b3, "atxmega128b3", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega128c3, "atxmega128c3", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega128d3, "atxmega128d3", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega128d4, "atxmega128d4", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega16a4, "atxmega16a4", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega16a4u, "atxmega16a4u", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega16c4, "atxmega16c4", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega16d4, "atxmega16d4", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega16e5, "atxmega16e5", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega192a3, "atxmega192a3", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega192a3u, "atxmega192a3u", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega192c3, "atxmega192c3", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega192d3, "atxmega192d3", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega256a3, "atxmega256a3", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega256a3b, "atxmega256a3b", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega256a3bu, "atxmega256a3bu", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega256a3u, "atxmega256a3u", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega256c3, "atxmega256c3", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega256d3, "atxmega256d3", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega32a4, "atxmega32a4", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega32a4u, "atxmega32a4u", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega32c4, "atxmega32c4", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega32d4, "atxmega32d4", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega32e5, "atxmega32e5", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega32x1, "atxmega32x1", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega384c3, "atxmega384c3", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega384d3, "atxmega384d3", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega64a1, "atxmega64a1", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega64a1u, "atxmega64a1u", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega64a3, "atxmega64a3", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega64a3u, "atxmega64a3u", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega64a4u, "atxmega64a4u", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega64b1, "atxmega64b1", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega64b3, "atxmega64b3", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega64c3, "atxmega64c3", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmegau,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega64d3, "atxmega64d3", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega64d4, "atxmega64d4", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Atxmega8e5, "atxmega8e5", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Avr1, "avr1", &[_]FeatureType {
- .Avr0,
- .Lpm,
- .Avr1,
- }),
- CpuInfo(@This(), FeatureType).create(.Avr2, "avr2", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Ijmpcall,
- .Avr2,
- }),
- CpuInfo(@This(), FeatureType).create(.Avr25, "avr25", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr25,
- }),
- CpuInfo(@This(), FeatureType).create(.Avr3, "avr3", &[_]FeatureType {
- .Lpm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Ijmpcall,
- .Avr3,
- }),
- CpuInfo(@This(), FeatureType).create(.Avr31, "avr31", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Ijmpcall,
- .Avr31,
- }),
- CpuInfo(@This(), FeatureType).create(.Avr35, "avr35", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr35,
- }),
- CpuInfo(@This(), FeatureType).create(.Avr4, "avr4", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr4,
- }),
- CpuInfo(@This(), FeatureType).create(.Avr5, "avr5", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- CpuInfo(@This(), FeatureType).create(.Avr51, "avr51", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr51,
- }),
- CpuInfo(@This(), FeatureType).create(.Avr6, "avr6", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr6,
- }),
- CpuInfo(@This(), FeatureType).create(.Avrtiny, "avrtiny", &[_]FeatureType {
- .Avr0,
- .Sram,
- .Break,
- .Tinyencoding,
- .Avrtiny,
- }),
- CpuInfo(@This(), FeatureType).create(.Avrxmega1, "avrxmega1", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Avrxmega2, "avrxmega2", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Avrxmega3, "avrxmega3", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Avrxmega4, "avrxmega4", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Avrxmega5, "avrxmega5", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Avrxmega6, "avrxmega6", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.Avrxmega7, "avrxmega7", &[_]FeatureType {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- .Xmega,
- }),
- CpuInfo(@This(), FeatureType).create(.M3000, "m3000", &[_]FeatureType {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- .Avr5,
- }),
- };
-};
lib/std/target/cpu/BpfCpu.zig
@@ -1,29 +0,0 @@
-const feature = @import("std").target.feature;
-const CpuInfo = @import("std").target.cpu.CpuInfo;
-
-pub const BpfCpu = enum {
- Generic,
- Probe,
- V1,
- V2,
- V3,
-
- const FeatureType = feature.BpfFeature;
-
- pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
- return cpu_infos[@enumToInt(self)];
- }
-
- pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
- CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.Probe, "probe", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.V1, "v1", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.V2, "v2", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.V3, "v3", &[_]FeatureType {
- }),
- };
-};
lib/std/target/cpu/empty.zig
@@ -1,6 +0,0 @@
-const feature = @import("std").target.feature;
-const CpuInfo = @import("std").target.cpu.CpuInfo;
-
-pub const EmptyCpu = struct {
- pub const cpu_infos = [0]CpuInfo(@This(), feature.EmptyFeature) {};
-};
lib/std/target/cpu/HexagonCpu.zig
@@ -1,103 +0,0 @@
-const feature = @import("std").target.feature;
-const CpuInfo = @import("std").target.cpu.CpuInfo;
-
-pub const HexagonCpu = enum {
- Generic,
- Hexagonv5,
- Hexagonv55,
- Hexagonv60,
- Hexagonv62,
- Hexagonv65,
- Hexagonv66,
-
- const FeatureType = feature.HexagonFeature;
-
- pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
- return cpu_infos[@enumToInt(self)];
- }
-
- pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
- CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
- .V5,
- .V55,
- .V60,
- .Duplex,
- .Memops,
- .Packets,
- .Nvj,
- .Nvs,
- .SmallData,
- }),
- CpuInfo(@This(), FeatureType).create(.Hexagonv5, "hexagonv5", &[_]FeatureType {
- .V5,
- .Duplex,
- .Memops,
- .Packets,
- .Nvj,
- .Nvs,
- .SmallData,
- }),
- CpuInfo(@This(), FeatureType).create(.Hexagonv55, "hexagonv55", &[_]FeatureType {
- .V5,
- .V55,
- .Duplex,
- .Memops,
- .Packets,
- .Nvj,
- .Nvs,
- .SmallData,
- }),
- CpuInfo(@This(), FeatureType).create(.Hexagonv60, "hexagonv60", &[_]FeatureType {
- .V5,
- .V55,
- .V60,
- .Duplex,
- .Memops,
- .Packets,
- .Nvj,
- .Nvs,
- .SmallData,
- }),
- CpuInfo(@This(), FeatureType).create(.Hexagonv62, "hexagonv62", &[_]FeatureType {
- .V5,
- .V55,
- .V60,
- .V62,
- .Duplex,
- .Memops,
- .Packets,
- .Nvj,
- .Nvs,
- .SmallData,
- }),
- CpuInfo(@This(), FeatureType).create(.Hexagonv65, "hexagonv65", &[_]FeatureType {
- .V5,
- .V55,
- .V60,
- .V62,
- .V65,
- .Duplex,
- .Mem_noshuf,
- .Memops,
- .Packets,
- .Nvj,
- .Nvs,
- .SmallData,
- }),
- CpuInfo(@This(), FeatureType).create(.Hexagonv66, "hexagonv66", &[_]FeatureType {
- .V5,
- .V55,
- .V60,
- .V62,
- .V65,
- .V66,
- .Duplex,
- .Mem_noshuf,
- .Memops,
- .Packets,
- .Nvj,
- .Nvs,
- .SmallData,
- }),
- };
-};
lib/std/target/cpu/MipsCpu.zig
@@ -1,190 +0,0 @@
-const feature = @import("std").target.feature;
-const CpuInfo = @import("std").target.cpu.CpuInfo;
-
-pub const MipsCpu = enum {
- Mips1,
- Mips2,
- Mips3,
- Mips32,
- Mips32r2,
- Mips32r3,
- Mips32r5,
- Mips32r6,
- Mips4,
- Mips5,
- Mips64,
- Mips64r2,
- Mips64r3,
- Mips64r5,
- Mips64r6,
- Octeon,
- P5600,
-
- const FeatureType = feature.MipsFeature;
-
- pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
- return cpu_infos[@enumToInt(self)];
- }
-
- pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
- CpuInfo(@This(), FeatureType).create(.Mips1, "mips1", &[_]FeatureType {
- .Mips1,
- }),
- CpuInfo(@This(), FeatureType).create(.Mips2, "mips2", &[_]FeatureType {
- .Mips1,
- .Mips2,
- }),
- CpuInfo(@This(), FeatureType).create(.Mips3, "mips3", &[_]FeatureType {
- .Mips3_32r2,
- .Fp64,
- .Gp64,
- .Mips1,
- .Mips3_32,
- .Mips3,
- }),
- CpuInfo(@This(), FeatureType).create(.Mips32, "mips32", &[_]FeatureType {
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- .Mips32,
- }),
- CpuInfo(@This(), FeatureType).create(.Mips32r2, "mips32r2", &[_]FeatureType {
- .Mips5_32r2,
- .Mips4_32r2,
- .Mips3_32r2,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- .Mips32r2,
- }),
- CpuInfo(@This(), FeatureType).create(.Mips32r3, "mips32r3", &[_]FeatureType {
- .Mips5_32r2,
- .Mips3_32r2,
- .Mips4_32r2,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- .Mips32r3,
- }),
- CpuInfo(@This(), FeatureType).create(.Mips32r5, "mips32r5", &[_]FeatureType {
- .Mips5_32r2,
- .Mips3_32r2,
- .Mips4_32r2,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- .Mips32r5,
- }),
- CpuInfo(@This(), FeatureType).create(.Mips32r6, "mips32r6", &[_]FeatureType {
- .Mips5_32r2,
- .Mips3_32r2,
- .Mips4_32r2,
- .Abs2008,
- .Nan2008,
- .Fp64,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- .Mips32r6,
- }),
- CpuInfo(@This(), FeatureType).create(.Mips4, "mips4", &[_]FeatureType {
- .Mips3_32r2,
- .Mips4_32r2,
- .Fp64,
- .Gp64,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- .Mips4,
- }),
- CpuInfo(@This(), FeatureType).create(.Mips5, "mips5", &[_]FeatureType {
- .Mips5_32r2,
- .Mips4_32r2,
- .Mips3_32r2,
- .Gp64,
- .Fp64,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- .Mips5,
- }),
- CpuInfo(@This(), FeatureType).create(.Mips64, "mips64", &[_]FeatureType {
- .Mips5_32r2,
- .Mips3_32r2,
- .Mips4_32r2,
- .Gp64,
- .Fp64,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- .Mips64,
- }),
- CpuInfo(@This(), FeatureType).create(.Mips64r2, "mips64r2", &[_]FeatureType {
- .Mips5_32r2,
- .Mips3_32r2,
- .Mips4_32r2,
- .Gp64,
- .Fp64,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- .Mips64r2,
- }),
- CpuInfo(@This(), FeatureType).create(.Mips64r3, "mips64r3", &[_]FeatureType {
- .Mips5_32r2,
- .Mips3_32r2,
- .Mips4_32r2,
- .Gp64,
- .Fp64,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- .Mips64r3,
- }),
- CpuInfo(@This(), FeatureType).create(.Mips64r5, "mips64r5", &[_]FeatureType {
- .Mips5_32r2,
- .Mips3_32r2,
- .Mips4_32r2,
- .Gp64,
- .Fp64,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- .Mips64r5,
- }),
- CpuInfo(@This(), FeatureType).create(.Mips64r6, "mips64r6", &[_]FeatureType {
- .Mips5_32r2,
- .Mips3_32r2,
- .Nan2008,
- .Abs2008,
- .Mips4_32r2,
- .Fp64,
- .Gp64,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- .Mips64r6,
- }),
- CpuInfo(@This(), FeatureType).create(.Octeon, "octeon", &[_]FeatureType {
- .Mips5_32r2,
- .Mips3_32r2,
- .Mips4_32r2,
- .Gp64,
- .Fp64,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- .Cnmips,
- .Mips64r2,
- }),
- CpuInfo(@This(), FeatureType).create(.P5600, "p5600", &[_]FeatureType {
- .Mips5_32r2,
- .Mips3_32r2,
- .Mips4_32r2,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- .P5600,
- }),
- };
-};
lib/std/target/cpu/Msp430Cpu.zig
@@ -1,24 +0,0 @@
-const feature = @import("std").target.feature;
-const CpuInfo = @import("std").target.cpu.CpuInfo;
-
-pub const Msp430Cpu = enum {
- Generic,
- Msp430,
- Msp430x,
-
- const FeatureType = feature.Msp430Feature;
-
- pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
- return cpu_infos[@enumToInt(self)];
- }
-
- pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
- CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.Msp430, "msp430", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.Msp430x, "msp430x", &[_]FeatureType {
- .Ext,
- }),
- };
-};
lib/std/target/cpu/NvptxCpu.zig
@@ -1,85 +0,0 @@
-const feature = @import("std").target.feature;
-const CpuInfo = @import("std").target.cpu.CpuInfo;
-
-pub const NvptxCpu = enum {
- Sm_20,
- Sm_21,
- Sm_30,
- Sm_32,
- Sm_35,
- Sm_37,
- Sm_50,
- Sm_52,
- Sm_53,
- Sm_60,
- Sm_61,
- Sm_62,
- Sm_70,
- Sm_72,
- Sm_75,
-
- const FeatureType = feature.NvptxFeature;
-
- pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
- return cpu_infos[@enumToInt(self)];
- }
-
- pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
- CpuInfo(@This(), FeatureType).create(.Sm_20, "sm_20", &[_]FeatureType {
- .Sm_20,
- }),
- CpuInfo(@This(), FeatureType).create(.Sm_21, "sm_21", &[_]FeatureType {
- .Sm_21,
- }),
- CpuInfo(@This(), FeatureType).create(.Sm_30, "sm_30", &[_]FeatureType {
- .Sm_30,
- }),
- CpuInfo(@This(), FeatureType).create(.Sm_32, "sm_32", &[_]FeatureType {
- .Ptx40,
- .Sm_32,
- }),
- CpuInfo(@This(), FeatureType).create(.Sm_35, "sm_35", &[_]FeatureType {
- .Sm_35,
- }),
- CpuInfo(@This(), FeatureType).create(.Sm_37, "sm_37", &[_]FeatureType {
- .Ptx41,
- .Sm_37,
- }),
- CpuInfo(@This(), FeatureType).create(.Sm_50, "sm_50", &[_]FeatureType {
- .Ptx40,
- .Sm_50,
- }),
- CpuInfo(@This(), FeatureType).create(.Sm_52, "sm_52", &[_]FeatureType {
- .Ptx41,
- .Sm_52,
- }),
- CpuInfo(@This(), FeatureType).create(.Sm_53, "sm_53", &[_]FeatureType {
- .Ptx42,
- .Sm_53,
- }),
- CpuInfo(@This(), FeatureType).create(.Sm_60, "sm_60", &[_]FeatureType {
- .Ptx50,
- .Sm_60,
- }),
- CpuInfo(@This(), FeatureType).create(.Sm_61, "sm_61", &[_]FeatureType {
- .Ptx50,
- .Sm_61,
- }),
- CpuInfo(@This(), FeatureType).create(.Sm_62, "sm_62", &[_]FeatureType {
- .Ptx50,
- .Sm_62,
- }),
- CpuInfo(@This(), FeatureType).create(.Sm_70, "sm_70", &[_]FeatureType {
- .Ptx60,
- .Sm_70,
- }),
- CpuInfo(@This(), FeatureType).create(.Sm_72, "sm_72", &[_]FeatureType {
- .Ptx61,
- .Sm_72,
- }),
- CpuInfo(@This(), FeatureType).create(.Sm_75, "sm_75", &[_]FeatureType {
- .Ptx63,
- .Sm_75,
- }),
- };
-};
lib/std/target/cpu/PowerPcCpu.zig
@@ -1,451 +0,0 @@
-const feature = @import("std").target.feature;
-const CpuInfo = @import("std").target.cpu.CpuInfo;
-
-pub const PowerPcCpu = enum {
- Cpu440,
- Cpu450,
- Cpu601,
- Cpu602,
- Cpu603,
- E603,
- Ev603,
- Cpu604,
- E604,
- Cpu620,
- Cpu7400,
- Cpu7450,
- Cpu750,
- Cpu970,
- A2,
- A2q,
- E500,
- E500mc,
- E5500,
- G3,
- G4,
- G4plus,
- G5,
- Generic,
- Ppc,
- Ppc32,
- Ppc64,
- Ppc64le,
- Pwr3,
- Pwr4,
- Pwr5,
- Pwr5x,
- Pwr6,
- Pwr6x,
- Pwr7,
- Pwr8,
- Pwr9,
-
- const FeatureType = feature.PowerPcFeature;
-
- pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
- return cpu_infos[@enumToInt(self)];
- }
-
- pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
- CpuInfo(@This(), FeatureType).create(.Cpu440, "440", &[_]FeatureType {
- .Icbt,
- .Booke,
- .HardFloat,
- .Fres,
- .Frsqrte,
- .Isel,
- .Msync,
- }),
- CpuInfo(@This(), FeatureType).create(.Cpu450, "450", &[_]FeatureType {
- .Icbt,
- .Booke,
- .HardFloat,
- .Fres,
- .Frsqrte,
- .Isel,
- .Msync,
- }),
- CpuInfo(@This(), FeatureType).create(.Cpu601, "601", &[_]FeatureType {
- .HardFloat,
- .Fpu,
- }),
- CpuInfo(@This(), FeatureType).create(.Cpu602, "602", &[_]FeatureType {
- .HardFloat,
- .Fpu,
- }),
- CpuInfo(@This(), FeatureType).create(.Cpu603, "603", &[_]FeatureType {
- .HardFloat,
- .Fres,
- .Frsqrte,
- }),
- CpuInfo(@This(), FeatureType).create(.E603, "603e", &[_]FeatureType {
- .HardFloat,
- .Fres,
- .Frsqrte,
- }),
- CpuInfo(@This(), FeatureType).create(.Ev603, "603ev", &[_]FeatureType {
- .HardFloat,
- .Fres,
- .Frsqrte,
- }),
- CpuInfo(@This(), FeatureType).create(.Cpu604, "604", &[_]FeatureType {
- .HardFloat,
- .Fres,
- .Frsqrte,
- }),
- CpuInfo(@This(), FeatureType).create(.E604, "604e", &[_]FeatureType {
- .HardFloat,
- .Fres,
- .Frsqrte,
- }),
- CpuInfo(@This(), FeatureType).create(.Cpu620, "620", &[_]FeatureType {
- .HardFloat,
- .Fres,
- .Frsqrte,
- }),
- CpuInfo(@This(), FeatureType).create(.Cpu7400, "7400", &[_]FeatureType {
- .HardFloat,
- .Altivec,
- .Fres,
- .Frsqrte,
- }),
- CpuInfo(@This(), FeatureType).create(.Cpu7450, "7450", &[_]FeatureType {
- .HardFloat,
- .Altivec,
- .Fres,
- .Frsqrte,
- }),
- CpuInfo(@This(), FeatureType).create(.Cpu750, "750", &[_]FeatureType {
- .HardFloat,
- .Fres,
- .Frsqrte,
- }),
- CpuInfo(@This(), FeatureType).create(.Cpu970, "970", &[_]FeatureType {
- .Bit64,
- .HardFloat,
- .Altivec,
- .Fres,
- .Frsqrte,
- .Fsqrt,
- .Mfocrf,
- .Stfiwx,
- }),
- CpuInfo(@This(), FeatureType).create(.A2, "a2", &[_]FeatureType {
- .Bit64,
- .Icbt,
- .Booke,
- .Cmpb,
- .HardFloat,
- .Fcpsgn,
- .Fpcvt,
- .Fprnd,
- .Fre,
- .Fres,
- .Frsqrte,
- .Frsqrtes,
- .Fsqrt,
- .Isel,
- .Ldbrx,
- .Lfiwax,
- .Mfocrf,
- .Recipprec,
- .Stfiwx,
- .SlowPopcntd,
- }),
- CpuInfo(@This(), FeatureType).create(.A2q, "a2q", &[_]FeatureType {
- .Bit64,
- .Icbt,
- .Booke,
- .Cmpb,
- .HardFloat,
- .Fcpsgn,
- .Fpcvt,
- .Fprnd,
- .Fre,
- .Fres,
- .Frsqrte,
- .Frsqrtes,
- .Fsqrt,
- .Isel,
- .Ldbrx,
- .Lfiwax,
- .Mfocrf,
- .Qpx,
- .Recipprec,
- .Stfiwx,
- .SlowPopcntd,
- }),
- CpuInfo(@This(), FeatureType).create(.E500, "e500", &[_]FeatureType {
- .Icbt,
- .Booke,
- .Isel,
- }),
- CpuInfo(@This(), FeatureType).create(.E500mc, "e500mc", &[_]FeatureType {
- .Icbt,
- .Booke,
- .Isel,
- .HardFloat,
- .Stfiwx,
- }),
- CpuInfo(@This(), FeatureType).create(.E5500, "e5500", &[_]FeatureType {
- .Bit64,
- .Icbt,
- .Booke,
- .Isel,
- .Mfocrf,
- .HardFloat,
- .Stfiwx,
- }),
- CpuInfo(@This(), FeatureType).create(.G3, "g3", &[_]FeatureType {
- .HardFloat,
- .Fres,
- .Frsqrte,
- }),
- CpuInfo(@This(), FeatureType).create(.G4, "g4", &[_]FeatureType {
- .HardFloat,
- .Altivec,
- .Fres,
- .Frsqrte,
- }),
- CpuInfo(@This(), FeatureType).create(.G4plus, "g4+", &[_]FeatureType {
- .HardFloat,
- .Altivec,
- .Fres,
- .Frsqrte,
- }),
- CpuInfo(@This(), FeatureType).create(.G5, "g5", &[_]FeatureType {
- .Bit64,
- .HardFloat,
- .Altivec,
- .Fres,
- .Frsqrte,
- .Fsqrt,
- .Mfocrf,
- .Stfiwx,
- }),
- CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
- .HardFloat,
- }),
- CpuInfo(@This(), FeatureType).create(.Ppc, "ppc", &[_]FeatureType {
- .HardFloat,
- }),
- CpuInfo(@This(), FeatureType).create(.Ppc32, "ppc32", &[_]FeatureType {
- .HardFloat,
- }),
- CpuInfo(@This(), FeatureType).create(.Ppc64, "ppc64", &[_]FeatureType {
- .Bit64,
- .HardFloat,
- .Altivec,
- .Fres,
- .Frsqrte,
- .Fsqrt,
- .Mfocrf,
- .Stfiwx,
- }),
- CpuInfo(@This(), FeatureType).create(.Ppc64le, "ppc64le", &[_]FeatureType {
- .Bit64,
- .HardFloat,
- .Altivec,
- .Bpermd,
- .Cmpb,
- .DirectMove,
- .Extdiv,
- .Fcpsgn,
- .Fpcvt,
- .Fprnd,
- .Fre,
- .Fres,
- .Frsqrte,
- .Frsqrtes,
- .Fsqrt,
- .Htm,
- .Icbt,
- .Isel,
- .Ldbrx,
- .Lfiwax,
- .Mfocrf,
- .Power8Altivec,
- .Crypto,
- .Power8Vector,
- .Popcntd,
- .PartwordAtomics,
- .Recipprec,
- .Stfiwx,
- .TwoConstNr,
- .Vsx,
- }),
- CpuInfo(@This(), FeatureType).create(.Pwr3, "pwr3", &[_]FeatureType {
- .Bit64,
- .HardFloat,
- .Altivec,
- .Fres,
- .Frsqrte,
- .Mfocrf,
- .Stfiwx,
- }),
- CpuInfo(@This(), FeatureType).create(.Pwr4, "pwr4", &[_]FeatureType {
- .Bit64,
- .HardFloat,
- .Altivec,
- .Fres,
- .Frsqrte,
- .Fsqrt,
- .Mfocrf,
- .Stfiwx,
- }),
- CpuInfo(@This(), FeatureType).create(.Pwr5, "pwr5", &[_]FeatureType {
- .Bit64,
- .HardFloat,
- .Altivec,
- .Fre,
- .Fres,
- .Frsqrte,
- .Frsqrtes,
- .Fsqrt,
- .Mfocrf,
- .Stfiwx,
- }),
- CpuInfo(@This(), FeatureType).create(.Pwr5x, "pwr5x", &[_]FeatureType {
- .Bit64,
- .HardFloat,
- .Altivec,
- .Fprnd,
- .Fre,
- .Fres,
- .Frsqrte,
- .Frsqrtes,
- .Fsqrt,
- .Mfocrf,
- .Stfiwx,
- }),
- CpuInfo(@This(), FeatureType).create(.Pwr6, "pwr6", &[_]FeatureType {
- .Bit64,
- .HardFloat,
- .Altivec,
- .Cmpb,
- .Fcpsgn,
- .Fprnd,
- .Fre,
- .Fres,
- .Frsqrte,
- .Frsqrtes,
- .Fsqrt,
- .Lfiwax,
- .Mfocrf,
- .Recipprec,
- .Stfiwx,
- }),
- CpuInfo(@This(), FeatureType).create(.Pwr6x, "pwr6x", &[_]FeatureType {
- .Bit64,
- .HardFloat,
- .Altivec,
- .Cmpb,
- .Fcpsgn,
- .Fprnd,
- .Fre,
- .Fres,
- .Frsqrte,
- .Frsqrtes,
- .Fsqrt,
- .Lfiwax,
- .Mfocrf,
- .Recipprec,
- .Stfiwx,
- }),
- CpuInfo(@This(), FeatureType).create(.Pwr7, "pwr7", &[_]FeatureType {
- .Bit64,
- .HardFloat,
- .Altivec,
- .Bpermd,
- .Cmpb,
- .Extdiv,
- .Fcpsgn,
- .Fpcvt,
- .Fprnd,
- .Fre,
- .Fres,
- .Frsqrte,
- .Frsqrtes,
- .Fsqrt,
- .Isel,
- .Ldbrx,
- .Lfiwax,
- .Mfocrf,
- .Popcntd,
- .Recipprec,
- .Stfiwx,
- .TwoConstNr,
- .Vsx,
- }),
- CpuInfo(@This(), FeatureType).create(.Pwr8, "pwr8", &[_]FeatureType {
- .Bit64,
- .HardFloat,
- .Altivec,
- .Bpermd,
- .Cmpb,
- .DirectMove,
- .Extdiv,
- .Fcpsgn,
- .Fpcvt,
- .Fprnd,
- .Fre,
- .Fres,
- .Frsqrte,
- .Frsqrtes,
- .Fsqrt,
- .Htm,
- .Icbt,
- .Isel,
- .Ldbrx,
- .Lfiwax,
- .Mfocrf,
- .Power8Altivec,
- .Crypto,
- .Power8Vector,
- .Popcntd,
- .PartwordAtomics,
- .Recipprec,
- .Stfiwx,
- .TwoConstNr,
- .Vsx,
- }),
- CpuInfo(@This(), FeatureType).create(.Pwr9, "pwr9", &[_]FeatureType {
- .Bit64,
- .HardFloat,
- .Altivec,
- .Bpermd,
- .Cmpb,
- .DirectMove,
- .Extdiv,
- .Fcpsgn,
- .Fpcvt,
- .Fprnd,
- .Fre,
- .Fres,
- .Frsqrte,
- .Frsqrtes,
- .Fsqrt,
- .Htm,
- .Icbt,
- .IsaV30Instructions,
- .Isel,
- .Ldbrx,
- .Lfiwax,
- .Mfocrf,
- .Power8Altivec,
- .Crypto,
- .Power8Vector,
- .Power9Altivec,
- .Power9Vector,
- .Popcntd,
- .PpcPostraSched,
- .PpcPreraSched,
- .PartwordAtomics,
- .Recipprec,
- .Stfiwx,
- .TwoConstNr,
- .Vsx,
- .VectorsUseTwoUnits,
- }),
- };
-};
lib/std/target/cpu/RiscVCpu.zig
@@ -1,23 +0,0 @@
-const feature = @import("std").target.feature;
-const CpuInfo = @import("std").target.cpu.CpuInfo;
-
-pub const RiscVCpu = enum {
- GenericRv32,
- GenericRv64,
-
- const FeatureType = feature.RiscVFeature;
-
- pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
- return cpu_infos[@enumToInt(self)];
- }
-
- pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
- CpuInfo(@This(), FeatureType).create(.GenericRv32, "generic-rv32", &[_]FeatureType {
- .RvcHints,
- }),
- CpuInfo(@This(), FeatureType).create(.GenericRv64, "generic-rv64", &[_]FeatureType {
- .Bit64,
- .RvcHints,
- }),
- };
-};
lib/std/target/cpu/SparcCpu.zig
@@ -1,216 +0,0 @@
-const feature = @import("std").target.feature;
-const CpuInfo = @import("std").target.cpu.CpuInfo;
-
-pub const SparcCpu = enum {
- At697e,
- At697f,
- F934,
- Generic,
- Gr712rc,
- Gr740,
- Hypersparc,
- Leon2,
- Leon3,
- Leon4,
- Ma2080,
- Ma2085,
- Ma2100,
- Ma2150,
- Ma2155,
- Ma2450,
- Ma2455,
- Ma2480,
- Ma2485,
- Ma2x5x,
- Ma2x8x,
- Myriad2,
- Myriad21,
- Myriad22,
- Myriad23,
- Niagara,
- Niagara2,
- Niagara3,
- Niagara4,
- Sparclet,
- Sparclite,
- Sparclite86x,
- Supersparc,
- Tsc701,
- Ultrasparc,
- Ultrasparc3,
- Ut699,
- V7,
- V8,
- V9,
-
- const FeatureType = feature.SparcFeature;
-
- pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
- return cpu_infos[@enumToInt(self)];
- }
-
- pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
- CpuInfo(@This(), FeatureType).create(.At697e, "at697e", &[_]FeatureType {
- .Leon,
- .Insertnopload,
- }),
- CpuInfo(@This(), FeatureType).create(.At697f, "at697f", &[_]FeatureType {
- .Leon,
- .Insertnopload,
- }),
- CpuInfo(@This(), FeatureType).create(.F934, "f934", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.Gr712rc, "gr712rc", &[_]FeatureType {
- .Leon,
- .Hasleoncasa,
- }),
- CpuInfo(@This(), FeatureType).create(.Gr740, "gr740", &[_]FeatureType {
- .Leon,
- .Leonpwrpsr,
- .Hasleoncasa,
- .Leoncyclecounter,
- .Hasumacsmac,
- }),
- CpuInfo(@This(), FeatureType).create(.Hypersparc, "hypersparc", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.Leon2, "leon2", &[_]FeatureType {
- .Leon,
- }),
- CpuInfo(@This(), FeatureType).create(.Leon3, "leon3", &[_]FeatureType {
- .Leon,
- .Hasumacsmac,
- }),
- CpuInfo(@This(), FeatureType).create(.Leon4, "leon4", &[_]FeatureType {
- .Leon,
- .Hasleoncasa,
- .Hasumacsmac,
- }),
- CpuInfo(@This(), FeatureType).create(.Ma2080, "ma2080", &[_]FeatureType {
- .Leon,
- .Hasleoncasa,
- }),
- CpuInfo(@This(), FeatureType).create(.Ma2085, "ma2085", &[_]FeatureType {
- .Leon,
- .Hasleoncasa,
- }),
- CpuInfo(@This(), FeatureType).create(.Ma2100, "ma2100", &[_]FeatureType {
- .Leon,
- .Hasleoncasa,
- }),
- CpuInfo(@This(), FeatureType).create(.Ma2150, "ma2150", &[_]FeatureType {
- .Leon,
- .Hasleoncasa,
- }),
- CpuInfo(@This(), FeatureType).create(.Ma2155, "ma2155", &[_]FeatureType {
- .Leon,
- .Hasleoncasa,
- }),
- CpuInfo(@This(), FeatureType).create(.Ma2450, "ma2450", &[_]FeatureType {
- .Leon,
- .Hasleoncasa,
- }),
- CpuInfo(@This(), FeatureType).create(.Ma2455, "ma2455", &[_]FeatureType {
- .Leon,
- .Hasleoncasa,
- }),
- CpuInfo(@This(), FeatureType).create(.Ma2480, "ma2480", &[_]FeatureType {
- .Leon,
- .Hasleoncasa,
- }),
- CpuInfo(@This(), FeatureType).create(.Ma2485, "ma2485", &[_]FeatureType {
- .Leon,
- .Hasleoncasa,
- }),
- CpuInfo(@This(), FeatureType).create(.Ma2x5x, "ma2x5x", &[_]FeatureType {
- .Leon,
- .Hasleoncasa,
- }),
- CpuInfo(@This(), FeatureType).create(.Ma2x8x, "ma2x8x", &[_]FeatureType {
- .Leon,
- .Hasleoncasa,
- }),
- CpuInfo(@This(), FeatureType).create(.Myriad2, "myriad2", &[_]FeatureType {
- .Leon,
- .Hasleoncasa,
- }),
- CpuInfo(@This(), FeatureType).create(.Myriad21, "myriad2.1", &[_]FeatureType {
- .Leon,
- .Hasleoncasa,
- }),
- CpuInfo(@This(), FeatureType).create(.Myriad22, "myriad2.2", &[_]FeatureType {
- .Leon,
- .Hasleoncasa,
- }),
- CpuInfo(@This(), FeatureType).create(.Myriad23, "myriad2.3", &[_]FeatureType {
- .Leon,
- .Hasleoncasa,
- }),
- CpuInfo(@This(), FeatureType).create(.Niagara, "niagara", &[_]FeatureType {
- .DeprecatedV8,
- .V9,
- .Vis,
- .Vis2,
- }),
- CpuInfo(@This(), FeatureType).create(.Niagara2, "niagara2", &[_]FeatureType {
- .DeprecatedV8,
- .V9,
- .Vis,
- .Vis2,
- .Popc,
- }),
- CpuInfo(@This(), FeatureType).create(.Niagara3, "niagara3", &[_]FeatureType {
- .DeprecatedV8,
- .V9,
- .Vis,
- .Vis2,
- .Popc,
- }),
- CpuInfo(@This(), FeatureType).create(.Niagara4, "niagara4", &[_]FeatureType {
- .DeprecatedV8,
- .V9,
- .Vis,
- .Vis2,
- .Vis3,
- .Popc,
- }),
- CpuInfo(@This(), FeatureType).create(.Sparclet, "sparclet", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.Sparclite, "sparclite", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.Sparclite86x, "sparclite86x", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.Supersparc, "supersparc", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.Tsc701, "tsc701", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.Ultrasparc, "ultrasparc", &[_]FeatureType {
- .DeprecatedV8,
- .V9,
- .Vis,
- }),
- CpuInfo(@This(), FeatureType).create(.Ultrasparc3, "ultrasparc3", &[_]FeatureType {
- .DeprecatedV8,
- .V9,
- .Vis,
- .Vis2,
- }),
- CpuInfo(@This(), FeatureType).create(.Ut699, "ut699", &[_]FeatureType {
- .Leon,
- .NoFmuls,
- .NoFsmuld,
- .Fixallfdivsqrt,
- .Insertnopload,
- }),
- CpuInfo(@This(), FeatureType).create(.V7, "v7", &[_]FeatureType {
- .NoFsmuld,
- .SoftMulDiv,
- }),
- CpuInfo(@This(), FeatureType).create(.V8, "v8", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.V9, "v9", &[_]FeatureType {
- .V9,
- }),
- };
-};
lib/std/target/cpu/SystemZCpu.zig
@@ -1,279 +0,0 @@
-const feature = @import("std").target.feature;
-const CpuInfo = @import("std").target.cpu.CpuInfo;
-
-pub const SystemZCpu = enum {
- Arch10,
- Arch11,
- Arch12,
- Arch13,
- Arch8,
- Arch9,
- Generic,
- Z10,
- Z13,
- Z14,
- Z15,
- Z196,
- ZEC12,
-
- const FeatureType = feature.SystemZFeature;
-
- pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
- return cpu_infos[@enumToInt(self)];
- }
-
- pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
- CpuInfo(@This(), FeatureType).create(.Arch10, "arch10", &[_]FeatureType {
- .DfpZonedConversion,
- .DistinctOps,
- .EnhancedDat2,
- .ExecutionHint,
- .FpExtension,
- .FastSerialization,
- .HighWord,
- .InterlockedAccess1,
- .LoadAndTrap,
- .LoadStoreOnCond,
- .MessageSecurityAssistExtension3,
- .MessageSecurityAssistExtension4,
- .MiscellaneousExtensions,
- .PopulationCount,
- .ProcessorAssist,
- .ResetReferenceBitsMultiple,
- .TransactionalExecution,
- }),
- CpuInfo(@This(), FeatureType).create(.Arch11, "arch11", &[_]FeatureType {
- .DfpPackedConversion,
- .DfpZonedConversion,
- .DistinctOps,
- .EnhancedDat2,
- .ExecutionHint,
- .FpExtension,
- .FastSerialization,
- .HighWord,
- .InterlockedAccess1,
- .LoadAndTrap,
- .LoadAndZeroRightmostByte,
- .LoadStoreOnCond,
- .LoadStoreOnCond2,
- .MessageSecurityAssistExtension3,
- .MessageSecurityAssistExtension4,
- .MessageSecurityAssistExtension5,
- .MiscellaneousExtensions,
- .PopulationCount,
- .ProcessorAssist,
- .ResetReferenceBitsMultiple,
- .TransactionalExecution,
- .Vector,
- }),
- CpuInfo(@This(), FeatureType).create(.Arch12, "arch12", &[_]FeatureType {
- .DfpPackedConversion,
- .DfpZonedConversion,
- .DistinctOps,
- .EnhancedDat2,
- .ExecutionHint,
- .FpExtension,
- .FastSerialization,
- .GuardedStorage,
- .HighWord,
- .InsertReferenceBitsMultiple,
- .InterlockedAccess1,
- .LoadAndTrap,
- .LoadAndZeroRightmostByte,
- .LoadStoreOnCond,
- .LoadStoreOnCond2,
- .MessageSecurityAssistExtension3,
- .MessageSecurityAssistExtension4,
- .MessageSecurityAssistExtension5,
- .MessageSecurityAssistExtension7,
- .MessageSecurityAssistExtension8,
- .MiscellaneousExtensions,
- .MiscellaneousExtensions2,
- .PopulationCount,
- .ProcessorAssist,
- .ResetReferenceBitsMultiple,
- .TransactionalExecution,
- .Vector,
- .VectorEnhancements1,
- .VectorPackedDecimal,
- }),
- CpuInfo(@This(), FeatureType).create(.Arch13, "arch13", &[_]FeatureType {
- .DfpPackedConversion,
- .DfpZonedConversion,
- .DeflateConversion,
- .DistinctOps,
- .EnhancedDat2,
- .EnhancedSort,
- .ExecutionHint,
- .FpExtension,
- .FastSerialization,
- .GuardedStorage,
- .HighWord,
- .InsertReferenceBitsMultiple,
- .InterlockedAccess1,
- .LoadAndTrap,
- .LoadAndZeroRightmostByte,
- .LoadStoreOnCond,
- .LoadStoreOnCond2,
- .MessageSecurityAssistExtension3,
- .MessageSecurityAssistExtension4,
- .MessageSecurityAssistExtension5,
- .MessageSecurityAssistExtension7,
- .MessageSecurityAssistExtension8,
- .MessageSecurityAssistExtension9,
- .MiscellaneousExtensions,
- .MiscellaneousExtensions2,
- .MiscellaneousExtensions3,
- .PopulationCount,
- .ProcessorAssist,
- .ResetReferenceBitsMultiple,
- .TransactionalExecution,
- .Vector,
- .VectorEnhancements1,
- .VectorEnhancements2,
- .VectorPackedDecimal,
- .VectorPackedDecimalEnhancement,
- }),
- CpuInfo(@This(), FeatureType).create(.Arch8, "arch8", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.Arch9, "arch9", &[_]FeatureType {
- .DistinctOps,
- .FpExtension,
- .FastSerialization,
- .HighWord,
- .InterlockedAccess1,
- .LoadStoreOnCond,
- .MessageSecurityAssistExtension3,
- .MessageSecurityAssistExtension4,
- .PopulationCount,
- .ResetReferenceBitsMultiple,
- }),
- CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.Z10, "z10", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.Z13, "z13", &[_]FeatureType {
- .DfpPackedConversion,
- .DfpZonedConversion,
- .DistinctOps,
- .EnhancedDat2,
- .ExecutionHint,
- .FpExtension,
- .FastSerialization,
- .HighWord,
- .InterlockedAccess1,
- .LoadAndTrap,
- .LoadAndZeroRightmostByte,
- .LoadStoreOnCond,
- .LoadStoreOnCond2,
- .MessageSecurityAssistExtension3,
- .MessageSecurityAssistExtension4,
- .MessageSecurityAssistExtension5,
- .MiscellaneousExtensions,
- .PopulationCount,
- .ProcessorAssist,
- .ResetReferenceBitsMultiple,
- .TransactionalExecution,
- .Vector,
- }),
- CpuInfo(@This(), FeatureType).create(.Z14, "z14", &[_]FeatureType {
- .DfpPackedConversion,
- .DfpZonedConversion,
- .DistinctOps,
- .EnhancedDat2,
- .ExecutionHint,
- .FpExtension,
- .FastSerialization,
- .GuardedStorage,
- .HighWord,
- .InsertReferenceBitsMultiple,
- .InterlockedAccess1,
- .LoadAndTrap,
- .LoadAndZeroRightmostByte,
- .LoadStoreOnCond,
- .LoadStoreOnCond2,
- .MessageSecurityAssistExtension3,
- .MessageSecurityAssistExtension4,
- .MessageSecurityAssistExtension5,
- .MessageSecurityAssistExtension7,
- .MessageSecurityAssistExtension8,
- .MiscellaneousExtensions,
- .MiscellaneousExtensions2,
- .PopulationCount,
- .ProcessorAssist,
- .ResetReferenceBitsMultiple,
- .TransactionalExecution,
- .Vector,
- .VectorEnhancements1,
- .VectorPackedDecimal,
- }),
- CpuInfo(@This(), FeatureType).create(.Z15, "z15", &[_]FeatureType {
- .DfpPackedConversion,
- .DfpZonedConversion,
- .DeflateConversion,
- .DistinctOps,
- .EnhancedDat2,
- .EnhancedSort,
- .ExecutionHint,
- .FpExtension,
- .FastSerialization,
- .GuardedStorage,
- .HighWord,
- .InsertReferenceBitsMultiple,
- .InterlockedAccess1,
- .LoadAndTrap,
- .LoadAndZeroRightmostByte,
- .LoadStoreOnCond,
- .LoadStoreOnCond2,
- .MessageSecurityAssistExtension3,
- .MessageSecurityAssistExtension4,
- .MessageSecurityAssistExtension5,
- .MessageSecurityAssistExtension7,
- .MessageSecurityAssistExtension8,
- .MessageSecurityAssistExtension9,
- .MiscellaneousExtensions,
- .MiscellaneousExtensions2,
- .MiscellaneousExtensions3,
- .PopulationCount,
- .ProcessorAssist,
- .ResetReferenceBitsMultiple,
- .TransactionalExecution,
- .Vector,
- .VectorEnhancements1,
- .VectorEnhancements2,
- .VectorPackedDecimal,
- .VectorPackedDecimalEnhancement,
- }),
- CpuInfo(@This(), FeatureType).create(.Z196, "z196", &[_]FeatureType {
- .DistinctOps,
- .FpExtension,
- .FastSerialization,
- .HighWord,
- .InterlockedAccess1,
- .LoadStoreOnCond,
- .MessageSecurityAssistExtension3,
- .MessageSecurityAssistExtension4,
- .PopulationCount,
- .ResetReferenceBitsMultiple,
- }),
- CpuInfo(@This(), FeatureType).create(.ZEC12, "zEC12", &[_]FeatureType {
- .DfpZonedConversion,
- .DistinctOps,
- .EnhancedDat2,
- .ExecutionHint,
- .FpExtension,
- .FastSerialization,
- .HighWord,
- .InterlockedAccess1,
- .LoadAndTrap,
- .LoadStoreOnCond,
- .MessageSecurityAssistExtension3,
- .MessageSecurityAssistExtension4,
- .MiscellaneousExtensions,
- .PopulationCount,
- .ProcessorAssist,
- .ResetReferenceBitsMultiple,
- .TransactionalExecution,
- }),
- };
-};
lib/std/target/cpu/WebAssemblyCpu.zig
@@ -1,28 +0,0 @@
-const feature = @import("std").target.feature;
-const CpuInfo = @import("std").target.cpu.CpuInfo;
-
-pub const WebAssemblyCpu = enum {
- BleedingEdge,
- Generic,
- Mvp,
-
- const FeatureType = feature.WebAssemblyFeature;
-
- pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
- return cpu_infos[@enumToInt(self)];
- }
-
- pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
- CpuInfo(@This(), FeatureType).create(.BleedingEdge, "bleeding-edge", &[_]FeatureType {
- .Atomics,
- .MutableGlobals,
- .NontrappingFptoint,
- .Simd128,
- .SignExt,
- }),
- CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.Mvp, "mvp", &[_]FeatureType {
- }),
- };
-};
lib/std/target/cpu/X86Cpu.zig
@@ -1,1864 +0,0 @@
-const feature = @import("std").target.feature;
-const CpuInfo = @import("std").target.cpu.CpuInfo;
-
-pub const X86Cpu = enum {
- Amdfam10,
- Athlon,
- Athlon4,
- AthlonFx,
- AthlonMp,
- AthlonTbird,
- AthlonXp,
- Athlon64,
- Athlon64Sse3,
- Atom,
- Barcelona,
- Bdver1,
- Bdver2,
- Bdver3,
- Bdver4,
- Bonnell,
- Broadwell,
- Btver1,
- Btver2,
- C3,
- C32,
- Cannonlake,
- Cascadelake,
- Cooperlake,
- CoreAvxI,
- CoreAvx2,
- Core2,
- Corei7,
- Corei7Avx,
- Generic,
- Geode,
- Goldmont,
- GoldmontPlus,
- Haswell,
- I386,
- I486,
- I586,
- I686,
- IcelakeClient,
- IcelakeServer,
- Ivybridge,
- K6,
- K62,
- K63,
- K8,
- K8Sse3,
- Knl,
- Knm,
- Lakemont,
- Nehalem,
- Nocona,
- Opteron,
- OpteronSse3,
- Penryn,
- Pentium,
- PentiumM,
- PentiumMmx,
- Pentium2,
- Pentium3,
- Pentium3m,
- Pentium4,
- Pentium4m,
- Pentiumpro,
- Prescott,
- Sandybridge,
- Silvermont,
- Skx,
- Skylake,
- SkylakeAvx512,
- Slm,
- Tigerlake,
- Tremont,
- Westmere,
- WinchipC6,
- Winchip2,
- X8664,
- Yonah,
- Znver1,
- Znver2,
-
- const FeatureType = feature.X86Feature;
-
- pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
- return cpu_infos[@enumToInt(self)];
- }
-
- pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
- CpuInfo(@This(), FeatureType).create(.Amdfam10, "amdfam10", &[_]FeatureType {
- .Mmx,
- .Dnowa3,
- .Bit64,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fxsr,
- .FastScalarShiftMasks,
- .Sahf,
- .Lzcnt,
- .Nopl,
- .Popcnt,
- .Sse,
- .Sse4a,
- .SlowShld,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Athlon, "athlon", &[_]FeatureType {
- .Mmx,
- .Dnowa3,
- .Cmov,
- .Cx8,
- .Nopl,
- .SlowShld,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Athlon4, "athlon-4", &[_]FeatureType {
- .Mmx,
- .Dnowa3,
- .Cmov,
- .Cx8,
- .Fxsr,
- .Nopl,
- .Sse,
- .SlowShld,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.AthlonFx, "athlon-fx", &[_]FeatureType {
- .Mmx,
- .Dnowa3,
- .Bit64,
- .Cmov,
- .Cx8,
- .Fxsr,
- .FastScalarShiftMasks,
- .Nopl,
- .Sse,
- .Sse2,
- .SlowShld,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.AthlonMp, "athlon-mp", &[_]FeatureType {
- .Mmx,
- .Dnowa3,
- .Cmov,
- .Cx8,
- .Fxsr,
- .Nopl,
- .Sse,
- .SlowShld,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.AthlonTbird, "athlon-tbird", &[_]FeatureType {
- .Mmx,
- .Dnowa3,
- .Cmov,
- .Cx8,
- .Nopl,
- .SlowShld,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.AthlonXp, "athlon-xp", &[_]FeatureType {
- .Mmx,
- .Dnowa3,
- .Cmov,
- .Cx8,
- .Fxsr,
- .Nopl,
- .Sse,
- .SlowShld,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Athlon64, "athlon64", &[_]FeatureType {
- .Mmx,
- .Dnowa3,
- .Bit64,
- .Cmov,
- .Cx8,
- .Fxsr,
- .FastScalarShiftMasks,
- .Nopl,
- .Sse,
- .Sse2,
- .SlowShld,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Athlon64Sse3, "athlon64-sse3", &[_]FeatureType {
- .Mmx,
- .Dnowa3,
- .Bit64,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fxsr,
- .FastScalarShiftMasks,
- .Nopl,
- .Sse,
- .Sse3,
- .SlowShld,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Atom, "atom", &[_]FeatureType {
- .Bit64,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fxsr,
- .Sahf,
- .LeaSp,
- .LeaUsesAg,
- .Mmx,
- .Movbe,
- .Nopl,
- .PadShortFunctions,
- .Sse,
- .Ssse3,
- .IdivlToDivb,
- .IdivqToDivl,
- .SlowTwoMemOps,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Barcelona, "barcelona", &[_]FeatureType {
- .Mmx,
- .Dnowa3,
- .Bit64,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fxsr,
- .FastScalarShiftMasks,
- .Sahf,
- .Lzcnt,
- .Nopl,
- .Popcnt,
- .Sse,
- .Sse4a,
- .SlowShld,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Bdver1, "bdver1", &[_]FeatureType {
- .Bit64,
- .Sse,
- .Aes,
- .Branchfusion,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fxsr,
- .Fast11bytenop,
- .FastScalarShiftMasks,
- .Sahf,
- .Lwp,
- .Lzcnt,
- .Mmx,
- .Nopl,
- .Pclmul,
- .Popcnt,
- .Prfchw,
- .SlowShld,
- .X87,
- .Xop,
- .Xsave,
- }),
- CpuInfo(@This(), FeatureType).create(.Bdver2, "bdver2", &[_]FeatureType {
- .Bit64,
- .Sse,
- .Aes,
- .Bmi,
- .Branchfusion,
- .Cmov,
- .Cx8,
- .Cx16,
- .F16c,
- .Fma,
- .Fxsr,
- .Fast11bytenop,
- .FastBextr,
- .FastScalarShiftMasks,
- .Sahf,
- .Lwp,
- .Lzcnt,
- .Mmx,
- .Nopl,
- .Pclmul,
- .Popcnt,
- .Prfchw,
- .SlowShld,
- .Tbm,
- .X87,
- .Xop,
- .Xsave,
- }),
- CpuInfo(@This(), FeatureType).create(.Bdver3, "bdver3", &[_]FeatureType {
- .Bit64,
- .Sse,
- .Aes,
- .Bmi,
- .Branchfusion,
- .Cmov,
- .Cx8,
- .Cx16,
- .F16c,
- .Fma,
- .Fsgsbase,
- .Fxsr,
- .Fast11bytenop,
- .FastBextr,
- .FastScalarShiftMasks,
- .Sahf,
- .Lwp,
- .Lzcnt,
- .Mmx,
- .Nopl,
- .Pclmul,
- .Popcnt,
- .Prfchw,
- .SlowShld,
- .Tbm,
- .X87,
- .Xop,
- .Xsave,
- .Xsaveopt,
- }),
- CpuInfo(@This(), FeatureType).create(.Bdver4, "bdver4", &[_]FeatureType {
- .Bit64,
- .Sse,
- .Aes,
- .Avx2,
- .Bmi,
- .Bmi2,
- .Branchfusion,
- .Cmov,
- .Cx8,
- .Cx16,
- .F16c,
- .Fma,
- .Fsgsbase,
- .Fxsr,
- .Fast11bytenop,
- .FastBextr,
- .FastScalarShiftMasks,
- .Sahf,
- .Lwp,
- .Lzcnt,
- .Mmx,
- .Mwaitx,
- .Nopl,
- .Pclmul,
- .Popcnt,
- .Prfchw,
- .SlowShld,
- .Tbm,
- .X87,
- .Xop,
- .Xsave,
- .Xsaveopt,
- }),
- CpuInfo(@This(), FeatureType).create(.Bonnell, "bonnell", &[_]FeatureType {
- .Bit64,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fxsr,
- .Sahf,
- .LeaSp,
- .LeaUsesAg,
- .Mmx,
- .Movbe,
- .Nopl,
- .PadShortFunctions,
- .Sse,
- .Ssse3,
- .IdivlToDivb,
- .IdivqToDivl,
- .SlowTwoMemOps,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Broadwell, "broadwell", &[_]FeatureType {
- .Bit64,
- .Adx,
- .Sse,
- .Avx,
- .Avx2,
- .Bmi,
- .Bmi2,
- .Cmov,
- .Cx8,
- .Cx16,
- .Ermsb,
- .F16c,
- .Fma,
- .Fsgsbase,
- .Fxsr,
- .FastShldRotate,
- .FastScalarFsqrt,
- .FastVariableShuffle,
- .Invpcid,
- .Sahf,
- .Lzcnt,
- .FalseDepsLzcntTzcnt,
- .Mmx,
- .Movbe,
- .Macrofusion,
- .MergeToThreewayBranch,
- .Nopl,
- .Pclmul,
- .Popcnt,
- .FalseDepsPopcnt,
- .Prfchw,
- .Rdrnd,
- .Rdseed,
- .Sse42,
- .Slow3opsLea,
- .IdivqToDivl,
- .X87,
- .Xsave,
- .Xsaveopt,
- }),
- CpuInfo(@This(), FeatureType).create(.Btver1, "btver1", &[_]FeatureType {
- .Bit64,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fxsr,
- .Fast15bytenop,
- .FastScalarShiftMasks,
- .FastVectorShiftMasks,
- .Sahf,
- .Lzcnt,
- .Mmx,
- .Nopl,
- .Popcnt,
- .Prfchw,
- .Sse,
- .Sse4a,
- .Ssse3,
- .SlowShld,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Btver2, "btver2", &[_]FeatureType {
- .Bit64,
- .Sse,
- .Aes,
- .Avx,
- .Bmi,
- .Cmov,
- .Cx8,
- .Cx16,
- .F16c,
- .Fxsr,
- .Fast15bytenop,
- .FastBextr,
- .FastHops,
- .FastLzcnt,
- .FastPartialYmmOrZmmWrite,
- .FastScalarShiftMasks,
- .FastVectorShiftMasks,
- .Sahf,
- .Lzcnt,
- .Mmx,
- .Movbe,
- .Nopl,
- .Pclmul,
- .Popcnt,
- .Prfchw,
- .Sse4a,
- .Ssse3,
- .SlowShld,
- .X87,
- .Xsave,
- .Xsaveopt,
- }),
- CpuInfo(@This(), FeatureType).create(.C3, "c3", &[_]FeatureType {
- .Mmx,
- .Dnow3,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.C32, "c3-2", &[_]FeatureType {
- .Cmov,
- .Cx8,
- .Fxsr,
- .Mmx,
- .Sse,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Cannonlake, "cannonlake", &[_]FeatureType {
- .Bit64,
- .Adx,
- .Sse,
- .Aes,
- .Avx,
- .Avx2,
- .Avx512f,
- .Bmi,
- .Bmi2,
- .Avx512bw,
- .Avx512cd,
- .Clflushopt,
- .Cmov,
- .Cx8,
- .Cx16,
- .Avx512dq,
- .Ermsb,
- .F16c,
- .Fma,
- .Fsgsbase,
- .Fxsr,
- .FastShldRotate,
- .FastScalarFsqrt,
- .FastVariableShuffle,
- .FastVectorFsqrt,
- .FastGather,
- .Avx512ifma,
- .Invpcid,
- .Sahf,
- .Lzcnt,
- .Mmx,
- .Movbe,
- .Macrofusion,
- .MergeToThreewayBranch,
- .Nopl,
- .Pclmul,
- .Pku,
- .Popcnt,
- .Prfchw,
- .Prefer256Bit,
- .Rdrnd,
- .Rdseed,
- .Sgx,
- .Sha,
- .Sse42,
- .Slow3opsLea,
- .IdivqToDivl,
- .Avx512vbmi,
- .Avx512vl,
- .X87,
- .Xsave,
- .Xsavec,
- .Xsaveopt,
- .Xsaves,
- }),
- CpuInfo(@This(), FeatureType).create(.Cascadelake, "cascadelake", &[_]FeatureType {
- .Bit64,
- .Adx,
- .Sse,
- .Aes,
- .Avx,
- .Avx2,
- .Avx512f,
- .Bmi,
- .Bmi2,
- .Avx512bw,
- .Avx512cd,
- .Clflushopt,
- .Clwb,
- .Cmov,
- .Cx8,
- .Cx16,
- .Avx512dq,
- .Ermsb,
- .F16c,
- .Fma,
- .Fsgsbase,
- .Fxsr,
- .FastShldRotate,
- .FastScalarFsqrt,
- .FastVariableShuffle,
- .FastVectorFsqrt,
- .FastGather,
- .Invpcid,
- .Sahf,
- .Lzcnt,
- .Mmx,
- .Movbe,
- .Macrofusion,
- .MergeToThreewayBranch,
- .Nopl,
- .Pclmul,
- .Pku,
- .Popcnt,
- .FalseDepsPopcnt,
- .Prfchw,
- .Prefer256Bit,
- .Rdrnd,
- .Rdseed,
- .Sse42,
- .Slow3opsLea,
- .IdivqToDivl,
- .Avx512vl,
- .Avx512vnni,
- .X87,
- .Xsave,
- .Xsavec,
- .Xsaveopt,
- .Xsaves,
- }),
- CpuInfo(@This(), FeatureType).create(.Cooperlake, "cooperlake", &[_]FeatureType {
- .Bit64,
- .Adx,
- .Sse,
- .Aes,
- .Avx,
- .Avx2,
- .Avx512f,
- .Avx512bf16,
- .Bmi,
- .Bmi2,
- .Avx512bw,
- .Avx512cd,
- .Clflushopt,
- .Clwb,
- .Cmov,
- .Cx8,
- .Cx16,
- .Avx512dq,
- .Ermsb,
- .F16c,
- .Fma,
- .Fsgsbase,
- .Fxsr,
- .FastShldRotate,
- .FastScalarFsqrt,
- .FastVariableShuffle,
- .FastVectorFsqrt,
- .FastGather,
- .Invpcid,
- .Sahf,
- .Lzcnt,
- .Mmx,
- .Movbe,
- .Macrofusion,
- .MergeToThreewayBranch,
- .Nopl,
- .Pclmul,
- .Pku,
- .Popcnt,
- .FalseDepsPopcnt,
- .Prfchw,
- .Prefer256Bit,
- .Rdrnd,
- .Rdseed,
- .Sse42,
- .Slow3opsLea,
- .IdivqToDivl,
- .Avx512vl,
- .Avx512vnni,
- .X87,
- .Xsave,
- .Xsavec,
- .Xsaveopt,
- .Xsaves,
- }),
- CpuInfo(@This(), FeatureType).create(.CoreAvxI, "core-avx-i", &[_]FeatureType {
- .Bit64,
- .Sse,
- .Avx,
- .Cmov,
- .Cx8,
- .Cx16,
- .F16c,
- .Fsgsbase,
- .Fxsr,
- .FastShldRotate,
- .FastScalarFsqrt,
- .Sahf,
- .Mmx,
- .Macrofusion,
- .MergeToThreewayBranch,
- .Nopl,
- .Pclmul,
- .Popcnt,
- .FalseDepsPopcnt,
- .Rdrnd,
- .Sse42,
- .Slow3opsLea,
- .IdivqToDivl,
- .SlowUnalignedMem32,
- .X87,
- .Xsave,
- .Xsaveopt,
- }),
- CpuInfo(@This(), FeatureType).create(.CoreAvx2, "core-avx2", &[_]FeatureType {
- .Bit64,
- .Sse,
- .Avx,
- .Avx2,
- .Bmi,
- .Bmi2,
- .Cmov,
- .Cx8,
- .Cx16,
- .Ermsb,
- .F16c,
- .Fma,
- .Fsgsbase,
- .Fxsr,
- .FastShldRotate,
- .FastScalarFsqrt,
- .FastVariableShuffle,
- .Invpcid,
- .Sahf,
- .Lzcnt,
- .FalseDepsLzcntTzcnt,
- .Mmx,
- .Movbe,
- .Macrofusion,
- .MergeToThreewayBranch,
- .Nopl,
- .Pclmul,
- .Popcnt,
- .FalseDepsPopcnt,
- .Rdrnd,
- .Sse42,
- .Slow3opsLea,
- .IdivqToDivl,
- .X87,
- .Xsave,
- .Xsaveopt,
- }),
- CpuInfo(@This(), FeatureType).create(.Core2, "core2", &[_]FeatureType {
- .Bit64,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fxsr,
- .Sahf,
- .Mmx,
- .Macrofusion,
- .Nopl,
- .Sse,
- .Ssse3,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Corei7, "corei7", &[_]FeatureType {
- .Bit64,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fxsr,
- .Sahf,
- .Mmx,
- .Macrofusion,
- .Nopl,
- .Popcnt,
- .Sse,
- .Sse42,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Corei7Avx, "corei7-avx", &[_]FeatureType {
- .Bit64,
- .Sse,
- .Avx,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fxsr,
- .FastShldRotate,
- .FastScalarFsqrt,
- .Sahf,
- .Mmx,
- .Macrofusion,
- .MergeToThreewayBranch,
- .Nopl,
- .Pclmul,
- .Popcnt,
- .FalseDepsPopcnt,
- .Sse42,
- .Slow3opsLea,
- .IdivqToDivl,
- .SlowUnalignedMem32,
- .X87,
- .Xsave,
- .Xsaveopt,
- }),
- CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
- .Cx8,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Geode, "geode", &[_]FeatureType {
- .Mmx,
- .Dnowa3,
- .Cx8,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Goldmont, "goldmont", &[_]FeatureType {
- .Bit64,
- .Sse,
- .Aes,
- .Clflushopt,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fsgsbase,
- .Fxsr,
- .Sahf,
- .Mmx,
- .Movbe,
- .Nopl,
- .Pclmul,
- .Popcnt,
- .FalseDepsPopcnt,
- .Prfchw,
- .Rdrnd,
- .Rdseed,
- .Sha,
- .Sse42,
- .Ssse3,
- .SlowIncdec,
- .SlowLea,
- .SlowTwoMemOps,
- .X87,
- .Xsave,
- .Xsavec,
- .Xsaveopt,
- .Xsaves,
- }),
- CpuInfo(@This(), FeatureType).create(.GoldmontPlus, "goldmont-plus", &[_]FeatureType {
- .Bit64,
- .Sse,
- .Aes,
- .Clflushopt,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fsgsbase,
- .Fxsr,
- .Sahf,
- .Mmx,
- .Movbe,
- .Nopl,
- .Pclmul,
- .Popcnt,
- .Prfchw,
- .Ptwrite,
- .Rdpid,
- .Rdrnd,
- .Rdseed,
- .Sgx,
- .Sha,
- .Sse42,
- .Ssse3,
- .SlowIncdec,
- .SlowLea,
- .SlowTwoMemOps,
- .X87,
- .Xsave,
- .Xsavec,
- .Xsaveopt,
- .Xsaves,
- }),
- CpuInfo(@This(), FeatureType).create(.Haswell, "haswell", &[_]FeatureType {
- .Bit64,
- .Sse,
- .Avx,
- .Avx2,
- .Bmi,
- .Bmi2,
- .Cmov,
- .Cx8,
- .Cx16,
- .Ermsb,
- .F16c,
- .Fma,
- .Fsgsbase,
- .Fxsr,
- .FastShldRotate,
- .FastScalarFsqrt,
- .FastVariableShuffle,
- .Invpcid,
- .Sahf,
- .Lzcnt,
- .FalseDepsLzcntTzcnt,
- .Mmx,
- .Movbe,
- .Macrofusion,
- .MergeToThreewayBranch,
- .Nopl,
- .Pclmul,
- .Popcnt,
- .FalseDepsPopcnt,
- .Rdrnd,
- .Sse42,
- .Slow3opsLea,
- .IdivqToDivl,
- .X87,
- .Xsave,
- .Xsaveopt,
- }),
- CpuInfo(@This(), FeatureType).create(.I386, "i386", &[_]FeatureType {
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.I486, "i486", &[_]FeatureType {
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.I586, "i586", &[_]FeatureType {
- .Cx8,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.I686, "i686", &[_]FeatureType {
- .Cmov,
- .Cx8,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.IcelakeClient, "icelake-client", &[_]FeatureType {
- .Bit64,
- .Adx,
- .Sse,
- .Aes,
- .Avx,
- .Avx2,
- .Avx512f,
- .Avx512bitalg,
- .Bmi,
- .Bmi2,
- .Avx512bw,
- .Avx512cd,
- .Clflushopt,
- .Clwb,
- .Cmov,
- .Cx8,
- .Cx16,
- .Avx512dq,
- .Ermsb,
- .F16c,
- .Fma,
- .Fsgsbase,
- .Fxsr,
- .FastShldRotate,
- .FastScalarFsqrt,
- .FastVariableShuffle,
- .FastVectorFsqrt,
- .Gfni,
- .FastGather,
- .Avx512ifma,
- .Invpcid,
- .Sahf,
- .Lzcnt,
- .Mmx,
- .Movbe,
- .Macrofusion,
- .MergeToThreewayBranch,
- .Nopl,
- .Pclmul,
- .Pku,
- .Popcnt,
- .Prfchw,
- .Prefer256Bit,
- .Rdpid,
- .Rdrnd,
- .Rdseed,
- .Sgx,
- .Sha,
- .Sse42,
- .Slow3opsLea,
- .IdivqToDivl,
- .Vaes,
- .Avx512vbmi,
- .Avx512vbmi2,
- .Avx512vl,
- .Avx512vnni,
- .Vpclmulqdq,
- .Avx512vpopcntdq,
- .X87,
- .Xsave,
- .Xsavec,
- .Xsaveopt,
- .Xsaves,
- }),
- CpuInfo(@This(), FeatureType).create(.IcelakeServer, "icelake-server", &[_]FeatureType {
- .Bit64,
- .Adx,
- .Sse,
- .Aes,
- .Avx,
- .Avx2,
- .Avx512f,
- .Avx512bitalg,
- .Bmi,
- .Bmi2,
- .Avx512bw,
- .Avx512cd,
- .Clflushopt,
- .Clwb,
- .Cmov,
- .Cx8,
- .Cx16,
- .Avx512dq,
- .Ermsb,
- .F16c,
- .Fma,
- .Fsgsbase,
- .Fxsr,
- .FastShldRotate,
- .FastScalarFsqrt,
- .FastVariableShuffle,
- .FastVectorFsqrt,
- .Gfni,
- .FastGather,
- .Avx512ifma,
- .Invpcid,
- .Sahf,
- .Lzcnt,
- .Mmx,
- .Movbe,
- .Macrofusion,
- .MergeToThreewayBranch,
- .Nopl,
- .Pclmul,
- .Pconfig,
- .Pku,
- .Popcnt,
- .Prfchw,
- .Prefer256Bit,
- .Rdpid,
- .Rdrnd,
- .Rdseed,
- .Sgx,
- .Sha,
- .Sse42,
- .Slow3opsLea,
- .IdivqToDivl,
- .Vaes,
- .Avx512vbmi,
- .Avx512vbmi2,
- .Avx512vl,
- .Avx512vnni,
- .Vpclmulqdq,
- .Avx512vpopcntdq,
- .Wbnoinvd,
- .X87,
- .Xsave,
- .Xsavec,
- .Xsaveopt,
- .Xsaves,
- }),
- CpuInfo(@This(), FeatureType).create(.Ivybridge, "ivybridge", &[_]FeatureType {
- .Bit64,
- .Sse,
- .Avx,
- .Cmov,
- .Cx8,
- .Cx16,
- .F16c,
- .Fsgsbase,
- .Fxsr,
- .FastShldRotate,
- .FastScalarFsqrt,
- .Sahf,
- .Mmx,
- .Macrofusion,
- .MergeToThreewayBranch,
- .Nopl,
- .Pclmul,
- .Popcnt,
- .FalseDepsPopcnt,
- .Rdrnd,
- .Sse42,
- .Slow3opsLea,
- .IdivqToDivl,
- .SlowUnalignedMem32,
- .X87,
- .Xsave,
- .Xsaveopt,
- }),
- CpuInfo(@This(), FeatureType).create(.K6, "k6", &[_]FeatureType {
- .Cx8,
- .Mmx,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.K62, "k6-2", &[_]FeatureType {
- .Mmx,
- .Dnow3,
- .Cx8,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.K63, "k6-3", &[_]FeatureType {
- .Mmx,
- .Dnow3,
- .Cx8,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.K8, "k8", &[_]FeatureType {
- .Mmx,
- .Dnowa3,
- .Bit64,
- .Cmov,
- .Cx8,
- .Fxsr,
- .FastScalarShiftMasks,
- .Nopl,
- .Sse,
- .Sse2,
- .SlowShld,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.K8Sse3, "k8-sse3", &[_]FeatureType {
- .Mmx,
- .Dnowa3,
- .Bit64,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fxsr,
- .FastScalarShiftMasks,
- .Nopl,
- .Sse,
- .Sse3,
- .SlowShld,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Knl, "knl", &[_]FeatureType {
- .Bit64,
- .Adx,
- .Sse,
- .Aes,
- .Avx512f,
- .Bmi,
- .Bmi2,
- .Avx512cd,
- .Cmov,
- .Cx8,
- .Cx16,
- .Avx512er,
- .F16c,
- .Fma,
- .Fsgsbase,
- .Fxsr,
- .FastPartialYmmOrZmmWrite,
- .FastGather,
- .Sahf,
- .Lzcnt,
- .Mmx,
- .Movbe,
- .Nopl,
- .Pclmul,
- .Avx512pf,
- .Popcnt,
- .Prefetchwt1,
- .Prfchw,
- .Rdrnd,
- .Rdseed,
- .Slow3opsLea,
- .IdivqToDivl,
- .SlowIncdec,
- .SlowPmaddwd,
- .SlowTwoMemOps,
- .X87,
- .Xsave,
- .Xsaveopt,
- }),
- CpuInfo(@This(), FeatureType).create(.Knm, "knm", &[_]FeatureType {
- .Bit64,
- .Adx,
- .Sse,
- .Aes,
- .Avx512f,
- .Bmi,
- .Bmi2,
- .Avx512cd,
- .Cmov,
- .Cx8,
- .Cx16,
- .Avx512er,
- .F16c,
- .Fma,
- .Fsgsbase,
- .Fxsr,
- .FastPartialYmmOrZmmWrite,
- .FastGather,
- .Sahf,
- .Lzcnt,
- .Mmx,
- .Movbe,
- .Nopl,
- .Pclmul,
- .Avx512pf,
- .Popcnt,
- .Prefetchwt1,
- .Prfchw,
- .Rdrnd,
- .Rdseed,
- .Slow3opsLea,
- .IdivqToDivl,
- .SlowIncdec,
- .SlowPmaddwd,
- .SlowTwoMemOps,
- .Avx512vpopcntdq,
- .X87,
- .Xsave,
- .Xsaveopt,
- }),
- CpuInfo(@This(), FeatureType).create(.Lakemont, "lakemont", &[_]FeatureType {
- }),
- CpuInfo(@This(), FeatureType).create(.Nehalem, "nehalem", &[_]FeatureType {
- .Bit64,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fxsr,
- .Sahf,
- .Mmx,
- .Macrofusion,
- .Nopl,
- .Popcnt,
- .Sse,
- .Sse42,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Nocona, "nocona", &[_]FeatureType {
- .Bit64,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fxsr,
- .Mmx,
- .Nopl,
- .Sse,
- .Sse3,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Opteron, "opteron", &[_]FeatureType {
- .Mmx,
- .Dnowa3,
- .Bit64,
- .Cmov,
- .Cx8,
- .Fxsr,
- .FastScalarShiftMasks,
- .Nopl,
- .Sse,
- .Sse2,
- .SlowShld,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.OpteronSse3, "opteron-sse3", &[_]FeatureType {
- .Mmx,
- .Dnowa3,
- .Bit64,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fxsr,
- .FastScalarShiftMasks,
- .Nopl,
- .Sse,
- .Sse3,
- .SlowShld,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Penryn, "penryn", &[_]FeatureType {
- .Bit64,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fxsr,
- .Sahf,
- .Mmx,
- .Macrofusion,
- .Nopl,
- .Sse,
- .Sse41,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Pentium, "pentium", &[_]FeatureType {
- .Cx8,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.PentiumM, "pentium-m", &[_]FeatureType {
- .Cmov,
- .Cx8,
- .Fxsr,
- .Mmx,
- .Nopl,
- .Sse,
- .Sse2,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.PentiumMmx, "pentium-mmx", &[_]FeatureType {
- .Cx8,
- .Mmx,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Pentium2, "pentium2", &[_]FeatureType {
- .Cmov,
- .Cx8,
- .Fxsr,
- .Mmx,
- .Nopl,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Pentium3, "pentium3", &[_]FeatureType {
- .Cmov,
- .Cx8,
- .Fxsr,
- .Mmx,
- .Nopl,
- .Sse,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Pentium3m, "pentium3m", &[_]FeatureType {
- .Cmov,
- .Cx8,
- .Fxsr,
- .Mmx,
- .Nopl,
- .Sse,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Pentium4, "pentium4", &[_]FeatureType {
- .Cmov,
- .Cx8,
- .Fxsr,
- .Mmx,
- .Nopl,
- .Sse,
- .Sse2,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Pentium4m, "pentium4m", &[_]FeatureType {
- .Cmov,
- .Cx8,
- .Fxsr,
- .Mmx,
- .Nopl,
- .Sse,
- .Sse2,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Pentiumpro, "pentiumpro", &[_]FeatureType {
- .Cmov,
- .Cx8,
- .Nopl,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Prescott, "prescott", &[_]FeatureType {
- .Cmov,
- .Cx8,
- .Fxsr,
- .Mmx,
- .Nopl,
- .Sse,
- .Sse3,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Sandybridge, "sandybridge", &[_]FeatureType {
- .Bit64,
- .Sse,
- .Avx,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fxsr,
- .FastShldRotate,
- .FastScalarFsqrt,
- .Sahf,
- .Mmx,
- .Macrofusion,
- .MergeToThreewayBranch,
- .Nopl,
- .Pclmul,
- .Popcnt,
- .FalseDepsPopcnt,
- .Sse42,
- .Slow3opsLea,
- .IdivqToDivl,
- .SlowUnalignedMem32,
- .X87,
- .Xsave,
- .Xsaveopt,
- }),
- CpuInfo(@This(), FeatureType).create(.Silvermont, "silvermont", &[_]FeatureType {
- .Bit64,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fxsr,
- .Sahf,
- .Mmx,
- .Movbe,
- .Nopl,
- .Sse,
- .Pclmul,
- .Popcnt,
- .FalseDepsPopcnt,
- .Prfchw,
- .Rdrnd,
- .Sse42,
- .Ssse3,
- .IdivqToDivl,
- .SlowIncdec,
- .SlowLea,
- .SlowPmulld,
- .SlowTwoMemOps,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Skx, "skx", &[_]FeatureType {
- .Bit64,
- .Adx,
- .Sse,
- .Aes,
- .Avx,
- .Avx2,
- .Avx512f,
- .Bmi,
- .Bmi2,
- .Avx512bw,
- .Avx512cd,
- .Clflushopt,
- .Clwb,
- .Cmov,
- .Cx8,
- .Cx16,
- .Avx512dq,
- .Ermsb,
- .F16c,
- .Fma,
- .Fsgsbase,
- .Fxsr,
- .FastShldRotate,
- .FastScalarFsqrt,
- .FastVariableShuffle,
- .FastVectorFsqrt,
- .FastGather,
- .Invpcid,
- .Sahf,
- .Lzcnt,
- .Mmx,
- .Movbe,
- .Macrofusion,
- .MergeToThreewayBranch,
- .Nopl,
- .Pclmul,
- .Pku,
- .Popcnt,
- .FalseDepsPopcnt,
- .Prfchw,
- .Prefer256Bit,
- .Rdrnd,
- .Rdseed,
- .Sse42,
- .Slow3opsLea,
- .IdivqToDivl,
- .Avx512vl,
- .X87,
- .Xsave,
- .Xsavec,
- .Xsaveopt,
- .Xsaves,
- }),
- CpuInfo(@This(), FeatureType).create(.Skylake, "skylake", &[_]FeatureType {
- .Bit64,
- .Adx,
- .Sse,
- .Aes,
- .Avx,
- .Avx2,
- .Bmi,
- .Bmi2,
- .Clflushopt,
- .Cmov,
- .Cx8,
- .Cx16,
- .Ermsb,
- .F16c,
- .Fma,
- .Fsgsbase,
- .Fxsr,
- .FastShldRotate,
- .FastScalarFsqrt,
- .FastVariableShuffle,
- .FastVectorFsqrt,
- .FastGather,
- .Invpcid,
- .Sahf,
- .Lzcnt,
- .Mmx,
- .Movbe,
- .Macrofusion,
- .MergeToThreewayBranch,
- .Nopl,
- .Pclmul,
- .Popcnt,
- .FalseDepsPopcnt,
- .Prfchw,
- .Rdrnd,
- .Rdseed,
- .Sgx,
- .Sse42,
- .Slow3opsLea,
- .IdivqToDivl,
- .X87,
- .Xsave,
- .Xsavec,
- .Xsaveopt,
- .Xsaves,
- }),
- CpuInfo(@This(), FeatureType).create(.SkylakeAvx512, "skylake-avx512", &[_]FeatureType {
- .Bit64,
- .Adx,
- .Sse,
- .Aes,
- .Avx,
- .Avx2,
- .Avx512f,
- .Bmi,
- .Bmi2,
- .Avx512bw,
- .Avx512cd,
- .Clflushopt,
- .Clwb,
- .Cmov,
- .Cx8,
- .Cx16,
- .Avx512dq,
- .Ermsb,
- .F16c,
- .Fma,
- .Fsgsbase,
- .Fxsr,
- .FastShldRotate,
- .FastScalarFsqrt,
- .FastVariableShuffle,
- .FastVectorFsqrt,
- .FastGather,
- .Invpcid,
- .Sahf,
- .Lzcnt,
- .Mmx,
- .Movbe,
- .Macrofusion,
- .MergeToThreewayBranch,
- .Nopl,
- .Pclmul,
- .Pku,
- .Popcnt,
- .FalseDepsPopcnt,
- .Prfchw,
- .Prefer256Bit,
- .Rdrnd,
- .Rdseed,
- .Sse42,
- .Slow3opsLea,
- .IdivqToDivl,
- .Avx512vl,
- .X87,
- .Xsave,
- .Xsavec,
- .Xsaveopt,
- .Xsaves,
- }),
- CpuInfo(@This(), FeatureType).create(.Slm, "slm", &[_]FeatureType {
- .Bit64,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fxsr,
- .Sahf,
- .Mmx,
- .Movbe,
- .Nopl,
- .Sse,
- .Pclmul,
- .Popcnt,
- .FalseDepsPopcnt,
- .Prfchw,
- .Rdrnd,
- .Sse42,
- .Ssse3,
- .IdivqToDivl,
- .SlowIncdec,
- .SlowLea,
- .SlowPmulld,
- .SlowTwoMemOps,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Tigerlake, "tigerlake", &[_]FeatureType {
- .Bit64,
- .Adx,
- .Sse,
- .Aes,
- .Avx,
- .Avx2,
- .Avx512f,
- .Avx512bitalg,
- .Bmi,
- .Bmi2,
- .Avx512bw,
- .Avx512cd,
- .Clflushopt,
- .Clwb,
- .Cmov,
- .Cx8,
- .Cx16,
- .Avx512dq,
- .Ermsb,
- .F16c,
- .Fma,
- .Fsgsbase,
- .Fxsr,
- .FastShldRotate,
- .FastScalarFsqrt,
- .FastVariableShuffle,
- .FastVectorFsqrt,
- .Gfni,
- .FastGather,
- .Avx512ifma,
- .Invpcid,
- .Sahf,
- .Lzcnt,
- .Mmx,
- .Movbe,
- .Movdir64b,
- .Movdiri,
- .Macrofusion,
- .MergeToThreewayBranch,
- .Nopl,
- .Pclmul,
- .Pku,
- .Popcnt,
- .Prfchw,
- .Prefer256Bit,
- .Rdpid,
- .Rdrnd,
- .Rdseed,
- .Sgx,
- .Sha,
- .Shstk,
- .Sse42,
- .Slow3opsLea,
- .IdivqToDivl,
- .Vaes,
- .Avx512vbmi,
- .Avx512vbmi2,
- .Avx512vl,
- .Avx512vnni,
- .Avx512vp2intersect,
- .Vpclmulqdq,
- .Avx512vpopcntdq,
- .X87,
- .Xsave,
- .Xsavec,
- .Xsaveopt,
- .Xsaves,
- }),
- CpuInfo(@This(), FeatureType).create(.Tremont, "tremont", &[_]FeatureType {
- .Bit64,
- .Sse,
- .Aes,
- .Cldemote,
- .Clflushopt,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fsgsbase,
- .Fxsr,
- .Gfni,
- .Sahf,
- .Mmx,
- .Movbe,
- .Movdir64b,
- .Movdiri,
- .Nopl,
- .Pclmul,
- .Popcnt,
- .Prfchw,
- .Ptwrite,
- .Rdpid,
- .Rdrnd,
- .Rdseed,
- .Sgx,
- .Sha,
- .Sse42,
- .Ssse3,
- .SlowIncdec,
- .SlowLea,
- .SlowTwoMemOps,
- .Waitpkg,
- .X87,
- .Xsave,
- .Xsavec,
- .Xsaveopt,
- .Xsaves,
- }),
- CpuInfo(@This(), FeatureType).create(.Westmere, "westmere", &[_]FeatureType {
- .Bit64,
- .Cmov,
- .Cx8,
- .Cx16,
- .Fxsr,
- .Sahf,
- .Mmx,
- .Macrofusion,
- .Nopl,
- .Sse,
- .Pclmul,
- .Popcnt,
- .Sse42,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.WinchipC6, "winchip-c6", &[_]FeatureType {
- .Mmx,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Winchip2, "winchip2", &[_]FeatureType {
- .Mmx,
- .Dnow3,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.X8664, "x86-64", &[_]FeatureType {
- .Bit64,
- .Cmov,
- .Cx8,
- .Fxsr,
- .Mmx,
- .Macrofusion,
- .Nopl,
- .Sse,
- .Sse2,
- .Slow3opsLea,
- .SlowIncdec,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Yonah, "yonah", &[_]FeatureType {
- .Cmov,
- .Cx8,
- .Fxsr,
- .Mmx,
- .Nopl,
- .Sse,
- .Sse3,
- .SlowUnalignedMem16,
- .X87,
- }),
- CpuInfo(@This(), FeatureType).create(.Znver1, "znver1", &[_]FeatureType {
- .Bit64,
- .Adx,
- .Sse,
- .Aes,
- .Avx2,
- .Bmi,
- .Bmi2,
- .Branchfusion,
- .Clflushopt,
- .Clzero,
- .Cmov,
- .Cx8,
- .Cx16,
- .F16c,
- .Fma,
- .Fsgsbase,
- .Fxsr,
- .Fast15bytenop,
- .FastBextr,
- .FastLzcnt,
- .FastScalarShiftMasks,
- .Sahf,
- .Lzcnt,
- .Mmx,
- .Movbe,
- .Mwaitx,
- .Nopl,
- .Pclmul,
- .Popcnt,
- .Prfchw,
- .Rdrnd,
- .Rdseed,
- .Sha,
- .Sse4a,
- .SlowShld,
- .X87,
- .Xsave,
- .Xsavec,
- .Xsaveopt,
- .Xsaves,
- }),
- CpuInfo(@This(), FeatureType).create(.Znver2, "znver2", &[_]FeatureType {
- .Bit64,
- .Adx,
- .Sse,
- .Aes,
- .Avx2,
- .Bmi,
- .Bmi2,
- .Branchfusion,
- .Clflushopt,
- .Clwb,
- .Clzero,
- .Cmov,
- .Cx8,
- .Cx16,
- .F16c,
- .Fma,
- .Fsgsbase,
- .Fxsr,
- .Fast15bytenop,
- .FastBextr,
- .FastLzcnt,
- .FastScalarShiftMasks,
- .Sahf,
- .Lzcnt,
- .Mmx,
- .Movbe,
- .Mwaitx,
- .Nopl,
- .Pclmul,
- .Popcnt,
- .Prfchw,
- .Rdpid,
- .Rdrnd,
- .Rdseed,
- .Sha,
- .Sse4a,
- .SlowShld,
- .Wbnoinvd,
- .X87,
- .Xsave,
- .Xsavec,
- .Xsaveopt,
- .Xsaves,
- }),
- };
-};
lib/std/target/feature/AArch64Feature.zig
@@ -1,750 +0,0 @@
-const FeatureInfo = @import("std").target.feature.FeatureInfo;
-
-pub const AArch64Feature = enum {
- Aes,
- Am,
- AggressiveFma,
- Altnzcv,
- AlternateSextloadCvtF32Pattern,
- ArithBccFusion,
- ArithCbzFusion,
- BalanceFpOps,
- Bti,
- Ccidx,
- Ccpp,
- Crc,
- Ccdp,
- CallSavedX8,
- CallSavedX9,
- CallSavedX10,
- CallSavedX11,
- CallSavedX12,
- CallSavedX13,
- CallSavedX14,
- CallSavedX15,
- CallSavedX18,
- Complxnum,
- Crypto,
- CustomCheapAsMove,
- Dit,
- DisableLatencySchedHeuristic,
- Dotprod,
- Ete,
- ExynosCheapAsMove,
- Fmi,
- Fp16fml,
- FpArmv8,
- Fptoint,
- Force32bitJumpTables,
- Fullfp16,
- FuseAes,
- FuseAddress,
- FuseArithLogic,
- FuseCsel,
- FuseCryptoEor,
- FuseLiterals,
- Jsconv,
- Lor,
- Lse,
- LslFast,
- Mpam,
- Mte,
- Neon,
- Nv,
- NoNegImmediates,
- Pa,
- Pan,
- PanRwv,
- Perfmon,
- UsePostraScheduler,
- Predres,
- PredictableSelectExpensive,
- Uaops,
- Ras,
- Rasv8_4,
- Rcpc,
- RcpcImmo,
- Rdm,
- Rand,
- ReserveX1,
- ReserveX2,
- ReserveX3,
- ReserveX4,
- ReserveX5,
- ReserveX6,
- ReserveX7,
- ReserveX9,
- ReserveX10,
- ReserveX11,
- ReserveX12,
- ReserveX13,
- ReserveX14,
- ReserveX15,
- ReserveX18,
- ReserveX20,
- ReserveX21,
- ReserveX22,
- ReserveX23,
- ReserveX24,
- ReserveX25,
- ReserveX26,
- ReserveX27,
- ReserveX28,
- Sb,
- Sel2,
- Sha2,
- Sha3,
- Sm4,
- Spe,
- Ssbs,
- Sve,
- Sve2,
- Sve2Aes,
- Sve2Bitperm,
- Sve2Sha3,
- Sve2Sm4,
- SlowMisaligned128store,
- SlowPaired128,
- SlowStrqroStore,
- Specrestrict,
- StrictAlign,
- TlbRmi,
- Tme,
- Tracev84,
- Trbe,
- TaggedGlobals,
- UseAa,
- TpidrEl1,
- TpidrEl2,
- TpidrEl3,
- UseReciprocalSquareRoot,
- Vh,
- Zcm,
- Zcz,
- ZczFp,
- ZczFpWorkaround,
- ZczGp,
- V81a,
- V82a,
- V83a,
- V84a,
- V85a,
- A35,
- A53,
- A55,
- A57,
- A65,
- A72,
- A73,
- A75,
- A76,
- Cyclone,
- Exynosm1,
- Exynosm2,
- Exynosm3,
- Exynosm4,
- Falkor,
- Kryo,
- Neoversee1,
- Neoversen1,
- Saphira,
- Tsv110,
- Thunderx,
- Thunderx2t99,
- Thunderxt81,
- Thunderxt83,
- Thunderxt88,
-
- pub fn getInfo(self: @This()) FeatureInfo(@This()) {
- return feature_infos[@enumToInt(self)];
- }
-
- pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
- FeatureInfo(@This()).createWithSubfeatures(.Aes, "aes", "Enable AES support", "aes", &[_]@This() {
- .FpArmv8,
- }),
- FeatureInfo(@This()).create(.Am, "am", "Enable v8.4-A Activity Monitors extension", "am"),
- FeatureInfo(@This()).create(.AggressiveFma, "aggressive-fma", "Enable Aggressive FMA for floating-point.", "aggressive-fma"),
- FeatureInfo(@This()).create(.Altnzcv, "altnzcv", "Enable alternative NZCV format for floating point comparisons", "altnzcv"),
- FeatureInfo(@This()).create(.AlternateSextloadCvtF32Pattern, "alternate-sextload-cvt-f32-pattern", "Use alternative pattern for sextload convert to f32", "alternate-sextload-cvt-f32-pattern"),
- FeatureInfo(@This()).create(.ArithBccFusion, "arith-bcc-fusion", "CPU fuses arithmetic+bcc operations", "arith-bcc-fusion"),
- FeatureInfo(@This()).create(.ArithCbzFusion, "arith-cbz-fusion", "CPU fuses arithmetic + cbz/cbnz operations", "arith-cbz-fusion"),
- FeatureInfo(@This()).create(.BalanceFpOps, "balance-fp-ops", "balance mix of odd and even D-registers for fp multiply(-accumulate) ops", "balance-fp-ops"),
- FeatureInfo(@This()).create(.Bti, "bti", "Enable Branch Target Identification", "bti"),
- FeatureInfo(@This()).create(.Ccidx, "ccidx", "Enable v8.3-A Extend of the CCSIDR number of sets", "ccidx"),
- FeatureInfo(@This()).create(.Ccpp, "ccpp", "Enable v8.2 data Cache Clean to Point of Persistence", "ccpp"),
- FeatureInfo(@This()).create(.Crc, "crc", "Enable ARMv8 CRC-32 checksum instructions", "crc"),
- FeatureInfo(@This()).create(.Ccdp, "ccdp", "Enable v8.5 Cache Clean to Point of Deep Persistence", "ccdp"),
- FeatureInfo(@This()).create(.CallSavedX8, "call-saved-x8", "Make X8 callee saved.", "call-saved-x8"),
- FeatureInfo(@This()).create(.CallSavedX9, "call-saved-x9", "Make X9 callee saved.", "call-saved-x9"),
- FeatureInfo(@This()).create(.CallSavedX10, "call-saved-x10", "Make X10 callee saved.", "call-saved-x10"),
- FeatureInfo(@This()).create(.CallSavedX11, "call-saved-x11", "Make X11 callee saved.", "call-saved-x11"),
- FeatureInfo(@This()).create(.CallSavedX12, "call-saved-x12", "Make X12 callee saved.", "call-saved-x12"),
- FeatureInfo(@This()).create(.CallSavedX13, "call-saved-x13", "Make X13 callee saved.", "call-saved-x13"),
- FeatureInfo(@This()).create(.CallSavedX14, "call-saved-x14", "Make X14 callee saved.", "call-saved-x14"),
- FeatureInfo(@This()).create(.CallSavedX15, "call-saved-x15", "Make X15 callee saved.", "call-saved-x15"),
- FeatureInfo(@This()).create(.CallSavedX18, "call-saved-x18", "Make X18 callee saved.", "call-saved-x18"),
- FeatureInfo(@This()).createWithSubfeatures(.Complxnum, "complxnum", "Enable v8.3-A Floating-point complex number support", "complxnum", &[_]@This() {
- .FpArmv8,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Crypto, "crypto", "Enable cryptographic instructions", "crypto", &[_]@This() {
- .FpArmv8,
- }),
- FeatureInfo(@This()).create(.CustomCheapAsMove, "custom-cheap-as-move", "Use custom handling of cheap instructions", "custom-cheap-as-move"),
- FeatureInfo(@This()).create(.Dit, "dit", "Enable v8.4-A Data Independent Timing instructions", "dit"),
- FeatureInfo(@This()).create(.DisableLatencySchedHeuristic, "disable-latency-sched-heuristic", "Disable latency scheduling heuristic", "disable-latency-sched-heuristic"),
- FeatureInfo(@This()).create(.Dotprod, "dotprod", "Enable dot product support", "dotprod"),
- FeatureInfo(@This()).createWithSubfeatures(.Ete, "ete", "Enable Embedded Trace Extension", "ete", &[_]@This() {
- .Trbe,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.ExynosCheapAsMove, "exynos-cheap-as-move", "Use Exynos specific handling of cheap instructions", "exynos-cheap-as-move", &[_]@This() {
- .CustomCheapAsMove,
- }),
- FeatureInfo(@This()).create(.Fmi, "fmi", "Enable v8.4-A Flag Manipulation Instructions", "fmi"),
- FeatureInfo(@This()).createWithSubfeatures(.Fp16fml, "fp16fml", "Enable FP16 FML instructions", "fp16fml", &[_]@This() {
- .FpArmv8,
- }),
- FeatureInfo(@This()).create(.FpArmv8, "fp-armv8", "Enable ARMv8 FP", "fp-armv8"),
- FeatureInfo(@This()).create(.Fptoint, "fptoint", "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int", "fptoint"),
- FeatureInfo(@This()).create(.Force32bitJumpTables, "force-32bit-jump-tables", "Force jump table entries to be 32-bits wide except at MinSize", "force-32bit-jump-tables"),
- FeatureInfo(@This()).createWithSubfeatures(.Fullfp16, "fullfp16", "Full FP16", "fullfp16", &[_]@This() {
- .FpArmv8,
- }),
- FeatureInfo(@This()).create(.FuseAes, "fuse-aes", "CPU fuses AES crypto operations", "fuse-aes"),
- FeatureInfo(@This()).create(.FuseAddress, "fuse-address", "CPU fuses address generation and memory operations", "fuse-address"),
- FeatureInfo(@This()).create(.FuseArithLogic, "fuse-arith-logic", "CPU fuses arithmetic and logic operations", "fuse-arith-logic"),
- FeatureInfo(@This()).create(.FuseCsel, "fuse-csel", "CPU fuses conditional select operations", "fuse-csel"),
- FeatureInfo(@This()).create(.FuseCryptoEor, "fuse-crypto-eor", "CPU fuses AES/PMULL and EOR operations", "fuse-crypto-eor"),
- FeatureInfo(@This()).create(.FuseLiterals, "fuse-literals", "CPU fuses literal generation operations", "fuse-literals"),
- FeatureInfo(@This()).createWithSubfeatures(.Jsconv, "jsconv", "Enable v8.3-A JavaScript FP conversion enchancement", "jsconv", &[_]@This() {
- .FpArmv8,
- }),
- FeatureInfo(@This()).create(.Lor, "lor", "Enables ARM v8.1 Limited Ordering Regions extension", "lor"),
- FeatureInfo(@This()).create(.Lse, "lse", "Enable ARMv8.1 Large System Extension (LSE) atomic instructions", "lse"),
- FeatureInfo(@This()).create(.LslFast, "lsl-fast", "CPU has a fastpath logical shift of up to 3 places", "lsl-fast"),
- FeatureInfo(@This()).create(.Mpam, "mpam", "Enable v8.4-A Memory system Partitioning and Monitoring extension", "mpam"),
- FeatureInfo(@This()).create(.Mte, "mte", "Enable Memory Tagging Extension", "mte"),
- FeatureInfo(@This()).createWithSubfeatures(.Neon, "neon", "Enable Advanced SIMD instructions", "neon", &[_]@This() {
- .FpArmv8,
- }),
- FeatureInfo(@This()).create(.Nv, "nv", "Enable v8.4-A Nested Virtualization Enchancement", "nv"),
- FeatureInfo(@This()).create(.NoNegImmediates, "no-neg-immediates", "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.", "no-neg-immediates"),
- FeatureInfo(@This()).create(.Pa, "pa", "Enable v8.3-A Pointer Authentication enchancement", "pa"),
- FeatureInfo(@This()).create(.Pan, "pan", "Enables ARM v8.1 Privileged Access-Never extension", "pan"),
- FeatureInfo(@This()).createWithSubfeatures(.PanRwv, "pan-rwv", "Enable v8.2 PAN s1e1R and s1e1W Variants", "pan-rwv", &[_]@This() {
- .Pan,
- }),
- FeatureInfo(@This()).create(.Perfmon, "perfmon", "Enable ARMv8 PMUv3 Performance Monitors extension", "perfmon"),
- FeatureInfo(@This()).create(.UsePostraScheduler, "use-postra-scheduler", "Schedule again after register allocation", "use-postra-scheduler"),
- FeatureInfo(@This()).create(.Predres, "predres", "Enable v8.5a execution and data prediction invalidation instructions", "predres"),
- FeatureInfo(@This()).create(.PredictableSelectExpensive, "predictable-select-expensive", "Prefer likely predicted branches over selects", "predictable-select-expensive"),
- FeatureInfo(@This()).create(.Uaops, "uaops", "Enable v8.2 UAO PState", "uaops"),
- FeatureInfo(@This()).create(.Ras, "ras", "Enable ARMv8 Reliability, Availability and Serviceability Extensions", "ras"),
- FeatureInfo(@This()).createWithSubfeatures(.Rasv8_4, "rasv8_4", "Enable v8.4-A Reliability, Availability and Serviceability extension", "rasv8_4", &[_]@This() {
- .Ras,
- }),
- FeatureInfo(@This()).create(.Rcpc, "rcpc", "Enable support for RCPC extension", "rcpc"),
- FeatureInfo(@This()).createWithSubfeatures(.RcpcImmo, "rcpc-immo", "Enable v8.4-A RCPC instructions with Immediate Offsets", "rcpc-immo", &[_]@This() {
- .Rcpc,
- }),
- FeatureInfo(@This()).create(.Rdm, "rdm", "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions", "rdm"),
- FeatureInfo(@This()).create(.Rand, "rand", "Enable Random Number generation instructions", "rand"),
- FeatureInfo(@This()).create(.ReserveX1, "reserve-x1", "Reserve X1, making it unavailable as a GPR", "reserve-x1"),
- FeatureInfo(@This()).create(.ReserveX2, "reserve-x2", "Reserve X2, making it unavailable as a GPR", "reserve-x2"),
- FeatureInfo(@This()).create(.ReserveX3, "reserve-x3", "Reserve X3, making it unavailable as a GPR", "reserve-x3"),
- FeatureInfo(@This()).create(.ReserveX4, "reserve-x4", "Reserve X4, making it unavailable as a GPR", "reserve-x4"),
- FeatureInfo(@This()).create(.ReserveX5, "reserve-x5", "Reserve X5, making it unavailable as a GPR", "reserve-x5"),
- FeatureInfo(@This()).create(.ReserveX6, "reserve-x6", "Reserve X6, making it unavailable as a GPR", "reserve-x6"),
- FeatureInfo(@This()).create(.ReserveX7, "reserve-x7", "Reserve X7, making it unavailable as a GPR", "reserve-x7"),
- FeatureInfo(@This()).create(.ReserveX9, "reserve-x9", "Reserve X9, making it unavailable as a GPR", "reserve-x9"),
- FeatureInfo(@This()).create(.ReserveX10, "reserve-x10", "Reserve X10, making it unavailable as a GPR", "reserve-x10"),
- FeatureInfo(@This()).create(.ReserveX11, "reserve-x11", "Reserve X11, making it unavailable as a GPR", "reserve-x11"),
- FeatureInfo(@This()).create(.ReserveX12, "reserve-x12", "Reserve X12, making it unavailable as a GPR", "reserve-x12"),
- FeatureInfo(@This()).create(.ReserveX13, "reserve-x13", "Reserve X13, making it unavailable as a GPR", "reserve-x13"),
- FeatureInfo(@This()).create(.ReserveX14, "reserve-x14", "Reserve X14, making it unavailable as a GPR", "reserve-x14"),
- FeatureInfo(@This()).create(.ReserveX15, "reserve-x15", "Reserve X15, making it unavailable as a GPR", "reserve-x15"),
- FeatureInfo(@This()).create(.ReserveX18, "reserve-x18", "Reserve X18, making it unavailable as a GPR", "reserve-x18"),
- FeatureInfo(@This()).create(.ReserveX20, "reserve-x20", "Reserve X20, making it unavailable as a GPR", "reserve-x20"),
- FeatureInfo(@This()).create(.ReserveX21, "reserve-x21", "Reserve X21, making it unavailable as a GPR", "reserve-x21"),
- FeatureInfo(@This()).create(.ReserveX22, "reserve-x22", "Reserve X22, making it unavailable as a GPR", "reserve-x22"),
- FeatureInfo(@This()).create(.ReserveX23, "reserve-x23", "Reserve X23, making it unavailable as a GPR", "reserve-x23"),
- FeatureInfo(@This()).create(.ReserveX24, "reserve-x24", "Reserve X24, making it unavailable as a GPR", "reserve-x24"),
- FeatureInfo(@This()).create(.ReserveX25, "reserve-x25", "Reserve X25, making it unavailable as a GPR", "reserve-x25"),
- FeatureInfo(@This()).create(.ReserveX26, "reserve-x26", "Reserve X26, making it unavailable as a GPR", "reserve-x26"),
- FeatureInfo(@This()).create(.ReserveX27, "reserve-x27", "Reserve X27, making it unavailable as a GPR", "reserve-x27"),
- FeatureInfo(@This()).create(.ReserveX28, "reserve-x28", "Reserve X28, making it unavailable as a GPR", "reserve-x28"),
- FeatureInfo(@This()).create(.Sb, "sb", "Enable v8.5 Speculation Barrier", "sb"),
- FeatureInfo(@This()).create(.Sel2, "sel2", "Enable v8.4-A Secure Exception Level 2 extension", "sel2"),
- FeatureInfo(@This()).createWithSubfeatures(.Sha2, "sha2", "Enable SHA1 and SHA256 support", "sha2", &[_]@This() {
- .FpArmv8,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Sha3, "sha3", "Enable SHA512 and SHA3 support", "sha3", &[_]@This() {
- .FpArmv8,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Sm4, "sm4", "Enable SM3 and SM4 support", "sm4", &[_]@This() {
- .FpArmv8,
- }),
- FeatureInfo(@This()).create(.Spe, "spe", "Enable Statistical Profiling extension", "spe"),
- FeatureInfo(@This()).create(.Ssbs, "ssbs", "Enable Speculative Store Bypass Safe bit", "ssbs"),
- FeatureInfo(@This()).create(.Sve, "sve", "Enable Scalable Vector Extension (SVE) instructions", "sve"),
- FeatureInfo(@This()).createWithSubfeatures(.Sve2, "sve2", "Enable Scalable Vector Extension 2 (SVE2) instructions", "sve2", &[_]@This() {
- .Sve,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Sve2Aes, "sve2-aes", "Enable AES SVE2 instructions", "sve2-aes", &[_]@This() {
- .FpArmv8,
- .Sve,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Sve2Bitperm, "sve2-bitperm", "Enable bit permutation SVE2 instructions", "sve2-bitperm", &[_]@This() {
- .Sve,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Sve2Sha3, "sve2-sha3", "Enable SHA3 SVE2 instructions", "sve2-sha3", &[_]@This() {
- .FpArmv8,
- .Sve,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Sve2Sm4, "sve2-sm4", "Enable SM4 SVE2 instructions", "sve2-sm4", &[_]@This() {
- .FpArmv8,
- .Sve,
- }),
- FeatureInfo(@This()).create(.SlowMisaligned128store, "slow-misaligned-128store", "Misaligned 128 bit stores are slow", "slow-misaligned-128store"),
- FeatureInfo(@This()).create(.SlowPaired128, "slow-paired-128", "Paired 128 bit loads and stores are slow", "slow-paired-128"),
- FeatureInfo(@This()).create(.SlowStrqroStore, "slow-strqro-store", "STR of Q register with register offset is slow", "slow-strqro-store"),
- FeatureInfo(@This()).create(.Specrestrict, "specrestrict", "Enable architectural speculation restriction", "specrestrict"),
- FeatureInfo(@This()).create(.StrictAlign, "strict-align", "Disallow all unaligned memory access", "strict-align"),
- FeatureInfo(@This()).create(.TlbRmi, "tlb-rmi", "Enable v8.4-A TLB Range and Maintenance Instructions", "tlb-rmi"),
- FeatureInfo(@This()).create(.Tme, "tme", "Enable Transactional Memory Extension", "tme"),
- FeatureInfo(@This()).create(.Tracev84, "tracev8.4", "Enable v8.4-A Trace extension", "tracev8.4"),
- FeatureInfo(@This()).create(.Trbe, "trbe", "Enable Trace Buffer Extension", "trbe"),
- FeatureInfo(@This()).create(.TaggedGlobals, "tagged-globals", "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits", "tagged-globals"),
- FeatureInfo(@This()).create(.UseAa, "use-aa", "Use alias analysis during codegen", "use-aa"),
- FeatureInfo(@This()).create(.TpidrEl1, "tpidr-el1", "Permit use of TPIDR_EL1 for the TLS base", "tpidr-el1"),
- FeatureInfo(@This()).create(.TpidrEl2, "tpidr-el2", "Permit use of TPIDR_EL2 for the TLS base", "tpidr-el2"),
- FeatureInfo(@This()).create(.TpidrEl3, "tpidr-el3", "Permit use of TPIDR_EL3 for the TLS base", "tpidr-el3"),
- FeatureInfo(@This()).create(.UseReciprocalSquareRoot, "use-reciprocal-square-root", "Use the reciprocal square root approximation", "use-reciprocal-square-root"),
- FeatureInfo(@This()).create(.Vh, "vh", "Enables ARM v8.1 Virtual Host extension", "vh"),
- FeatureInfo(@This()).create(.Zcm, "zcm", "Has zero-cycle register moves", "zcm"),
- FeatureInfo(@This()).createWithSubfeatures(.Zcz, "zcz", "Has zero-cycle zeroing instructions", "zcz", &[_]@This() {
- .ZczGp,
- .ZczFp,
- }),
- FeatureInfo(@This()).create(.ZczFp, "zcz-fp", "Has zero-cycle zeroing instructions for FP registers", "zcz-fp"),
- FeatureInfo(@This()).create(.ZczFpWorkaround, "zcz-fp-workaround", "The zero-cycle floating-point zeroing instruction has a bug", "zcz-fp-workaround"),
- FeatureInfo(@This()).create(.ZczGp, "zcz-gp", "Has zero-cycle zeroing instructions for generic registers", "zcz-gp"),
- FeatureInfo(@This()).createWithSubfeatures(.V81a, "v8.1a", "Support ARM v8.1a instructions", "v8.1a", &[_]@This() {
- .Lse,
- .Rdm,
- .Crc,
- .Lor,
- .Pan,
- .Vh,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.V82a, "v8.2a", "Support ARM v8.2a instructions", "v8.2a", &[_]@This() {
- .Lse,
- .Rdm,
- .Pan,
- .Crc,
- .Lor,
- .Uaops,
- .Ras,
- .Ccpp,
- .Vh,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.V83a, "v8.3a", "Support ARM v8.3a instructions", "v8.3a", &[_]@This() {
- .Lse,
- .Vh,
- .Pa,
- .Rdm,
- .Pan,
- .Crc,
- .Lor,
- .Uaops,
- .Ras,
- .Rcpc,
- .Ccpp,
- .Ccidx,
- .FpArmv8,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.V84a, "v8.4a", "Support ARM v8.4a instructions", "v8.4a", &[_]@This() {
- .Rdm,
- .Dit,
- .Am,
- .Ras,
- .Rcpc,
- .Sel2,
- .Ccpp,
- .Pa,
- .Pan,
- .Uaops,
- .Tracev84,
- .Mpam,
- .Lse,
- .Nv,
- .Dotprod,
- .TlbRmi,
- .Lor,
- .Ccidx,
- .FpArmv8,
- .Crc,
- .Fmi,
- .Vh,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.V85a, "v8.5a", "Support ARM v8.5a instructions", "v8.5a", &[_]@This() {
- .Vh,
- .Rdm,
- .Dit,
- .Am,
- .Ssbs,
- .Specrestrict,
- .Ras,
- .Rcpc,
- .Sel2,
- .Ccpp,
- .Pa,
- .Bti,
- .Ccdp,
- .Pan,
- .Uaops,
- .Tracev84,
- .Mpam,
- .Lse,
- .Sb,
- .Nv,
- .Altnzcv,
- .Dotprod,
- .TlbRmi,
- .Lor,
- .Ccidx,
- .Predres,
- .Crc,
- .Fptoint,
- .Fmi,
- .FpArmv8,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.A35, "a35", "Cortex-A35 ARM processors", "a35", &[_]@This() {
- .Perfmon,
- .FpArmv8,
- .Crc,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.A53, "a53", "Cortex-A53 ARM processors", "a53", &[_]@This() {
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .CustomCheapAsMove,
- .BalanceFpOps,
- .UseAa,
- .FpArmv8,
- .FuseAes,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.A55, "a55", "Cortex-A55 ARM processors", "a55", &[_]@This() {
- .Lse,
- .Vh,
- .Rdm,
- .Perfmon,
- .Pan,
- .Dotprod,
- .Crc,
- .Lor,
- .Uaops,
- .Ras,
- .Rcpc,
- .Ccpp,
- .FpArmv8,
- .FuseAes,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.A57, "a57", "Cortex-A57 ARM processors", "a57", &[_]@This() {
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .PredictableSelectExpensive,
- .CustomCheapAsMove,
- .BalanceFpOps,
- .FuseLiterals,
- .FpArmv8,
- .FuseAes,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.A65, "a65", "Cortex-A65 ARM processors", "a65", &[_]@This() {
- .Lse,
- .Vh,
- .Rdm,
- .Pan,
- .Dotprod,
- .Crc,
- .Ssbs,
- .Lor,
- .Uaops,
- .Ras,
- .Rcpc,
- .Ccpp,
- .FpArmv8,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.A72, "a72", "Cortex-A72 ARM processors", "a72", &[_]@This() {
- .Perfmon,
- .FpArmv8,
- .Crc,
- .FuseAes,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.A73, "a73", "Cortex-A73 ARM processors", "a73", &[_]@This() {
- .Perfmon,
- .FpArmv8,
- .Crc,
- .FuseAes,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.A75, "a75", "Cortex-A75 ARM processors", "a75", &[_]@This() {
- .Lse,
- .Vh,
- .Rdm,
- .Perfmon,
- .Pan,
- .Dotprod,
- .Crc,
- .Lor,
- .Uaops,
- .Ras,
- .Rcpc,
- .Ccpp,
- .FpArmv8,
- .FuseAes,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.A76, "a76", "Cortex-A76 ARM processors", "a76", &[_]@This() {
- .Lse,
- .Vh,
- .Rdm,
- .Pan,
- .Dotprod,
- .Crc,
- .Ssbs,
- .Lor,
- .Uaops,
- .Ras,
- .Rcpc,
- .Ccpp,
- .FpArmv8,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Cyclone, "cyclone", "Cyclone", "cyclone", &[_]@This() {
- .ArithBccFusion,
- .ArithCbzFusion,
- .ZczFp,
- .AlternateSextloadCvtF32Pattern,
- .DisableLatencySchedHeuristic,
- .Perfmon,
- .ZczGp,
- .ZczFpWorkaround,
- .Zcm,
- .FpArmv8,
- .FuseCryptoEor,
- .FuseAes,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Exynosm1, "exynosm1", "Samsung Exynos-M1 processors", "exynosm1", &[_]@This() {
- .ZczFp,
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .UseReciprocalSquareRoot,
- .CustomCheapAsMove,
- .Force32bitJumpTables,
- .SlowMisaligned128store,
- .FpArmv8,
- .SlowPaired128,
- .FuseAes,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Exynosm2, "exynosm2", "Samsung Exynos-M2 processors", "exynosm2", &[_]@This() {
- .ZczFp,
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .CustomCheapAsMove,
- .Force32bitJumpTables,
- .SlowMisaligned128store,
- .FpArmv8,
- .SlowPaired128,
- .FuseAes,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Exynosm3, "exynosm3", "Samsung Exynos-M3 processors", "exynosm3", &[_]@This() {
- .FuseCsel,
- .ZczFp,
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .PredictableSelectExpensive,
- .CustomCheapAsMove,
- .Force32bitJumpTables,
- .FuseLiterals,
- .FuseAddress,
- .LslFast,
- .FpArmv8,
- .FuseAes,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Exynosm4, "exynosm4", "Samsung Exynos-M4 processors", "exynosm4", &[_]@This() {
- .ArithBccFusion,
- .Vh,
- .ArithCbzFusion,
- .ZczFp,
- .Rdm,
- .UsePostraScheduler,
- .Ras,
- .Force32bitJumpTables,
- .Ccpp,
- .FuseCsel,
- .Pan,
- .Uaops,
- .FuseLiterals,
- .LslFast,
- .Lse,
- .Perfmon,
- .Dotprod,
- .Lor,
- .FuseArithLogic,
- .Crc,
- .CustomCheapAsMove,
- .FuseAddress,
- .ZczGp,
- .FpArmv8,
- .FuseAes,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Falkor, "falkor", "Qualcomm Falkor processors", "falkor", &[_]@This() {
- .ZczFp,
- .Rdm,
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .PredictableSelectExpensive,
- .CustomCheapAsMove,
- .ZczGp,
- .FpArmv8,
- .SlowStrqroStore,
- .LslFast,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Kryo, "kryo", "Qualcomm Kryo processors", "kryo", &[_]@This() {
- .ZczFp,
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .PredictableSelectExpensive,
- .CustomCheapAsMove,
- .ZczGp,
- .FpArmv8,
- .LslFast,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Neoversee1, "neoversee1", "Neoverse E1 ARM processors", "neoversee1", &[_]@This() {
- .Lse,
- .Vh,
- .Rdm,
- .Pan,
- .Dotprod,
- .Crc,
- .Ssbs,
- .Lor,
- .Uaops,
- .Ras,
- .Rcpc,
- .Ccpp,
- .FpArmv8,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Neoversen1, "neoversen1", "Neoverse N1 ARM processors", "neoversen1", &[_]@This() {
- .Lse,
- .Spe,
- .Vh,
- .Rdm,
- .Pan,
- .Dotprod,
- .Crc,
- .Ssbs,
- .Lor,
- .Uaops,
- .Ras,
- .Rcpc,
- .Ccpp,
- .FpArmv8,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Saphira, "saphira", "Qualcomm Saphira processors", "saphira", &[_]@This() {
- .Spe,
- .Vh,
- .ZczFp,
- .Rdm,
- .UsePostraScheduler,
- .Dit,
- .Am,
- .Ras,
- .Rcpc,
- .Sel2,
- .Ccpp,
- .Pa,
- .Pan,
- .Uaops,
- .Tracev84,
- .Mpam,
- .LslFast,
- .Lse,
- .Nv,
- .Perfmon,
- .Dotprod,
- .TlbRmi,
- .Lor,
- .Ccidx,
- .PredictableSelectExpensive,
- .Crc,
- .CustomCheapAsMove,
- .Fmi,
- .ZczGp,
- .FpArmv8,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Tsv110, "tsv110", "HiSilicon TS-V110 processors", "tsv110", &[_]@This() {
- .Lse,
- .Spe,
- .Vh,
- .Rdm,
- .Perfmon,
- .UsePostraScheduler,
- .Pan,
- .Dotprod,
- .Crc,
- .Lor,
- .Uaops,
- .CustomCheapAsMove,
- .Ras,
- .Ccpp,
- .FpArmv8,
- .FuseAes,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Thunderx, "thunderx", "Cavium ThunderX processors", "thunderx", &[_]@This() {
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .FpArmv8,
- .PredictableSelectExpensive,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Thunderx2t99, "thunderx2t99", "Cavium ThunderX2 processors", "thunderx2t99", &[_]@This() {
- .Lse,
- .ArithBccFusion,
- .Vh,
- .Rdm,
- .UsePostraScheduler,
- .Crc,
- .Lor,
- .Pan,
- .AggressiveFma,
- .FpArmv8,
- .PredictableSelectExpensive,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Thunderxt81, "thunderxt81", "Cavium ThunderX processors", "thunderxt81", &[_]@This() {
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .FpArmv8,
- .PredictableSelectExpensive,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Thunderxt83, "thunderxt83", "Cavium ThunderX processors", "thunderxt83", &[_]@This() {
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .FpArmv8,
- .PredictableSelectExpensive,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Thunderxt88, "thunderxt88", "Cavium ThunderX processors", "thunderxt88", &[_]@This() {
- .Perfmon,
- .UsePostraScheduler,
- .Crc,
- .FpArmv8,
- .PredictableSelectExpensive,
- }),
- };
-};
lib/std/target/feature/AmdGpuFeature.zig
@@ -1,343 +0,0 @@
-const FeatureInfo = @import("std").target.feature.FeatureInfo;
-
-pub const AmdGpuFeature = enum {
- BitInsts16,
- AddNoCarryInsts,
- ApertureRegs,
- AtomicFaddInsts,
- AutoWaitcntBeforeBarrier,
- CiInsts,
- CodeObjectV3,
- Cumode,
- DlInsts,
- Dpp,
- Dpp8,
- NoSramEccSupport,
- NoXnackSupport,
- Dot1Insts,
- Dot2Insts,
- Dot3Insts,
- Dot4Insts,
- Dot5Insts,
- Dot6Insts,
- DumpCode,
- Dumpcode,
- EnableDs128,
- LoadStoreOpt,
- EnablePrtStrictNull,
- SiScheduler,
- UnsafeDsOffsetFolding,
- Fmaf,
- Fp16Denormals,
- Fp32Denormals,
- Fp64,
- Fp64Denormals,
- Fp64Fp16Denormals,
- FpExceptions,
- FastFmaf,
- FlatAddressSpace,
- FlatForGlobal,
- FlatGlobalInsts,
- FlatInstOffsets,
- FlatScratchInsts,
- FlatSegmentOffsetBug,
- FmaMixInsts,
- Gcn3Encoding,
- Gfx7Gfx8Gfx9Insts,
- Gfx8Insts,
- Gfx9,
- Gfx9Insts,
- Gfx10,
- Gfx10Insts,
- InstFwdPrefetchBug,
- IntClampInsts,
- Inv2piInlineImm,
- Ldsbankcount16,
- Ldsbankcount32,
- LdsBranchVmemWarHazard,
- LdsMisalignedBug,
- Localmemorysize0,
- Localmemorysize32768,
- Localmemorysize65536,
- MaiInsts,
- MfmaInlineLiteralBug,
- MimgR128,
- MadMixInsts,
- MaxPrivateElementSize4,
- MaxPrivateElementSize8,
- MaxPrivateElementSize16,
- Movrel,
- NsaEncoding,
- NsaToVmemBug,
- NoDataDepHazard,
- NoSdstCmpx,
- Offset3fBug,
- PkFmacF16Inst,
- PromoteAlloca,
- R128A16,
- RegisterBanking,
- Sdwa,
- SdwaMav,
- SdwaOmod,
- SdwaOutModsVopc,
- SdwaScalar,
- SdwaSdst,
- SgprInitBug,
- SmemToVectorWriteHazard,
- SMemrealtime,
- SramEcc,
- ScalarAtomics,
- ScalarFlatScratchInsts,
- ScalarStores,
- SeaIslands,
- SouthernIslands,
- TrapHandler,
- TrigReducedRange,
- UnalignedBufferAccess,
- UnalignedScratchAccess,
- UnpackedD16Vmem,
- VgprIndexMode,
- VmemToScalarWriteHazard,
- Vop3Literal,
- Vop3p,
- VcmpxExecWarHazard,
- VcmpxPermlaneHazard,
- VolcanicIslands,
- Vscnt,
- Wavefrontsize16,
- Wavefrontsize32,
- Wavefrontsize64,
- Xnack,
- HalfRate64Ops,
-
- pub fn getInfo(self: @This()) FeatureInfo(@This()) {
- return feature_infos[@enumToInt(self)];
- }
-
- pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
- FeatureInfo(@This()).create(.BitInsts16, "16-bit-insts", "Has i16/f16 instructions", "16-bit-insts"),
- FeatureInfo(@This()).create(.AddNoCarryInsts, "add-no-carry-insts", "Have VALU add/sub instructions without carry out", "add-no-carry-insts"),
- FeatureInfo(@This()).create(.ApertureRegs, "aperture-regs", "Has Memory Aperture Base and Size Registers", "aperture-regs"),
- FeatureInfo(@This()).create(.AtomicFaddInsts, "atomic-fadd-insts", "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, global_atomic_pk_add_f16 instructions", "atomic-fadd-insts"),
- FeatureInfo(@This()).create(.AutoWaitcntBeforeBarrier, "auto-waitcnt-before-barrier", "Hardware automatically inserts waitcnt before barrier", "auto-waitcnt-before-barrier"),
- FeatureInfo(@This()).create(.CiInsts, "ci-insts", "Additional instructions for CI+", "ci-insts"),
- FeatureInfo(@This()).create(.CodeObjectV3, "code-object-v3", "Generate code object version 3", "code-object-v3"),
- FeatureInfo(@This()).create(.Cumode, "cumode", "Enable CU wavefront execution mode", "cumode"),
- FeatureInfo(@This()).create(.DlInsts, "dl-insts", "Has v_fmac_f32 and v_xnor_b32 instructions", "dl-insts"),
- FeatureInfo(@This()).create(.Dpp, "dpp", "Support DPP (Data Parallel Primitives) extension", "dpp"),
- FeatureInfo(@This()).create(.Dpp8, "dpp8", "Support DPP8 (Data Parallel Primitives) extension", "dpp8"),
- FeatureInfo(@This()).create(.NoSramEccSupport, "no-sram-ecc-support", "Hardware does not support SRAM ECC", "no-sram-ecc-support"),
- FeatureInfo(@This()).create(.NoXnackSupport, "no-xnack-support", "Hardware does not support XNACK", "no-xnack-support"),
- FeatureInfo(@This()).create(.Dot1Insts, "dot1-insts", "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions", "dot1-insts"),
- FeatureInfo(@This()).create(.Dot2Insts, "dot2-insts", "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions", "dot2-insts"),
- FeatureInfo(@This()).create(.Dot3Insts, "dot3-insts", "Has v_dot8c_i32_i4 instruction", "dot3-insts"),
- FeatureInfo(@This()).create(.Dot4Insts, "dot4-insts", "Has v_dot2c_i32_i16 instruction", "dot4-insts"),
- FeatureInfo(@This()).create(.Dot5Insts, "dot5-insts", "Has v_dot2c_f32_f16 instruction", "dot5-insts"),
- FeatureInfo(@This()).create(.Dot6Insts, "dot6-insts", "Has v_dot4c_i32_i8 instruction", "dot6-insts"),
- FeatureInfo(@This()).create(.DumpCode, "DumpCode", "Dump MachineInstrs in the CodeEmitter", "DumpCode"),
- FeatureInfo(@This()).create(.Dumpcode, "dumpcode", "Dump MachineInstrs in the CodeEmitter", "dumpcode"),
- FeatureInfo(@This()).create(.EnableDs128, "enable-ds128", "Use ds_{read|write}_b128", "enable-ds128"),
- FeatureInfo(@This()).create(.LoadStoreOpt, "load-store-opt", "Enable SI load/store optimizer pass", "load-store-opt"),
- FeatureInfo(@This()).create(.EnablePrtStrictNull, "enable-prt-strict-null", "Enable zeroing of result registers for sparse texture fetches", "enable-prt-strict-null"),
- FeatureInfo(@This()).create(.SiScheduler, "si-scheduler", "Enable SI Machine Scheduler", "si-scheduler"),
- FeatureInfo(@This()).create(.UnsafeDsOffsetFolding, "unsafe-ds-offset-folding", "Force using DS instruction immediate offsets on SI", "unsafe-ds-offset-folding"),
- FeatureInfo(@This()).create(.Fmaf, "fmaf", "Enable single precision FMA (not as fast as mul+add, but fused)", "fmaf"),
- FeatureInfo(@This()).createWithSubfeatures(.Fp16Denormals, "fp16-denormals", "Enable half precision denormal handling", "fp16-denormals", &[_]@This() {
- .Fp64,
- }),
- FeatureInfo(@This()).create(.Fp32Denormals, "fp32-denormals", "Enable single precision denormal handling", "fp32-denormals"),
- FeatureInfo(@This()).create(.Fp64, "fp64", "Enable double precision operations", "fp64"),
- FeatureInfo(@This()).createWithSubfeatures(.Fp64Denormals, "fp64-denormals", "Enable double and half precision denormal handling", "fp64-denormals", &[_]@This() {
- .Fp64,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Fp64Fp16Denormals, "fp64-fp16-denormals", "Enable double and half precision denormal handling", "fp64-fp16-denormals", &[_]@This() {
- .Fp64,
- }),
- FeatureInfo(@This()).create(.FpExceptions, "fp-exceptions", "Enable floating point exceptions", "fp-exceptions"),
- FeatureInfo(@This()).create(.FastFmaf, "fast-fmaf", "Assuming f32 fma is at least as fast as mul + add", "fast-fmaf"),
- FeatureInfo(@This()).create(.FlatAddressSpace, "flat-address-space", "Support flat address space", "flat-address-space"),
- FeatureInfo(@This()).create(.FlatForGlobal, "flat-for-global", "Force to generate flat instruction for global", "flat-for-global"),
- FeatureInfo(@This()).create(.FlatGlobalInsts, "flat-global-insts", "Have global_* flat memory instructions", "flat-global-insts"),
- FeatureInfo(@This()).create(.FlatInstOffsets, "flat-inst-offsets", "Flat instructions have immediate offset addressing mode", "flat-inst-offsets"),
- FeatureInfo(@This()).create(.FlatScratchInsts, "flat-scratch-insts", "Have scratch_* flat memory instructions", "flat-scratch-insts"),
- FeatureInfo(@This()).create(.FlatSegmentOffsetBug, "flat-segment-offset-bug", "GFX10 bug, inst_offset ignored in flat segment", "flat-segment-offset-bug"),
- FeatureInfo(@This()).create(.FmaMixInsts, "fma-mix-insts", "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions", "fma-mix-insts"),
- FeatureInfo(@This()).create(.Gcn3Encoding, "gcn3-encoding", "Encoding format for VI", "gcn3-encoding"),
- FeatureInfo(@This()).create(.Gfx7Gfx8Gfx9Insts, "gfx7-gfx8-gfx9-insts", "Instructions shared in GFX7, GFX8, GFX9", "gfx7-gfx8-gfx9-insts"),
- FeatureInfo(@This()).create(.Gfx8Insts, "gfx8-insts", "Additional instructions for GFX8+", "gfx8-insts"),
- FeatureInfo(@This()).createWithSubfeatures(.Gfx9, "gfx9", "GFX9 GPU generation", "gfx9", &[_]@This() {
- .ApertureRegs,
- .IntClampInsts,
- .SdwaOmod,
- .SdwaScalar,
- .AddNoCarryInsts,
- .ScalarAtomics,
- .SMemrealtime,
- .Gcn3Encoding,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .Wavefrontsize64,
- .SdwaSdst,
- .FlatInstOffsets,
- .ScalarStores,
- .Gfx7Gfx8Gfx9Insts,
- .R128A16,
- .Dpp,
- .Localmemorysize65536,
- .Vop3p,
- .BitInsts16,
- .VgprIndexMode,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .Gfx9Insts,
- .ScalarFlatScratchInsts,
- .FlatGlobalInsts,
- .FlatScratchInsts,
- .Fp64,
- .FastFmaf,
- }),
- FeatureInfo(@This()).create(.Gfx9Insts, "gfx9-insts", "Additional instructions for GFX9+", "gfx9-insts"),
- FeatureInfo(@This()).createWithSubfeatures(.Gfx10, "gfx10", "GFX10 GPU generation", "gfx10", &[_]@This() {
- .Vscnt,
- .ApertureRegs,
- .Gfx10Insts,
- .IntClampInsts,
- .PkFmacF16Inst,
- .SdwaOmod,
- .SdwaScalar,
- .AddNoCarryInsts,
- .Movrel,
- .SMemrealtime,
- .NoSdstCmpx,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .NoSramEccSupport,
- .SdwaSdst,
- .FlatInstOffsets,
- .RegisterBanking,
- .Dpp,
- .Localmemorysize65536,
- .Vop3p,
- .BitInsts16,
- .Dpp8,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .Gfx9Insts,
- .FmaMixInsts,
- .MimgR128,
- .Vop3Literal,
- .FlatGlobalInsts,
- .FlatScratchInsts,
- .Fp64,
- .FastFmaf,
- .NoDataDepHazard,
- }),
- FeatureInfo(@This()).create(.Gfx10Insts, "gfx10-insts", "Additional instructions for GFX10+", "gfx10-insts"),
- FeatureInfo(@This()).create(.InstFwdPrefetchBug, "inst-fwd-prefetch-bug", "S_INST_PREFETCH instruction causes shader to hang", "inst-fwd-prefetch-bug"),
- FeatureInfo(@This()).create(.IntClampInsts, "int-clamp-insts", "Support clamp for integer destination", "int-clamp-insts"),
- FeatureInfo(@This()).create(.Inv2piInlineImm, "inv-2pi-inline-imm", "Has 1 / (2 * pi) as inline immediate", "inv-2pi-inline-imm"),
- FeatureInfo(@This()).create(.Ldsbankcount16, "ldsbankcount16", "The number of LDS banks per compute unit.", "ldsbankcount16"),
- FeatureInfo(@This()).create(.Ldsbankcount32, "ldsbankcount32", "The number of LDS banks per compute unit.", "ldsbankcount32"),
- FeatureInfo(@This()).create(.LdsBranchVmemWarHazard, "lds-branch-vmem-war-hazard", "Switching between LDS and VMEM-tex not waiting VM_VSRC=0", "lds-branch-vmem-war-hazard"),
- FeatureInfo(@This()).create(.LdsMisalignedBug, "lds-misaligned-bug", "Some GFX10 bug with misaligned multi-dword LDS access in WGP mode", "lds-misaligned-bug"),
- FeatureInfo(@This()).create(.Localmemorysize0, "localmemorysize0", "The size of local memory in bytes", "localmemorysize0"),
- FeatureInfo(@This()).create(.Localmemorysize32768, "localmemorysize32768", "The size of local memory in bytes", "localmemorysize32768"),
- FeatureInfo(@This()).create(.Localmemorysize65536, "localmemorysize65536", "The size of local memory in bytes", "localmemorysize65536"),
- FeatureInfo(@This()).create(.MaiInsts, "mai-insts", "Has mAI instructions", "mai-insts"),
- FeatureInfo(@This()).create(.MfmaInlineLiteralBug, "mfma-inline-literal-bug", "MFMA cannot use inline literal as SrcC", "mfma-inline-literal-bug"),
- FeatureInfo(@This()).create(.MimgR128, "mimg-r128", "Support 128-bit texture resources", "mimg-r128"),
- FeatureInfo(@This()).create(.MadMixInsts, "mad-mix-insts", "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions", "mad-mix-insts"),
- FeatureInfo(@This()).create(.MaxPrivateElementSize4, "max-private-element-size-4", "Maximum private access size may be 4", "max-private-element-size-4"),
- FeatureInfo(@This()).create(.MaxPrivateElementSize8, "max-private-element-size-8", "Maximum private access size may be 8", "max-private-element-size-8"),
- FeatureInfo(@This()).create(.MaxPrivateElementSize16, "max-private-element-size-16", "Maximum private access size may be 16", "max-private-element-size-16"),
- FeatureInfo(@This()).create(.Movrel, "movrel", "Has v_movrel*_b32 instructions", "movrel"),
- FeatureInfo(@This()).create(.NsaEncoding, "nsa-encoding", "Support NSA encoding for image instructions", "nsa-encoding"),
- FeatureInfo(@This()).create(.NsaToVmemBug, "nsa-to-vmem-bug", "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero", "nsa-to-vmem-bug"),
- FeatureInfo(@This()).create(.NoDataDepHazard, "no-data-dep-hazard", "Does not need SW waitstates", "no-data-dep-hazard"),
- FeatureInfo(@This()).create(.NoSdstCmpx, "no-sdst-cmpx", "V_CMPX does not write VCC/SGPR in addition to EXEC", "no-sdst-cmpx"),
- FeatureInfo(@This()).create(.Offset3fBug, "offset-3f-bug", "Branch offset of 3f hardware bug", "offset-3f-bug"),
- FeatureInfo(@This()).create(.PkFmacF16Inst, "pk-fmac-f16-inst", "Has v_pk_fmac_f16 instruction", "pk-fmac-f16-inst"),
- FeatureInfo(@This()).create(.PromoteAlloca, "promote-alloca", "Enable promote alloca pass", "promote-alloca"),
- FeatureInfo(@This()).create(.R128A16, "r128-a16", "Support 16 bit coordindates/gradients/lod/clamp/mip types on gfx9", "r128-a16"),
- FeatureInfo(@This()).create(.RegisterBanking, "register-banking", "Has register banking", "register-banking"),
- FeatureInfo(@This()).create(.Sdwa, "sdwa", "Support SDWA (Sub-DWORD Addressing) extension", "sdwa"),
- FeatureInfo(@This()).create(.SdwaMav, "sdwa-mav", "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension", "sdwa-mav"),
- FeatureInfo(@This()).create(.SdwaOmod, "sdwa-omod", "Support OMod with SDWA (Sub-DWORD Addressing) extension", "sdwa-omod"),
- FeatureInfo(@This()).create(.SdwaOutModsVopc, "sdwa-out-mods-vopc", "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension", "sdwa-out-mods-vopc"),
- FeatureInfo(@This()).create(.SdwaScalar, "sdwa-scalar", "Support scalar register with SDWA (Sub-DWORD Addressing) extension", "sdwa-scalar"),
- FeatureInfo(@This()).create(.SdwaSdst, "sdwa-sdst", "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension", "sdwa-sdst"),
- FeatureInfo(@This()).create(.SgprInitBug, "sgpr-init-bug", "VI SGPR initialization bug requiring a fixed SGPR allocation size", "sgpr-init-bug"),
- FeatureInfo(@This()).create(.SmemToVectorWriteHazard, "smem-to-vector-write-hazard", "s_load_dword followed by v_cmp page faults", "smem-to-vector-write-hazard"),
- FeatureInfo(@This()).create(.SMemrealtime, "s-memrealtime", "Has s_memrealtime instruction", "s-memrealtime"),
- FeatureInfo(@This()).create(.SramEcc, "sram-ecc", "Enable SRAM ECC", "sram-ecc"),
- FeatureInfo(@This()).create(.ScalarAtomics, "scalar-atomics", "Has atomic scalar memory instructions", "scalar-atomics"),
- FeatureInfo(@This()).create(.ScalarFlatScratchInsts, "scalar-flat-scratch-insts", "Have s_scratch_* flat memory instructions", "scalar-flat-scratch-insts"),
- FeatureInfo(@This()).create(.ScalarStores, "scalar-stores", "Has store scalar memory instructions", "scalar-stores"),
- FeatureInfo(@This()).createWithSubfeatures(.SeaIslands, "sea-islands", "SEA_ISLANDS GPU generation", "sea-islands", &[_]@This() {
- .Movrel,
- .Gfx7Gfx8Gfx9Insts,
- .Fp64,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Localmemorysize65536,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .MimgR128,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.SouthernIslands, "southern-islands", "SOUTHERN_ISLANDS GPU generation", "southern-islands", &[_]@This() {
- .Movrel,
- .MimgR128,
- .Fp64,
- .TrigReducedRange,
- .NoXnackSupport,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .Ldsbankcount32,
- .Localmemorysize32768,
- }),
- FeatureInfo(@This()).create(.TrapHandler, "trap-handler", "Trap handler support", "trap-handler"),
- FeatureInfo(@This()).create(.TrigReducedRange, "trig-reduced-range", "Requires use of fract on arguments to trig instructions", "trig-reduced-range"),
- FeatureInfo(@This()).create(.UnalignedBufferAccess, "unaligned-buffer-access", "Support unaligned global loads and stores", "unaligned-buffer-access"),
- FeatureInfo(@This()).create(.UnalignedScratchAccess, "unaligned-scratch-access", "Support unaligned scratch loads and stores", "unaligned-scratch-access"),
- FeatureInfo(@This()).create(.UnpackedD16Vmem, "unpacked-d16-vmem", "Has unpacked d16 vmem instructions", "unpacked-d16-vmem"),
- FeatureInfo(@This()).create(.VgprIndexMode, "vgpr-index-mode", "Has VGPR mode register indexing", "vgpr-index-mode"),
- FeatureInfo(@This()).create(.VmemToScalarWriteHazard, "vmem-to-scalar-write-hazard", "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.", "vmem-to-scalar-write-hazard"),
- FeatureInfo(@This()).create(.Vop3Literal, "vop3-literal", "Can use one literal in VOP3", "vop3-literal"),
- FeatureInfo(@This()).create(.Vop3p, "vop3p", "Has VOP3P packed instructions", "vop3p"),
- FeatureInfo(@This()).create(.VcmpxExecWarHazard, "vcmpx-exec-war-hazard", "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)", "vcmpx-exec-war-hazard"),
- FeatureInfo(@This()).create(.VcmpxPermlaneHazard, "vcmpx-permlane-hazard", "TODO: describe me", "vcmpx-permlane-hazard"),
- FeatureInfo(@This()).createWithSubfeatures(.VolcanicIslands, "volcanic-islands", "VOLCANIC_ISLANDS GPU generation", "volcanic-islands", &[_]@This() {
- .IntClampInsts,
- .SdwaMav,
- .Movrel,
- .SMemrealtime,
- .Gcn3Encoding,
- .TrigReducedRange,
- .CiInsts,
- .FlatAddressSpace,
- .Sdwa,
- .Wavefrontsize64,
- .NoSramEccSupport,
- .ScalarStores,
- .Gfx7Gfx8Gfx9Insts,
- .Dpp,
- .Localmemorysize65536,
- .BitInsts16,
- .VgprIndexMode,
- .Gfx8Insts,
- .Inv2piInlineImm,
- .MimgR128,
- .SdwaOutModsVopc,
- .Fp64,
- }),
- FeatureInfo(@This()).create(.Vscnt, "vscnt", "Has separate store vscnt counter", "vscnt"),
- FeatureInfo(@This()).create(.Wavefrontsize16, "wavefrontsize16", "The number of threads per wavefront", "wavefrontsize16"),
- FeatureInfo(@This()).create(.Wavefrontsize32, "wavefrontsize32", "The number of threads per wavefront", "wavefrontsize32"),
- FeatureInfo(@This()).create(.Wavefrontsize64, "wavefrontsize64", "The number of threads per wavefront", "wavefrontsize64"),
- FeatureInfo(@This()).create(.Xnack, "xnack", "Enable XNACK support", "xnack"),
- FeatureInfo(@This()).create(.HalfRate64Ops, "half-rate-64-ops", "Most fp64 instructions are half rate instead of quarter", "half-rate-64-ops"),
- };
-};
lib/std/target/feature/ArmFeature.zig
@@ -1,818 +0,0 @@
-const FeatureInfo = @import("std").target.feature.FeatureInfo;
-
-pub const ArmFeature = enum {
- Armv2,
- Armv2a,
- Armv3,
- Armv3m,
- Armv4,
- Armv4t,
- Armv5t,
- Armv5te,
- Armv5tej,
- Armv6,
- Armv6j,
- Armv6k,
- Armv6kz,
- Armv6M,
- Armv6sM,
- Armv6t2,
- Armv7A,
- Armv7eM,
- Armv7k,
- Armv7M,
- Armv7R,
- Armv7s,
- Armv7ve,
- Armv8A,
- Armv8Mbase,
- Armv8Mmain,
- Armv8R,
- Armv81A,
- Armv81Mmain,
- Armv82A,
- Armv83A,
- Armv84A,
- Armv85A,
- Msecext8,
- Aclass,
- Aes,
- AcquireRelease,
- AvoidMovsShop,
- AvoidPartialCpsr,
- Crc,
- CheapPredicableCpsr,
- VldnAlign,
- Crypto,
- D32,
- Db,
- Dfb,
- Dsp,
- DontWidenVmovs,
- Dotprod,
- ExecuteOnly,
- ExpandFpMlx,
- Fp16,
- Fp16fml,
- Fp64,
- Fpao,
- FpArmv8,
- FpArmv8d16,
- FpArmv8d16sp,
- FpArmv8sp,
- Fpregs,
- Fpregs16,
- Fpregs64,
- Fullfp16,
- FuseAes,
- FuseLiterals,
- HwdivArm,
- Hwdiv,
- NoBranchPredictor,
- RetAddrStack,
- Slowfpvmlx,
- VmlxHazards,
- Lob,
- LongCalls,
- Mclass,
- Mp,
- Mve1beat,
- Mve2beat,
- Mve4beat,
- MuxedUnits,
- Neon,
- Neonfp,
- NeonFpmovs,
- NaclTrap,
- Noarm,
- NoMovt,
- NoNegImmediates,
- DisablePostraScheduler,
- NonpipelinedVfp,
- Perfmon,
- Bit32,
- PreferIshst,
- LoopAlign,
- PreferVmovsr,
- ProfUnpr,
- Ras,
- Rclass,
- ReadTpHard,
- ReserveR9,
- Sb,
- Sha2,
- SlowFpBrcc,
- SlowLoadDSubreg,
- SlowOddReg,
- SlowVdup32,
- SlowVgetlni32,
- SplatVfpNeon,
- StrictAlign,
- Thumb2,
- Trustzone,
- UseAa,
- UseMisched,
- WideStrideVfp,
- V7clrex,
- Vfp2,
- Vfp2sp,
- Vfp3,
- Vfp3d16,
- Vfp3d16sp,
- Vfp3sp,
- Vfp4,
- Vfp4d16,
- Vfp4d16sp,
- Vfp4sp,
- VmlxForwarding,
- Virtualization,
- Zcz,
- Mvefp,
- Mve,
- V4t,
- V5te,
- V5t,
- V6k,
- V6m,
- V6,
- V6t2,
- V7,
- V8m,
- V8mmain,
- V8,
- V81mmain,
- V81a,
- V82a,
- V83a,
- V84a,
- V85a,
- Iwmmxt,
- Iwmmxt2,
- SoftFloat,
- ThumbMode,
- A5,
- A7,
- A8,
- A9,
- A12,
- A15,
- A17,
- A32,
- A35,
- A53,
- A55,
- A57,
- A72,
- A73,
- A75,
- A76,
- Exynos,
- Krait,
- Kryo,
- M3,
- R4,
- R5,
- R7,
- R52,
- Swift,
- Xscale,
-
- pub fn getInfo(self: @This()) FeatureInfo(@This()) {
- return feature_infos[@enumToInt(self)];
- }
-
- pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
- FeatureInfo(@This()).create(.Armv2, "armv2", "ARMv2 architecture", "armv2"),
- FeatureInfo(@This()).create(.Armv2a, "armv2a", "ARMv2a architecture", "armv2a"),
- FeatureInfo(@This()).create(.Armv3, "armv3", "ARMv3 architecture", "armv3"),
- FeatureInfo(@This()).create(.Armv3m, "armv3m", "ARMv3m architecture", "armv3m"),
- FeatureInfo(@This()).create(.Armv4, "armv4", "ARMv4 architecture", "armv4"),
- FeatureInfo(@This()).createWithSubfeatures(.Armv4t, "armv4t", "ARMv4t architecture", "armv4t", &[_]@This() {
- .V4t,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv5t, "armv5t", "ARMv5t architecture", "armv5t", &[_]@This() {
- .V4t,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv5te, "armv5te", "ARMv5te architecture", "armv5te", &[_]@This() {
- .V4t,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv5tej, "armv5tej", "ARMv5tej architecture", "armv5tej", &[_]@This() {
- .V4t,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv6, "armv6", "ARMv6 architecture", "armv6", &[_]@This() {
- .V4t,
- .Dsp,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv6j, "armv6j", "ARMv7a architecture", "armv6j", &[_]@This() {
- .V4t,
- .Dsp,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv6k, "armv6k", "ARMv6k architecture", "armv6k", &[_]@This() {
- .V4t,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv6kz, "armv6kz", "ARMv6kz architecture", "armv6kz", &[_]@This() {
- .V4t,
- .Trustzone,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv6M, "armv6-m", "ARMv6m architecture", "armv6-m", &[_]@This() {
- .V4t,
- .ThumbMode,
- .Db,
- .StrictAlign,
- .Mclass,
- .Noarm,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv6sM, "armv6s-m", "ARMv6sm architecture", "armv6s-m", &[_]@This() {
- .V4t,
- .ThumbMode,
- .Db,
- .StrictAlign,
- .Mclass,
- .Noarm,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv6t2, "armv6t2", "ARMv6t2 architecture", "armv6t2", &[_]@This() {
- .V4t,
- .Thumb2,
- .Dsp,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv7A, "armv7-a", "ARMv7a architecture", "armv7-a", &[_]@This() {
- .Perfmon,
- .V4t,
- .D32,
- .Fpregs,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Aclass,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv7eM, "armv7e-m", "ARMv7em architecture", "armv7e-m", &[_]@This() {
- .Perfmon,
- .V4t,
- .ThumbMode,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Mclass,
- .Noarm,
- .Hwdiv,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv7k, "armv7k", "ARMv7a architecture", "armv7k", &[_]@This() {
- .Perfmon,
- .V4t,
- .D32,
- .Fpregs,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Aclass,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv7M, "armv7-m", "ARMv7m architecture", "armv7-m", &[_]@This() {
- .Perfmon,
- .V4t,
- .ThumbMode,
- .V7clrex,
- .Thumb2,
- .Db,
- .Mclass,
- .Noarm,
- .Hwdiv,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv7R, "armv7-r", "ARMv7r architecture", "armv7-r", &[_]@This() {
- .Perfmon,
- .V4t,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Hwdiv,
- .Rclass,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv7s, "armv7s", "ARMv7a architecture", "armv7s", &[_]@This() {
- .Perfmon,
- .V4t,
- .D32,
- .Fpregs,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Aclass,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv7ve, "armv7ve", "ARMv7ve architecture", "armv7ve", &[_]@This() {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Mp,
- .Fpregs,
- .V4t,
- .V7clrex,
- .Dsp,
- .Thumb2,
- .Db,
- .Aclass,
- .Hwdiv,
- .Trustzone,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv8A, "armv8-a", "ARMv8a architecture", "armv8-a", &[_]@This() {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv8Mbase, "armv8-m.base", "ARMv8mBaseline architecture", "armv8-m.base", &[_]@This() {
- .V4t,
- .ThumbMode,
- .Msecext8,
- .V7clrex,
- .Db,
- .StrictAlign,
- .Mclass,
- .Noarm,
- .AcquireRelease,
- .Hwdiv,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv8Mmain, "armv8-m.main", "ARMv8mMainline architecture", "armv8-m.main", &[_]@This() {
- .Perfmon,
- .V4t,
- .ThumbMode,
- .Msecext8,
- .V7clrex,
- .Thumb2,
- .Db,
- .Mclass,
- .Noarm,
- .AcquireRelease,
- .Hwdiv,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv8R, "armv8-r", "ARMv8r architecture", "armv8-r", &[_]@This() {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Crc,
- .Fpregs,
- .Mp,
- .Dfb,
- .Dsp,
- .Fp16,
- .V4t,
- .Db,
- .V7clrex,
- .Thumb2,
- .AcquireRelease,
- .Hwdiv,
- .Rclass,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv81A, "armv8.1-a", "ARMv81a architecture", "armv8.1-a", &[_]@This() {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv81Mmain, "armv8.1-m.main", "ARMv81mMainline architecture", "armv8.1-m.main", &[_]@This() {
- .Perfmon,
- .V4t,
- .ThumbMode,
- .Msecext8,
- .V7clrex,
- .Thumb2,
- .Db,
- .Ras,
- .Mclass,
- .Noarm,
- .AcquireRelease,
- .Hwdiv,
- .Lob,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv82A, "armv8.2-a", "ARMv82a architecture", "armv8.2-a", &[_]@This() {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .Ras,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv83A, "armv8.3-a", "ARMv83a architecture", "armv8.3-a", &[_]@This() {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .Ras,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv84A, "armv8.4-a", "ARMv84a architecture", "armv8.4-a", &[_]@This() {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .Ras,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Armv85A, "armv8.5-a", "ARMv85a architecture", "armv8.5-a", &[_]@This() {
- .HwdivArm,
- .Perfmon,
- .D32,
- .Fpregs,
- .Crc,
- .Mp,
- .Fp16,
- .Dsp,
- .V4t,
- .V7clrex,
- .Db,
- .Aclass,
- .Thumb2,
- .Ras,
- .Sb,
- .AcquireRelease,
- .Hwdiv,
- .Trustzone,
- }),
- FeatureInfo(@This()).create(.Msecext8, "8msecext", "Enable support for ARMv8-M Security Extensions", "8msecext"),
- FeatureInfo(@This()).create(.Aclass, "aclass", "Is application profile ('A' series)", "aclass"),
- FeatureInfo(@This()).createWithSubfeatures(.Aes, "aes", "Enable AES support", "aes", &[_]@This() {
- .D32,
- .Fpregs,
- }),
- FeatureInfo(@This()).create(.AcquireRelease, "acquire-release", "Has v8 acquire/release (lda/ldaex etc) instructions", "acquire-release"),
- FeatureInfo(@This()).create(.AvoidMovsShop, "avoid-movs-shop", "Avoid movs instructions with shifter operand", "avoid-movs-shop"),
- FeatureInfo(@This()).create(.AvoidPartialCpsr, "avoid-partial-cpsr", "Avoid CPSR partial update for OOO execution", "avoid-partial-cpsr"),
- FeatureInfo(@This()).create(.Crc, "crc", "Enable support for CRC instructions", "crc"),
- FeatureInfo(@This()).create(.CheapPredicableCpsr, "cheap-predicable-cpsr", "Disable +1 predication cost for instructions updating CPSR", "cheap-predicable-cpsr"),
- FeatureInfo(@This()).create(.VldnAlign, "vldn-align", "Check for VLDn unaligned access", "vldn-align"),
- FeatureInfo(@This()).createWithSubfeatures(.Crypto, "crypto", "Enable support for Cryptography extensions", "crypto", &[_]@This() {
- .D32,
- .Fpregs,
- }),
- FeatureInfo(@This()).create(.D32, "d32", "Extend FP to 32 double registers", "d32"),
- FeatureInfo(@This()).create(.Db, "db", "Has data barrier (dmb/dsb) instructions", "db"),
- FeatureInfo(@This()).create(.Dfb, "dfb", "Has full data barrier (dfb) instruction", "dfb"),
- FeatureInfo(@This()).create(.Dsp, "dsp", "Supports DSP instructions in ARM and/or Thumb2", "dsp"),
- FeatureInfo(@This()).create(.DontWidenVmovs, "dont-widen-vmovs", "Don't widen VMOVS to VMOVD", "dont-widen-vmovs"),
- FeatureInfo(@This()).createWithSubfeatures(.Dotprod, "dotprod", "Enable support for dot product instructions", "dotprod", &[_]@This() {
- .D32,
- .Fpregs,
- }),
- FeatureInfo(@This()).create(.ExecuteOnly, "execute-only", "Enable the generation of execute only code.", "execute-only"),
- FeatureInfo(@This()).create(.ExpandFpMlx, "expand-fp-mlx", "Expand VFP/NEON MLA/MLS instructions", "expand-fp-mlx"),
- FeatureInfo(@This()).create(.Fp16, "fp16", "Enable half-precision floating point", "fp16"),
- FeatureInfo(@This()).createWithSubfeatures(.Fp16fml, "fp16fml", "Enable full half-precision floating point fml instructions", "fp16fml", &[_]@This() {
- .Fpregs,
- .Fp16,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Fp64, "fp64", "Floating point unit supports double precision", "fp64", &[_]@This() {
- .Fpregs,
- }),
- FeatureInfo(@This()).create(.Fpao, "fpao", "Enable fast computation of positive address offsets", "fpao"),
- FeatureInfo(@This()).createWithSubfeatures(.FpArmv8, "fp-armv8", "Enable ARMv8 FP", "fp-armv8", &[_]@This() {
- .D32,
- .Fpregs,
- .Fp16,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.FpArmv8d16, "fp-armv8d16", "Enable ARMv8 FP with only 16 d-registers", "fp-armv8d16", &[_]@This() {
- .Fpregs,
- .Fp16,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.FpArmv8d16sp, "fp-armv8d16sp", "Enable ARMv8 FP with only 16 d-registers and no double precision", "fp-armv8d16sp", &[_]@This() {
- .Fpregs,
- .Fp16,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.FpArmv8sp, "fp-armv8sp", "Enable ARMv8 FP with no double precision", "fp-armv8sp", &[_]@This() {
- .D32,
- .Fpregs,
- .Fp16,
- }),
- FeatureInfo(@This()).create(.Fpregs, "fpregs", "Enable FP registers", "fpregs"),
- FeatureInfo(@This()).createWithSubfeatures(.Fpregs16, "fpregs16", "Enable 16-bit FP registers", "fpregs16", &[_]@This() {
- .Fpregs,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Fpregs64, "fpregs64", "Enable 64-bit FP registers", "fpregs64", &[_]@This() {
- .Fpregs,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Fullfp16, "fullfp16", "Enable full half-precision floating point", "fullfp16", &[_]@This() {
- .Fpregs,
- .Fp16,
- }),
- FeatureInfo(@This()).create(.FuseAes, "fuse-aes", "CPU fuses AES crypto operations", "fuse-aes"),
- FeatureInfo(@This()).create(.FuseLiterals, "fuse-literals", "CPU fuses literal generation operations", "fuse-literals"),
- FeatureInfo(@This()).create(.HwdivArm, "hwdiv-arm", "Enable divide instructions in ARM mode", "hwdiv-arm"),
- FeatureInfo(@This()).create(.Hwdiv, "hwdiv", "Enable divide instructions in Thumb", "hwdiv"),
- FeatureInfo(@This()).create(.NoBranchPredictor, "no-branch-predictor", "Has no branch predictor", "no-branch-predictor"),
- FeatureInfo(@This()).create(.RetAddrStack, "ret-addr-stack", "Has return address stack", "ret-addr-stack"),
- FeatureInfo(@This()).create(.Slowfpvmlx, "slowfpvmlx", "Disable VFP / NEON MAC instructions", "slowfpvmlx"),
- FeatureInfo(@This()).create(.VmlxHazards, "vmlx-hazards", "Has VMLx hazards", "vmlx-hazards"),
- FeatureInfo(@This()).create(.Lob, "lob", "Enable Low Overhead Branch extensions", "lob"),
- FeatureInfo(@This()).create(.LongCalls, "long-calls", "Generate calls via indirect call instructions", "long-calls"),
- FeatureInfo(@This()).create(.Mclass, "mclass", "Is microcontroller profile ('M' series)", "mclass"),
- FeatureInfo(@This()).create(.Mp, "mp", "Supports Multiprocessing extension", "mp"),
- FeatureInfo(@This()).create(.Mve1beat, "mve1beat", "Model MVE instructions as a 1 beat per tick architecture", "mve1beat"),
- FeatureInfo(@This()).create(.Mve2beat, "mve2beat", "Model MVE instructions as a 2 beats per tick architecture", "mve2beat"),
- FeatureInfo(@This()).create(.Mve4beat, "mve4beat", "Model MVE instructions as a 4 beats per tick architecture", "mve4beat"),
- FeatureInfo(@This()).create(.MuxedUnits, "muxed-units", "Has muxed AGU and NEON/FPU", "muxed-units"),
- FeatureInfo(@This()).createWithSubfeatures(.Neon, "neon", "Enable NEON instructions", "neon", &[_]@This() {
- .D32,
- .Fpregs,
- }),
- FeatureInfo(@This()).create(.Neonfp, "neonfp", "Use NEON for single precision FP", "neonfp"),
- FeatureInfo(@This()).create(.NeonFpmovs, "neon-fpmovs", "Convert VMOVSR, VMOVRS, VMOVS to NEON", "neon-fpmovs"),
- FeatureInfo(@This()).create(.NaclTrap, "nacl-trap", "NaCl trap", "nacl-trap"),
- FeatureInfo(@This()).create(.Noarm, "noarm", "Does not support ARM mode execution", "noarm"),
- FeatureInfo(@This()).create(.NoMovt, "no-movt", "Don't use movt/movw pairs for 32-bit imms", "no-movt"),
- FeatureInfo(@This()).create(.NoNegImmediates, "no-neg-immediates", "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.", "no-neg-immediates"),
- FeatureInfo(@This()).create(.DisablePostraScheduler, "disable-postra-scheduler", "Don't schedule again after register allocation", "disable-postra-scheduler"),
- FeatureInfo(@This()).create(.NonpipelinedVfp, "nonpipelined-vfp", "VFP instructions are not pipelined", "nonpipelined-vfp"),
- FeatureInfo(@This()).create(.Perfmon, "perfmon", "Enable support for Performance Monitor extensions", "perfmon"),
- FeatureInfo(@This()).create(.Bit32, "32bit", "Prefer 32-bit Thumb instrs", "32bit"),
- FeatureInfo(@This()).create(.PreferIshst, "prefer-ishst", "Prefer ISHST barriers", "prefer-ishst"),
- FeatureInfo(@This()).create(.LoopAlign, "loop-align", "Prefer 32-bit alignment for loops", "loop-align"),
- FeatureInfo(@This()).create(.PreferVmovsr, "prefer-vmovsr", "Prefer VMOVSR", "prefer-vmovsr"),
- FeatureInfo(@This()).create(.ProfUnpr, "prof-unpr", "Is profitable to unpredicate", "prof-unpr"),
- FeatureInfo(@This()).create(.Ras, "ras", "Enable Reliability, Availability and Serviceability extensions", "ras"),
- FeatureInfo(@This()).create(.Rclass, "rclass", "Is realtime profile ('R' series)", "rclass"),
- FeatureInfo(@This()).create(.ReadTpHard, "read-tp-hard", "Reading thread pointer from register", "read-tp-hard"),
- FeatureInfo(@This()).create(.ReserveR9, "reserve-r9", "Reserve R9, making it unavailable as GPR", "reserve-r9"),
- FeatureInfo(@This()).create(.Sb, "sb", "Enable v8.5a Speculation Barrier", "sb"),
- FeatureInfo(@This()).createWithSubfeatures(.Sha2, "sha2", "Enable SHA1 and SHA256 support", "sha2", &[_]@This() {
- .D32,
- .Fpregs,
- }),
- FeatureInfo(@This()).create(.SlowFpBrcc, "slow-fp-brcc", "FP compare + branch is slow", "slow-fp-brcc"),
- FeatureInfo(@This()).create(.SlowLoadDSubreg, "slow-load-D-subreg", "Loading into D subregs is slow", "slow-load-D-subreg"),
- FeatureInfo(@This()).create(.SlowOddReg, "slow-odd-reg", "VLDM/VSTM starting with an odd register is slow", "slow-odd-reg"),
- FeatureInfo(@This()).create(.SlowVdup32, "slow-vdup32", "Has slow VDUP32 - prefer VMOV", "slow-vdup32"),
- FeatureInfo(@This()).create(.SlowVgetlni32, "slow-vgetlni32", "Has slow VGETLNi32 - prefer VMOV", "slow-vgetlni32"),
- FeatureInfo(@This()).createWithSubfeatures(.SplatVfpNeon, "splat-vfp-neon", "Splat register from VFP to NEON", "splat-vfp-neon", &[_]@This() {
- .DontWidenVmovs,
- }),
- FeatureInfo(@This()).create(.StrictAlign, "strict-align", "Disallow all unaligned memory access", "strict-align"),
- FeatureInfo(@This()).create(.Thumb2, "thumb2", "Enable Thumb2 instructions", "thumb2"),
- FeatureInfo(@This()).create(.Trustzone, "trustzone", "Enable support for TrustZone security extensions", "trustzone"),
- FeatureInfo(@This()).create(.UseAa, "use-aa", "Use alias analysis during codegen", "use-aa"),
- FeatureInfo(@This()).create(.UseMisched, "use-misched", "Use the MachineScheduler", "use-misched"),
- FeatureInfo(@This()).create(.WideStrideVfp, "wide-stride-vfp", "Use a wide stride when allocating VFP registers", "wide-stride-vfp"),
- FeatureInfo(@This()).create(.V7clrex, "v7clrex", "Has v7 clrex instruction", "v7clrex"),
- FeatureInfo(@This()).createWithSubfeatures(.Vfp2, "vfp2", "Enable VFP2 instructions", "vfp2", &[_]@This() {
- .Fpregs,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Vfp2sp, "vfp2sp", "Enable VFP2 instructions with no double precision", "vfp2sp", &[_]@This() {
- .Fpregs,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Vfp3, "vfp3", "Enable VFP3 instructions", "vfp3", &[_]@This() {
- .D32,
- .Fpregs,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Vfp3d16, "vfp3d16", "Enable VFP3 instructions with only 16 d-registers", "vfp3d16", &[_]@This() {
- .Fpregs,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Vfp3d16sp, "vfp3d16sp", "Enable VFP3 instructions with only 16 d-registers and no double precision", "vfp3d16sp", &[_]@This() {
- .Fpregs,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Vfp3sp, "vfp3sp", "Enable VFP3 instructions with no double precision", "vfp3sp", &[_]@This() {
- .D32,
- .Fpregs,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Vfp4, "vfp4", "Enable VFP4 instructions", "vfp4", &[_]@This() {
- .D32,
- .Fpregs,
- .Fp16,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Vfp4d16, "vfp4d16", "Enable VFP4 instructions with only 16 d-registers", "vfp4d16", &[_]@This() {
- .Fpregs,
- .Fp16,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Vfp4d16sp, "vfp4d16sp", "Enable VFP4 instructions with only 16 d-registers and no double precision", "vfp4d16sp", &[_]@This() {
- .Fpregs,
- .Fp16,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Vfp4sp, "vfp4sp", "Enable VFP4 instructions with no double precision", "vfp4sp", &[_]@This() {
- .D32,
- .Fpregs,
- .Fp16,
- }),
- FeatureInfo(@This()).create(.VmlxForwarding, "vmlx-forwarding", "Has multiplier accumulator forwarding", "vmlx-forwarding"),
- FeatureInfo(@This()).createWithSubfeatures(.Virtualization, "virtualization", "Supports Virtualization extension", "virtualization", &[_]@This() {
- .HwdivArm,
- .Hwdiv,
- }),
- FeatureInfo(@This()).create(.Zcz, "zcz", "Has zero-cycle zeroing instructions", "zcz"),
- FeatureInfo(@This()).createWithSubfeatures(.Mvefp, "mve.fp", "Support M-Class Vector Extension with integer and floating ops", "mve.fp", &[_]@This() {
- .Perfmon,
- .V4t,
- .Fpregs,
- .V7clrex,
- .Fp16,
- .Dsp,
- .Thumb2,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Mve, "mve", "Support M-Class Vector Extension with integer ops", "mve", &[_]@This() {
- .Perfmon,
- .V4t,
- .Fpregs,
- .V7clrex,
- .Dsp,
- .Thumb2,
- }),
- FeatureInfo(@This()).create(.V4t, "v4t", "Support ARM v4T instructions", "v4t"),
- FeatureInfo(@This()).createWithSubfeatures(.V5te, "v5te", "Support ARM v5TE, v5TEj, and v5TExp instructions", "v5te", &[_]@This() {
- .V4t,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.V5t, "v5t", "Support ARM v5T instructions", "v5t", &[_]@This() {
- .V4t,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.V6k, "v6k", "Support ARM v6k instructions", "v6k", &[_]@This() {
- .V4t,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.V6m, "v6m", "Support ARM v6M instructions", "v6m", &[_]@This() {
- .V4t,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.V6, "v6", "Support ARM v6 instructions", "v6", &[_]@This() {
- .V4t,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.V6t2, "v6t2", "Support ARM v6t2 instructions", "v6t2", &[_]@This() {
- .V4t,
- .Thumb2,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.V7, "v7", "Support ARM v7 instructions", "v7", &[_]@This() {
- .Perfmon,
- .Thumb2,
- .V4t,
- .V7clrex,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.V8m, "v8m", "Support ARM v8M Baseline instructions", "v8m", &[_]@This() {
- .V4t,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.V8mmain, "v8m.main", "Support ARM v8M Mainline instructions", "v8m.main", &[_]@This() {
- .Perfmon,
- .Thumb2,
- .V4t,
- .V7clrex,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.V8, "v8", "Support ARM v8 instructions", "v8", &[_]@This() {
- .Perfmon,
- .V4t,
- .V7clrex,
- .Thumb2,
- .AcquireRelease,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.V81mmain, "v8.1m.main", "Support ARM v8-1M Mainline instructions", "v8.1m.main", &[_]@This() {
- .Perfmon,
- .Thumb2,
- .V4t,
- .V7clrex,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.V81a, "v8.1a", "Support ARM v8.1a instructions", "v8.1a", &[_]@This() {
- .Perfmon,
- .V4t,
- .V7clrex,
- .Thumb2,
- .AcquireRelease,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.V82a, "v8.2a", "Support ARM v8.2a instructions", "v8.2a", &[_]@This() {
- .Perfmon,
- .V4t,
- .V7clrex,
- .Thumb2,
- .AcquireRelease,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.V83a, "v8.3a", "Support ARM v8.3a instructions", "v8.3a", &[_]@This() {
- .Perfmon,
- .V4t,
- .V7clrex,
- .Thumb2,
- .AcquireRelease,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.V84a, "v8.4a", "Support ARM v8.4a instructions", "v8.4a", &[_]@This() {
- .Perfmon,
- .V4t,
- .D32,
- .Fpregs,
- .V7clrex,
- .Thumb2,
- .AcquireRelease,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.V85a, "v8.5a", "Support ARM v8.5a instructions", "v8.5a", &[_]@This() {
- .Perfmon,
- .V4t,
- .D32,
- .Fpregs,
- .V7clrex,
- .Thumb2,
- .AcquireRelease,
- .Sb,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Iwmmxt, "iwmmxt", "ARMv5te architecture", "iwmmxt", &[_]@This() {
- .V4t,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Iwmmxt2, "iwmmxt2", "ARMv5te architecture", "iwmmxt2", &[_]@This() {
- .V4t,
- }),
- FeatureInfo(@This()).create(.SoftFloat, "soft-float", "Use software floating point features.", "soft-float"),
- FeatureInfo(@This()).create(.ThumbMode, "thumb-mode", "Thumb mode", "thumb-mode"),
- FeatureInfo(@This()).create(.A5, "a5", "Cortex-A5 ARM processors", "a5"),
- FeatureInfo(@This()).create(.A7, "a7", "Cortex-A7 ARM processors", "a7"),
- FeatureInfo(@This()).create(.A8, "a8", "Cortex-A8 ARM processors", "a8"),
- FeatureInfo(@This()).create(.A9, "a9", "Cortex-A9 ARM processors", "a9"),
- FeatureInfo(@This()).create(.A12, "a12", "Cortex-A12 ARM processors", "a12"),
- FeatureInfo(@This()).create(.A15, "a15", "Cortex-A15 ARM processors", "a15"),
- FeatureInfo(@This()).create(.A17, "a17", "Cortex-A17 ARM processors", "a17"),
- FeatureInfo(@This()).create(.A32, "a32", "Cortex-A32 ARM processors", "a32"),
- FeatureInfo(@This()).create(.A35, "a35", "Cortex-A35 ARM processors", "a35"),
- FeatureInfo(@This()).create(.A53, "a53", "Cortex-A53 ARM processors", "a53"),
- FeatureInfo(@This()).create(.A55, "a55", "Cortex-A55 ARM processors", "a55"),
- FeatureInfo(@This()).create(.A57, "a57", "Cortex-A57 ARM processors", "a57"),
- FeatureInfo(@This()).create(.A72, "a72", "Cortex-A72 ARM processors", "a72"),
- FeatureInfo(@This()).create(.A73, "a73", "Cortex-A73 ARM processors", "a73"),
- FeatureInfo(@This()).create(.A75, "a75", "Cortex-A75 ARM processors", "a75"),
- FeatureInfo(@This()).create(.A76, "a76", "Cortex-A76 ARM processors", "a76"),
- FeatureInfo(@This()).createWithSubfeatures(.Exynos, "exynos", "Samsung Exynos processors", "exynos", &[_]@This() {
- .HwdivArm,
- .D32,
- .Crc,
- .Fpregs,
- .RetAddrStack,
- .SlowVgetlni32,
- .WideStrideVfp,
- .SlowVdup32,
- .SlowFpBrcc,
- .ProfUnpr,
- .DontWidenVmovs,
- .Zcz,
- .Hwdiv,
- .FuseAes,
- .Slowfpvmlx,
- .UseAa,
- .FuseLiterals,
- .ExpandFpMlx,
- }),
- FeatureInfo(@This()).create(.Krait, "krait", "Qualcomm Krait processors", "krait"),
- FeatureInfo(@This()).create(.Kryo, "kryo", "Qualcomm Kryo processors", "kryo"),
- FeatureInfo(@This()).create(.M3, "m3", "Cortex-M3 ARM processors", "m3"),
- FeatureInfo(@This()).create(.R4, "r4", "Cortex-R4 ARM processors", "r4"),
- FeatureInfo(@This()).create(.R5, "r5", "Cortex-R5 ARM processors", "r5"),
- FeatureInfo(@This()).create(.R7, "r7", "Cortex-R7 ARM processors", "r7"),
- FeatureInfo(@This()).create(.R52, "r52", "Cortex-R52 ARM processors", "r52"),
- FeatureInfo(@This()).create(.Swift, "swift", "Swift ARM processors", "swift"),
- FeatureInfo(@This()).createWithSubfeatures(.Xscale, "xscale", "ARMv5te architecture", "xscale", &[_]@This() {
- .V4t,
- }),
- };
-};
lib/std/target/feature/AvrFeature.zig
@@ -1,230 +0,0 @@
-const FeatureInfo = @import("std").target.feature.FeatureInfo;
-
-pub const AvrFeature = enum {
- Avr0,
- Avr1,
- Avr2,
- Avr3,
- Avr4,
- Avr5,
- Avr6,
- Avr25,
- Avr31,
- Avr35,
- Avr51,
- Avrtiny,
- Xmega,
- Xmegau,
- Addsubiw,
- Break,
- Des,
- Eijmpcall,
- Elpm,
- Elpmx,
- Ijmpcall,
- Jmpcall,
- Lpm,
- Lpmx,
- Movw,
- Mul,
- Rmw,
- Spm,
- Spmx,
- Sram,
- Special,
- Smallstack,
- Tinyencoding,
-
- pub fn getInfo(self: @This()) FeatureInfo(@This()) {
- return feature_infos[@enumToInt(self)];
- }
-
- pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
- FeatureInfo(@This()).create(.Avr0, "avr0", "The device is a part of the avr0 family", "avr0"),
- FeatureInfo(@This()).createWithSubfeatures(.Avr1, "avr1", "The device is a part of the avr1 family", "avr1", &[_]@This() {
- .Avr0,
- .Lpm,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avr2, "avr2", "The device is a part of the avr2 family", "avr2", &[_]@This() {
- .Lpm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Ijmpcall,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avr3, "avr3", "The device is a part of the avr3 family", "avr3", &[_]@This() {
- .Lpm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Ijmpcall,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avr4, "avr4", "The device is a part of the avr4 family", "avr4", &[_]@This() {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avr5, "avr5", "The device is a part of the avr5 family", "avr5", &[_]@This() {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avr6, "avr6", "The device is a part of the avr6 family", "avr6", &[_]@This() {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avr25, "avr25", "The device is a part of the avr25 family", "avr25", &[_]@This() {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avr31, "avr31", "The device is a part of the avr31 family", "avr31", &[_]@This() {
- .Lpm,
- .Elpm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Ijmpcall,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avr35, "avr35", "The device is a part of the avr35 family", "avr35", &[_]@This() {
- .Lpm,
- .Movw,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Lpmx,
- .Ijmpcall,
- .Break,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avr51, "avr51", "The device is a part of the avr51 family", "avr51", &[_]@This() {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Ijmpcall,
- .Break,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avrtiny, "avrtiny", "The device is a part of the avrtiny family", "avrtiny", &[_]@This() {
- .Avr0,
- .Sram,
- .Break,
- .Tinyencoding,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Xmega, "xmega", "The device is a part of the xmega family", "xmega", &[_]@This() {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Des,
- .Ijmpcall,
- .Break,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Xmegau, "xmegau", "The device is a part of the xmegau family", "xmegau", &[_]@This() {
- .Lpm,
- .Elpm,
- .Movw,
- .Elpmx,
- .Spm,
- .Avr0,
- .Sram,
- .Jmpcall,
- .Eijmpcall,
- .Spmx,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- }),
- FeatureInfo(@This()).create(.Addsubiw, "addsubiw", "Enable 16-bit register-immediate addition and subtraction instructions", "addsubiw"),
- FeatureInfo(@This()).create(.Break, "break", "The device supports the `BREAK` debugging instruction", "break"),
- FeatureInfo(@This()).create(.Des, "des", "The device supports the `DES k` encryption instruction", "des"),
- FeatureInfo(@This()).create(.Eijmpcall, "eijmpcall", "The device supports the `EIJMP`/`EICALL` instructions", "eijmpcall"),
- FeatureInfo(@This()).create(.Elpm, "elpm", "The device supports the ELPM instruction", "elpm"),
- FeatureInfo(@This()).create(.Elpmx, "elpmx", "The device supports the `ELPM Rd, Z[+]` instructions", "elpmx"),
- FeatureInfo(@This()).create(.Ijmpcall, "ijmpcall", "The device supports `IJMP`/`ICALL`instructions", "ijmpcall"),
- FeatureInfo(@This()).create(.Jmpcall, "jmpcall", "The device supports the `JMP` and `CALL` instructions", "jmpcall"),
- FeatureInfo(@This()).create(.Lpm, "lpm", "The device supports the `LPM` instruction", "lpm"),
- FeatureInfo(@This()).create(.Lpmx, "lpmx", "The device supports the `LPM Rd, Z[+]` instruction", "lpmx"),
- FeatureInfo(@This()).create(.Movw, "movw", "The device supports the 16-bit MOVW instruction", "movw"),
- FeatureInfo(@This()).create(.Mul, "mul", "The device supports the multiplication instructions", "mul"),
- FeatureInfo(@This()).create(.Rmw, "rmw", "The device supports the read-write-modify instructions: XCH, LAS, LAC, LAT", "rmw"),
- FeatureInfo(@This()).create(.Spm, "spm", "The device supports the `SPM` instruction", "spm"),
- FeatureInfo(@This()).create(.Spmx, "spmx", "The device supports the `SPM Z+` instruction", "spmx"),
- FeatureInfo(@This()).create(.Sram, "sram", "The device has random access memory", "sram"),
- FeatureInfo(@This()).createWithSubfeatures(.Special, "special", "Enable use of the entire instruction set - used for debugging", "special", &[_]@This() {
- .Lpm,
- .Elpm,
- .Elpmx,
- .Movw,
- .Spm,
- .Eijmpcall,
- .Spmx,
- .Jmpcall,
- .Sram,
- .Addsubiw,
- .Mul,
- .Lpmx,
- .Rmw,
- .Des,
- .Ijmpcall,
- .Break,
- }),
- FeatureInfo(@This()).create(.Smallstack, "smallstack", "The device has an 8-bit stack pointer", "smallstack"),
- FeatureInfo(@This()).create(.Tinyencoding, "tinyencoding", "The device has Tiny core specific instruction encodings", "tinyencoding"),
- };
-};
lib/std/target/feature/BpfFeature.zig
@@ -1,17 +0,0 @@
-const FeatureInfo = @import("std").target.feature.FeatureInfo;
-
-pub const BpfFeature = enum {
- Alu32,
- Dummy,
- Dwarfris,
-
- pub fn getInfo(self: @This()) FeatureInfo(@This()) {
- return feature_infos[@enumToInt(self)];
- }
-
- pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
- FeatureInfo(@This()).create(.Alu32, "alu32", "Enable ALU32 instructions", "alu32"),
- FeatureInfo(@This()).create(.Dummy, "dummy", "unused feature", "dummy"),
- FeatureInfo(@This()).create(.Dwarfris, "dwarfris", "Disable MCAsmInfo DwarfUsesRelocationsAcrossSections", "dwarfris"),
- };
-};
lib/std/target/feature/empty.zig
@@ -1,5 +0,0 @@
-const FeatureInfo = @import("std").target.feature.FeatureInfo;
-
-pub const EmptyFeature = struct {
- pub const feature_infos = [0]FeatureInfo(@This()) {};
-};
lib/std/target/feature/HexagonFeature.zig
@@ -1,76 +0,0 @@
-const FeatureInfo = @import("std").target.feature.FeatureInfo;
-
-pub const HexagonFeature = enum {
- V5,
- V55,
- V60,
- V62,
- V65,
- V66,
- Hvx,
- HvxLength64b,
- HvxLength128b,
- Hvxv60,
- Hvxv62,
- Hvxv65,
- Hvxv66,
- Zreg,
- Duplex,
- LongCalls,
- Mem_noshuf,
- Memops,
- Nvj,
- Nvs,
- NoreturnStackElim,
- Packets,
- ReservedR19,
- SmallData,
-
- pub fn getInfo(self: @This()) FeatureInfo(@This()) {
- return feature_infos[@enumToInt(self)];
- }
-
- pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
- FeatureInfo(@This()).create(.V5, "v5", "Enable Hexagon V5 architecture", "v5"),
- FeatureInfo(@This()).create(.V55, "v55", "Enable Hexagon V55 architecture", "v55"),
- FeatureInfo(@This()).create(.V60, "v60", "Enable Hexagon V60 architecture", "v60"),
- FeatureInfo(@This()).create(.V62, "v62", "Enable Hexagon V62 architecture", "v62"),
- FeatureInfo(@This()).create(.V65, "v65", "Enable Hexagon V65 architecture", "v65"),
- FeatureInfo(@This()).create(.V66, "v66", "Enable Hexagon V66 architecture", "v66"),
- FeatureInfo(@This()).create(.Hvx, "hvx", "Hexagon HVX instructions", "hvx"),
- FeatureInfo(@This()).createWithSubfeatures(.HvxLength64b, "hvx-length64b", "Hexagon HVX 64B instructions", "hvx-length64b", &[_]@This() {
- .Hvx,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.HvxLength128b, "hvx-length128b", "Hexagon HVX 128B instructions", "hvx-length128b", &[_]@This() {
- .Hvx,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Hvxv60, "hvxv60", "Hexagon HVX instructions", "hvxv60", &[_]@This() {
- .Hvx,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Hvxv62, "hvxv62", "Hexagon HVX instructions", "hvxv62", &[_]@This() {
- .Hvx,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Hvxv65, "hvxv65", "Hexagon HVX instructions", "hvxv65", &[_]@This() {
- .Hvx,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Hvxv66, "hvxv66", "Hexagon HVX instructions", "hvxv66", &[_]@This() {
- .Hvx,
- .Zreg,
- }),
- FeatureInfo(@This()).create(.Zreg, "zreg", "Hexagon ZReg extension instructions", "zreg"),
- FeatureInfo(@This()).create(.Duplex, "duplex", "Enable generation of duplex instruction", "duplex"),
- FeatureInfo(@This()).create(.LongCalls, "long-calls", "Use constant-extended calls", "long-calls"),
- FeatureInfo(@This()).create(.Mem_noshuf, "mem_noshuf", "Supports mem_noshuf feature", "mem_noshuf"),
- FeatureInfo(@This()).create(.Memops, "memops", "Use memop instructions", "memops"),
- FeatureInfo(@This()).createWithSubfeatures(.Nvj, "nvj", "Support for new-value jumps", "nvj", &[_]@This() {
- .Packets,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Nvs, "nvs", "Support for new-value stores", "nvs", &[_]@This() {
- .Packets,
- }),
- FeatureInfo(@This()).create(.NoreturnStackElim, "noreturn-stack-elim", "Eliminate stack allocation in a noreturn function when possible", "noreturn-stack-elim"),
- FeatureInfo(@This()).create(.Packets, "packets", "Support for instruction packets", "packets"),
- FeatureInfo(@This()).create(.ReservedR19, "reserved-r19", "Reserve register R19", "reserved-r19"),
- FeatureInfo(@This()).create(.SmallData, "small-data", "Allow GP-relative addressing of global variables", "small-data"),
- };
-};
lib/std/target/feature/MipsFeature.zig
@@ -1,238 +0,0 @@
-const FeatureInfo = @import("std").target.feature.FeatureInfo;
-
-pub const MipsFeature = enum {
- Abs2008,
- Crc,
- Cnmips,
- Dsp,
- Dspr2,
- Dspr3,
- Eva,
- Fp64,
- Fpxx,
- Ginv,
- Gp64,
- LongCalls,
- Msa,
- Mt,
- Nomadd4,
- Micromips,
- Mips1,
- Mips2,
- Mips3,
- Mips3_32,
- Mips3_32r2,
- Mips4,
- Mips4_32,
- Mips4_32r2,
- Mips5,
- Mips5_32r2,
- Mips16,
- Mips32,
- Mips32r2,
- Mips32r3,
- Mips32r5,
- Mips32r6,
- Mips64,
- Mips64r2,
- Mips64r3,
- Mips64r5,
- Mips64r6,
- Nan2008,
- Noabicalls,
- Nooddspreg,
- Ptr64,
- SingleFloat,
- SoftFloat,
- Sym32,
- UseIndirectJumpHazard,
- UseTccInDiv,
- Vfpu,
- Virt,
- Xgot,
- P5600,
-
- pub fn getInfo(self: @This()) FeatureInfo(@This()) {
- return feature_infos[@enumToInt(self)];
- }
-
- pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
- FeatureInfo(@This()).create(.Abs2008, "abs2008", "Disable IEEE 754-2008 abs.fmt mode", "abs2008"),
- FeatureInfo(@This()).create(.Crc, "crc", "Mips R6 CRC ASE", "crc"),
- FeatureInfo(@This()).createWithSubfeatures(.Cnmips, "cnmips", "Octeon cnMIPS Support", "cnmips", &[_]@This() {
- .Mips5_32r2,
- .Mips3_32r2,
- .Mips4_32r2,
- .Gp64,
- .Fp64,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- }),
- FeatureInfo(@This()).create(.Dsp, "dsp", "Mips DSP ASE", "dsp"),
- FeatureInfo(@This()).createWithSubfeatures(.Dspr2, "dspr2", "Mips DSP-R2 ASE", "dspr2", &[_]@This() {
- .Dsp,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Dspr3, "dspr3", "Mips DSP-R3 ASE", "dspr3", &[_]@This() {
- .Dsp,
- }),
- FeatureInfo(@This()).create(.Eva, "eva", "Mips EVA ASE", "eva"),
- FeatureInfo(@This()).create(.Fp64, "fp64", "Support 64-bit FP registers", "fp64"),
- FeatureInfo(@This()).create(.Fpxx, "fpxx", "Support for FPXX", "fpxx"),
- FeatureInfo(@This()).create(.Ginv, "ginv", "Mips Global Invalidate ASE", "ginv"),
- FeatureInfo(@This()).create(.Gp64, "gp64", "General Purpose Registers are 64-bit wide", "gp64"),
- FeatureInfo(@This()).create(.LongCalls, "long-calls", "Disable use of the jal instruction", "long-calls"),
- FeatureInfo(@This()).create(.Msa, "msa", "Mips MSA ASE", "msa"),
- FeatureInfo(@This()).create(.Mt, "mt", "Mips MT ASE", "mt"),
- FeatureInfo(@This()).create(.Nomadd4, "nomadd4", "Disable 4-operand madd.fmt and related instructions", "nomadd4"),
- FeatureInfo(@This()).create(.Micromips, "micromips", "microMips mode", "micromips"),
- FeatureInfo(@This()).create(.Mips1, "mips1", "Mips I ISA Support [highly experimental]", "mips1"),
- FeatureInfo(@This()).createWithSubfeatures(.Mips2, "mips2", "Mips II ISA Support [highly experimental]", "mips2", &[_]@This() {
- .Mips1,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Mips3, "mips3", "MIPS III ISA Support [highly experimental]", "mips3", &[_]@This() {
- .Mips3_32r2,
- .Fp64,
- .Gp64,
- .Mips1,
- .Mips3_32,
- }),
- FeatureInfo(@This()).create(.Mips3_32, "mips3_32", "Subset of MIPS-III that is also in MIPS32 [highly experimental]", "mips3_32"),
- FeatureInfo(@This()).create(.Mips3_32r2, "mips3_32r2", "Subset of MIPS-III that is also in MIPS32r2 [highly experimental]", "mips3_32r2"),
- FeatureInfo(@This()).createWithSubfeatures(.Mips4, "mips4", "MIPS IV ISA Support", "mips4", &[_]@This() {
- .Mips3_32r2,
- .Mips4_32r2,
- .Fp64,
- .Gp64,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- }),
- FeatureInfo(@This()).create(.Mips4_32, "mips4_32", "Subset of MIPS-IV that is also in MIPS32 [highly experimental]", "mips4_32"),
- FeatureInfo(@This()).create(.Mips4_32r2, "mips4_32r2", "Subset of MIPS-IV that is also in MIPS32r2 [highly experimental]", "mips4_32r2"),
- FeatureInfo(@This()).createWithSubfeatures(.Mips5, "mips5", "MIPS V ISA Support [highly experimental]", "mips5", &[_]@This() {
- .Mips5_32r2,
- .Mips4_32r2,
- .Mips3_32r2,
- .Gp64,
- .Fp64,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- }),
- FeatureInfo(@This()).create(.Mips5_32r2, "mips5_32r2", "Subset of MIPS-V that is also in MIPS32r2 [highly experimental]", "mips5_32r2"),
- FeatureInfo(@This()).create(.Mips16, "mips16", "Mips16 mode", "mips16"),
- FeatureInfo(@This()).createWithSubfeatures(.Mips32, "mips32", "Mips32 ISA Support", "mips32", &[_]@This() {
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Mips32r2, "mips32r2", "Mips32r2 ISA Support", "mips32r2", &[_]@This() {
- .Mips5_32r2,
- .Mips4_32r2,
- .Mips3_32r2,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Mips32r3, "mips32r3", "Mips32r3 ISA Support", "mips32r3", &[_]@This() {
- .Mips5_32r2,
- .Mips3_32r2,
- .Mips4_32r2,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Mips32r5, "mips32r5", "Mips32r5 ISA Support", "mips32r5", &[_]@This() {
- .Mips5_32r2,
- .Mips3_32r2,
- .Mips4_32r2,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Mips32r6, "mips32r6", "Mips32r6 ISA Support [experimental]", "mips32r6", &[_]@This() {
- .Mips5_32r2,
- .Mips3_32r2,
- .Mips4_32r2,
- .Abs2008,
- .Nan2008,
- .Fp64,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Mips64, "mips64", "Mips64 ISA Support", "mips64", &[_]@This() {
- .Mips5_32r2,
- .Mips3_32r2,
- .Mips4_32r2,
- .Gp64,
- .Fp64,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Mips64r2, "mips64r2", "Mips64r2 ISA Support", "mips64r2", &[_]@This() {
- .Mips5_32r2,
- .Mips3_32r2,
- .Mips4_32r2,
- .Gp64,
- .Fp64,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Mips64r3, "mips64r3", "Mips64r3 ISA Support", "mips64r3", &[_]@This() {
- .Mips5_32r2,
- .Mips3_32r2,
- .Mips4_32r2,
- .Gp64,
- .Fp64,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Mips64r5, "mips64r5", "Mips64r5 ISA Support", "mips64r5", &[_]@This() {
- .Mips5_32r2,
- .Mips3_32r2,
- .Mips4_32r2,
- .Gp64,
- .Fp64,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Mips64r6, "mips64r6", "Mips64r6 ISA Support [experimental]", "mips64r6", &[_]@This() {
- .Mips5_32r2,
- .Mips3_32r2,
- .Nan2008,
- .Abs2008,
- .Mips4_32r2,
- .Fp64,
- .Gp64,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- }),
- FeatureInfo(@This()).create(.Nan2008, "nan2008", "IEEE 754-2008 NaN encoding", "nan2008"),
- FeatureInfo(@This()).create(.Noabicalls, "noabicalls", "Disable SVR4-style position-independent code", "noabicalls"),
- FeatureInfo(@This()).create(.Nooddspreg, "nooddspreg", "Disable odd numbered single-precision registers", "nooddspreg"),
- FeatureInfo(@This()).create(.Ptr64, "ptr64", "Pointers are 64-bit wide", "ptr64"),
- FeatureInfo(@This()).create(.SingleFloat, "single-float", "Only supports single precision float", "single-float"),
- FeatureInfo(@This()).create(.SoftFloat, "soft-float", "Does not support floating point instructions", "soft-float"),
- FeatureInfo(@This()).create(.Sym32, "sym32", "Symbols are 32 bit on Mips64", "sym32"),
- FeatureInfo(@This()).create(.UseIndirectJumpHazard, "use-indirect-jump-hazard", "Use indirect jump guards to prevent certain speculation based attacks", "use-indirect-jump-hazard"),
- FeatureInfo(@This()).create(.UseTccInDiv, "use-tcc-in-div", "Force the assembler to use trapping", "use-tcc-in-div"),
- FeatureInfo(@This()).create(.Vfpu, "vfpu", "Enable vector FPU instructions", "vfpu"),
- FeatureInfo(@This()).create(.Virt, "virt", "Mips Virtualization ASE", "virt"),
- FeatureInfo(@This()).create(.Xgot, "xgot", "Assume 32-bit GOT", "xgot"),
- FeatureInfo(@This()).createWithSubfeatures(.P5600, "p5600", "The P5600 Processor", "p5600", &[_]@This() {
- .Mips5_32r2,
- .Mips3_32r2,
- .Mips4_32r2,
- .Mips4_32,
- .Mips1,
- .Mips3_32,
- }),
- };
-};
lib/std/target/feature/Msp430Feature.zig
@@ -1,19 +0,0 @@
-const FeatureInfo = @import("std").target.feature.FeatureInfo;
-
-pub const Msp430Feature = enum {
- Hwmult16,
- Hwmult32,
- Hwmultf5,
- Ext,
-
- pub fn getInfo(self: @This()) FeatureInfo(@This()) {
- return feature_infos[@enumToInt(self)];
- }
-
- pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
- FeatureInfo(@This()).create(.Hwmult16, "hwmult16", "Enable 16-bit hardware multiplier", "hwmult16"),
- FeatureInfo(@This()).create(.Hwmult32, "hwmult32", "Enable 32-bit hardware multiplier", "hwmult32"),
- FeatureInfo(@This()).create(.Hwmultf5, "hwmultf5", "Enable F5 series hardware multiplier", "hwmultf5"),
- FeatureInfo(@This()).create(.Ext, "ext", "Enable MSP430-X extensions", "ext"),
- };
-};
lib/std/target/feature/NvptxFeature.zig
@@ -1,61 +0,0 @@
-const FeatureInfo = @import("std").target.feature.FeatureInfo;
-
-pub const NvptxFeature = enum {
- Ptx32,
- Ptx40,
- Ptx41,
- Ptx42,
- Ptx43,
- Ptx50,
- Ptx60,
- Ptx61,
- Ptx63,
- Ptx64,
- Sm_20,
- Sm_21,
- Sm_30,
- Sm_32,
- Sm_35,
- Sm_37,
- Sm_50,
- Sm_52,
- Sm_53,
- Sm_60,
- Sm_61,
- Sm_62,
- Sm_70,
- Sm_72,
- Sm_75,
-
- pub fn getInfo(self: @This()) FeatureInfo(@This()) {
- return feature_infos[@enumToInt(self)];
- }
-
- pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
- FeatureInfo(@This()).create(.Ptx32, "ptx32", "Use PTX version 3.2", "ptx32"),
- FeatureInfo(@This()).create(.Ptx40, "ptx40", "Use PTX version 4.0", "ptx40"),
- FeatureInfo(@This()).create(.Ptx41, "ptx41", "Use PTX version 4.1", "ptx41"),
- FeatureInfo(@This()).create(.Ptx42, "ptx42", "Use PTX version 4.2", "ptx42"),
- FeatureInfo(@This()).create(.Ptx43, "ptx43", "Use PTX version 4.3", "ptx43"),
- FeatureInfo(@This()).create(.Ptx50, "ptx50", "Use PTX version 5.0", "ptx50"),
- FeatureInfo(@This()).create(.Ptx60, "ptx60", "Use PTX version 6.0", "ptx60"),
- FeatureInfo(@This()).create(.Ptx61, "ptx61", "Use PTX version 6.1", "ptx61"),
- FeatureInfo(@This()).create(.Ptx63, "ptx63", "Use PTX version 6.3", "ptx63"),
- FeatureInfo(@This()).create(.Ptx64, "ptx64", "Use PTX version 6.4", "ptx64"),
- FeatureInfo(@This()).create(.Sm_20, "sm_20", "Target SM 2.0", "sm_20"),
- FeatureInfo(@This()).create(.Sm_21, "sm_21", "Target SM 2.1", "sm_21"),
- FeatureInfo(@This()).create(.Sm_30, "sm_30", "Target SM 3.0", "sm_30"),
- FeatureInfo(@This()).create(.Sm_32, "sm_32", "Target SM 3.2", "sm_32"),
- FeatureInfo(@This()).create(.Sm_35, "sm_35", "Target SM 3.5", "sm_35"),
- FeatureInfo(@This()).create(.Sm_37, "sm_37", "Target SM 3.7", "sm_37"),
- FeatureInfo(@This()).create(.Sm_50, "sm_50", "Target SM 5.0", "sm_50"),
- FeatureInfo(@This()).create(.Sm_52, "sm_52", "Target SM 5.2", "sm_52"),
- FeatureInfo(@This()).create(.Sm_53, "sm_53", "Target SM 5.3", "sm_53"),
- FeatureInfo(@This()).create(.Sm_60, "sm_60", "Target SM 6.0", "sm_60"),
- FeatureInfo(@This()).create(.Sm_61, "sm_61", "Target SM 6.1", "sm_61"),
- FeatureInfo(@This()).create(.Sm_62, "sm_62", "Target SM 6.2", "sm_62"),
- FeatureInfo(@This()).create(.Sm_70, "sm_70", "Target SM 7.0", "sm_70"),
- FeatureInfo(@This()).create(.Sm_72, "sm_72", "Target SM 7.2", "sm_72"),
- FeatureInfo(@This()).create(.Sm_75, "sm_75", "Target SM 7.5", "sm_75"),
- };
-};
lib/std/target/feature/PowerPcFeature.zig
@@ -1,163 +0,0 @@
-const FeatureInfo = @import("std").target.feature.FeatureInfo;
-
-pub const PowerPcFeature = enum {
- Bit64,
- Bitregs64,
- Altivec,
- Bpermd,
- Booke,
- Cmpb,
- Crbits,
- DirectMove,
- E500,
- Extdiv,
- Fcpsgn,
- Fpcvt,
- Fprnd,
- Fpu,
- Fre,
- Fres,
- Frsqrte,
- Frsqrtes,
- Fsqrt,
- Float128,
- Htm,
- HardFloat,
- Icbt,
- IsaV30Instructions,
- Isel,
- InvariantFunctionDescriptors,
- Ldbrx,
- Lfiwax,
- Longcall,
- Mfocrf,
- Msync,
- Power8Altivec,
- Crypto,
- Power8Vector,
- Power9Altivec,
- Power9Vector,
- Popcntd,
- Ppc4xx,
- Ppc6xx,
- PpcPostraSched,
- PpcPreraSched,
- PartwordAtomics,
- Qpx,
- Recipprec,
- Spe,
- Stfiwx,
- SecurePlt,
- SlowPopcntd,
- TwoConstNr,
- Vsx,
- VectorsUseTwoUnits,
-
- pub fn getInfo(self: @This()) FeatureInfo(@This()) {
- return feature_infos[@enumToInt(self)];
- }
-
- pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
- FeatureInfo(@This()).create(.Bit64, "64bit", "Enable 64-bit instructions", "64bit"),
- FeatureInfo(@This()).create(.Bitregs64, "64bitregs", "Enable 64-bit registers usage for ppc32 [beta]", "64bitregs"),
- FeatureInfo(@This()).createWithSubfeatures(.Altivec, "altivec", "Enable Altivec instructions", "altivec", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).create(.Bpermd, "bpermd", "Enable the bpermd instruction", "bpermd"),
- FeatureInfo(@This()).createWithSubfeatures(.Booke, "booke", "Enable Book E instructions", "booke", &[_]@This() {
- .Icbt,
- }),
- FeatureInfo(@This()).create(.Cmpb, "cmpb", "Enable the cmpb instruction", "cmpb"),
- FeatureInfo(@This()).create(.Crbits, "crbits", "Use condition-register bits individually", "crbits"),
- FeatureInfo(@This()).createWithSubfeatures(.DirectMove, "direct-move", "Enable Power8 direct move instructions", "direct-move", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).create(.E500, "e500", "Enable E500/E500mc instructions", "e500"),
- FeatureInfo(@This()).create(.Extdiv, "extdiv", "Enable extended divide instructions", "extdiv"),
- FeatureInfo(@This()).createWithSubfeatures(.Fcpsgn, "fcpsgn", "Enable the fcpsgn instruction", "fcpsgn", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Fpcvt, "fpcvt", "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", "fpcvt", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Fprnd, "fprnd", "Enable the fri[mnpz] instructions", "fprnd", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Fpu, "fpu", "Enable classic FPU instructions", "fpu", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Fre, "fre", "Enable the fre instruction", "fre", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Fres, "fres", "Enable the fres instruction", "fres", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Frsqrte, "frsqrte", "Enable the frsqrte instruction", "frsqrte", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Frsqrtes, "frsqrtes", "Enable the frsqrtes instruction", "frsqrtes", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Fsqrt, "fsqrt", "Enable the fsqrt instruction", "fsqrt", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Float128, "float128", "Enable the __float128 data type for IEEE-754R Binary128.", "float128", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).create(.Htm, "htm", "Enable Hardware Transactional Memory instructions", "htm"),
- FeatureInfo(@This()).create(.HardFloat, "hard-float", "Enable floating-point instructions", "hard-float"),
- FeatureInfo(@This()).create(.Icbt, "icbt", "Enable icbt instruction", "icbt"),
- FeatureInfo(@This()).create(.IsaV30Instructions, "isa-v30-instructions", "Enable instructions added in ISA 3.0.", "isa-v30-instructions"),
- FeatureInfo(@This()).create(.Isel, "isel", "Enable the isel instruction", "isel"),
- FeatureInfo(@This()).create(.InvariantFunctionDescriptors, "invariant-function-descriptors", "Assume function descriptors are invariant", "invariant-function-descriptors"),
- FeatureInfo(@This()).create(.Ldbrx, "ldbrx", "Enable the ldbrx instruction", "ldbrx"),
- FeatureInfo(@This()).createWithSubfeatures(.Lfiwax, "lfiwax", "Enable the lfiwax instruction", "lfiwax", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).create(.Longcall, "longcall", "Always use indirect calls", "longcall"),
- FeatureInfo(@This()).create(.Mfocrf, "mfocrf", "Enable the MFOCRF instruction", "mfocrf"),
- FeatureInfo(@This()).createWithSubfeatures(.Msync, "msync", "Has only the msync instruction instead of sync", "msync", &[_]@This() {
- .Icbt,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Power8Altivec, "power8-altivec", "Enable POWER8 Altivec instructions", "power8-altivec", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Crypto, "crypto", "Enable POWER8 Crypto instructions", "crypto", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Power8Vector, "power8-vector", "Enable POWER8 vector instructions", "power8-vector", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Power9Altivec, "power9-altivec", "Enable POWER9 Altivec instructions", "power9-altivec", &[_]@This() {
- .IsaV30Instructions,
- .HardFloat,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Power9Vector, "power9-vector", "Enable POWER9 vector instructions", "power9-vector", &[_]@This() {
- .IsaV30Instructions,
- .HardFloat,
- }),
- FeatureInfo(@This()).create(.Popcntd, "popcntd", "Enable the popcnt[dw] instructions", "popcntd"),
- FeatureInfo(@This()).create(.Ppc4xx, "ppc4xx", "Enable PPC 4xx instructions", "ppc4xx"),
- FeatureInfo(@This()).create(.Ppc6xx, "ppc6xx", "Enable PPC 6xx instructions", "ppc6xx"),
- FeatureInfo(@This()).create(.PpcPostraSched, "ppc-postra-sched", "Use PowerPC post-RA scheduling strategy", "ppc-postra-sched"),
- FeatureInfo(@This()).create(.PpcPreraSched, "ppc-prera-sched", "Use PowerPC pre-RA scheduling strategy", "ppc-prera-sched"),
- FeatureInfo(@This()).create(.PartwordAtomics, "partword-atomics", "Enable l[bh]arx and st[bh]cx.", "partword-atomics"),
- FeatureInfo(@This()).createWithSubfeatures(.Qpx, "qpx", "Enable QPX instructions", "qpx", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).create(.Recipprec, "recipprec", "Assume higher precision reciprocal estimates", "recipprec"),
- FeatureInfo(@This()).createWithSubfeatures(.Spe, "spe", "Enable SPE instructions", "spe", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Stfiwx, "stfiwx", "Enable the stfiwx instruction", "stfiwx", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).create(.SecurePlt, "secure-plt", "Enable secure plt mode", "secure-plt"),
- FeatureInfo(@This()).create(.SlowPopcntd, "slow-popcntd", "Has slow popcnt[dw] instructions", "slow-popcntd"),
- FeatureInfo(@This()).create(.TwoConstNr, "two-const-nr", "Requires two constant Newton-Raphson computation", "two-const-nr"),
- FeatureInfo(@This()).createWithSubfeatures(.Vsx, "vsx", "Enable VSX instructions", "vsx", &[_]@This() {
- .HardFloat,
- }),
- FeatureInfo(@This()).create(.VectorsUseTwoUnits, "vectors-use-two-units", "Vectors use two units", "vectors-use-two-units"),
- };
-};
lib/std/target/feature/RiscVFeature.zig
@@ -1,31 +0,0 @@
-const FeatureInfo = @import("std").target.feature.FeatureInfo;
-
-pub const RiscVFeature = enum {
- Bit64,
- E,
- RvcHints,
- Relax,
- A,
- C,
- D,
- F,
- M,
-
- pub fn getInfo(self: @This()) FeatureInfo(@This()) {
- return feature_infos[@enumToInt(self)];
- }
-
- pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
- FeatureInfo(@This()).create(.Bit64, "64bit", "Implements RV64", "64bit"),
- FeatureInfo(@This()).create(.E, "e", "Implements RV32E (provides 16 rather than 32 GPRs)", "e"),
- FeatureInfo(@This()).create(.RvcHints, "rvc-hints", "Enable RVC Hint Instructions.", "rvc-hints"),
- FeatureInfo(@This()).create(.Relax, "relax", "Enable Linker relaxation.", "relax"),
- FeatureInfo(@This()).create(.A, "a", "'A' (Atomic Instructions)", "a"),
- FeatureInfo(@This()).create(.C, "c", "'C' (Compressed Instructions)", "c"),
- FeatureInfo(@This()).createWithSubfeatures(.D, "d", "'D' (Double-Precision Floating-Point)", "d", &[_]@This() {
- .F,
- }),
- FeatureInfo(@This()).create(.F, "f", "'F' (Single-Precision Floating-Point)", "f"),
- FeatureInfo(@This()).create(.M, "m", "'M' (Integer Multiplication and Division)", "m"),
- };
-};
lib/std/target/feature/SparcFeature.zig
@@ -1,49 +0,0 @@
-const FeatureInfo = @import("std").target.feature.FeatureInfo;
-
-pub const SparcFeature = enum {
- Detectroundchange,
- HardQuadFloat,
- Leon,
- NoFmuls,
- NoFsmuld,
- Leonpwrpsr,
- SoftFloat,
- SoftMulDiv,
- DeprecatedV8,
- V9,
- Vis,
- Vis2,
- Vis3,
- Fixallfdivsqrt,
- Insertnopload,
- Hasleoncasa,
- Leoncyclecounter,
- Hasumacsmac,
- Popc,
-
- pub fn getInfo(self: @This()) FeatureInfo(@This()) {
- return feature_infos[@enumToInt(self)];
- }
-
- pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
- FeatureInfo(@This()).create(.Detectroundchange, "detectroundchange", "LEON3 erratum detection: Detects any rounding mode change request: use only the round-to-nearest rounding mode", "detectroundchange"),
- FeatureInfo(@This()).create(.HardQuadFloat, "hard-quad-float", "Enable quad-word floating point instructions", "hard-quad-float"),
- FeatureInfo(@This()).create(.Leon, "leon", "Enable LEON extensions", "leon"),
- FeatureInfo(@This()).create(.NoFmuls, "no-fmuls", "Disable the fmuls instruction.", "no-fmuls"),
- FeatureInfo(@This()).create(.NoFsmuld, "no-fsmuld", "Disable the fsmuld instruction.", "no-fsmuld"),
- FeatureInfo(@This()).create(.Leonpwrpsr, "leonpwrpsr", "Enable the PWRPSR instruction", "leonpwrpsr"),
- FeatureInfo(@This()).create(.SoftFloat, "soft-float", "Use software emulation for floating point", "soft-float"),
- FeatureInfo(@This()).create(.SoftMulDiv, "soft-mul-div", "Use software emulation for integer multiply and divide", "soft-mul-div"),
- FeatureInfo(@This()).create(.DeprecatedV8, "deprecated-v8", "Enable deprecated V8 instructions in V9 mode", "deprecated-v8"),
- FeatureInfo(@This()).create(.V9, "v9", "Enable SPARC-V9 instructions", "v9"),
- FeatureInfo(@This()).create(.Vis, "vis", "Enable UltraSPARC Visual Instruction Set extensions", "vis"),
- FeatureInfo(@This()).create(.Vis2, "vis2", "Enable Visual Instruction Set extensions II", "vis2"),
- FeatureInfo(@This()).create(.Vis3, "vis3", "Enable Visual Instruction Set extensions III", "vis3"),
- FeatureInfo(@This()).create(.Fixallfdivsqrt, "fixallfdivsqrt", "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store", "fixallfdivsqrt"),
- FeatureInfo(@This()).create(.Insertnopload, "insertnopload", "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction", "insertnopload"),
- FeatureInfo(@This()).create(.Hasleoncasa, "hasleoncasa", "Enable CASA instruction for LEON3 and LEON4 processors", "hasleoncasa"),
- FeatureInfo(@This()).create(.Leoncyclecounter, "leoncyclecounter", "Use the Leon cycle counter register", "leoncyclecounter"),
- FeatureInfo(@This()).create(.Hasumacsmac, "hasumacsmac", "Enable UMAC and SMAC for LEON3 and LEON4 processors", "hasumacsmac"),
- FeatureInfo(@This()).create(.Popc, "popc", "Use the popc (population count) instruction", "popc"),
- };
-};
lib/std/target/feature/SystemZFeature.zig
@@ -1,81 +0,0 @@
-const FeatureInfo = @import("std").target.feature.FeatureInfo;
-
-pub const SystemZFeature = enum {
- DfpPackedConversion,
- DfpZonedConversion,
- DeflateConversion,
- DistinctOps,
- EnhancedDat2,
- EnhancedSort,
- ExecutionHint,
- FpExtension,
- FastSerialization,
- GuardedStorage,
- HighWord,
- InsertReferenceBitsMultiple,
- InterlockedAccess1,
- LoadAndTrap,
- LoadAndZeroRightmostByte,
- LoadStoreOnCond,
- LoadStoreOnCond2,
- MessageSecurityAssistExtension3,
- MessageSecurityAssistExtension4,
- MessageSecurityAssistExtension5,
- MessageSecurityAssistExtension7,
- MessageSecurityAssistExtension8,
- MessageSecurityAssistExtension9,
- MiscellaneousExtensions,
- MiscellaneousExtensions2,
- MiscellaneousExtensions3,
- PopulationCount,
- ProcessorAssist,
- ResetReferenceBitsMultiple,
- TransactionalExecution,
- Vector,
- VectorEnhancements1,
- VectorEnhancements2,
- VectorPackedDecimal,
- VectorPackedDecimalEnhancement,
-
- pub fn getInfo(self: @This()) FeatureInfo(@This()) {
- return feature_infos[@enumToInt(self)];
- }
-
- pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
- FeatureInfo(@This()).create(.DfpPackedConversion, "dfp-packed-conversion", "Assume that the DFP packed-conversion facility is installed", "dfp-packed-conversion"),
- FeatureInfo(@This()).create(.DfpZonedConversion, "dfp-zoned-conversion", "Assume that the DFP zoned-conversion facility is installed", "dfp-zoned-conversion"),
- FeatureInfo(@This()).create(.DeflateConversion, "deflate-conversion", "Assume that the deflate-conversion facility is installed", "deflate-conversion"),
- FeatureInfo(@This()).create(.DistinctOps, "distinct-ops", "Assume that the distinct-operands facility is installed", "distinct-ops"),
- FeatureInfo(@This()).create(.EnhancedDat2, "enhanced-dat-2", "Assume that the enhanced-DAT facility 2 is installed", "enhanced-dat-2"),
- FeatureInfo(@This()).create(.EnhancedSort, "enhanced-sort", "Assume that the enhanced-sort facility is installed", "enhanced-sort"),
- FeatureInfo(@This()).create(.ExecutionHint, "execution-hint", "Assume that the execution-hint facility is installed", "execution-hint"),
- FeatureInfo(@This()).create(.FpExtension, "fp-extension", "Assume that the floating-point extension facility is installed", "fp-extension"),
- FeatureInfo(@This()).create(.FastSerialization, "fast-serialization", "Assume that the fast-serialization facility is installed", "fast-serialization"),
- FeatureInfo(@This()).create(.GuardedStorage, "guarded-storage", "Assume that the guarded-storage facility is installed", "guarded-storage"),
- FeatureInfo(@This()).create(.HighWord, "high-word", "Assume that the high-word facility is installed", "high-word"),
- FeatureInfo(@This()).create(.InsertReferenceBitsMultiple, "insert-reference-bits-multiple", "Assume that the insert-reference-bits-multiple facility is installed", "insert-reference-bits-multiple"),
- FeatureInfo(@This()).create(.InterlockedAccess1, "interlocked-access1", "Assume that interlocked-access facility 1 is installed", "interlocked-access1"),
- FeatureInfo(@This()).create(.LoadAndTrap, "load-and-trap", "Assume that the load-and-trap facility is installed", "load-and-trap"),
- FeatureInfo(@This()).create(.LoadAndZeroRightmostByte, "load-and-zero-rightmost-byte", "Assume that the load-and-zero-rightmost-byte facility is installed", "load-and-zero-rightmost-byte"),
- FeatureInfo(@This()).create(.LoadStoreOnCond, "load-store-on-cond", "Assume that the load/store-on-condition facility is installed", "load-store-on-cond"),
- FeatureInfo(@This()).create(.LoadStoreOnCond2, "load-store-on-cond-2", "Assume that the load/store-on-condition facility 2 is installed", "load-store-on-cond-2"),
- FeatureInfo(@This()).create(.MessageSecurityAssistExtension3, "message-security-assist-extension3", "Assume that the message-security-assist extension facility 3 is installed", "message-security-assist-extension3"),
- FeatureInfo(@This()).create(.MessageSecurityAssistExtension4, "message-security-assist-extension4", "Assume that the message-security-assist extension facility 4 is installed", "message-security-assist-extension4"),
- FeatureInfo(@This()).create(.MessageSecurityAssistExtension5, "message-security-assist-extension5", "Assume that the message-security-assist extension facility 5 is installed", "message-security-assist-extension5"),
- FeatureInfo(@This()).create(.MessageSecurityAssistExtension7, "message-security-assist-extension7", "Assume that the message-security-assist extension facility 7 is installed", "message-security-assist-extension7"),
- FeatureInfo(@This()).create(.MessageSecurityAssistExtension8, "message-security-assist-extension8", "Assume that the message-security-assist extension facility 8 is installed", "message-security-assist-extension8"),
- FeatureInfo(@This()).create(.MessageSecurityAssistExtension9, "message-security-assist-extension9", "Assume that the message-security-assist extension facility 9 is installed", "message-security-assist-extension9"),
- FeatureInfo(@This()).create(.MiscellaneousExtensions, "miscellaneous-extensions", "Assume that the miscellaneous-extensions facility is installed", "miscellaneous-extensions"),
- FeatureInfo(@This()).create(.MiscellaneousExtensions2, "miscellaneous-extensions-2", "Assume that the miscellaneous-extensions facility 2 is installed", "miscellaneous-extensions-2"),
- FeatureInfo(@This()).create(.MiscellaneousExtensions3, "miscellaneous-extensions-3", "Assume that the miscellaneous-extensions facility 3 is installed", "miscellaneous-extensions-3"),
- FeatureInfo(@This()).create(.PopulationCount, "population-count", "Assume that the population-count facility is installed", "population-count"),
- FeatureInfo(@This()).create(.ProcessorAssist, "processor-assist", "Assume that the processor-assist facility is installed", "processor-assist"),
- FeatureInfo(@This()).create(.ResetReferenceBitsMultiple, "reset-reference-bits-multiple", "Assume that the reset-reference-bits-multiple facility is installed", "reset-reference-bits-multiple"),
- FeatureInfo(@This()).create(.TransactionalExecution, "transactional-execution", "Assume that the transactional-execution facility is installed", "transactional-execution"),
- FeatureInfo(@This()).create(.Vector, "vector", "Assume that the vectory facility is installed", "vector"),
- FeatureInfo(@This()).create(.VectorEnhancements1, "vector-enhancements-1", "Assume that the vector enhancements facility 1 is installed", "vector-enhancements-1"),
- FeatureInfo(@This()).create(.VectorEnhancements2, "vector-enhancements-2", "Assume that the vector enhancements facility 2 is installed", "vector-enhancements-2"),
- FeatureInfo(@This()).create(.VectorPackedDecimal, "vector-packed-decimal", "Assume that the vector packed decimal facility is installed", "vector-packed-decimal"),
- FeatureInfo(@This()).create(.VectorPackedDecimalEnhancement, "vector-packed-decimal-enhancement", "Assume that the vector packed decimal enhancement facility is installed", "vector-packed-decimal-enhancement"),
- };
-};
lib/std/target/feature/WebAssemblyFeature.zig
@@ -1,33 +0,0 @@
-const FeatureInfo = @import("std").target.feature.FeatureInfo;
-
-pub const WebAssemblyFeature = enum {
- Atomics,
- BulkMemory,
- ExceptionHandling,
- Multivalue,
- MutableGlobals,
- NontrappingFptoint,
- Simd128,
- SignExt,
- TailCall,
- UnimplementedSimd128,
-
- pub fn getInfo(self: @This()) FeatureInfo(@This()) {
- return feature_infos[@enumToInt(self)];
- }
-
- pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
- FeatureInfo(@This()).create(.Atomics, "atomics", "Enable Atomics", "atomics"),
- FeatureInfo(@This()).create(.BulkMemory, "bulk-memory", "Enable bulk memory operations", "bulk-memory"),
- FeatureInfo(@This()).create(.ExceptionHandling, "exception-handling", "Enable Wasm exception handling", "exception-handling"),
- FeatureInfo(@This()).create(.Multivalue, "multivalue", "Enable multivalue blocks, instructions, and functions", "multivalue"),
- FeatureInfo(@This()).create(.MutableGlobals, "mutable-globals", "Enable mutable globals", "mutable-globals"),
- FeatureInfo(@This()).create(.NontrappingFptoint, "nontrapping-fptoint", "Enable non-trapping float-to-int conversion operators", "nontrapping-fptoint"),
- FeatureInfo(@This()).create(.Simd128, "simd128", "Enable 128-bit SIMD", "simd128"),
- FeatureInfo(@This()).create(.SignExt, "sign-ext", "Enable sign extension operators", "sign-ext"),
- FeatureInfo(@This()).create(.TailCall, "tail-call", "Enable tail call instructions", "tail-call"),
- FeatureInfo(@This()).createWithSubfeatures(.UnimplementedSimd128, "unimplemented-simd128", "Enable 128-bit SIMD not yet implemented in engines", "unimplemented-simd128", &[_]@This() {
- .Simd128,
- }),
- };
-};
lib/std/target/feature/X86Feature.zig
@@ -1,342 +0,0 @@
-const FeatureInfo = @import("std").target.feature.FeatureInfo;
-
-pub const X86Feature = enum {
- Dnow3,
- Dnowa3,
- Bit64,
- Adx,
- Aes,
- Avx,
- Avx2,
- Avx512f,
- Avx512bf16,
- Avx512bitalg,
- Bmi,
- Bmi2,
- Avx512bw,
- Branchfusion,
- Avx512cd,
- Cldemote,
- Clflushopt,
- Clwb,
- Clzero,
- Cmov,
- Cx8,
- Cx16,
- Avx512dq,
- Mpx,
- Enqcmd,
- Avx512er,
- Ermsb,
- F16c,
- Fma,
- Fma4,
- Fsgsbase,
- Fxsr,
- Fast11bytenop,
- Fast15bytenop,
- FastBextr,
- FastHops,
- FastLzcnt,
- FastPartialYmmOrZmmWrite,
- FastShldRotate,
- FastScalarFsqrt,
- FastScalarShiftMasks,
- FastVariableShuffle,
- FastVectorFsqrt,
- FastVectorShiftMasks,
- Gfni,
- FastGather,
- Avx512ifma,
- Invpcid,
- Sahf,
- LeaSp,
- LeaUsesAg,
- Lwp,
- Lzcnt,
- FalseDepsLzcntTzcnt,
- Mmx,
- Movbe,
- Movdir64b,
- Movdiri,
- Mwaitx,
- Macrofusion,
- MergeToThreewayBranch,
- Nopl,
- Pclmul,
- Pconfig,
- Avx512pf,
- Pku,
- Popcnt,
- FalseDepsPopcnt,
- Prefetchwt1,
- Prfchw,
- Ptwrite,
- PadShortFunctions,
- Prefer128Bit,
- Prefer256Bit,
- Rdpid,
- Rdrnd,
- Rdseed,
- Rtm,
- Retpoline,
- RetpolineExternalThunk,
- RetpolineIndirectBranches,
- RetpolineIndirectCalls,
- Sgx,
- Sha,
- Shstk,
- Sse,
- Sse2,
- Sse3,
- Sse4a,
- Sse41,
- Sse42,
- SseUnalignedMem,
- Ssse3,
- Slow3opsLea,
- IdivlToDivb,
- IdivqToDivl,
- SlowIncdec,
- SlowLea,
- SlowPmaddwd,
- SlowPmulld,
- SlowShld,
- SlowTwoMemOps,
- SlowUnalignedMem16,
- SlowUnalignedMem32,
- SoftFloat,
- Tbm,
- UseAa,
- Vaes,
- Avx512vbmi,
- Avx512vbmi2,
- Avx512vl,
- Avx512vnni,
- Avx512vp2intersect,
- Vpclmulqdq,
- Avx512vpopcntdq,
- Waitpkg,
- Wbnoinvd,
- X87,
- Xop,
- Xsave,
- Xsavec,
- Xsaveopt,
- Xsaves,
- BitMode16,
- BitMode32,
- BitMode64,
-
- pub fn getInfo(self: @This()) FeatureInfo(@This()) {
- return feature_infos[@enumToInt(self)];
- }
-
- pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
- FeatureInfo(@This()).createWithSubfeatures(.Dnow3, "3dnow", "Enable 3DNow! instructions", "3dnow", &[_]@This() {
- .Mmx,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Dnowa3, "3dnowa", "Enable 3DNow! Athlon instructions", "3dnowa", &[_]@This() {
- .Mmx,
- }),
- FeatureInfo(@This()).create(.Bit64, "64bit", "Support 64-bit instructions", "64bit"),
- FeatureInfo(@This()).create(.Adx, "adx", "Support ADX instructions", "adx"),
- FeatureInfo(@This()).createWithSubfeatures(.Aes, "aes", "Enable AES instructions", "aes", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avx, "avx", "Enable AVX instructions", "avx", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avx2, "avx2", "Enable AVX2 instructions", "avx2", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avx512f, "avx512f", "Enable AVX-512 instructions", "avx512f", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avx512bf16, "avx512bf16", "Support bfloat16 floating point", "avx512bf16", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avx512bitalg, "avx512bitalg", "Enable AVX-512 Bit Algorithms", "avx512bitalg", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).create(.Bmi, "bmi", "Support BMI instructions", "bmi"),
- FeatureInfo(@This()).create(.Bmi2, "bmi2", "Support BMI2 instructions", "bmi2"),
- FeatureInfo(@This()).createWithSubfeatures(.Avx512bw, "avx512bw", "Enable AVX-512 Byte and Word Instructions", "avx512bw", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).create(.Branchfusion, "branchfusion", "CMP/TEST can be fused with conditional branches", "branchfusion"),
- FeatureInfo(@This()).createWithSubfeatures(.Avx512cd, "avx512cd", "Enable AVX-512 Conflict Detection Instructions", "avx512cd", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).create(.Cldemote, "cldemote", "Enable Cache Demote", "cldemote"),
- FeatureInfo(@This()).create(.Clflushopt, "clflushopt", "Flush A Cache Line Optimized", "clflushopt"),
- FeatureInfo(@This()).create(.Clwb, "clwb", "Cache Line Write Back", "clwb"),
- FeatureInfo(@This()).create(.Clzero, "clzero", "Enable Cache Line Zero", "clzero"),
- FeatureInfo(@This()).create(.Cmov, "cmov", "Enable conditional move instructions", "cmov"),
- FeatureInfo(@This()).create(.Cx8, "cx8", "Support CMPXCHG8B instructions", "cx8"),
- FeatureInfo(@This()).createWithSubfeatures(.Cx16, "cx16", "64-bit with cmpxchg16b", "cx16", &[_]@This() {
- .Cx8,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avx512dq, "avx512dq", "Enable AVX-512 Doubleword and Quadword Instructions", "avx512dq", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).create(.Mpx, "mpx", "Deprecated. Support MPX instructions", "mpx"),
- FeatureInfo(@This()).create(.Enqcmd, "enqcmd", "Has ENQCMD instructions", "enqcmd"),
- FeatureInfo(@This()).createWithSubfeatures(.Avx512er, "avx512er", "Enable AVX-512 Exponential and Reciprocal Instructions", "avx512er", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).create(.Ermsb, "ermsb", "REP MOVS/STOS are fast", "ermsb"),
- FeatureInfo(@This()).createWithSubfeatures(.F16c, "f16c", "Support 16-bit floating point conversion instructions", "f16c", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Fma, "fma", "Enable three-operand fused multiple-add", "fma", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Fma4, "fma4", "Enable four-operand fused multiple-add", "fma4", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).create(.Fsgsbase, "fsgsbase", "Support FS/GS Base instructions", "fsgsbase"),
- FeatureInfo(@This()).create(.Fxsr, "fxsr", "Support fxsave/fxrestore instructions", "fxsr"),
- FeatureInfo(@This()).create(.Fast11bytenop, "fast-11bytenop", "Target can quickly decode up to 11 byte NOPs", "fast-11bytenop"),
- FeatureInfo(@This()).create(.Fast15bytenop, "fast-15bytenop", "Target can quickly decode up to 15 byte NOPs", "fast-15bytenop"),
- FeatureInfo(@This()).create(.FastBextr, "fast-bextr", "Indicates that the BEXTR instruction is implemented as a single uop with good throughput", "fast-bextr"),
- FeatureInfo(@This()).createWithSubfeatures(.FastHops, "fast-hops", "Prefer horizontal vector math instructions (haddp, phsub, etc.) over normal vector instructions with shuffles", "fast-hops", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).create(.FastLzcnt, "fast-lzcnt", "LZCNT instructions are as fast as most simple integer ops", "fast-lzcnt"),
- FeatureInfo(@This()).create(.FastPartialYmmOrZmmWrite, "fast-partial-ymm-or-zmm-write", "Partial writes to YMM/ZMM registers are fast", "fast-partial-ymm-or-zmm-write"),
- FeatureInfo(@This()).create(.FastShldRotate, "fast-shld-rotate", "SHLD can be used as a faster rotate", "fast-shld-rotate"),
- FeatureInfo(@This()).create(.FastScalarFsqrt, "fast-scalar-fsqrt", "Scalar SQRT is fast (disable Newton-Raphson)", "fast-scalar-fsqrt"),
- FeatureInfo(@This()).create(.FastScalarShiftMasks, "fast-scalar-shift-masks", "Prefer a left/right scalar logical shift pair over a shift+and pair", "fast-scalar-shift-masks"),
- FeatureInfo(@This()).create(.FastVariableShuffle, "fast-variable-shuffle", "Shuffles with variable masks are fast", "fast-variable-shuffle"),
- FeatureInfo(@This()).create(.FastVectorFsqrt, "fast-vector-fsqrt", "Vector SQRT is fast (disable Newton-Raphson)", "fast-vector-fsqrt"),
- FeatureInfo(@This()).create(.FastVectorShiftMasks, "fast-vector-shift-masks", "Prefer a left/right vector logical shift pair over a shift+and pair", "fast-vector-shift-masks"),
- FeatureInfo(@This()).createWithSubfeatures(.Gfni, "gfni", "Enable Galois Field Arithmetic Instructions", "gfni", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).create(.FastGather, "fast-gather", "Indicates if gather is reasonably fast", "fast-gather"),
- FeatureInfo(@This()).createWithSubfeatures(.Avx512ifma, "avx512ifma", "Enable AVX-512 Integer Fused Multiple-Add", "avx512ifma", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).create(.Invpcid, "invpcid", "Invalidate Process-Context Identifier", "invpcid"),
- FeatureInfo(@This()).create(.Sahf, "sahf", "Support LAHF and SAHF instructions", "sahf"),
- FeatureInfo(@This()).create(.LeaSp, "lea-sp", "Use LEA for adjusting the stack pointer", "lea-sp"),
- FeatureInfo(@This()).create(.LeaUsesAg, "lea-uses-ag", "LEA instruction needs inputs at AG stage", "lea-uses-ag"),
- FeatureInfo(@This()).create(.Lwp, "lwp", "Enable LWP instructions", "lwp"),
- FeatureInfo(@This()).create(.Lzcnt, "lzcnt", "Support LZCNT instruction", "lzcnt"),
- FeatureInfo(@This()).create(.FalseDepsLzcntTzcnt, "false-deps-lzcnt-tzcnt", "LZCNT/TZCNT have a false dependency on dest register", "false-deps-lzcnt-tzcnt"),
- FeatureInfo(@This()).create(.Mmx, "mmx", "Enable MMX instructions", "mmx"),
- FeatureInfo(@This()).create(.Movbe, "movbe", "Support MOVBE instruction", "movbe"),
- FeatureInfo(@This()).create(.Movdir64b, "movdir64b", "Support movdir64b instruction", "movdir64b"),
- FeatureInfo(@This()).create(.Movdiri, "movdiri", "Support movdiri instruction", "movdiri"),
- FeatureInfo(@This()).create(.Mwaitx, "mwaitx", "Enable MONITORX/MWAITX timer functionality", "mwaitx"),
- FeatureInfo(@This()).create(.Macrofusion, "macrofusion", "Various instructions can be fused with conditional branches", "macrofusion"),
- FeatureInfo(@This()).create(.MergeToThreewayBranch, "merge-to-threeway-branch", "Merge branches to a three-way conditional branch", "merge-to-threeway-branch"),
- FeatureInfo(@This()).create(.Nopl, "nopl", "Enable NOPL instruction", "nopl"),
- FeatureInfo(@This()).createWithSubfeatures(.Pclmul, "pclmul", "Enable packed carry-less multiplication instructions", "pclmul", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).create(.Pconfig, "pconfig", "platform configuration instruction", "pconfig"),
- FeatureInfo(@This()).createWithSubfeatures(.Avx512pf, "avx512pf", "Enable AVX-512 PreFetch Instructions", "avx512pf", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).create(.Pku, "pku", "Enable protection keys", "pku"),
- FeatureInfo(@This()).create(.Popcnt, "popcnt", "Support POPCNT instruction", "popcnt"),
- FeatureInfo(@This()).create(.FalseDepsPopcnt, "false-deps-popcnt", "POPCNT has a false dependency on dest register", "false-deps-popcnt"),
- FeatureInfo(@This()).create(.Prefetchwt1, "prefetchwt1", "Prefetch with Intent to Write and T1 Hint", "prefetchwt1"),
- FeatureInfo(@This()).create(.Prfchw, "prfchw", "Support PRFCHW instructions", "prfchw"),
- FeatureInfo(@This()).create(.Ptwrite, "ptwrite", "Support ptwrite instruction", "ptwrite"),
- FeatureInfo(@This()).create(.PadShortFunctions, "pad-short-functions", "Pad short functions", "pad-short-functions"),
- FeatureInfo(@This()).create(.Prefer128Bit, "prefer-128-bit", "Prefer 128-bit AVX instructions", "prefer-128-bit"),
- FeatureInfo(@This()).create(.Prefer256Bit, "prefer-256-bit", "Prefer 256-bit AVX instructions", "prefer-256-bit"),
- FeatureInfo(@This()).create(.Rdpid, "rdpid", "Support RDPID instructions", "rdpid"),
- FeatureInfo(@This()).create(.Rdrnd, "rdrnd", "Support RDRAND instruction", "rdrnd"),
- FeatureInfo(@This()).create(.Rdseed, "rdseed", "Support RDSEED instruction", "rdseed"),
- FeatureInfo(@This()).create(.Rtm, "rtm", "Support RTM instructions", "rtm"),
- FeatureInfo(@This()).createWithSubfeatures(.Retpoline, "retpoline", "Remove speculation of indirect branches from the generated code, either by avoiding them entirely or lowering them with a speculation blocking construct", "retpoline", &[_]@This() {
- .RetpolineIndirectCalls,
- .RetpolineIndirectBranches,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.RetpolineExternalThunk, "retpoline-external-thunk", "When lowering an indirect call or branch using a `retpoline`, rely on the specified user provided thunk rather than emitting one ourselves. Only has effect when combined with some other retpoline feature", "retpoline-external-thunk", &[_]@This() {
- .RetpolineIndirectCalls,
- }),
- FeatureInfo(@This()).create(.RetpolineIndirectBranches, "retpoline-indirect-branches", "Remove speculation of indirect branches from the generated code", "retpoline-indirect-branches"),
- FeatureInfo(@This()).create(.RetpolineIndirectCalls, "retpoline-indirect-calls", "Remove speculation of indirect calls from the generated code", "retpoline-indirect-calls"),
- FeatureInfo(@This()).create(.Sgx, "sgx", "Enable Software Guard Extensions", "sgx"),
- FeatureInfo(@This()).createWithSubfeatures(.Sha, "sha", "Enable SHA instructions", "sha", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).create(.Shstk, "shstk", "Support CET Shadow-Stack instructions", "shstk"),
- FeatureInfo(@This()).create(.Sse, "sse", "Enable SSE instructions", "sse"),
- FeatureInfo(@This()).createWithSubfeatures(.Sse2, "sse2", "Enable SSE2 instructions", "sse2", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Sse3, "sse3", "Enable SSE3 instructions", "sse3", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Sse4a, "sse4a", "Support SSE 4a instructions", "sse4a", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Sse41, "sse4.1", "Enable SSE 4.1 instructions", "sse4.1", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Sse42, "sse4.2", "Enable SSE 4.2 instructions", "sse4.2", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).create(.SseUnalignedMem, "sse-unaligned-mem", "Allow unaligned memory operands with SSE instructions", "sse-unaligned-mem"),
- FeatureInfo(@This()).createWithSubfeatures(.Ssse3, "ssse3", "Enable SSSE3 instructions", "ssse3", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).create(.Slow3opsLea, "slow-3ops-lea", "LEA instruction with 3 ops or certain registers is slow", "slow-3ops-lea"),
- FeatureInfo(@This()).create(.IdivlToDivb, "idivl-to-divb", "Use 8-bit divide for positive values less than 256", "idivl-to-divb"),
- FeatureInfo(@This()).create(.IdivqToDivl, "idivq-to-divl", "Use 32-bit divide for positive values less than 2^32", "idivq-to-divl"),
- FeatureInfo(@This()).create(.SlowIncdec, "slow-incdec", "INC and DEC instructions are slower than ADD and SUB", "slow-incdec"),
- FeatureInfo(@This()).create(.SlowLea, "slow-lea", "LEA instruction with certain arguments is slow", "slow-lea"),
- FeatureInfo(@This()).create(.SlowPmaddwd, "slow-pmaddwd", "PMADDWD is slower than PMULLD", "slow-pmaddwd"),
- FeatureInfo(@This()).create(.SlowPmulld, "slow-pmulld", "PMULLD instruction is slow", "slow-pmulld"),
- FeatureInfo(@This()).create(.SlowShld, "slow-shld", "SHLD instruction is slow", "slow-shld"),
- FeatureInfo(@This()).create(.SlowTwoMemOps, "slow-two-mem-ops", "Two memory operand instructions are slow", "slow-two-mem-ops"),
- FeatureInfo(@This()).create(.SlowUnalignedMem16, "slow-unaligned-mem-16", "Slow unaligned 16-byte memory access", "slow-unaligned-mem-16"),
- FeatureInfo(@This()).create(.SlowUnalignedMem32, "slow-unaligned-mem-32", "Slow unaligned 32-byte memory access", "slow-unaligned-mem-32"),
- FeatureInfo(@This()).create(.SoftFloat, "soft-float", "Use software floating point features", "soft-float"),
- FeatureInfo(@This()).create(.Tbm, "tbm", "Enable TBM instructions", "tbm"),
- FeatureInfo(@This()).create(.UseAa, "use-aa", "Use alias analysis during codegen", "use-aa"),
- FeatureInfo(@This()).createWithSubfeatures(.Vaes, "vaes", "Promote selected AES instructions to AVX512/AVX registers", "vaes", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avx512vbmi, "avx512vbmi", "Enable AVX-512 Vector Byte Manipulation Instructions", "avx512vbmi", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avx512vbmi2, "avx512vbmi2", "Enable AVX-512 further Vector Byte Manipulation Instructions", "avx512vbmi2", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avx512vl, "avx512vl", "Enable AVX-512 Vector Length eXtensions", "avx512vl", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avx512vnni, "avx512vnni", "Enable AVX-512 Vector Neural Network Instructions", "avx512vnni", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avx512vp2intersect, "avx512vp2intersect", "Enable AVX-512 vp2intersect", "avx512vp2intersect", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Vpclmulqdq, "vpclmulqdq", "Enable vpclmulqdq instructions", "vpclmulqdq", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).createWithSubfeatures(.Avx512vpopcntdq, "avx512vpopcntdq", "Enable AVX-512 Population Count Instructions", "avx512vpopcntdq", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).create(.Waitpkg, "waitpkg", "Wait and pause enhancements", "waitpkg"),
- FeatureInfo(@This()).create(.Wbnoinvd, "wbnoinvd", "Write Back No Invalidate", "wbnoinvd"),
- FeatureInfo(@This()).create(.X87, "x87", "Enable X87 float instructions", "x87"),
- FeatureInfo(@This()).createWithSubfeatures(.Xop, "xop", "Enable XOP instructions", "xop", &[_]@This() {
- .Sse,
- }),
- FeatureInfo(@This()).create(.Xsave, "xsave", "Support xsave instructions", "xsave"),
- FeatureInfo(@This()).create(.Xsavec, "xsavec", "Support xsavec instructions", "xsavec"),
- FeatureInfo(@This()).create(.Xsaveopt, "xsaveopt", "Support xsaveopt instructions", "xsaveopt"),
- FeatureInfo(@This()).create(.Xsaves, "xsaves", "Support xsaves instructions", "xsaves"),
- FeatureInfo(@This()).create(.BitMode16, "16bit-mode", "16-bit mode (i8086)", "16bit-mode"),
- FeatureInfo(@This()).create(.BitMode32, "32bit-mode", "32-bit mode (80386)", "32bit-mode"),
- FeatureInfo(@This()).create(.BitMode64, "64bit-mode", "64-bit mode (x86_64)", "64bit-mode"),
- };
-};
lib/std/target/aarch64.zig
@@ -0,0 +1,2383 @@
+const Feature = @import("std").target.Feature;
+const Cpu = @import("std").target.Cpu;
+
+pub const feature_aes = Feature{
+ .name = "aes",
+ .description = "Enable AES support",
+ .llvm_name = "aes",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpArmv8,
+ },
+};
+
+pub const feature_am = Feature{
+ .name = "am",
+ .description = "Enable v8.4-A Activity Monitors extension",
+ .llvm_name = "am",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_aggressiveFma = Feature{
+ .name = "aggressive-fma",
+ .description = "Enable Aggressive FMA for floating-point.",
+ .llvm_name = "aggressive-fma",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_altnzcv = Feature{
+ .name = "altnzcv",
+ .description = "Enable alternative NZCV format for floating point comparisons",
+ .llvm_name = "altnzcv",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_alternateSextloadCvtF32Pattern = Feature{
+ .name = "alternate-sextload-cvt-f32-pattern",
+ .description = "Use alternative pattern for sextload convert to f32",
+ .llvm_name = "alternate-sextload-cvt-f32-pattern",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_arithBccFusion = Feature{
+ .name = "arith-bcc-fusion",
+ .description = "CPU fuses arithmetic+bcc operations",
+ .llvm_name = "arith-bcc-fusion",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_arithCbzFusion = Feature{
+ .name = "arith-cbz-fusion",
+ .description = "CPU fuses arithmetic + cbz/cbnz operations",
+ .llvm_name = "arith-cbz-fusion",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_balanceFpOps = Feature{
+ .name = "balance-fp-ops",
+ .description = "balance mix of odd and even D-registers for fp multiply(-accumulate) ops",
+ .llvm_name = "balance-fp-ops",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_bti = Feature{
+ .name = "bti",
+ .description = "Enable Branch Target Identification",
+ .llvm_name = "bti",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ccidx = Feature{
+ .name = "ccidx",
+ .description = "Enable v8.3-A Extend of the CCSIDR number of sets",
+ .llvm_name = "ccidx",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ccpp = Feature{
+ .name = "ccpp",
+ .description = "Enable v8.2 data Cache Clean to Point of Persistence",
+ .llvm_name = "ccpp",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_crc = Feature{
+ .name = "crc",
+ .description = "Enable ARMv8 CRC-32 checksum instructions",
+ .llvm_name = "crc",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ccdp = Feature{
+ .name = "ccdp",
+ .description = "Enable v8.5 Cache Clean to Point of Deep Persistence",
+ .llvm_name = "ccdp",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_callSavedX8 = Feature{
+ .name = "call-saved-x8",
+ .description = "Make X8 callee saved.",
+ .llvm_name = "call-saved-x8",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_callSavedX9 = Feature{
+ .name = "call-saved-x9",
+ .description = "Make X9 callee saved.",
+ .llvm_name = "call-saved-x9",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_callSavedX10 = Feature{
+ .name = "call-saved-x10",
+ .description = "Make X10 callee saved.",
+ .llvm_name = "call-saved-x10",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_callSavedX11 = Feature{
+ .name = "call-saved-x11",
+ .description = "Make X11 callee saved.",
+ .llvm_name = "call-saved-x11",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_callSavedX12 = Feature{
+ .name = "call-saved-x12",
+ .description = "Make X12 callee saved.",
+ .llvm_name = "call-saved-x12",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_callSavedX13 = Feature{
+ .name = "call-saved-x13",
+ .description = "Make X13 callee saved.",
+ .llvm_name = "call-saved-x13",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_callSavedX14 = Feature{
+ .name = "call-saved-x14",
+ .description = "Make X14 callee saved.",
+ .llvm_name = "call-saved-x14",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_callSavedX15 = Feature{
+ .name = "call-saved-x15",
+ .description = "Make X15 callee saved.",
+ .llvm_name = "call-saved-x15",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_callSavedX18 = Feature{
+ .name = "call-saved-x18",
+ .description = "Make X18 callee saved.",
+ .llvm_name = "call-saved-x18",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_complxnum = Feature{
+ .name = "complxnum",
+ .description = "Enable v8.3-A Floating-point complex number support",
+ .llvm_name = "complxnum",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpArmv8,
+ },
+};
+
+pub const feature_crypto = Feature{
+ .name = "crypto",
+ .description = "Enable cryptographic instructions",
+ .llvm_name = "crypto",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpArmv8,
+ },
+};
+
+pub const feature_customCheapAsMove = Feature{
+ .name = "custom-cheap-as-move",
+ .description = "Use custom handling of cheap instructions",
+ .llvm_name = "custom-cheap-as-move",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dit = Feature{
+ .name = "dit",
+ .description = "Enable v8.4-A Data Independent Timing instructions",
+ .llvm_name = "dit",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_disableLatencySchedHeuristic = Feature{
+ .name = "disable-latency-sched-heuristic",
+ .description = "Disable latency scheduling heuristic",
+ .llvm_name = "disable-latency-sched-heuristic",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dotprod = Feature{
+ .name = "dotprod",
+ .description = "Enable dot product support",
+ .llvm_name = "dotprod",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ete = Feature{
+ .name = "ete",
+ .description = "Enable Embedded Trace Extension",
+ .llvm_name = "ete",
+ .subfeatures = &[_]*const Feature {
+ &feature_trbe,
+ },
+};
+
+pub const feature_exynosCheapAsMove = Feature{
+ .name = "exynos-cheap-as-move",
+ .description = "Use Exynos specific handling of cheap instructions",
+ .llvm_name = "exynos-cheap-as-move",
+ .subfeatures = &[_]*const Feature {
+ &feature_customCheapAsMove,
+ },
+};
+
+pub const feature_fmi = Feature{
+ .name = "fmi",
+ .description = "Enable v8.4-A Flag Manipulation Instructions",
+ .llvm_name = "fmi",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fp16fml = Feature{
+ .name = "fp16fml",
+ .description = "Enable FP16 FML instructions",
+ .llvm_name = "fp16fml",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpArmv8,
+ },
+};
+
+pub const feature_fpArmv8 = Feature{
+ .name = "fp-armv8",
+ .description = "Enable ARMv8 FP",
+ .llvm_name = "fp-armv8",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fptoint = Feature{
+ .name = "fptoint",
+ .description = "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int",
+ .llvm_name = "fptoint",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_force32bitJumpTables = Feature{
+ .name = "force-32bit-jump-tables",
+ .description = "Force jump table entries to be 32-bits wide except at MinSize",
+ .llvm_name = "force-32bit-jump-tables",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fullfp16 = Feature{
+ .name = "fullfp16",
+ .description = "Full FP16",
+ .llvm_name = "fullfp16",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpArmv8,
+ },
+};
+
+pub const feature_fuseAes = Feature{
+ .name = "fuse-aes",
+ .description = "CPU fuses AES crypto operations",
+ .llvm_name = "fuse-aes",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fuseAddress = Feature{
+ .name = "fuse-address",
+ .description = "CPU fuses address generation and memory operations",
+ .llvm_name = "fuse-address",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fuseArithLogic = Feature{
+ .name = "fuse-arith-logic",
+ .description = "CPU fuses arithmetic and logic operations",
+ .llvm_name = "fuse-arith-logic",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fuseCsel = Feature{
+ .name = "fuse-csel",
+ .description = "CPU fuses conditional select operations",
+ .llvm_name = "fuse-csel",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fuseCryptoEor = Feature{
+ .name = "fuse-crypto-eor",
+ .description = "CPU fuses AES/PMULL and EOR operations",
+ .llvm_name = "fuse-crypto-eor",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fuseLiterals = Feature{
+ .name = "fuse-literals",
+ .description = "CPU fuses literal generation operations",
+ .llvm_name = "fuse-literals",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_jsconv = Feature{
+ .name = "jsconv",
+ .description = "Enable v8.3-A JavaScript FP conversion enchancement",
+ .llvm_name = "jsconv",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpArmv8,
+ },
+};
+
+pub const feature_lor = Feature{
+ .name = "lor",
+ .description = "Enables ARM v8.1 Limited Ordering Regions extension",
+ .llvm_name = "lor",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_lse = Feature{
+ .name = "lse",
+ .description = "Enable ARMv8.1 Large System Extension (LSE) atomic instructions",
+ .llvm_name = "lse",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_lslFast = Feature{
+ .name = "lsl-fast",
+ .description = "CPU has a fastpath logical shift of up to 3 places",
+ .llvm_name = "lsl-fast",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mpam = Feature{
+ .name = "mpam",
+ .description = "Enable v8.4-A Memory system Partitioning and Monitoring extension",
+ .llvm_name = "mpam",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mte = Feature{
+ .name = "mte",
+ .description = "Enable Memory Tagging Extension",
+ .llvm_name = "mte",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_neon = Feature{
+ .name = "neon",
+ .description = "Enable Advanced SIMD instructions",
+ .llvm_name = "neon",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpArmv8,
+ },
+};
+
+pub const feature_nv = Feature{
+ .name = "nv",
+ .description = "Enable v8.4-A Nested Virtualization Enchancement",
+ .llvm_name = "nv",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_noNegImmediates = Feature{
+ .name = "no-neg-immediates",
+ .description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.",
+ .llvm_name = "no-neg-immediates",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_pa = Feature{
+ .name = "pa",
+ .description = "Enable v8.3-A Pointer Authentication enchancement",
+ .llvm_name = "pa",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_pan = Feature{
+ .name = "pan",
+ .description = "Enables ARM v8.1 Privileged Access-Never extension",
+ .llvm_name = "pan",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_panRwv = Feature{
+ .name = "pan-rwv",
+ .description = "Enable v8.2 PAN s1e1R and s1e1W Variants",
+ .llvm_name = "pan-rwv",
+ .subfeatures = &[_]*const Feature {
+ &feature_pan,
+ },
+};
+
+pub const feature_perfmon = Feature{
+ .name = "perfmon",
+ .description = "Enable ARMv8 PMUv3 Performance Monitors extension",
+ .llvm_name = "perfmon",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_usePostraScheduler = Feature{
+ .name = "use-postra-scheduler",
+ .description = "Schedule again after register allocation",
+ .llvm_name = "use-postra-scheduler",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_predres = Feature{
+ .name = "predres",
+ .description = "Enable v8.5a execution and data prediction invalidation instructions",
+ .llvm_name = "predres",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_predictableSelectExpensive = Feature{
+ .name = "predictable-select-expensive",
+ .description = "Prefer likely predicted branches over selects",
+ .llvm_name = "predictable-select-expensive",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_uaops = Feature{
+ .name = "uaops",
+ .description = "Enable v8.2 UAO PState",
+ .llvm_name = "uaops",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ras = Feature{
+ .name = "ras",
+ .description = "Enable ARMv8 Reliability, Availability and Serviceability Extensions",
+ .llvm_name = "ras",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_rasv8_4 = Feature{
+ .name = "rasv8_4",
+ .description = "Enable v8.4-A Reliability, Availability and Serviceability extension",
+ .llvm_name = "rasv8_4",
+ .subfeatures = &[_]*const Feature {
+ &feature_ras,
+ },
+};
+
+pub const feature_rcpc = Feature{
+ .name = "rcpc",
+ .description = "Enable support for RCPC extension",
+ .llvm_name = "rcpc",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_rcpcImmo = Feature{
+ .name = "rcpc-immo",
+ .description = "Enable v8.4-A RCPC instructions with Immediate Offsets",
+ .llvm_name = "rcpc-immo",
+ .subfeatures = &[_]*const Feature {
+ &feature_rcpc,
+ },
+};
+
+pub const feature_rdm = Feature{
+ .name = "rdm",
+ .description = "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions",
+ .llvm_name = "rdm",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_rand = Feature{
+ .name = "rand",
+ .description = "Enable Random Number generation instructions",
+ .llvm_name = "rand",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX1 = Feature{
+ .name = "reserve-x1",
+ .description = "Reserve X1, making it unavailable as a GPR",
+ .llvm_name = "reserve-x1",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX2 = Feature{
+ .name = "reserve-x2",
+ .description = "Reserve X2, making it unavailable as a GPR",
+ .llvm_name = "reserve-x2",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX3 = Feature{
+ .name = "reserve-x3",
+ .description = "Reserve X3, making it unavailable as a GPR",
+ .llvm_name = "reserve-x3",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX4 = Feature{
+ .name = "reserve-x4",
+ .description = "Reserve X4, making it unavailable as a GPR",
+ .llvm_name = "reserve-x4",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX5 = Feature{
+ .name = "reserve-x5",
+ .description = "Reserve X5, making it unavailable as a GPR",
+ .llvm_name = "reserve-x5",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX6 = Feature{
+ .name = "reserve-x6",
+ .description = "Reserve X6, making it unavailable as a GPR",
+ .llvm_name = "reserve-x6",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX7 = Feature{
+ .name = "reserve-x7",
+ .description = "Reserve X7, making it unavailable as a GPR",
+ .llvm_name = "reserve-x7",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX9 = Feature{
+ .name = "reserve-x9",
+ .description = "Reserve X9, making it unavailable as a GPR",
+ .llvm_name = "reserve-x9",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX10 = Feature{
+ .name = "reserve-x10",
+ .description = "Reserve X10, making it unavailable as a GPR",
+ .llvm_name = "reserve-x10",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX11 = Feature{
+ .name = "reserve-x11",
+ .description = "Reserve X11, making it unavailable as a GPR",
+ .llvm_name = "reserve-x11",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX12 = Feature{
+ .name = "reserve-x12",
+ .description = "Reserve X12, making it unavailable as a GPR",
+ .llvm_name = "reserve-x12",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX13 = Feature{
+ .name = "reserve-x13",
+ .description = "Reserve X13, making it unavailable as a GPR",
+ .llvm_name = "reserve-x13",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX14 = Feature{
+ .name = "reserve-x14",
+ .description = "Reserve X14, making it unavailable as a GPR",
+ .llvm_name = "reserve-x14",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX15 = Feature{
+ .name = "reserve-x15",
+ .description = "Reserve X15, making it unavailable as a GPR",
+ .llvm_name = "reserve-x15",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX18 = Feature{
+ .name = "reserve-x18",
+ .description = "Reserve X18, making it unavailable as a GPR",
+ .llvm_name = "reserve-x18",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX20 = Feature{
+ .name = "reserve-x20",
+ .description = "Reserve X20, making it unavailable as a GPR",
+ .llvm_name = "reserve-x20",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX21 = Feature{
+ .name = "reserve-x21",
+ .description = "Reserve X21, making it unavailable as a GPR",
+ .llvm_name = "reserve-x21",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX22 = Feature{
+ .name = "reserve-x22",
+ .description = "Reserve X22, making it unavailable as a GPR",
+ .llvm_name = "reserve-x22",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX23 = Feature{
+ .name = "reserve-x23",
+ .description = "Reserve X23, making it unavailable as a GPR",
+ .llvm_name = "reserve-x23",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX24 = Feature{
+ .name = "reserve-x24",
+ .description = "Reserve X24, making it unavailable as a GPR",
+ .llvm_name = "reserve-x24",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX25 = Feature{
+ .name = "reserve-x25",
+ .description = "Reserve X25, making it unavailable as a GPR",
+ .llvm_name = "reserve-x25",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX26 = Feature{
+ .name = "reserve-x26",
+ .description = "Reserve X26, making it unavailable as a GPR",
+ .llvm_name = "reserve-x26",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX27 = Feature{
+ .name = "reserve-x27",
+ .description = "Reserve X27, making it unavailable as a GPR",
+ .llvm_name = "reserve-x27",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveX28 = Feature{
+ .name = "reserve-x28",
+ .description = "Reserve X28, making it unavailable as a GPR",
+ .llvm_name = "reserve-x28",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sb = Feature{
+ .name = "sb",
+ .description = "Enable v8.5 Speculation Barrier",
+ .llvm_name = "sb",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sel2 = Feature{
+ .name = "sel2",
+ .description = "Enable v8.4-A Secure Exception Level 2 extension",
+ .llvm_name = "sel2",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sha2 = Feature{
+ .name = "sha2",
+ .description = "Enable SHA1 and SHA256 support",
+ .llvm_name = "sha2",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpArmv8,
+ },
+};
+
+pub const feature_sha3 = Feature{
+ .name = "sha3",
+ .description = "Enable SHA512 and SHA3 support",
+ .llvm_name = "sha3",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpArmv8,
+ },
+};
+
+pub const feature_sm4 = Feature{
+ .name = "sm4",
+ .description = "Enable SM3 and SM4 support",
+ .llvm_name = "sm4",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpArmv8,
+ },
+};
+
+pub const feature_spe = Feature{
+ .name = "spe",
+ .description = "Enable Statistical Profiling extension",
+ .llvm_name = "spe",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ssbs = Feature{
+ .name = "ssbs",
+ .description = "Enable Speculative Store Bypass Safe bit",
+ .llvm_name = "ssbs",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sve = Feature{
+ .name = "sve",
+ .description = "Enable Scalable Vector Extension (SVE) instructions",
+ .llvm_name = "sve",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sve2 = Feature{
+ .name = "sve2",
+ .description = "Enable Scalable Vector Extension 2 (SVE2) instructions",
+ .llvm_name = "sve2",
+ .subfeatures = &[_]*const Feature {
+ &feature_sve,
+ },
+};
+
+pub const feature_sve2Aes = Feature{
+ .name = "sve2-aes",
+ .description = "Enable AES SVE2 instructions",
+ .llvm_name = "sve2-aes",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpArmv8,
+ &feature_sve,
+ },
+};
+
+pub const feature_sve2Bitperm = Feature{
+ .name = "sve2-bitperm",
+ .description = "Enable bit permutation SVE2 instructions",
+ .llvm_name = "sve2-bitperm",
+ .subfeatures = &[_]*const Feature {
+ &feature_sve,
+ },
+};
+
+pub const feature_sve2Sha3 = Feature{
+ .name = "sve2-sha3",
+ .description = "Enable SHA3 SVE2 instructions",
+ .llvm_name = "sve2-sha3",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpArmv8,
+ &feature_sve,
+ },
+};
+
+pub const feature_sve2Sm4 = Feature{
+ .name = "sve2-sm4",
+ .description = "Enable SM4 SVE2 instructions",
+ .llvm_name = "sve2-sm4",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpArmv8,
+ &feature_sve,
+ },
+};
+
+pub const feature_slowMisaligned128store = Feature{
+ .name = "slow-misaligned-128store",
+ .description = "Misaligned 128 bit stores are slow",
+ .llvm_name = "slow-misaligned-128store",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_slowPaired128 = Feature{
+ .name = "slow-paired-128",
+ .description = "Paired 128 bit loads and stores are slow",
+ .llvm_name = "slow-paired-128",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_slowStrqroStore = Feature{
+ .name = "slow-strqro-store",
+ .description = "STR of Q register with register offset is slow",
+ .llvm_name = "slow-strqro-store",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_specrestrict = Feature{
+ .name = "specrestrict",
+ .description = "Enable architectural speculation restriction",
+ .llvm_name = "specrestrict",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_strictAlign = Feature{
+ .name = "strict-align",
+ .description = "Disallow all unaligned memory access",
+ .llvm_name = "strict-align",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_tlbRmi = Feature{
+ .name = "tlb-rmi",
+ .description = "Enable v8.4-A TLB Range and Maintenance Instructions",
+ .llvm_name = "tlb-rmi",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_tme = Feature{
+ .name = "tme",
+ .description = "Enable Transactional Memory Extension",
+ .llvm_name = "tme",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_tracev84 = Feature{
+ .name = "tracev8.4",
+ .description = "Enable v8.4-A Trace extension",
+ .llvm_name = "tracev8.4",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_trbe = Feature{
+ .name = "trbe",
+ .description = "Enable Trace Buffer Extension",
+ .llvm_name = "trbe",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_taggedGlobals = Feature{
+ .name = "tagged-globals",
+ .description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits",
+ .llvm_name = "tagged-globals",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_useAa = Feature{
+ .name = "use-aa",
+ .description = "Use alias analysis during codegen",
+ .llvm_name = "use-aa",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_tpidrEl1 = Feature{
+ .name = "tpidr-el1",
+ .description = "Permit use of TPIDR_EL1 for the TLS base",
+ .llvm_name = "tpidr-el1",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_tpidrEl2 = Feature{
+ .name = "tpidr-el2",
+ .description = "Permit use of TPIDR_EL2 for the TLS base",
+ .llvm_name = "tpidr-el2",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_tpidrEl3 = Feature{
+ .name = "tpidr-el3",
+ .description = "Permit use of TPIDR_EL3 for the TLS base",
+ .llvm_name = "tpidr-el3",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_useReciprocalSquareRoot = Feature{
+ .name = "use-reciprocal-square-root",
+ .description = "Use the reciprocal square root approximation",
+ .llvm_name = "use-reciprocal-square-root",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vh = Feature{
+ .name = "vh",
+ .description = "Enables ARM v8.1 Virtual Host extension",
+ .llvm_name = "vh",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_zcm = Feature{
+ .name = "zcm",
+ .description = "Has zero-cycle register moves",
+ .llvm_name = "zcm",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_zcz = Feature{
+ .name = "zcz",
+ .description = "Has zero-cycle zeroing instructions",
+ .llvm_name = "zcz",
+ .subfeatures = &[_]*const Feature {
+ &feature_zczGp,
+ &feature_zczFp,
+ },
+};
+
+pub const feature_zczFp = Feature{
+ .name = "zcz-fp",
+ .description = "Has zero-cycle zeroing instructions for FP registers",
+ .llvm_name = "zcz-fp",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_zczFpWorkaround = Feature{
+ .name = "zcz-fp-workaround",
+ .description = "The zero-cycle floating-point zeroing instruction has a bug",
+ .llvm_name = "zcz-fp-workaround",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_zczGp = Feature{
+ .name = "zcz-gp",
+ .description = "Has zero-cycle zeroing instructions for generic registers",
+ .llvm_name = "zcz-gp",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_v81a = Feature{
+ .name = "v8.1a",
+ .description = "Support ARM v8.1a instructions",
+ .llvm_name = "v8.1a",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_lse,
+ &feature_lor,
+ &feature_crc,
+ &feature_pan,
+ &feature_vh,
+ },
+};
+
+pub const feature_v82a = Feature{
+ .name = "v8.2a",
+ .description = "Support ARM v8.2a instructions",
+ .llvm_name = "v8.2a",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_ccpp,
+ &feature_lse,
+ &feature_ras,
+ &feature_lor,
+ &feature_crc,
+ &feature_pan,
+ &feature_uaops,
+ &feature_vh,
+ },
+};
+
+pub const feature_v83a = Feature{
+ .name = "v8.3a",
+ .description = "Support ARM v8.3a instructions",
+ .llvm_name = "v8.3a",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_pa,
+ &feature_ccpp,
+ &feature_uaops,
+ &feature_lse,
+ &feature_fpArmv8,
+ &feature_ras,
+ &feature_lor,
+ &feature_pan,
+ &feature_crc,
+ &feature_rcpc,
+ &feature_ccidx,
+ &feature_vh,
+ },
+};
+
+pub const feature_v84a = Feature{
+ .name = "v8.4a",
+ .description = "Support ARM v8.4a instructions",
+ .llvm_name = "v8.4a",
+ .subfeatures = &[_]*const Feature {
+ &feature_am,
+ &feature_nv,
+ &feature_ccpp,
+ &feature_dotprod,
+ &feature_lse,
+ &feature_rcpc,
+ &feature_uaops,
+ &feature_ccidx,
+ &feature_vh,
+ &feature_tracev84,
+ &feature_rdm,
+ &feature_fpArmv8,
+ &feature_dit,
+ &feature_mpam,
+ &feature_ras,
+ &feature_tlbRmi,
+ &feature_fmi,
+ &feature_crc,
+ &feature_pa,
+ &feature_sel2,
+ &feature_lor,
+ &feature_pan,
+ },
+};
+
+pub const feature_v85a = Feature{
+ .name = "v8.5a",
+ .description = "Support ARM v8.5a instructions",
+ .llvm_name = "v8.5a",
+ .subfeatures = &[_]*const Feature {
+ &feature_am,
+ &feature_nv,
+ &feature_specrestrict,
+ &feature_ccpp,
+ &feature_dotprod,
+ &feature_lse,
+ &feature_ccdp,
+ &feature_sb,
+ &feature_rcpc,
+ &feature_ccidx,
+ &feature_uaops,
+ &feature_vh,
+ &feature_altnzcv,
+ &feature_tracev84,
+ &feature_rdm,
+ &feature_ssbs,
+ &feature_fpArmv8,
+ &feature_dit,
+ &feature_mpam,
+ &feature_ras,
+ &feature_tlbRmi,
+ &feature_fmi,
+ &feature_crc,
+ &feature_predres,
+ &feature_pa,
+ &feature_sel2,
+ &feature_lor,
+ &feature_fptoint,
+ &feature_bti,
+ &feature_pan,
+ },
+};
+
+pub const feature_a35 = Feature{
+ .name = "a35",
+ .description = "Cortex-A35 ARM processors",
+ .llvm_name = "a35",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_crc,
+ },
+};
+
+pub const feature_a53 = Feature{
+ .name = "a53",
+ .description = "Cortex-A53 ARM processors",
+ .llvm_name = "a53",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_customCheapAsMove,
+ &feature_fuseAes,
+ &feature_balanceFpOps,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_useAa,
+ &feature_crc,
+ },
+};
+
+pub const feature_a55 = Feature{
+ .name = "a55",
+ .description = "Cortex-A55 ARM processors",
+ .llvm_name = "a55",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_fuseAes,
+ &feature_ccpp,
+ &feature_lse,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_ras,
+ &feature_dotprod,
+ &feature_lor,
+ &feature_pan,
+ &feature_crc,
+ &feature_rcpc,
+ &feature_uaops,
+ &feature_vh,
+ },
+};
+
+pub const feature_a57 = Feature{
+ .name = "a57",
+ .description = "Cortex-A57 ARM processors",
+ .llvm_name = "a57",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_customCheapAsMove,
+ &feature_fuseAes,
+ &feature_balanceFpOps,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_predictableSelectExpensive,
+ &feature_fuseLiterals,
+ &feature_crc,
+ },
+};
+
+pub const feature_a65 = Feature{
+ .name = "a65",
+ .description = "Cortex-A65 ARM processors",
+ .llvm_name = "a65",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_ccpp,
+ &feature_lse,
+ &feature_fpArmv8,
+ &feature_ras,
+ &feature_dotprod,
+ &feature_lor,
+ &feature_pan,
+ &feature_crc,
+ &feature_rcpc,
+ &feature_uaops,
+ &feature_vh,
+ &feature_ssbs,
+ },
+};
+
+pub const feature_a72 = Feature{
+ .name = "a72",
+ .description = "Cortex-A72 ARM processors",
+ .llvm_name = "a72",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_crc,
+ &feature_fuseAes,
+ },
+};
+
+pub const feature_a73 = Feature{
+ .name = "a73",
+ .description = "Cortex-A73 ARM processors",
+ .llvm_name = "a73",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_crc,
+ &feature_fuseAes,
+ },
+};
+
+pub const feature_a75 = Feature{
+ .name = "a75",
+ .description = "Cortex-A75 ARM processors",
+ .llvm_name = "a75",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_fuseAes,
+ &feature_ccpp,
+ &feature_lse,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_ras,
+ &feature_dotprod,
+ &feature_lor,
+ &feature_pan,
+ &feature_crc,
+ &feature_rcpc,
+ &feature_uaops,
+ &feature_vh,
+ },
+};
+
+pub const feature_a76 = Feature{
+ .name = "a76",
+ .description = "Cortex-A76 ARM processors",
+ .llvm_name = "a76",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_ccpp,
+ &feature_lse,
+ &feature_fpArmv8,
+ &feature_ras,
+ &feature_dotprod,
+ &feature_lor,
+ &feature_pan,
+ &feature_crc,
+ &feature_rcpc,
+ &feature_uaops,
+ &feature_vh,
+ &feature_ssbs,
+ },
+};
+
+pub const feature_cyclone = Feature{
+ .name = "cyclone",
+ .description = "Cyclone",
+ .llvm_name = "cyclone",
+ .subfeatures = &[_]*const Feature {
+ &feature_zczGp,
+ &feature_arithBccFusion,
+ &feature_fuseAes,
+ &feature_zczFp,
+ &feature_zczFpWorkaround,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_disableLatencySchedHeuristic,
+ &feature_zcm,
+ &feature_arithCbzFusion,
+ &feature_fuseCryptoEor,
+ &feature_alternateSextloadCvtF32Pattern,
+ },
+};
+
+pub const feature_exynosm1 = Feature{
+ .name = "exynosm1",
+ .description = "Samsung Exynos-M1 processors",
+ .llvm_name = "exynosm1",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_slowMisaligned128store,
+ &feature_customCheapAsMove,
+ &feature_fuseAes,
+ &feature_zczFp,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_slowPaired128,
+ &feature_useReciprocalSquareRoot,
+ &feature_force32bitJumpTables,
+ &feature_crc,
+ },
+};
+
+pub const feature_exynosm2 = Feature{
+ .name = "exynosm2",
+ .description = "Samsung Exynos-M2 processors",
+ .llvm_name = "exynosm2",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_slowMisaligned128store,
+ &feature_customCheapAsMove,
+ &feature_fuseAes,
+ &feature_zczFp,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_slowPaired128,
+ &feature_force32bitJumpTables,
+ &feature_crc,
+ },
+};
+
+pub const feature_exynosm3 = Feature{
+ .name = "exynosm3",
+ .description = "Samsung Exynos-M3 processors",
+ .llvm_name = "exynosm3",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_customCheapAsMove,
+ &feature_fuseAes,
+ &feature_fuseAddress,
+ &feature_zczFp,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_predictableSelectExpensive,
+ &feature_fuseLiterals,
+ &feature_force32bitJumpTables,
+ &feature_crc,
+ &feature_lslFast,
+ &feature_fuseCsel,
+ },
+};
+
+pub const feature_exynosm4 = Feature{
+ .name = "exynosm4",
+ .description = "Samsung Exynos-M4 processors",
+ .llvm_name = "exynosm4",
+ .subfeatures = &[_]*const Feature {
+ &feature_ccpp,
+ &feature_perfmon,
+ &feature_dotprod,
+ &feature_fuseArithLogic,
+ &feature_force32bitJumpTables,
+ &feature_lslFast,
+ &feature_zczGp,
+ &feature_customCheapAsMove,
+ &feature_fuseAes,
+ &feature_fuseAddress,
+ &feature_lse,
+ &feature_arithCbzFusion,
+ &feature_uaops,
+ &feature_fuseCsel,
+ &feature_vh,
+ &feature_rdm,
+ &feature_fpArmv8,
+ &feature_ras,
+ &feature_fuseLiterals,
+ &feature_crc,
+ &feature_usePostraScheduler,
+ &feature_arithBccFusion,
+ &feature_zczFp,
+ &feature_lor,
+ &feature_pan,
+ },
+};
+
+pub const feature_falkor = Feature{
+ .name = "falkor",
+ .description = "Qualcomm Falkor processors",
+ .llvm_name = "falkor",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_usePostraScheduler,
+ &feature_zczGp,
+ &feature_slowStrqroStore,
+ &feature_customCheapAsMove,
+ &feature_zczFp,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_predictableSelectExpensive,
+ &feature_crc,
+ &feature_lslFast,
+ },
+};
+
+pub const feature_kryo = Feature{
+ .name = "kryo",
+ .description = "Qualcomm Kryo processors",
+ .llvm_name = "kryo",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_zczGp,
+ &feature_customCheapAsMove,
+ &feature_zczFp,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_predictableSelectExpensive,
+ &feature_crc,
+ &feature_lslFast,
+ },
+};
+
+pub const feature_neoversee1 = Feature{
+ .name = "neoversee1",
+ .description = "Neoverse E1 ARM processors",
+ .llvm_name = "neoversee1",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_ccpp,
+ &feature_lse,
+ &feature_fpArmv8,
+ &feature_ras,
+ &feature_dotprod,
+ &feature_lor,
+ &feature_pan,
+ &feature_crc,
+ &feature_rcpc,
+ &feature_uaops,
+ &feature_vh,
+ &feature_ssbs,
+ },
+};
+
+pub const feature_neoversen1 = Feature{
+ .name = "neoversen1",
+ .description = "Neoverse N1 ARM processors",
+ .llvm_name = "neoversen1",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_ccpp,
+ &feature_lse,
+ &feature_fpArmv8,
+ &feature_ras,
+ &feature_dotprod,
+ &feature_lor,
+ &feature_spe,
+ &feature_pan,
+ &feature_crc,
+ &feature_rcpc,
+ &feature_uaops,
+ &feature_vh,
+ &feature_ssbs,
+ },
+};
+
+pub const feature_saphira = Feature{
+ .name = "saphira",
+ .description = "Qualcomm Saphira processors",
+ .llvm_name = "saphira",
+ .subfeatures = &[_]*const Feature {
+ &feature_am,
+ &feature_nv,
+ &feature_ccpp,
+ &feature_predictableSelectExpensive,
+ &feature_perfmon,
+ &feature_dotprod,
+ &feature_spe,
+ &feature_lslFast,
+ &feature_zczGp,
+ &feature_customCheapAsMove,
+ &feature_lse,
+ &feature_rcpc,
+ &feature_uaops,
+ &feature_ccidx,
+ &feature_vh,
+ &feature_tracev84,
+ &feature_rdm,
+ &feature_fpArmv8,
+ &feature_dit,
+ &feature_mpam,
+ &feature_ras,
+ &feature_tlbRmi,
+ &feature_fmi,
+ &feature_crc,
+ &feature_usePostraScheduler,
+ &feature_pa,
+ &feature_zczFp,
+ &feature_sel2,
+ &feature_lor,
+ &feature_pan,
+ },
+};
+
+pub const feature_tsv110 = Feature{
+ .name = "tsv110",
+ .description = "HiSilicon TS-V110 processors",
+ .llvm_name = "tsv110",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_usePostraScheduler,
+ &feature_customCheapAsMove,
+ &feature_fuseAes,
+ &feature_ccpp,
+ &feature_lse,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_ras,
+ &feature_dotprod,
+ &feature_lor,
+ &feature_spe,
+ &feature_crc,
+ &feature_pan,
+ &feature_uaops,
+ &feature_vh,
+ },
+};
+
+pub const feature_thunderx = Feature{
+ .name = "thunderx",
+ .description = "Cavium ThunderX processors",
+ .llvm_name = "thunderx",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_predictableSelectExpensive,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_crc,
+ },
+};
+
+pub const feature_thunderx2t99 = Feature{
+ .name = "thunderx2t99",
+ .description = "Cavium ThunderX2 processors",
+ .llvm_name = "thunderx2t99",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_usePostraScheduler,
+ &feature_arithBccFusion,
+ &feature_lse,
+ &feature_fpArmv8,
+ &feature_predictableSelectExpensive,
+ &feature_lor,
+ &feature_crc,
+ &feature_pan,
+ &feature_aggressiveFma,
+ &feature_vh,
+ },
+};
+
+pub const feature_thunderxt81 = Feature{
+ .name = "thunderxt81",
+ .description = "Cavium ThunderX processors",
+ .llvm_name = "thunderxt81",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_predictableSelectExpensive,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_crc,
+ },
+};
+
+pub const feature_thunderxt83 = Feature{
+ .name = "thunderxt83",
+ .description = "Cavium ThunderX processors",
+ .llvm_name = "thunderxt83",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_predictableSelectExpensive,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_crc,
+ },
+};
+
+pub const feature_thunderxt88 = Feature{
+ .name = "thunderxt88",
+ .description = "Cavium ThunderX processors",
+ .llvm_name = "thunderxt88",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_predictableSelectExpensive,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_crc,
+ },
+};
+
+pub const features = &[_]*const Feature {
+ &feature_aes,
+ &feature_am,
+ &feature_aggressiveFma,
+ &feature_altnzcv,
+ &feature_alternateSextloadCvtF32Pattern,
+ &feature_arithBccFusion,
+ &feature_arithCbzFusion,
+ &feature_balanceFpOps,
+ &feature_bti,
+ &feature_ccidx,
+ &feature_ccpp,
+ &feature_crc,
+ &feature_ccdp,
+ &feature_callSavedX8,
+ &feature_callSavedX9,
+ &feature_callSavedX10,
+ &feature_callSavedX11,
+ &feature_callSavedX12,
+ &feature_callSavedX13,
+ &feature_callSavedX14,
+ &feature_callSavedX15,
+ &feature_callSavedX18,
+ &feature_complxnum,
+ &feature_crypto,
+ &feature_customCheapAsMove,
+ &feature_dit,
+ &feature_disableLatencySchedHeuristic,
+ &feature_dotprod,
+ &feature_ete,
+ &feature_exynosCheapAsMove,
+ &feature_fmi,
+ &feature_fp16fml,
+ &feature_fpArmv8,
+ &feature_fptoint,
+ &feature_force32bitJumpTables,
+ &feature_fullfp16,
+ &feature_fuseAes,
+ &feature_fuseAddress,
+ &feature_fuseArithLogic,
+ &feature_fuseCsel,
+ &feature_fuseCryptoEor,
+ &feature_fuseLiterals,
+ &feature_jsconv,
+ &feature_lor,
+ &feature_lse,
+ &feature_lslFast,
+ &feature_mpam,
+ &feature_mte,
+ &feature_neon,
+ &feature_nv,
+ &feature_noNegImmediates,
+ &feature_pa,
+ &feature_pan,
+ &feature_panRwv,
+ &feature_perfmon,
+ &feature_usePostraScheduler,
+ &feature_predres,
+ &feature_predictableSelectExpensive,
+ &feature_uaops,
+ &feature_ras,
+ &feature_rasv8_4,
+ &feature_rcpc,
+ &feature_rcpcImmo,
+ &feature_rdm,
+ &feature_rand,
+ &feature_reserveX1,
+ &feature_reserveX2,
+ &feature_reserveX3,
+ &feature_reserveX4,
+ &feature_reserveX5,
+ &feature_reserveX6,
+ &feature_reserveX7,
+ &feature_reserveX9,
+ &feature_reserveX10,
+ &feature_reserveX11,
+ &feature_reserveX12,
+ &feature_reserveX13,
+ &feature_reserveX14,
+ &feature_reserveX15,
+ &feature_reserveX18,
+ &feature_reserveX20,
+ &feature_reserveX21,
+ &feature_reserveX22,
+ &feature_reserveX23,
+ &feature_reserveX24,
+ &feature_reserveX25,
+ &feature_reserveX26,
+ &feature_reserveX27,
+ &feature_reserveX28,
+ &feature_sb,
+ &feature_sel2,
+ &feature_sha2,
+ &feature_sha3,
+ &feature_sm4,
+ &feature_spe,
+ &feature_ssbs,
+ &feature_sve,
+ &feature_sve2,
+ &feature_sve2Aes,
+ &feature_sve2Bitperm,
+ &feature_sve2Sha3,
+ &feature_sve2Sm4,
+ &feature_slowMisaligned128store,
+ &feature_slowPaired128,
+ &feature_slowStrqroStore,
+ &feature_specrestrict,
+ &feature_strictAlign,
+ &feature_tlbRmi,
+ &feature_tme,
+ &feature_tracev84,
+ &feature_trbe,
+ &feature_taggedGlobals,
+ &feature_useAa,
+ &feature_tpidrEl1,
+ &feature_tpidrEl2,
+ &feature_tpidrEl3,
+ &feature_useReciprocalSquareRoot,
+ &feature_vh,
+ &feature_zcm,
+ &feature_zcz,
+ &feature_zczFp,
+ &feature_zczFpWorkaround,
+ &feature_zczGp,
+ &feature_v81a,
+ &feature_v82a,
+ &feature_v83a,
+ &feature_v84a,
+ &feature_v85a,
+ &feature_a35,
+ &feature_a53,
+ &feature_a55,
+ &feature_a57,
+ &feature_a65,
+ &feature_a72,
+ &feature_a73,
+ &feature_a75,
+ &feature_a76,
+ &feature_cyclone,
+ &feature_exynosm1,
+ &feature_exynosm2,
+ &feature_exynosm3,
+ &feature_exynosm4,
+ &feature_falkor,
+ &feature_kryo,
+ &feature_neoversee1,
+ &feature_neoversen1,
+ &feature_saphira,
+ &feature_tsv110,
+ &feature_thunderx,
+ &feature_thunderx2t99,
+ &feature_thunderxt81,
+ &feature_thunderxt83,
+ &feature_thunderxt88,
+};
+
+pub const cpu_appleLatest = Cpu{
+ .name = "apple-latest",
+ .llvm_name = "apple-latest",
+ .subfeatures = &[_]*const Feature {
+ &feature_zczGp,
+ &feature_arithBccFusion,
+ &feature_fuseAes,
+ &feature_zczFp,
+ &feature_zczFpWorkaround,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_disableLatencySchedHeuristic,
+ &feature_zcm,
+ &feature_arithCbzFusion,
+ &feature_fuseCryptoEor,
+ &feature_alternateSextloadCvtF32Pattern,
+ &feature_cyclone,
+ },
+};
+
+pub const cpu_cortexA35 = Cpu{
+ .name = "cortex-a35",
+ .llvm_name = "cortex-a35",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_crc,
+ &feature_a35,
+ },
+};
+
+pub const cpu_cortexA53 = Cpu{
+ .name = "cortex-a53",
+ .llvm_name = "cortex-a53",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_customCheapAsMove,
+ &feature_fuseAes,
+ &feature_balanceFpOps,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_useAa,
+ &feature_crc,
+ &feature_a53,
+ },
+};
+
+pub const cpu_cortexA55 = Cpu{
+ .name = "cortex-a55",
+ .llvm_name = "cortex-a55",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_fuseAes,
+ &feature_ccpp,
+ &feature_lse,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_ras,
+ &feature_dotprod,
+ &feature_lor,
+ &feature_pan,
+ &feature_crc,
+ &feature_rcpc,
+ &feature_uaops,
+ &feature_vh,
+ &feature_a55,
+ },
+};
+
+pub const cpu_cortexA57 = Cpu{
+ .name = "cortex-a57",
+ .llvm_name = "cortex-a57",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_customCheapAsMove,
+ &feature_fuseAes,
+ &feature_balanceFpOps,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_predictableSelectExpensive,
+ &feature_fuseLiterals,
+ &feature_crc,
+ &feature_a57,
+ },
+};
+
+pub const cpu_cortexA65 = Cpu{
+ .name = "cortex-a65",
+ .llvm_name = "cortex-a65",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_ccpp,
+ &feature_lse,
+ &feature_fpArmv8,
+ &feature_ras,
+ &feature_dotprod,
+ &feature_lor,
+ &feature_pan,
+ &feature_crc,
+ &feature_rcpc,
+ &feature_uaops,
+ &feature_vh,
+ &feature_ssbs,
+ &feature_a65,
+ },
+};
+
+pub const cpu_cortexA65ae = Cpu{
+ .name = "cortex-a65ae",
+ .llvm_name = "cortex-a65ae",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_ccpp,
+ &feature_lse,
+ &feature_fpArmv8,
+ &feature_ras,
+ &feature_dotprod,
+ &feature_lor,
+ &feature_pan,
+ &feature_crc,
+ &feature_rcpc,
+ &feature_uaops,
+ &feature_vh,
+ &feature_ssbs,
+ &feature_a65,
+ },
+};
+
+pub const cpu_cortexA72 = Cpu{
+ .name = "cortex-a72",
+ .llvm_name = "cortex-a72",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_crc,
+ &feature_fuseAes,
+ &feature_a72,
+ },
+};
+
+pub const cpu_cortexA73 = Cpu{
+ .name = "cortex-a73",
+ .llvm_name = "cortex-a73",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_crc,
+ &feature_fuseAes,
+ &feature_a73,
+ },
+};
+
+pub const cpu_cortexA75 = Cpu{
+ .name = "cortex-a75",
+ .llvm_name = "cortex-a75",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_fuseAes,
+ &feature_ccpp,
+ &feature_lse,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_ras,
+ &feature_dotprod,
+ &feature_lor,
+ &feature_pan,
+ &feature_crc,
+ &feature_rcpc,
+ &feature_uaops,
+ &feature_vh,
+ &feature_a75,
+ },
+};
+
+pub const cpu_cortexA76 = Cpu{
+ .name = "cortex-a76",
+ .llvm_name = "cortex-a76",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_ccpp,
+ &feature_lse,
+ &feature_fpArmv8,
+ &feature_ras,
+ &feature_dotprod,
+ &feature_lor,
+ &feature_pan,
+ &feature_crc,
+ &feature_rcpc,
+ &feature_uaops,
+ &feature_vh,
+ &feature_ssbs,
+ &feature_a76,
+ },
+};
+
+pub const cpu_cortexA76ae = Cpu{
+ .name = "cortex-a76ae",
+ .llvm_name = "cortex-a76ae",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_ccpp,
+ &feature_lse,
+ &feature_fpArmv8,
+ &feature_ras,
+ &feature_dotprod,
+ &feature_lor,
+ &feature_pan,
+ &feature_crc,
+ &feature_rcpc,
+ &feature_uaops,
+ &feature_vh,
+ &feature_ssbs,
+ &feature_a76,
+ },
+};
+
+pub const cpu_cyclone = Cpu{
+ .name = "cyclone",
+ .llvm_name = "cyclone",
+ .subfeatures = &[_]*const Feature {
+ &feature_zczGp,
+ &feature_arithBccFusion,
+ &feature_fuseAes,
+ &feature_zczFp,
+ &feature_zczFpWorkaround,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_disableLatencySchedHeuristic,
+ &feature_zcm,
+ &feature_arithCbzFusion,
+ &feature_fuseCryptoEor,
+ &feature_alternateSextloadCvtF32Pattern,
+ &feature_cyclone,
+ },
+};
+
+pub const cpu_exynosM1 = Cpu{
+ .name = "exynos-m1",
+ .llvm_name = "exynos-m1",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_slowMisaligned128store,
+ &feature_customCheapAsMove,
+ &feature_fuseAes,
+ &feature_zczFp,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_slowPaired128,
+ &feature_useReciprocalSquareRoot,
+ &feature_force32bitJumpTables,
+ &feature_crc,
+ &feature_exynosm1,
+ },
+};
+
+pub const cpu_exynosM2 = Cpu{
+ .name = "exynos-m2",
+ .llvm_name = "exynos-m2",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_slowMisaligned128store,
+ &feature_customCheapAsMove,
+ &feature_fuseAes,
+ &feature_zczFp,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_slowPaired128,
+ &feature_force32bitJumpTables,
+ &feature_crc,
+ &feature_exynosm2,
+ },
+};
+
+pub const cpu_exynosM3 = Cpu{
+ .name = "exynos-m3",
+ .llvm_name = "exynos-m3",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_customCheapAsMove,
+ &feature_fuseAes,
+ &feature_fuseAddress,
+ &feature_zczFp,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_predictableSelectExpensive,
+ &feature_fuseLiterals,
+ &feature_force32bitJumpTables,
+ &feature_crc,
+ &feature_lslFast,
+ &feature_fuseCsel,
+ &feature_exynosm3,
+ },
+};
+
+pub const cpu_exynosM4 = Cpu{
+ .name = "exynos-m4",
+ .llvm_name = "exynos-m4",
+ .subfeatures = &[_]*const Feature {
+ &feature_ccpp,
+ &feature_perfmon,
+ &feature_dotprod,
+ &feature_fuseArithLogic,
+ &feature_force32bitJumpTables,
+ &feature_lslFast,
+ &feature_zczGp,
+ &feature_customCheapAsMove,
+ &feature_fuseAes,
+ &feature_fuseAddress,
+ &feature_lse,
+ &feature_arithCbzFusion,
+ &feature_uaops,
+ &feature_fuseCsel,
+ &feature_vh,
+ &feature_rdm,
+ &feature_fpArmv8,
+ &feature_ras,
+ &feature_fuseLiterals,
+ &feature_crc,
+ &feature_usePostraScheduler,
+ &feature_arithBccFusion,
+ &feature_zczFp,
+ &feature_lor,
+ &feature_pan,
+ &feature_exynosm4,
+ },
+};
+
+pub const cpu_exynosM5 = Cpu{
+ .name = "exynos-m5",
+ .llvm_name = "exynos-m5",
+ .subfeatures = &[_]*const Feature {
+ &feature_ccpp,
+ &feature_perfmon,
+ &feature_dotprod,
+ &feature_fuseArithLogic,
+ &feature_force32bitJumpTables,
+ &feature_lslFast,
+ &feature_zczGp,
+ &feature_customCheapAsMove,
+ &feature_fuseAes,
+ &feature_fuseAddress,
+ &feature_lse,
+ &feature_arithCbzFusion,
+ &feature_uaops,
+ &feature_fuseCsel,
+ &feature_vh,
+ &feature_rdm,
+ &feature_fpArmv8,
+ &feature_ras,
+ &feature_fuseLiterals,
+ &feature_crc,
+ &feature_usePostraScheduler,
+ &feature_arithBccFusion,
+ &feature_zczFp,
+ &feature_lor,
+ &feature_pan,
+ &feature_exynosm4,
+ },
+};
+
+pub const cpu_falkor = Cpu{
+ .name = "falkor",
+ .llvm_name = "falkor",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_usePostraScheduler,
+ &feature_zczGp,
+ &feature_slowStrqroStore,
+ &feature_customCheapAsMove,
+ &feature_zczFp,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_predictableSelectExpensive,
+ &feature_crc,
+ &feature_lslFast,
+ &feature_falkor,
+ },
+};
+
+pub const cpu_generic = Cpu{
+ .name = "generic",
+ .llvm_name = "generic",
+ .subfeatures = &[_]*const Feature {
+ &feature_trbe,
+ &feature_ete,
+ &feature_fpArmv8,
+ &feature_fuseAes,
+ &feature_neon,
+ &feature_perfmon,
+ &feature_usePostraScheduler,
+ },
+};
+
+pub const cpu_kryo = Cpu{
+ .name = "kryo",
+ .llvm_name = "kryo",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_zczGp,
+ &feature_customCheapAsMove,
+ &feature_zczFp,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_predictableSelectExpensive,
+ &feature_crc,
+ &feature_lslFast,
+ &feature_kryo,
+ },
+};
+
+pub const cpu_neoverseE1 = Cpu{
+ .name = "neoverse-e1",
+ .llvm_name = "neoverse-e1",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_ccpp,
+ &feature_lse,
+ &feature_fpArmv8,
+ &feature_ras,
+ &feature_dotprod,
+ &feature_lor,
+ &feature_pan,
+ &feature_crc,
+ &feature_rcpc,
+ &feature_uaops,
+ &feature_vh,
+ &feature_ssbs,
+ &feature_neoversee1,
+ },
+};
+
+pub const cpu_neoverseN1 = Cpu{
+ .name = "neoverse-n1",
+ .llvm_name = "neoverse-n1",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_ccpp,
+ &feature_lse,
+ &feature_fpArmv8,
+ &feature_ras,
+ &feature_dotprod,
+ &feature_lor,
+ &feature_spe,
+ &feature_pan,
+ &feature_crc,
+ &feature_rcpc,
+ &feature_uaops,
+ &feature_vh,
+ &feature_ssbs,
+ &feature_neoversen1,
+ },
+};
+
+pub const cpu_saphira = Cpu{
+ .name = "saphira",
+ .llvm_name = "saphira",
+ .subfeatures = &[_]*const Feature {
+ &feature_am,
+ &feature_nv,
+ &feature_ccpp,
+ &feature_predictableSelectExpensive,
+ &feature_perfmon,
+ &feature_dotprod,
+ &feature_spe,
+ &feature_lslFast,
+ &feature_zczGp,
+ &feature_customCheapAsMove,
+ &feature_lse,
+ &feature_rcpc,
+ &feature_uaops,
+ &feature_ccidx,
+ &feature_vh,
+ &feature_tracev84,
+ &feature_rdm,
+ &feature_fpArmv8,
+ &feature_dit,
+ &feature_mpam,
+ &feature_ras,
+ &feature_tlbRmi,
+ &feature_fmi,
+ &feature_crc,
+ &feature_usePostraScheduler,
+ &feature_pa,
+ &feature_zczFp,
+ &feature_sel2,
+ &feature_lor,
+ &feature_pan,
+ &feature_saphira,
+ },
+};
+
+pub const cpu_thunderx = Cpu{
+ .name = "thunderx",
+ .llvm_name = "thunderx",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_predictableSelectExpensive,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_crc,
+ &feature_thunderx,
+ },
+};
+
+pub const cpu_thunderx2t99 = Cpu{
+ .name = "thunderx2t99",
+ .llvm_name = "thunderx2t99",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_usePostraScheduler,
+ &feature_arithBccFusion,
+ &feature_lse,
+ &feature_fpArmv8,
+ &feature_predictableSelectExpensive,
+ &feature_lor,
+ &feature_crc,
+ &feature_pan,
+ &feature_aggressiveFma,
+ &feature_vh,
+ &feature_thunderx2t99,
+ },
+};
+
+pub const cpu_thunderxt81 = Cpu{
+ .name = "thunderxt81",
+ .llvm_name = "thunderxt81",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_predictableSelectExpensive,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_crc,
+ &feature_thunderxt81,
+ },
+};
+
+pub const cpu_thunderxt83 = Cpu{
+ .name = "thunderxt83",
+ .llvm_name = "thunderxt83",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_predictableSelectExpensive,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_crc,
+ &feature_thunderxt83,
+ },
+};
+
+pub const cpu_thunderxt88 = Cpu{
+ .name = "thunderxt88",
+ .llvm_name = "thunderxt88",
+ .subfeatures = &[_]*const Feature {
+ &feature_usePostraScheduler,
+ &feature_predictableSelectExpensive,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_crc,
+ &feature_thunderxt88,
+ },
+};
+
+pub const cpu_tsv110 = Cpu{
+ .name = "tsv110",
+ .llvm_name = "tsv110",
+ .subfeatures = &[_]*const Feature {
+ &feature_rdm,
+ &feature_usePostraScheduler,
+ &feature_customCheapAsMove,
+ &feature_fuseAes,
+ &feature_ccpp,
+ &feature_lse,
+ &feature_fpArmv8,
+ &feature_perfmon,
+ &feature_ras,
+ &feature_dotprod,
+ &feature_lor,
+ &feature_spe,
+ &feature_crc,
+ &feature_pan,
+ &feature_uaops,
+ &feature_vh,
+ &feature_tsv110,
+ },
+};
+
+pub const cpus = &[_]*const Cpu {
+ &cpu_appleLatest,
+ &cpu_cortexA35,
+ &cpu_cortexA53,
+ &cpu_cortexA55,
+ &cpu_cortexA57,
+ &cpu_cortexA65,
+ &cpu_cortexA65ae,
+ &cpu_cortexA72,
+ &cpu_cortexA73,
+ &cpu_cortexA75,
+ &cpu_cortexA76,
+ &cpu_cortexA76ae,
+ &cpu_cyclone,
+ &cpu_exynosM1,
+ &cpu_exynosM2,
+ &cpu_exynosM3,
+ &cpu_exynosM4,
+ &cpu_exynosM5,
+ &cpu_falkor,
+ &cpu_generic,
+ &cpu_kryo,
+ &cpu_neoverseE1,
+ &cpu_neoverseN1,
+ &cpu_saphira,
+ &cpu_thunderx,
+ &cpu_thunderx2t99,
+ &cpu_thunderxt81,
+ &cpu_thunderxt83,
+ &cpu_thunderxt88,
+ &cpu_tsv110,
+};
lib/std/target/amdgpu.zig
@@ -0,0 +1,2329 @@
+const Feature = @import("std").target.Feature;
+const Cpu = @import("std").target.Cpu;
+
+pub const feature_BitInsts16 = Feature{
+ .name = "16-bit-insts",
+ .description = "Has i16/f16 instructions",
+ .llvm_name = "16-bit-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_addNoCarryInsts = Feature{
+ .name = "add-no-carry-insts",
+ .description = "Have VALU add/sub instructions without carry out",
+ .llvm_name = "add-no-carry-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_apertureRegs = Feature{
+ .name = "aperture-regs",
+ .description = "Has Memory Aperture Base and Size Registers",
+ .llvm_name = "aperture-regs",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_atomicFaddInsts = Feature{
+ .name = "atomic-fadd-insts",
+ .description = "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, global_atomic_pk_add_f16 instructions",
+ .llvm_name = "atomic-fadd-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_autoWaitcntBeforeBarrier = Feature{
+ .name = "auto-waitcnt-before-barrier",
+ .description = "Hardware automatically inserts waitcnt before barrier",
+ .llvm_name = "auto-waitcnt-before-barrier",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ciInsts = Feature{
+ .name = "ci-insts",
+ .description = "Additional instructions for CI+",
+ .llvm_name = "ci-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_codeObjectV3 = Feature{
+ .name = "code-object-v3",
+ .description = "Generate code object version 3",
+ .llvm_name = "code-object-v3",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_cumode = Feature{
+ .name = "cumode",
+ .description = "Enable CU wavefront execution mode",
+ .llvm_name = "cumode",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dlInsts = Feature{
+ .name = "dl-insts",
+ .description = "Has v_fmac_f32 and v_xnor_b32 instructions",
+ .llvm_name = "dl-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dpp = Feature{
+ .name = "dpp",
+ .description = "Support DPP (Data Parallel Primitives) extension",
+ .llvm_name = "dpp",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dpp8 = Feature{
+ .name = "dpp8",
+ .description = "Support DPP8 (Data Parallel Primitives) extension",
+ .llvm_name = "dpp8",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_noSramEccSupport = Feature{
+ .name = "no-sram-ecc-support",
+ .description = "Hardware does not support SRAM ECC",
+ .llvm_name = "no-sram-ecc-support",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_noXnackSupport = Feature{
+ .name = "no-xnack-support",
+ .description = "Hardware does not support XNACK",
+ .llvm_name = "no-xnack-support",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dot1Insts = Feature{
+ .name = "dot1-insts",
+ .description = "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions",
+ .llvm_name = "dot1-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dot2Insts = Feature{
+ .name = "dot2-insts",
+ .description = "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions",
+ .llvm_name = "dot2-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dot3Insts = Feature{
+ .name = "dot3-insts",
+ .description = "Has v_dot8c_i32_i4 instruction",
+ .llvm_name = "dot3-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dot4Insts = Feature{
+ .name = "dot4-insts",
+ .description = "Has v_dot2c_i32_i16 instruction",
+ .llvm_name = "dot4-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dot5Insts = Feature{
+ .name = "dot5-insts",
+ .description = "Has v_dot2c_f32_f16 instruction",
+ .llvm_name = "dot5-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dot6Insts = Feature{
+ .name = "dot6-insts",
+ .description = "Has v_dot4c_i32_i8 instruction",
+ .llvm_name = "dot6-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_DumpCode = Feature{
+ .name = "DumpCode",
+ .description = "Dump MachineInstrs in the CodeEmitter",
+ .llvm_name = "DumpCode",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dumpcode = Feature{
+ .name = "dumpcode",
+ .description = "Dump MachineInstrs in the CodeEmitter",
+ .llvm_name = "dumpcode",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_enableDs128 = Feature{
+ .name = "enable-ds128",
+ .description = "Use ds_{read|write}_b128",
+ .llvm_name = "enable-ds128",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_loadStoreOpt = Feature{
+ .name = "load-store-opt",
+ .description = "Enable SI load/store optimizer pass",
+ .llvm_name = "load-store-opt",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_enablePrtStrictNull = Feature{
+ .name = "enable-prt-strict-null",
+ .description = "Enable zeroing of result registers for sparse texture fetches",
+ .llvm_name = "enable-prt-strict-null",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_siScheduler = Feature{
+ .name = "si-scheduler",
+ .description = "Enable SI Machine Scheduler",
+ .llvm_name = "si-scheduler",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_unsafeDsOffsetFolding = Feature{
+ .name = "unsafe-ds-offset-folding",
+ .description = "Force using DS instruction immediate offsets on SI",
+ .llvm_name = "unsafe-ds-offset-folding",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fmaf = Feature{
+ .name = "fmaf",
+ .description = "Enable single precision FMA (not as fast as mul+add, but fused)",
+ .llvm_name = "fmaf",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fp16Denormals = Feature{
+ .name = "fp16-denormals",
+ .description = "Enable half precision denormal handling",
+ .llvm_name = "fp16-denormals",
+ .subfeatures = &[_]*const Feature {
+ &feature_fp64,
+ },
+};
+
+pub const feature_fp32Denormals = Feature{
+ .name = "fp32-denormals",
+ .description = "Enable single precision denormal handling",
+ .llvm_name = "fp32-denormals",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fp64 = Feature{
+ .name = "fp64",
+ .description = "Enable double precision operations",
+ .llvm_name = "fp64",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fp64Denormals = Feature{
+ .name = "fp64-denormals",
+ .description = "Enable double and half precision denormal handling",
+ .llvm_name = "fp64-denormals",
+ .subfeatures = &[_]*const Feature {
+ &feature_fp64,
+ },
+};
+
+pub const feature_fp64Fp16Denormals = Feature{
+ .name = "fp64-fp16-denormals",
+ .description = "Enable double and half precision denormal handling",
+ .llvm_name = "fp64-fp16-denormals",
+ .subfeatures = &[_]*const Feature {
+ &feature_fp64,
+ },
+};
+
+pub const feature_fpExceptions = Feature{
+ .name = "fp-exceptions",
+ .description = "Enable floating point exceptions",
+ .llvm_name = "fp-exceptions",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fastFmaf = Feature{
+ .name = "fast-fmaf",
+ .description = "Assuming f32 fma is at least as fast as mul + add",
+ .llvm_name = "fast-fmaf",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_flatAddressSpace = Feature{
+ .name = "flat-address-space",
+ .description = "Support flat address space",
+ .llvm_name = "flat-address-space",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_flatForGlobal = Feature{
+ .name = "flat-for-global",
+ .description = "Force to generate flat instruction for global",
+ .llvm_name = "flat-for-global",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_flatGlobalInsts = Feature{
+ .name = "flat-global-insts",
+ .description = "Have global_* flat memory instructions",
+ .llvm_name = "flat-global-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_flatInstOffsets = Feature{
+ .name = "flat-inst-offsets",
+ .description = "Flat instructions have immediate offset addressing mode",
+ .llvm_name = "flat-inst-offsets",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_flatScratchInsts = Feature{
+ .name = "flat-scratch-insts",
+ .description = "Have scratch_* flat memory instructions",
+ .llvm_name = "flat-scratch-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_flatSegmentOffsetBug = Feature{
+ .name = "flat-segment-offset-bug",
+ .description = "GFX10 bug, inst_offset ignored in flat segment",
+ .llvm_name = "flat-segment-offset-bug",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fmaMixInsts = Feature{
+ .name = "fma-mix-insts",
+ .description = "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions",
+ .llvm_name = "fma-mix-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_gcn3Encoding = Feature{
+ .name = "gcn3-encoding",
+ .description = "Encoding format for VI",
+ .llvm_name = "gcn3-encoding",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_gfx7Gfx8Gfx9Insts = Feature{
+ .name = "gfx7-gfx8-gfx9-insts",
+ .description = "Instructions shared in GFX7, GFX8, GFX9",
+ .llvm_name = "gfx7-gfx8-gfx9-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_gfx8Insts = Feature{
+ .name = "gfx8-insts",
+ .description = "Additional instructions for GFX8+",
+ .llvm_name = "gfx8-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_gfx9 = Feature{
+ .name = "gfx9",
+ .description = "GFX9 GPU generation",
+ .llvm_name = "gfx9",
+ .subfeatures = &[_]*const Feature {
+ &feature_gfx9Insts,
+ &feature_ciInsts,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_scalarStores,
+ &feature_sdwaScalar,
+ &feature_sdwaSdst,
+ &feature_gcn3Encoding,
+ &feature_apertureRegs,
+ &feature_flatScratchInsts,
+ &feature_r128A16,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_addNoCarryInsts,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_BitInsts16,
+ &feature_vgprIndexMode,
+ &feature_wavefrontsize64,
+ &feature_gfx8Insts,
+ &feature_flatGlobalInsts,
+ &feature_scalarFlatScratchInsts,
+ &feature_scalarAtomics,
+ &feature_flatInstOffsets,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_vop3p,
+ &feature_sMemrealtime,
+ &feature_intClampInsts,
+ &feature_fastFmaf,
+ &feature_sdwaOmod,
+ },
+};
+
+pub const feature_gfx9Insts = Feature{
+ .name = "gfx9-insts",
+ .description = "Additional instructions for GFX9+",
+ .llvm_name = "gfx9-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_gfx10 = Feature{
+ .name = "gfx10",
+ .description = "GFX10 GPU generation",
+ .llvm_name = "gfx10",
+ .subfeatures = &[_]*const Feature {
+ &feature_movrel,
+ &feature_gfx9Insts,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_noSdstCmpx,
+ &feature_fmaMixInsts,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_sdwaScalar,
+ &feature_sdwaSdst,
+ &feature_apertureRegs,
+ &feature_flatScratchInsts,
+ &feature_vscnt,
+ &feature_noDataDepHazard,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_addNoCarryInsts,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_dpp8,
+ &feature_BitInsts16,
+ &feature_registerBanking,
+ &feature_gfx8Insts,
+ &feature_flatGlobalInsts,
+ &feature_flatInstOffsets,
+ &feature_pkFmacF16Inst,
+ &feature_vop3p,
+ &feature_mimgR128,
+ &feature_intClampInsts,
+ &feature_sMemrealtime,
+ &feature_fastFmaf,
+ &feature_vop3Literal,
+ &feature_sdwaOmod,
+ &feature_gfx10Insts,
+ },
+};
+
+pub const feature_gfx10Insts = Feature{
+ .name = "gfx10-insts",
+ .description = "Additional instructions for GFX10+",
+ .llvm_name = "gfx10-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_instFwdPrefetchBug = Feature{
+ .name = "inst-fwd-prefetch-bug",
+ .description = "S_INST_PREFETCH instruction causes shader to hang",
+ .llvm_name = "inst-fwd-prefetch-bug",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_intClampInsts = Feature{
+ .name = "int-clamp-insts",
+ .description = "Support clamp for integer destination",
+ .llvm_name = "int-clamp-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_inv2piInlineImm = Feature{
+ .name = "inv-2pi-inline-imm",
+ .description = "Has 1 / (2 * pi) as inline immediate",
+ .llvm_name = "inv-2pi-inline-imm",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ldsbankcount16 = Feature{
+ .name = "ldsbankcount16",
+ .description = "The number of LDS banks per compute unit.",
+ .llvm_name = "ldsbankcount16",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ldsbankcount32 = Feature{
+ .name = "ldsbankcount32",
+ .description = "The number of LDS banks per compute unit.",
+ .llvm_name = "ldsbankcount32",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ldsBranchVmemWarHazard = Feature{
+ .name = "lds-branch-vmem-war-hazard",
+ .description = "Switching between LDS and VMEM-tex not waiting VM_VSRC=0",
+ .llvm_name = "lds-branch-vmem-war-hazard",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ldsMisalignedBug = Feature{
+ .name = "lds-misaligned-bug",
+ .description = "Some GFX10 bug with misaligned multi-dword LDS access in WGP mode",
+ .llvm_name = "lds-misaligned-bug",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_localmemorysize0 = Feature{
+ .name = "localmemorysize0",
+ .description = "The size of local memory in bytes",
+ .llvm_name = "localmemorysize0",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_localmemorysize32768 = Feature{
+ .name = "localmemorysize32768",
+ .description = "The size of local memory in bytes",
+ .llvm_name = "localmemorysize32768",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_localmemorysize65536 = Feature{
+ .name = "localmemorysize65536",
+ .description = "The size of local memory in bytes",
+ .llvm_name = "localmemorysize65536",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_maiInsts = Feature{
+ .name = "mai-insts",
+ .description = "Has mAI instructions",
+ .llvm_name = "mai-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mfmaInlineLiteralBug = Feature{
+ .name = "mfma-inline-literal-bug",
+ .description = "MFMA cannot use inline literal as SrcC",
+ .llvm_name = "mfma-inline-literal-bug",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mimgR128 = Feature{
+ .name = "mimg-r128",
+ .description = "Support 128-bit texture resources",
+ .llvm_name = "mimg-r128",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_madMixInsts = Feature{
+ .name = "mad-mix-insts",
+ .description = "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions",
+ .llvm_name = "mad-mix-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_maxPrivateElementSize4 = Feature{
+ .name = "max-private-element-size-4",
+ .description = "Maximum private access size may be 4",
+ .llvm_name = "max-private-element-size-4",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_maxPrivateElementSize8 = Feature{
+ .name = "max-private-element-size-8",
+ .description = "Maximum private access size may be 8",
+ .llvm_name = "max-private-element-size-8",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_maxPrivateElementSize16 = Feature{
+ .name = "max-private-element-size-16",
+ .description = "Maximum private access size may be 16",
+ .llvm_name = "max-private-element-size-16",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_movrel = Feature{
+ .name = "movrel",
+ .description = "Has v_movrel*_b32 instructions",
+ .llvm_name = "movrel",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_nsaEncoding = Feature{
+ .name = "nsa-encoding",
+ .description = "Support NSA encoding for image instructions",
+ .llvm_name = "nsa-encoding",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_nsaToVmemBug = Feature{
+ .name = "nsa-to-vmem-bug",
+ .description = "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero",
+ .llvm_name = "nsa-to-vmem-bug",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_noDataDepHazard = Feature{
+ .name = "no-data-dep-hazard",
+ .description = "Does not need SW waitstates",
+ .llvm_name = "no-data-dep-hazard",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_noSdstCmpx = Feature{
+ .name = "no-sdst-cmpx",
+ .description = "V_CMPX does not write VCC/SGPR in addition to EXEC",
+ .llvm_name = "no-sdst-cmpx",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_offset3fBug = Feature{
+ .name = "offset-3f-bug",
+ .description = "Branch offset of 3f hardware bug",
+ .llvm_name = "offset-3f-bug",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_pkFmacF16Inst = Feature{
+ .name = "pk-fmac-f16-inst",
+ .description = "Has v_pk_fmac_f16 instruction",
+ .llvm_name = "pk-fmac-f16-inst",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_promoteAlloca = Feature{
+ .name = "promote-alloca",
+ .description = "Enable promote alloca pass",
+ .llvm_name = "promote-alloca",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_r128A16 = Feature{
+ .name = "r128-a16",
+ .description = "Support 16 bit coordindates/gradients/lod/clamp/mip types on gfx9",
+ .llvm_name = "r128-a16",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_registerBanking = Feature{
+ .name = "register-banking",
+ .description = "Has register banking",
+ .llvm_name = "register-banking",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sdwa = Feature{
+ .name = "sdwa",
+ .description = "Support SDWA (Sub-DWORD Addressing) extension",
+ .llvm_name = "sdwa",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sdwaMav = Feature{
+ .name = "sdwa-mav",
+ .description = "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension",
+ .llvm_name = "sdwa-mav",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sdwaOmod = Feature{
+ .name = "sdwa-omod",
+ .description = "Support OMod with SDWA (Sub-DWORD Addressing) extension",
+ .llvm_name = "sdwa-omod",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sdwaOutModsVopc = Feature{
+ .name = "sdwa-out-mods-vopc",
+ .description = "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension",
+ .llvm_name = "sdwa-out-mods-vopc",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sdwaScalar = Feature{
+ .name = "sdwa-scalar",
+ .description = "Support scalar register with SDWA (Sub-DWORD Addressing) extension",
+ .llvm_name = "sdwa-scalar",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sdwaSdst = Feature{
+ .name = "sdwa-sdst",
+ .description = "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension",
+ .llvm_name = "sdwa-sdst",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sgprInitBug = Feature{
+ .name = "sgpr-init-bug",
+ .description = "VI SGPR initialization bug requiring a fixed SGPR allocation size",
+ .llvm_name = "sgpr-init-bug",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_smemToVectorWriteHazard = Feature{
+ .name = "smem-to-vector-write-hazard",
+ .description = "s_load_dword followed by v_cmp page faults",
+ .llvm_name = "smem-to-vector-write-hazard",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sMemrealtime = Feature{
+ .name = "s-memrealtime",
+ .description = "Has s_memrealtime instruction",
+ .llvm_name = "s-memrealtime",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sramEcc = Feature{
+ .name = "sram-ecc",
+ .description = "Enable SRAM ECC",
+ .llvm_name = "sram-ecc",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_scalarAtomics = Feature{
+ .name = "scalar-atomics",
+ .description = "Has atomic scalar memory instructions",
+ .llvm_name = "scalar-atomics",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_scalarFlatScratchInsts = Feature{
+ .name = "scalar-flat-scratch-insts",
+ .description = "Have s_scratch_* flat memory instructions",
+ .llvm_name = "scalar-flat-scratch-insts",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_scalarStores = Feature{
+ .name = "scalar-stores",
+ .description = "Has store scalar memory instructions",
+ .llvm_name = "scalar-stores",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_seaIslands = Feature{
+ .name = "sea-islands",
+ .description = "SEA_ISLANDS GPU generation",
+ .llvm_name = "sea-islands",
+ .subfeatures = &[_]*const Feature {
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_localmemorysize65536,
+ &feature_movrel,
+ &feature_trigReducedRange,
+ &feature_wavefrontsize64,
+ &feature_flatAddressSpace,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_fp64,
+ },
+};
+
+pub const feature_southernIslands = Feature{
+ .name = "southern-islands",
+ .description = "SOUTHERN_ISLANDS GPU generation",
+ .llvm_name = "southern-islands",
+ .subfeatures = &[_]*const Feature {
+ &feature_mimgR128,
+ &feature_movrel,
+ &feature_localmemorysize32768,
+ &feature_trigReducedRange,
+ &feature_ldsbankcount32,
+ &feature_wavefrontsize64,
+ &feature_noSramEccSupport,
+ &feature_noXnackSupport,
+ &feature_fp64,
+ },
+};
+
+pub const feature_trapHandler = Feature{
+ .name = "trap-handler",
+ .description = "Trap handler support",
+ .llvm_name = "trap-handler",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_trigReducedRange = Feature{
+ .name = "trig-reduced-range",
+ .description = "Requires use of fract on arguments to trig instructions",
+ .llvm_name = "trig-reduced-range",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_unalignedBufferAccess = Feature{
+ .name = "unaligned-buffer-access",
+ .description = "Support unaligned global loads and stores",
+ .llvm_name = "unaligned-buffer-access",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_unalignedScratchAccess = Feature{
+ .name = "unaligned-scratch-access",
+ .description = "Support unaligned scratch loads and stores",
+ .llvm_name = "unaligned-scratch-access",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_unpackedD16Vmem = Feature{
+ .name = "unpacked-d16-vmem",
+ .description = "Has unpacked d16 vmem instructions",
+ .llvm_name = "unpacked-d16-vmem",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vgprIndexMode = Feature{
+ .name = "vgpr-index-mode",
+ .description = "Has VGPR mode register indexing",
+ .llvm_name = "vgpr-index-mode",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vmemToScalarWriteHazard = Feature{
+ .name = "vmem-to-scalar-write-hazard",
+ .description = "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.",
+ .llvm_name = "vmem-to-scalar-write-hazard",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vop3Literal = Feature{
+ .name = "vop3-literal",
+ .description = "Can use one literal in VOP3",
+ .llvm_name = "vop3-literal",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vop3p = Feature{
+ .name = "vop3p",
+ .description = "Has VOP3P packed instructions",
+ .llvm_name = "vop3p",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vcmpxExecWarHazard = Feature{
+ .name = "vcmpx-exec-war-hazard",
+ .description = "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)",
+ .llvm_name = "vcmpx-exec-war-hazard",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vcmpxPermlaneHazard = Feature{
+ .name = "vcmpx-permlane-hazard",
+ .description = "TODO: describe me",
+ .llvm_name = "vcmpx-permlane-hazard",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_volcanicIslands = Feature{
+ .name = "volcanic-islands",
+ .description = "VOLCANIC_ISLANDS GPU generation",
+ .llvm_name = "volcanic-islands",
+ .subfeatures = &[_]*const Feature {
+ &feature_movrel,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_scalarStores,
+ &feature_gcn3Encoding,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_BitInsts16,
+ &feature_trigReducedRange,
+ &feature_vgprIndexMode,
+ &feature_wavefrontsize64,
+ &feature_gfx8Insts,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_intClampInsts,
+ &feature_sMemrealtime,
+ &feature_sdwaMav,
+ &feature_sdwaOutModsVopc,
+ },
+};
+
+pub const feature_vscnt = Feature{
+ .name = "vscnt",
+ .description = "Has separate store vscnt counter",
+ .llvm_name = "vscnt",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_wavefrontsize16 = Feature{
+ .name = "wavefrontsize16",
+ .description = "The number of threads per wavefront",
+ .llvm_name = "wavefrontsize16",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_wavefrontsize32 = Feature{
+ .name = "wavefrontsize32",
+ .description = "The number of threads per wavefront",
+ .llvm_name = "wavefrontsize32",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_wavefrontsize64 = Feature{
+ .name = "wavefrontsize64",
+ .description = "The number of threads per wavefront",
+ .llvm_name = "wavefrontsize64",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_xnack = Feature{
+ .name = "xnack",
+ .description = "Enable XNACK support",
+ .llvm_name = "xnack",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_halfRate64Ops = Feature{
+ .name = "half-rate-64-ops",
+ .description = "Most fp64 instructions are half rate instead of quarter",
+ .llvm_name = "half-rate-64-ops",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const features = &[_]*const Feature {
+ &feature_BitInsts16,
+ &feature_addNoCarryInsts,
+ &feature_apertureRegs,
+ &feature_atomicFaddInsts,
+ &feature_autoWaitcntBeforeBarrier,
+ &feature_ciInsts,
+ &feature_codeObjectV3,
+ &feature_cumode,
+ &feature_dlInsts,
+ &feature_dpp,
+ &feature_dpp8,
+ &feature_noSramEccSupport,
+ &feature_noXnackSupport,
+ &feature_dot1Insts,
+ &feature_dot2Insts,
+ &feature_dot3Insts,
+ &feature_dot4Insts,
+ &feature_dot5Insts,
+ &feature_dot6Insts,
+ &feature_DumpCode,
+ &feature_dumpcode,
+ &feature_enableDs128,
+ &feature_loadStoreOpt,
+ &feature_enablePrtStrictNull,
+ &feature_siScheduler,
+ &feature_unsafeDsOffsetFolding,
+ &feature_fmaf,
+ &feature_fp16Denormals,
+ &feature_fp32Denormals,
+ &feature_fp64,
+ &feature_fp64Denormals,
+ &feature_fp64Fp16Denormals,
+ &feature_fpExceptions,
+ &feature_fastFmaf,
+ &feature_flatAddressSpace,
+ &feature_flatForGlobal,
+ &feature_flatGlobalInsts,
+ &feature_flatInstOffsets,
+ &feature_flatScratchInsts,
+ &feature_flatSegmentOffsetBug,
+ &feature_fmaMixInsts,
+ &feature_gcn3Encoding,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_gfx8Insts,
+ &feature_gfx9,
+ &feature_gfx9Insts,
+ &feature_gfx10,
+ &feature_gfx10Insts,
+ &feature_instFwdPrefetchBug,
+ &feature_intClampInsts,
+ &feature_inv2piInlineImm,
+ &feature_ldsbankcount16,
+ &feature_ldsbankcount32,
+ &feature_ldsBranchVmemWarHazard,
+ &feature_ldsMisalignedBug,
+ &feature_localmemorysize0,
+ &feature_localmemorysize32768,
+ &feature_localmemorysize65536,
+ &feature_maiInsts,
+ &feature_mfmaInlineLiteralBug,
+ &feature_mimgR128,
+ &feature_madMixInsts,
+ &feature_maxPrivateElementSize4,
+ &feature_maxPrivateElementSize8,
+ &feature_maxPrivateElementSize16,
+ &feature_movrel,
+ &feature_nsaEncoding,
+ &feature_nsaToVmemBug,
+ &feature_noDataDepHazard,
+ &feature_noSdstCmpx,
+ &feature_offset3fBug,
+ &feature_pkFmacF16Inst,
+ &feature_promoteAlloca,
+ &feature_r128A16,
+ &feature_registerBanking,
+ &feature_sdwa,
+ &feature_sdwaMav,
+ &feature_sdwaOmod,
+ &feature_sdwaOutModsVopc,
+ &feature_sdwaScalar,
+ &feature_sdwaSdst,
+ &feature_sgprInitBug,
+ &feature_smemToVectorWriteHazard,
+ &feature_sMemrealtime,
+ &feature_sramEcc,
+ &feature_scalarAtomics,
+ &feature_scalarFlatScratchInsts,
+ &feature_scalarStores,
+ &feature_seaIslands,
+ &feature_southernIslands,
+ &feature_trapHandler,
+ &feature_trigReducedRange,
+ &feature_unalignedBufferAccess,
+ &feature_unalignedScratchAccess,
+ &feature_unpackedD16Vmem,
+ &feature_vgprIndexMode,
+ &feature_vmemToScalarWriteHazard,
+ &feature_vop3Literal,
+ &feature_vop3p,
+ &feature_vcmpxExecWarHazard,
+ &feature_vcmpxPermlaneHazard,
+ &feature_volcanicIslands,
+ &feature_vscnt,
+ &feature_wavefrontsize16,
+ &feature_wavefrontsize32,
+ &feature_wavefrontsize64,
+ &feature_xnack,
+ &feature_halfRate64Ops,
+};
+
+pub const cpu_bonaire = Cpu{
+ .name = "bonaire",
+ .llvm_name = "bonaire",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_ldsbankcount32,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_localmemorysize65536,
+ &feature_movrel,
+ &feature_trigReducedRange,
+ &feature_wavefrontsize64,
+ &feature_flatAddressSpace,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_fp64,
+ &feature_seaIslands,
+ },
+};
+
+pub const cpu_carrizo = Cpu{
+ .name = "carrizo",
+ .llvm_name = "carrizo",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_fastFmaf,
+ &feature_ldsbankcount32,
+ &feature_unpackedD16Vmem,
+ &feature_movrel,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_scalarStores,
+ &feature_gcn3Encoding,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_BitInsts16,
+ &feature_trigReducedRange,
+ &feature_vgprIndexMode,
+ &feature_wavefrontsize64,
+ &feature_gfx8Insts,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_intClampInsts,
+ &feature_sMemrealtime,
+ &feature_sdwaMav,
+ &feature_sdwaOutModsVopc,
+ &feature_volcanicIslands,
+ &feature_xnack,
+ &feature_halfRate64Ops,
+ },
+};
+
+pub const cpu_fiji = Cpu{
+ .name = "fiji",
+ .llvm_name = "fiji",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_ldsbankcount32,
+ &feature_unpackedD16Vmem,
+ &feature_movrel,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_scalarStores,
+ &feature_gcn3Encoding,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_BitInsts16,
+ &feature_trigReducedRange,
+ &feature_vgprIndexMode,
+ &feature_wavefrontsize64,
+ &feature_gfx8Insts,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_intClampInsts,
+ &feature_sMemrealtime,
+ &feature_sdwaMav,
+ &feature_sdwaOutModsVopc,
+ &feature_volcanicIslands,
+ },
+};
+
+pub const cpu_generic = Cpu{
+ .name = "generic",
+ .llvm_name = "generic",
+ .subfeatures = &[_]*const Feature {
+ &feature_wavefrontsize64,
+ },
+};
+
+pub const cpu_genericHsa = Cpu{
+ .name = "generic-hsa",
+ .llvm_name = "generic-hsa",
+ .subfeatures = &[_]*const Feature {
+ &feature_flatAddressSpace,
+ &feature_wavefrontsize64,
+ },
+};
+
+pub const cpu_gfx1010 = Cpu{
+ .name = "gfx1010",
+ .llvm_name = "gfx1010",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_dlInsts,
+ &feature_noXnackSupport,
+ &feature_flatSegmentOffsetBug,
+ &feature_movrel,
+ &feature_gfx9Insts,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_noSdstCmpx,
+ &feature_fmaMixInsts,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_sdwaScalar,
+ &feature_sdwaSdst,
+ &feature_apertureRegs,
+ &feature_flatScratchInsts,
+ &feature_vscnt,
+ &feature_noDataDepHazard,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_addNoCarryInsts,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_dpp8,
+ &feature_BitInsts16,
+ &feature_registerBanking,
+ &feature_gfx8Insts,
+ &feature_flatGlobalInsts,
+ &feature_flatInstOffsets,
+ &feature_pkFmacF16Inst,
+ &feature_vop3p,
+ &feature_mimgR128,
+ &feature_intClampInsts,
+ &feature_sMemrealtime,
+ &feature_fastFmaf,
+ &feature_vop3Literal,
+ &feature_sdwaOmod,
+ &feature_gfx10Insts,
+ &feature_gfx10,
+ &feature_instFwdPrefetchBug,
+ &feature_ldsbankcount32,
+ &feature_ldsBranchVmemWarHazard,
+ &feature_ldsMisalignedBug,
+ &feature_nsaEncoding,
+ &feature_nsaToVmemBug,
+ &feature_offset3fBug,
+ &feature_smemToVectorWriteHazard,
+ &feature_scalarAtomics,
+ &feature_scalarFlatScratchInsts,
+ &feature_scalarStores,
+ &feature_vmemToScalarWriteHazard,
+ &feature_vcmpxExecWarHazard,
+ &feature_vcmpxPermlaneHazard,
+ &feature_wavefrontsize32,
+ },
+};
+
+pub const cpu_gfx1011 = Cpu{
+ .name = "gfx1011",
+ .llvm_name = "gfx1011",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_dlInsts,
+ &feature_noXnackSupport,
+ &feature_dot1Insts,
+ &feature_dot2Insts,
+ &feature_dot5Insts,
+ &feature_dot6Insts,
+ &feature_flatSegmentOffsetBug,
+ &feature_movrel,
+ &feature_gfx9Insts,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_noSdstCmpx,
+ &feature_fmaMixInsts,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_sdwaScalar,
+ &feature_sdwaSdst,
+ &feature_apertureRegs,
+ &feature_flatScratchInsts,
+ &feature_vscnt,
+ &feature_noDataDepHazard,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_addNoCarryInsts,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_dpp8,
+ &feature_BitInsts16,
+ &feature_registerBanking,
+ &feature_gfx8Insts,
+ &feature_flatGlobalInsts,
+ &feature_flatInstOffsets,
+ &feature_pkFmacF16Inst,
+ &feature_vop3p,
+ &feature_mimgR128,
+ &feature_intClampInsts,
+ &feature_sMemrealtime,
+ &feature_fastFmaf,
+ &feature_vop3Literal,
+ &feature_sdwaOmod,
+ &feature_gfx10Insts,
+ &feature_gfx10,
+ &feature_instFwdPrefetchBug,
+ &feature_ldsbankcount32,
+ &feature_ldsBranchVmemWarHazard,
+ &feature_nsaEncoding,
+ &feature_nsaToVmemBug,
+ &feature_offset3fBug,
+ &feature_smemToVectorWriteHazard,
+ &feature_scalarAtomics,
+ &feature_scalarFlatScratchInsts,
+ &feature_scalarStores,
+ &feature_vmemToScalarWriteHazard,
+ &feature_vcmpxExecWarHazard,
+ &feature_vcmpxPermlaneHazard,
+ &feature_wavefrontsize32,
+ },
+};
+
+pub const cpu_gfx1012 = Cpu{
+ .name = "gfx1012",
+ .llvm_name = "gfx1012",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_dlInsts,
+ &feature_noXnackSupport,
+ &feature_dot1Insts,
+ &feature_dot2Insts,
+ &feature_dot5Insts,
+ &feature_dot6Insts,
+ &feature_flatSegmentOffsetBug,
+ &feature_movrel,
+ &feature_gfx9Insts,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_noSdstCmpx,
+ &feature_fmaMixInsts,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_sdwaScalar,
+ &feature_sdwaSdst,
+ &feature_apertureRegs,
+ &feature_flatScratchInsts,
+ &feature_vscnt,
+ &feature_noDataDepHazard,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_addNoCarryInsts,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_dpp8,
+ &feature_BitInsts16,
+ &feature_registerBanking,
+ &feature_gfx8Insts,
+ &feature_flatGlobalInsts,
+ &feature_flatInstOffsets,
+ &feature_pkFmacF16Inst,
+ &feature_vop3p,
+ &feature_mimgR128,
+ &feature_intClampInsts,
+ &feature_sMemrealtime,
+ &feature_fastFmaf,
+ &feature_vop3Literal,
+ &feature_sdwaOmod,
+ &feature_gfx10Insts,
+ &feature_gfx10,
+ &feature_instFwdPrefetchBug,
+ &feature_ldsbankcount32,
+ &feature_ldsBranchVmemWarHazard,
+ &feature_ldsMisalignedBug,
+ &feature_nsaEncoding,
+ &feature_nsaToVmemBug,
+ &feature_offset3fBug,
+ &feature_smemToVectorWriteHazard,
+ &feature_scalarAtomics,
+ &feature_scalarFlatScratchInsts,
+ &feature_scalarStores,
+ &feature_vmemToScalarWriteHazard,
+ &feature_vcmpxExecWarHazard,
+ &feature_vcmpxPermlaneHazard,
+ &feature_wavefrontsize32,
+ },
+};
+
+pub const cpu_gfx600 = Cpu{
+ .name = "gfx600",
+ .llvm_name = "gfx600",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_fastFmaf,
+ &feature_ldsbankcount32,
+ &feature_mimgR128,
+ &feature_movrel,
+ &feature_localmemorysize32768,
+ &feature_trigReducedRange,
+ &feature_wavefrontsize64,
+ &feature_noSramEccSupport,
+ &feature_fp64,
+ &feature_southernIslands,
+ &feature_halfRate64Ops,
+ },
+};
+
+pub const cpu_gfx601 = Cpu{
+ .name = "gfx601",
+ .llvm_name = "gfx601",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_ldsbankcount32,
+ &feature_mimgR128,
+ &feature_movrel,
+ &feature_localmemorysize32768,
+ &feature_trigReducedRange,
+ &feature_wavefrontsize64,
+ &feature_noSramEccSupport,
+ &feature_fp64,
+ &feature_southernIslands,
+ },
+};
+
+pub const cpu_gfx700 = Cpu{
+ .name = "gfx700",
+ .llvm_name = "gfx700",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_ldsbankcount32,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_localmemorysize65536,
+ &feature_movrel,
+ &feature_trigReducedRange,
+ &feature_wavefrontsize64,
+ &feature_flatAddressSpace,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_fp64,
+ &feature_seaIslands,
+ },
+};
+
+pub const cpu_gfx701 = Cpu{
+ .name = "gfx701",
+ .llvm_name = "gfx701",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_fastFmaf,
+ &feature_ldsbankcount32,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_localmemorysize65536,
+ &feature_movrel,
+ &feature_trigReducedRange,
+ &feature_wavefrontsize64,
+ &feature_flatAddressSpace,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_fp64,
+ &feature_seaIslands,
+ &feature_halfRate64Ops,
+ },
+};
+
+pub const cpu_gfx702 = Cpu{
+ .name = "gfx702",
+ .llvm_name = "gfx702",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_fastFmaf,
+ &feature_ldsbankcount16,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_localmemorysize65536,
+ &feature_movrel,
+ &feature_trigReducedRange,
+ &feature_wavefrontsize64,
+ &feature_flatAddressSpace,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_fp64,
+ &feature_seaIslands,
+ },
+};
+
+pub const cpu_gfx703 = Cpu{
+ .name = "gfx703",
+ .llvm_name = "gfx703",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_ldsbankcount16,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_localmemorysize65536,
+ &feature_movrel,
+ &feature_trigReducedRange,
+ &feature_wavefrontsize64,
+ &feature_flatAddressSpace,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_fp64,
+ &feature_seaIslands,
+ },
+};
+
+pub const cpu_gfx704 = Cpu{
+ .name = "gfx704",
+ .llvm_name = "gfx704",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_ldsbankcount32,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_localmemorysize65536,
+ &feature_movrel,
+ &feature_trigReducedRange,
+ &feature_wavefrontsize64,
+ &feature_flatAddressSpace,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_fp64,
+ &feature_seaIslands,
+ },
+};
+
+pub const cpu_gfx801 = Cpu{
+ .name = "gfx801",
+ .llvm_name = "gfx801",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_fastFmaf,
+ &feature_ldsbankcount32,
+ &feature_unpackedD16Vmem,
+ &feature_movrel,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_scalarStores,
+ &feature_gcn3Encoding,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_BitInsts16,
+ &feature_trigReducedRange,
+ &feature_vgprIndexMode,
+ &feature_wavefrontsize64,
+ &feature_gfx8Insts,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_intClampInsts,
+ &feature_sMemrealtime,
+ &feature_sdwaMav,
+ &feature_sdwaOutModsVopc,
+ &feature_volcanicIslands,
+ &feature_xnack,
+ &feature_halfRate64Ops,
+ },
+};
+
+pub const cpu_gfx802 = Cpu{
+ .name = "gfx802",
+ .llvm_name = "gfx802",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_ldsbankcount32,
+ &feature_sgprInitBug,
+ &feature_unpackedD16Vmem,
+ &feature_movrel,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_scalarStores,
+ &feature_gcn3Encoding,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_BitInsts16,
+ &feature_trigReducedRange,
+ &feature_vgprIndexMode,
+ &feature_wavefrontsize64,
+ &feature_gfx8Insts,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_intClampInsts,
+ &feature_sMemrealtime,
+ &feature_sdwaMav,
+ &feature_sdwaOutModsVopc,
+ &feature_volcanicIslands,
+ },
+};
+
+pub const cpu_gfx803 = Cpu{
+ .name = "gfx803",
+ .llvm_name = "gfx803",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_ldsbankcount32,
+ &feature_unpackedD16Vmem,
+ &feature_movrel,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_scalarStores,
+ &feature_gcn3Encoding,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_BitInsts16,
+ &feature_trigReducedRange,
+ &feature_vgprIndexMode,
+ &feature_wavefrontsize64,
+ &feature_gfx8Insts,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_intClampInsts,
+ &feature_sMemrealtime,
+ &feature_sdwaMav,
+ &feature_sdwaOutModsVopc,
+ &feature_volcanicIslands,
+ },
+};
+
+pub const cpu_gfx810 = Cpu{
+ .name = "gfx810",
+ .llvm_name = "gfx810",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_ldsbankcount16,
+ &feature_movrel,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_scalarStores,
+ &feature_gcn3Encoding,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_BitInsts16,
+ &feature_trigReducedRange,
+ &feature_vgprIndexMode,
+ &feature_wavefrontsize64,
+ &feature_gfx8Insts,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_intClampInsts,
+ &feature_sMemrealtime,
+ &feature_sdwaMav,
+ &feature_sdwaOutModsVopc,
+ &feature_volcanicIslands,
+ &feature_xnack,
+ },
+};
+
+pub const cpu_gfx900 = Cpu{
+ .name = "gfx900",
+ .llvm_name = "gfx900",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noSramEccSupport,
+ &feature_noXnackSupport,
+ &feature_gfx9Insts,
+ &feature_ciInsts,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_scalarStores,
+ &feature_sdwaScalar,
+ &feature_sdwaSdst,
+ &feature_gcn3Encoding,
+ &feature_apertureRegs,
+ &feature_flatScratchInsts,
+ &feature_r128A16,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_addNoCarryInsts,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_BitInsts16,
+ &feature_vgprIndexMode,
+ &feature_wavefrontsize64,
+ &feature_gfx8Insts,
+ &feature_flatGlobalInsts,
+ &feature_scalarFlatScratchInsts,
+ &feature_scalarAtomics,
+ &feature_flatInstOffsets,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_vop3p,
+ &feature_sMemrealtime,
+ &feature_intClampInsts,
+ &feature_fastFmaf,
+ &feature_sdwaOmod,
+ &feature_gfx9,
+ &feature_ldsbankcount32,
+ &feature_madMixInsts,
+ },
+};
+
+pub const cpu_gfx902 = Cpu{
+ .name = "gfx902",
+ .llvm_name = "gfx902",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noSramEccSupport,
+ &feature_gfx9Insts,
+ &feature_ciInsts,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_scalarStores,
+ &feature_sdwaScalar,
+ &feature_sdwaSdst,
+ &feature_gcn3Encoding,
+ &feature_apertureRegs,
+ &feature_flatScratchInsts,
+ &feature_r128A16,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_addNoCarryInsts,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_BitInsts16,
+ &feature_vgprIndexMode,
+ &feature_wavefrontsize64,
+ &feature_gfx8Insts,
+ &feature_flatGlobalInsts,
+ &feature_scalarFlatScratchInsts,
+ &feature_scalarAtomics,
+ &feature_flatInstOffsets,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_vop3p,
+ &feature_sMemrealtime,
+ &feature_intClampInsts,
+ &feature_fastFmaf,
+ &feature_sdwaOmod,
+ &feature_gfx9,
+ &feature_ldsbankcount32,
+ &feature_madMixInsts,
+ &feature_xnack,
+ },
+};
+
+pub const cpu_gfx904 = Cpu{
+ .name = "gfx904",
+ .llvm_name = "gfx904",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noSramEccSupport,
+ &feature_noXnackSupport,
+ &feature_fmaMixInsts,
+ &feature_gfx9Insts,
+ &feature_ciInsts,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_scalarStores,
+ &feature_sdwaScalar,
+ &feature_sdwaSdst,
+ &feature_gcn3Encoding,
+ &feature_apertureRegs,
+ &feature_flatScratchInsts,
+ &feature_r128A16,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_addNoCarryInsts,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_BitInsts16,
+ &feature_vgprIndexMode,
+ &feature_wavefrontsize64,
+ &feature_gfx8Insts,
+ &feature_flatGlobalInsts,
+ &feature_scalarFlatScratchInsts,
+ &feature_scalarAtomics,
+ &feature_flatInstOffsets,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_vop3p,
+ &feature_sMemrealtime,
+ &feature_intClampInsts,
+ &feature_fastFmaf,
+ &feature_sdwaOmod,
+ &feature_gfx9,
+ &feature_ldsbankcount32,
+ },
+};
+
+pub const cpu_gfx906 = Cpu{
+ .name = "gfx906",
+ .llvm_name = "gfx906",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_dlInsts,
+ &feature_noXnackSupport,
+ &feature_dot1Insts,
+ &feature_dot2Insts,
+ &feature_fmaMixInsts,
+ &feature_gfx9Insts,
+ &feature_ciInsts,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_scalarStores,
+ &feature_sdwaScalar,
+ &feature_sdwaSdst,
+ &feature_gcn3Encoding,
+ &feature_apertureRegs,
+ &feature_flatScratchInsts,
+ &feature_r128A16,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_addNoCarryInsts,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_BitInsts16,
+ &feature_vgprIndexMode,
+ &feature_wavefrontsize64,
+ &feature_gfx8Insts,
+ &feature_flatGlobalInsts,
+ &feature_scalarFlatScratchInsts,
+ &feature_scalarAtomics,
+ &feature_flatInstOffsets,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_vop3p,
+ &feature_sMemrealtime,
+ &feature_intClampInsts,
+ &feature_fastFmaf,
+ &feature_sdwaOmod,
+ &feature_gfx9,
+ &feature_ldsbankcount32,
+ &feature_halfRate64Ops,
+ },
+};
+
+pub const cpu_gfx908 = Cpu{
+ .name = "gfx908",
+ .llvm_name = "gfx908",
+ .subfeatures = &[_]*const Feature {
+ &feature_atomicFaddInsts,
+ &feature_codeObjectV3,
+ &feature_dlInsts,
+ &feature_dot1Insts,
+ &feature_dot2Insts,
+ &feature_dot3Insts,
+ &feature_dot4Insts,
+ &feature_dot5Insts,
+ &feature_dot6Insts,
+ &feature_fmaMixInsts,
+ &feature_gfx9Insts,
+ &feature_ciInsts,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_scalarStores,
+ &feature_sdwaScalar,
+ &feature_sdwaSdst,
+ &feature_gcn3Encoding,
+ &feature_apertureRegs,
+ &feature_flatScratchInsts,
+ &feature_r128A16,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_addNoCarryInsts,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_BitInsts16,
+ &feature_vgprIndexMode,
+ &feature_wavefrontsize64,
+ &feature_gfx8Insts,
+ &feature_flatGlobalInsts,
+ &feature_scalarFlatScratchInsts,
+ &feature_scalarAtomics,
+ &feature_flatInstOffsets,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_vop3p,
+ &feature_sMemrealtime,
+ &feature_intClampInsts,
+ &feature_fastFmaf,
+ &feature_sdwaOmod,
+ &feature_gfx9,
+ &feature_ldsbankcount32,
+ &feature_maiInsts,
+ &feature_mfmaInlineLiteralBug,
+ &feature_pkFmacF16Inst,
+ &feature_sramEcc,
+ &feature_halfRate64Ops,
+ },
+};
+
+pub const cpu_gfx909 = Cpu{
+ .name = "gfx909",
+ .llvm_name = "gfx909",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_gfx9Insts,
+ &feature_ciInsts,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_scalarStores,
+ &feature_sdwaScalar,
+ &feature_sdwaSdst,
+ &feature_gcn3Encoding,
+ &feature_apertureRegs,
+ &feature_flatScratchInsts,
+ &feature_r128A16,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_addNoCarryInsts,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_BitInsts16,
+ &feature_vgprIndexMode,
+ &feature_wavefrontsize64,
+ &feature_gfx8Insts,
+ &feature_flatGlobalInsts,
+ &feature_scalarFlatScratchInsts,
+ &feature_scalarAtomics,
+ &feature_flatInstOffsets,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_vop3p,
+ &feature_sMemrealtime,
+ &feature_intClampInsts,
+ &feature_fastFmaf,
+ &feature_sdwaOmod,
+ &feature_gfx9,
+ &feature_ldsbankcount32,
+ &feature_madMixInsts,
+ &feature_xnack,
+ },
+};
+
+pub const cpu_hainan = Cpu{
+ .name = "hainan",
+ .llvm_name = "hainan",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_ldsbankcount32,
+ &feature_mimgR128,
+ &feature_movrel,
+ &feature_localmemorysize32768,
+ &feature_trigReducedRange,
+ &feature_wavefrontsize64,
+ &feature_noSramEccSupport,
+ &feature_fp64,
+ &feature_southernIslands,
+ },
+};
+
+pub const cpu_hawaii = Cpu{
+ .name = "hawaii",
+ .llvm_name = "hawaii",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_fastFmaf,
+ &feature_ldsbankcount32,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_localmemorysize65536,
+ &feature_movrel,
+ &feature_trigReducedRange,
+ &feature_wavefrontsize64,
+ &feature_flatAddressSpace,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_fp64,
+ &feature_seaIslands,
+ &feature_halfRate64Ops,
+ },
+};
+
+pub const cpu_iceland = Cpu{
+ .name = "iceland",
+ .llvm_name = "iceland",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_ldsbankcount32,
+ &feature_sgprInitBug,
+ &feature_unpackedD16Vmem,
+ &feature_movrel,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_scalarStores,
+ &feature_gcn3Encoding,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_BitInsts16,
+ &feature_trigReducedRange,
+ &feature_vgprIndexMode,
+ &feature_wavefrontsize64,
+ &feature_gfx8Insts,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_intClampInsts,
+ &feature_sMemrealtime,
+ &feature_sdwaMav,
+ &feature_sdwaOutModsVopc,
+ &feature_volcanicIslands,
+ },
+};
+
+pub const cpu_kabini = Cpu{
+ .name = "kabini",
+ .llvm_name = "kabini",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_ldsbankcount16,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_localmemorysize65536,
+ &feature_movrel,
+ &feature_trigReducedRange,
+ &feature_wavefrontsize64,
+ &feature_flatAddressSpace,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_fp64,
+ &feature_seaIslands,
+ },
+};
+
+pub const cpu_kaveri = Cpu{
+ .name = "kaveri",
+ .llvm_name = "kaveri",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_ldsbankcount32,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_localmemorysize65536,
+ &feature_movrel,
+ &feature_trigReducedRange,
+ &feature_wavefrontsize64,
+ &feature_flatAddressSpace,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_fp64,
+ &feature_seaIslands,
+ },
+};
+
+pub const cpu_mullins = Cpu{
+ .name = "mullins",
+ .llvm_name = "mullins",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_ldsbankcount16,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_localmemorysize65536,
+ &feature_movrel,
+ &feature_trigReducedRange,
+ &feature_wavefrontsize64,
+ &feature_flatAddressSpace,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_fp64,
+ &feature_seaIslands,
+ },
+};
+
+pub const cpu_oland = Cpu{
+ .name = "oland",
+ .llvm_name = "oland",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_ldsbankcount32,
+ &feature_mimgR128,
+ &feature_movrel,
+ &feature_localmemorysize32768,
+ &feature_trigReducedRange,
+ &feature_wavefrontsize64,
+ &feature_noSramEccSupport,
+ &feature_fp64,
+ &feature_southernIslands,
+ },
+};
+
+pub const cpu_pitcairn = Cpu{
+ .name = "pitcairn",
+ .llvm_name = "pitcairn",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_ldsbankcount32,
+ &feature_mimgR128,
+ &feature_movrel,
+ &feature_localmemorysize32768,
+ &feature_trigReducedRange,
+ &feature_wavefrontsize64,
+ &feature_noSramEccSupport,
+ &feature_fp64,
+ &feature_southernIslands,
+ },
+};
+
+pub const cpu_polaris10 = Cpu{
+ .name = "polaris10",
+ .llvm_name = "polaris10",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_ldsbankcount32,
+ &feature_unpackedD16Vmem,
+ &feature_movrel,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_scalarStores,
+ &feature_gcn3Encoding,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_BitInsts16,
+ &feature_trigReducedRange,
+ &feature_vgprIndexMode,
+ &feature_wavefrontsize64,
+ &feature_gfx8Insts,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_intClampInsts,
+ &feature_sMemrealtime,
+ &feature_sdwaMav,
+ &feature_sdwaOutModsVopc,
+ &feature_volcanicIslands,
+ },
+};
+
+pub const cpu_polaris11 = Cpu{
+ .name = "polaris11",
+ .llvm_name = "polaris11",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_ldsbankcount32,
+ &feature_unpackedD16Vmem,
+ &feature_movrel,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_scalarStores,
+ &feature_gcn3Encoding,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_BitInsts16,
+ &feature_trigReducedRange,
+ &feature_vgprIndexMode,
+ &feature_wavefrontsize64,
+ &feature_gfx8Insts,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_intClampInsts,
+ &feature_sMemrealtime,
+ &feature_sdwaMav,
+ &feature_sdwaOutModsVopc,
+ &feature_volcanicIslands,
+ },
+};
+
+pub const cpu_stoney = Cpu{
+ .name = "stoney",
+ .llvm_name = "stoney",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_ldsbankcount16,
+ &feature_movrel,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_scalarStores,
+ &feature_gcn3Encoding,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_BitInsts16,
+ &feature_trigReducedRange,
+ &feature_vgprIndexMode,
+ &feature_wavefrontsize64,
+ &feature_gfx8Insts,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_intClampInsts,
+ &feature_sMemrealtime,
+ &feature_sdwaMav,
+ &feature_sdwaOutModsVopc,
+ &feature_volcanicIslands,
+ &feature_xnack,
+ },
+};
+
+pub const cpu_tahiti = Cpu{
+ .name = "tahiti",
+ .llvm_name = "tahiti",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_fastFmaf,
+ &feature_ldsbankcount32,
+ &feature_mimgR128,
+ &feature_movrel,
+ &feature_localmemorysize32768,
+ &feature_trigReducedRange,
+ &feature_wavefrontsize64,
+ &feature_noSramEccSupport,
+ &feature_fp64,
+ &feature_southernIslands,
+ &feature_halfRate64Ops,
+ },
+};
+
+pub const cpu_tonga = Cpu{
+ .name = "tonga",
+ .llvm_name = "tonga",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_ldsbankcount32,
+ &feature_sgprInitBug,
+ &feature_unpackedD16Vmem,
+ &feature_movrel,
+ &feature_ciInsts,
+ &feature_noSramEccSupport,
+ &feature_sdwa,
+ &feature_localmemorysize65536,
+ &feature_scalarStores,
+ &feature_gcn3Encoding,
+ &feature_flatAddressSpace,
+ &feature_dpp,
+ &feature_inv2piInlineImm,
+ &feature_fp64,
+ &feature_BitInsts16,
+ &feature_trigReducedRange,
+ &feature_vgprIndexMode,
+ &feature_wavefrontsize64,
+ &feature_gfx8Insts,
+ &feature_gfx7Gfx8Gfx9Insts,
+ &feature_mimgR128,
+ &feature_intClampInsts,
+ &feature_sMemrealtime,
+ &feature_sdwaMav,
+ &feature_sdwaOutModsVopc,
+ &feature_volcanicIslands,
+ },
+};
+
+pub const cpu_verde = Cpu{
+ .name = "verde",
+ .llvm_name = "verde",
+ .subfeatures = &[_]*const Feature {
+ &feature_codeObjectV3,
+ &feature_noXnackSupport,
+ &feature_ldsbankcount32,
+ &feature_mimgR128,
+ &feature_movrel,
+ &feature_localmemorysize32768,
+ &feature_trigReducedRange,
+ &feature_wavefrontsize64,
+ &feature_noSramEccSupport,
+ &feature_fp64,
+ &feature_southernIslands,
+ },
+};
+
+pub const cpus = &[_]*const Cpu {
+ &cpu_bonaire,
+ &cpu_carrizo,
+ &cpu_fiji,
+ &cpu_generic,
+ &cpu_genericHsa,
+ &cpu_gfx1010,
+ &cpu_gfx1011,
+ &cpu_gfx1012,
+ &cpu_gfx600,
+ &cpu_gfx601,
+ &cpu_gfx700,
+ &cpu_gfx701,
+ &cpu_gfx702,
+ &cpu_gfx703,
+ &cpu_gfx704,
+ &cpu_gfx801,
+ &cpu_gfx802,
+ &cpu_gfx803,
+ &cpu_gfx810,
+ &cpu_gfx900,
+ &cpu_gfx902,
+ &cpu_gfx904,
+ &cpu_gfx906,
+ &cpu_gfx908,
+ &cpu_gfx909,
+ &cpu_hainan,
+ &cpu_hawaii,
+ &cpu_iceland,
+ &cpu_kabini,
+ &cpu_kaveri,
+ &cpu_mullins,
+ &cpu_oland,
+ &cpu_pitcairn,
+ &cpu_polaris10,
+ &cpu_polaris11,
+ &cpu_stoney,
+ &cpu_tahiti,
+ &cpu_tonga,
+ &cpu_verde,
+};
lib/std/target/arm.zig
@@ -0,0 +1,3595 @@
+const Feature = @import("std").target.Feature;
+const Cpu = @import("std").target.Cpu;
+
+pub const feature_armv2 = Feature{
+ .name = "armv2",
+ .description = "ARMv2 architecture",
+ .llvm_name = "armv2",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_armv2a = Feature{
+ .name = "armv2a",
+ .description = "ARMv2a architecture",
+ .llvm_name = "armv2a",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_armv3 = Feature{
+ .name = "armv3",
+ .description = "ARMv3 architecture",
+ .llvm_name = "armv3",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_armv3m = Feature{
+ .name = "armv3m",
+ .description = "ARMv3m architecture",
+ .llvm_name = "armv3m",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_armv4 = Feature{
+ .name = "armv4",
+ .description = "ARMv4 architecture",
+ .llvm_name = "armv4",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_armv4t = Feature{
+ .name = "armv4t",
+ .description = "ARMv4t architecture",
+ .llvm_name = "armv4t",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ },
+};
+
+pub const feature_armv5t = Feature{
+ .name = "armv5t",
+ .description = "ARMv5t architecture",
+ .llvm_name = "armv5t",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ },
+};
+
+pub const feature_armv5te = Feature{
+ .name = "armv5te",
+ .description = "ARMv5te architecture",
+ .llvm_name = "armv5te",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ },
+};
+
+pub const feature_armv5tej = Feature{
+ .name = "armv5tej",
+ .description = "ARMv5tej architecture",
+ .llvm_name = "armv5tej",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ },
+};
+
+pub const feature_armv6 = Feature{
+ .name = "armv6",
+ .description = "ARMv6 architecture",
+ .llvm_name = "armv6",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_dsp,
+ },
+};
+
+pub const feature_armv6j = Feature{
+ .name = "armv6j",
+ .description = "ARMv7a architecture",
+ .llvm_name = "armv6j",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_dsp,
+ },
+};
+
+pub const feature_armv6k = Feature{
+ .name = "armv6k",
+ .description = "ARMv6k architecture",
+ .llvm_name = "armv6k",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ },
+};
+
+pub const feature_armv6kz = Feature{
+ .name = "armv6kz",
+ .description = "ARMv6kz architecture",
+ .llvm_name = "armv6kz",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_trustzone,
+ },
+};
+
+pub const feature_armv6M = Feature{
+ .name = "armv6-m",
+ .description = "ARMv6m architecture",
+ .llvm_name = "armv6-m",
+ .subfeatures = &[_]*const Feature {
+ &feature_db,
+ &feature_thumbMode,
+ &feature_mclass,
+ &feature_noarm,
+ &feature_v4t,
+ &feature_strictAlign,
+ },
+};
+
+pub const feature_armv6sM = Feature{
+ .name = "armv6s-m",
+ .description = "ARMv6sm architecture",
+ .llvm_name = "armv6s-m",
+ .subfeatures = &[_]*const Feature {
+ &feature_db,
+ &feature_thumbMode,
+ &feature_mclass,
+ &feature_noarm,
+ &feature_v4t,
+ &feature_strictAlign,
+ },
+};
+
+pub const feature_armv6t2 = Feature{
+ .name = "armv6t2",
+ .description = "ARMv6t2 architecture",
+ .llvm_name = "armv6t2",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_dsp,
+ &feature_thumb2,
+ },
+};
+
+pub const feature_armv7A = Feature{
+ .name = "armv7-a",
+ .description = "ARMv7a architecture",
+ .llvm_name = "armv7-a",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_dsp,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_armv7eM = Feature{
+ .name = "armv7e-m",
+ .description = "ARMv7em architecture",
+ .llvm_name = "armv7e-m",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_mclass,
+ &feature_thumbMode,
+ &feature_noarm,
+ &feature_v4t,
+ &feature_dsp,
+ &feature_hwdiv,
+ },
+};
+
+pub const feature_armv7k = Feature{
+ .name = "armv7k",
+ .description = "ARMv7a architecture",
+ .llvm_name = "armv7k",
+ .subfeatures = &[_]*const Feature {
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_d32,
+ &feature_dsp,
+ &feature_aclass,
+ &feature_perfmon,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_armv7M = Feature{
+ .name = "armv7-m",
+ .description = "ARMv7m architecture",
+ .llvm_name = "armv7-m",
+ .subfeatures = &[_]*const Feature {
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_mclass,
+ &feature_thumbMode,
+ &feature_noarm,
+ &feature_v4t,
+ &feature_perfmon,
+ &feature_hwdiv,
+ },
+};
+
+pub const feature_armv7R = Feature{
+ .name = "armv7-r",
+ .description = "ARMv7r architecture",
+ .llvm_name = "armv7-r",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_dsp,
+ &feature_hwdiv,
+ &feature_rclass,
+ },
+};
+
+pub const feature_armv7s = Feature{
+ .name = "armv7s",
+ .description = "ARMv7a architecture",
+ .llvm_name = "armv7s",
+ .subfeatures = &[_]*const Feature {
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_d32,
+ &feature_dsp,
+ &feature_aclass,
+ &feature_perfmon,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_armv7ve = Feature{
+ .name = "armv7ve",
+ .description = "ARMv7ve architecture",
+ .llvm_name = "armv7ve",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_dsp,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_armv8A = Feature{
+ .name = "armv8-a",
+ .description = "ARMv8a architecture",
+ .llvm_name = "armv8-a",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_armv8Mbase = Feature{
+ .name = "armv8-m.base",
+ .description = "ARMv8mBaseline architecture",
+ .llvm_name = "armv8-m.base",
+ .subfeatures = &[_]*const Feature {
+ &feature_acquireRelease,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_msecext8,
+ &feature_thumbMode,
+ &feature_mclass,
+ &feature_noarm,
+ &feature_v4t,
+ &feature_strictAlign,
+ &feature_hwdiv,
+ },
+};
+
+pub const feature_armv8Mmain = Feature{
+ .name = "armv8-m.main",
+ .description = "ARMv8mMainline architecture",
+ .llvm_name = "armv8-m.main",
+ .subfeatures = &[_]*const Feature {
+ &feature_acquireRelease,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_msecext8,
+ &feature_thumb2,
+ &feature_mclass,
+ &feature_thumbMode,
+ &feature_noarm,
+ &feature_v4t,
+ &feature_perfmon,
+ &feature_hwdiv,
+ },
+};
+
+pub const feature_armv8R = Feature{
+ .name = "armv8-r",
+ .description = "ARMv8r architecture",
+ .llvm_name = "armv8-r",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_dfb,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_rclass,
+ },
+};
+
+pub const feature_armv81A = Feature{
+ .name = "armv8.1-a",
+ .description = "ARMv81a architecture",
+ .llvm_name = "armv8.1-a",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_armv81Mmain = Feature{
+ .name = "armv8.1-m.main",
+ .description = "ARMv81mMainline architecture",
+ .llvm_name = "armv8.1-m.main",
+ .subfeatures = &[_]*const Feature {
+ &feature_acquireRelease,
+ &feature_lob,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_msecext8,
+ &feature_thumb2,
+ &feature_mclass,
+ &feature_ras,
+ &feature_noarm,
+ &feature_v4t,
+ &feature_thumbMode,
+ &feature_perfmon,
+ &feature_hwdiv,
+ },
+};
+
+pub const feature_armv82A = Feature{
+ .name = "armv8.2-a",
+ .description = "ARMv82a architecture",
+ .llvm_name = "armv8.2-a",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_ras,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_armv83A = Feature{
+ .name = "armv8.3-a",
+ .description = "ARMv83a architecture",
+ .llvm_name = "armv8.3-a",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_ras,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_armv84A = Feature{
+ .name = "armv8.4-a",
+ .description = "ARMv84a architecture",
+ .llvm_name = "armv8.4-a",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_ras,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_armv85A = Feature{
+ .name = "armv8.5-a",
+ .description = "ARMv85a architecture",
+ .llvm_name = "armv8.5-a",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_ras,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_sb,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_msecext8 = Feature{
+ .name = "8msecext",
+ .description = "Enable support for ARMv8-M Security Extensions",
+ .llvm_name = "8msecext",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_aclass = Feature{
+ .name = "aclass",
+ .description = "Is application profile ('A' series)",
+ .llvm_name = "aclass",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_aes = Feature{
+ .name = "aes",
+ .description = "Enable AES support",
+ .llvm_name = "aes",
+ .subfeatures = &[_]*const Feature {
+ &feature_d32,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_acquireRelease = Feature{
+ .name = "acquire-release",
+ .description = "Has v8 acquire/release (lda/ldaex etc) instructions",
+ .llvm_name = "acquire-release",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_avoidMovsShop = Feature{
+ .name = "avoid-movs-shop",
+ .description = "Avoid movs instructions with shifter operand",
+ .llvm_name = "avoid-movs-shop",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_avoidPartialCpsr = Feature{
+ .name = "avoid-partial-cpsr",
+ .description = "Avoid CPSR partial update for OOO execution",
+ .llvm_name = "avoid-partial-cpsr",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_crc = Feature{
+ .name = "crc",
+ .description = "Enable support for CRC instructions",
+ .llvm_name = "crc",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_cheapPredicableCpsr = Feature{
+ .name = "cheap-predicable-cpsr",
+ .description = "Disable +1 predication cost for instructions updating CPSR",
+ .llvm_name = "cheap-predicable-cpsr",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vldnAlign = Feature{
+ .name = "vldn-align",
+ .description = "Check for VLDn unaligned access",
+ .llvm_name = "vldn-align",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_crypto = Feature{
+ .name = "crypto",
+ .description = "Enable support for Cryptography extensions",
+ .llvm_name = "crypto",
+ .subfeatures = &[_]*const Feature {
+ &feature_d32,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_d32 = Feature{
+ .name = "d32",
+ .description = "Extend FP to 32 double registers",
+ .llvm_name = "d32",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_db = Feature{
+ .name = "db",
+ .description = "Has data barrier (dmb/dsb) instructions",
+ .llvm_name = "db",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dfb = Feature{
+ .name = "dfb",
+ .description = "Has full data barrier (dfb) instruction",
+ .llvm_name = "dfb",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dsp = Feature{
+ .name = "dsp",
+ .description = "Supports DSP instructions in ARM and/or Thumb2",
+ .llvm_name = "dsp",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dontWidenVmovs = Feature{
+ .name = "dont-widen-vmovs",
+ .description = "Don't widen VMOVS to VMOVD",
+ .llvm_name = "dont-widen-vmovs",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dotprod = Feature{
+ .name = "dotprod",
+ .description = "Enable support for dot product instructions",
+ .llvm_name = "dotprod",
+ .subfeatures = &[_]*const Feature {
+ &feature_d32,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_executeOnly = Feature{
+ .name = "execute-only",
+ .description = "Enable the generation of execute only code.",
+ .llvm_name = "execute-only",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_expandFpMlx = Feature{
+ .name = "expand-fp-mlx",
+ .description = "Expand VFP/NEON MLA/MLS instructions",
+ .llvm_name = "expand-fp-mlx",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fp16 = Feature{
+ .name = "fp16",
+ .description = "Enable half-precision floating point",
+ .llvm_name = "fp16",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fp16fml = Feature{
+ .name = "fp16fml",
+ .description = "Enable full half-precision floating point fml instructions",
+ .llvm_name = "fp16fml",
+ .subfeatures = &[_]*const Feature {
+ &feature_fp16,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_fp64 = Feature{
+ .name = "fp64",
+ .description = "Floating point unit supports double precision",
+ .llvm_name = "fp64",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpregs,
+ },
+};
+
+pub const feature_fpao = Feature{
+ .name = "fpao",
+ .description = "Enable fast computation of positive address offsets",
+ .llvm_name = "fpao",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fpArmv8 = Feature{
+ .name = "fp-armv8",
+ .description = "Enable ARMv8 FP",
+ .llvm_name = "fp-armv8",
+ .subfeatures = &[_]*const Feature {
+ &feature_fp16,
+ &feature_d32,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_fpArmv8d16 = Feature{
+ .name = "fp-armv8d16",
+ .description = "Enable ARMv8 FP with only 16 d-registers",
+ .llvm_name = "fp-armv8d16",
+ .subfeatures = &[_]*const Feature {
+ &feature_fp16,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_fpArmv8d16sp = Feature{
+ .name = "fp-armv8d16sp",
+ .description = "Enable ARMv8 FP with only 16 d-registers and no double precision",
+ .llvm_name = "fp-armv8d16sp",
+ .subfeatures = &[_]*const Feature {
+ &feature_fp16,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_fpArmv8sp = Feature{
+ .name = "fp-armv8sp",
+ .description = "Enable ARMv8 FP with no double precision",
+ .llvm_name = "fp-armv8sp",
+ .subfeatures = &[_]*const Feature {
+ &feature_fp16,
+ &feature_d32,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_fpregs = Feature{
+ .name = "fpregs",
+ .description = "Enable FP registers",
+ .llvm_name = "fpregs",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fpregs16 = Feature{
+ .name = "fpregs16",
+ .description = "Enable 16-bit FP registers",
+ .llvm_name = "fpregs16",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpregs,
+ },
+};
+
+pub const feature_fpregs64 = Feature{
+ .name = "fpregs64",
+ .description = "Enable 64-bit FP registers",
+ .llvm_name = "fpregs64",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpregs,
+ },
+};
+
+pub const feature_fullfp16 = Feature{
+ .name = "fullfp16",
+ .description = "Enable full half-precision floating point",
+ .llvm_name = "fullfp16",
+ .subfeatures = &[_]*const Feature {
+ &feature_fp16,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_fuseAes = Feature{
+ .name = "fuse-aes",
+ .description = "CPU fuses AES crypto operations",
+ .llvm_name = "fuse-aes",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fuseLiterals = Feature{
+ .name = "fuse-literals",
+ .description = "CPU fuses literal generation operations",
+ .llvm_name = "fuse-literals",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_hwdivArm = Feature{
+ .name = "hwdiv-arm",
+ .description = "Enable divide instructions in ARM mode",
+ .llvm_name = "hwdiv-arm",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_hwdiv = Feature{
+ .name = "hwdiv",
+ .description = "Enable divide instructions in Thumb",
+ .llvm_name = "hwdiv",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_noBranchPredictor = Feature{
+ .name = "no-branch-predictor",
+ .description = "Has no branch predictor",
+ .llvm_name = "no-branch-predictor",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_retAddrStack = Feature{
+ .name = "ret-addr-stack",
+ .description = "Has return address stack",
+ .llvm_name = "ret-addr-stack",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_slowfpvmlx = Feature{
+ .name = "slowfpvmlx",
+ .description = "Disable VFP / NEON MAC instructions",
+ .llvm_name = "slowfpvmlx",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vmlxHazards = Feature{
+ .name = "vmlx-hazards",
+ .description = "Has VMLx hazards",
+ .llvm_name = "vmlx-hazards",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_lob = Feature{
+ .name = "lob",
+ .description = "Enable Low Overhead Branch extensions",
+ .llvm_name = "lob",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_longCalls = Feature{
+ .name = "long-calls",
+ .description = "Generate calls via indirect call instructions",
+ .llvm_name = "long-calls",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mclass = Feature{
+ .name = "mclass",
+ .description = "Is microcontroller profile ('M' series)",
+ .llvm_name = "mclass",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mp = Feature{
+ .name = "mp",
+ .description = "Supports Multiprocessing extension",
+ .llvm_name = "mp",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mve1beat = Feature{
+ .name = "mve1beat",
+ .description = "Model MVE instructions as a 1 beat per tick architecture",
+ .llvm_name = "mve1beat",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mve2beat = Feature{
+ .name = "mve2beat",
+ .description = "Model MVE instructions as a 2 beats per tick architecture",
+ .llvm_name = "mve2beat",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mve4beat = Feature{
+ .name = "mve4beat",
+ .description = "Model MVE instructions as a 4 beats per tick architecture",
+ .llvm_name = "mve4beat",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_muxedUnits = Feature{
+ .name = "muxed-units",
+ .description = "Has muxed AGU and NEON/FPU",
+ .llvm_name = "muxed-units",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_neon = Feature{
+ .name = "neon",
+ .description = "Enable NEON instructions",
+ .llvm_name = "neon",
+ .subfeatures = &[_]*const Feature {
+ &feature_d32,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_neonfp = Feature{
+ .name = "neonfp",
+ .description = "Use NEON for single precision FP",
+ .llvm_name = "neonfp",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_neonFpmovs = Feature{
+ .name = "neon-fpmovs",
+ .description = "Convert VMOVSR, VMOVRS, VMOVS to NEON",
+ .llvm_name = "neon-fpmovs",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_naclTrap = Feature{
+ .name = "nacl-trap",
+ .description = "NaCl trap",
+ .llvm_name = "nacl-trap",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_noarm = Feature{
+ .name = "noarm",
+ .description = "Does not support ARM mode execution",
+ .llvm_name = "noarm",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_noMovt = Feature{
+ .name = "no-movt",
+ .description = "Don't use movt/movw pairs for 32-bit imms",
+ .llvm_name = "no-movt",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_noNegImmediates = Feature{
+ .name = "no-neg-immediates",
+ .description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.",
+ .llvm_name = "no-neg-immediates",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_disablePostraScheduler = Feature{
+ .name = "disable-postra-scheduler",
+ .description = "Don't schedule again after register allocation",
+ .llvm_name = "disable-postra-scheduler",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_nonpipelinedVfp = Feature{
+ .name = "nonpipelined-vfp",
+ .description = "VFP instructions are not pipelined",
+ .llvm_name = "nonpipelined-vfp",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_perfmon = Feature{
+ .name = "perfmon",
+ .description = "Enable support for Performance Monitor extensions",
+ .llvm_name = "perfmon",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_bit32 = Feature{
+ .name = "32bit",
+ .description = "Prefer 32-bit Thumb instrs",
+ .llvm_name = "32bit",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_preferIshst = Feature{
+ .name = "prefer-ishst",
+ .description = "Prefer ISHST barriers",
+ .llvm_name = "prefer-ishst",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_loopAlign = Feature{
+ .name = "loop-align",
+ .description = "Prefer 32-bit alignment for loops",
+ .llvm_name = "loop-align",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_preferVmovsr = Feature{
+ .name = "prefer-vmovsr",
+ .description = "Prefer VMOVSR",
+ .llvm_name = "prefer-vmovsr",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_profUnpr = Feature{
+ .name = "prof-unpr",
+ .description = "Is profitable to unpredicate",
+ .llvm_name = "prof-unpr",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ras = Feature{
+ .name = "ras",
+ .description = "Enable Reliability, Availability and Serviceability extensions",
+ .llvm_name = "ras",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_rclass = Feature{
+ .name = "rclass",
+ .description = "Is realtime profile ('R' series)",
+ .llvm_name = "rclass",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_readTpHard = Feature{
+ .name = "read-tp-hard",
+ .description = "Reading thread pointer from register",
+ .llvm_name = "read-tp-hard",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reserveR9 = Feature{
+ .name = "reserve-r9",
+ .description = "Reserve R9, making it unavailable as GPR",
+ .llvm_name = "reserve-r9",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sb = Feature{
+ .name = "sb",
+ .description = "Enable v8.5a Speculation Barrier",
+ .llvm_name = "sb",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sha2 = Feature{
+ .name = "sha2",
+ .description = "Enable SHA1 and SHA256 support",
+ .llvm_name = "sha2",
+ .subfeatures = &[_]*const Feature {
+ &feature_d32,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_slowFpBrcc = Feature{
+ .name = "slow-fp-brcc",
+ .description = "FP compare + branch is slow",
+ .llvm_name = "slow-fp-brcc",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_slowLoadDSubreg = Feature{
+ .name = "slow-load-D-subreg",
+ .description = "Loading into D subregs is slow",
+ .llvm_name = "slow-load-D-subreg",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_slowOddReg = Feature{
+ .name = "slow-odd-reg",
+ .description = "VLDM/VSTM starting with an odd register is slow",
+ .llvm_name = "slow-odd-reg",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_slowVdup32 = Feature{
+ .name = "slow-vdup32",
+ .description = "Has slow VDUP32 - prefer VMOV",
+ .llvm_name = "slow-vdup32",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_slowVgetlni32 = Feature{
+ .name = "slow-vgetlni32",
+ .description = "Has slow VGETLNi32 - prefer VMOV",
+ .llvm_name = "slow-vgetlni32",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_splatVfpNeon = Feature{
+ .name = "splat-vfp-neon",
+ .description = "Splat register from VFP to NEON",
+ .llvm_name = "splat-vfp-neon",
+ .subfeatures = &[_]*const Feature {
+ &feature_dontWidenVmovs,
+ },
+};
+
+pub const feature_strictAlign = Feature{
+ .name = "strict-align",
+ .description = "Disallow all unaligned memory access",
+ .llvm_name = "strict-align",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_thumb2 = Feature{
+ .name = "thumb2",
+ .description = "Enable Thumb2 instructions",
+ .llvm_name = "thumb2",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_trustzone = Feature{
+ .name = "trustzone",
+ .description = "Enable support for TrustZone security extensions",
+ .llvm_name = "trustzone",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_useAa = Feature{
+ .name = "use-aa",
+ .description = "Use alias analysis during codegen",
+ .llvm_name = "use-aa",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_useMisched = Feature{
+ .name = "use-misched",
+ .description = "Use the MachineScheduler",
+ .llvm_name = "use-misched",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_wideStrideVfp = Feature{
+ .name = "wide-stride-vfp",
+ .description = "Use a wide stride when allocating VFP registers",
+ .llvm_name = "wide-stride-vfp",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_v7clrex = Feature{
+ .name = "v7clrex",
+ .description = "Has v7 clrex instruction",
+ .llvm_name = "v7clrex",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vfp2 = Feature{
+ .name = "vfp2",
+ .description = "Enable VFP2 instructions",
+ .llvm_name = "vfp2",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpregs,
+ },
+};
+
+pub const feature_vfp2sp = Feature{
+ .name = "vfp2sp",
+ .description = "Enable VFP2 instructions with no double precision",
+ .llvm_name = "vfp2sp",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpregs,
+ },
+};
+
+pub const feature_vfp3 = Feature{
+ .name = "vfp3",
+ .description = "Enable VFP3 instructions",
+ .llvm_name = "vfp3",
+ .subfeatures = &[_]*const Feature {
+ &feature_d32,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_vfp3d16 = Feature{
+ .name = "vfp3d16",
+ .description = "Enable VFP3 instructions with only 16 d-registers",
+ .llvm_name = "vfp3d16",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpregs,
+ },
+};
+
+pub const feature_vfp3d16sp = Feature{
+ .name = "vfp3d16sp",
+ .description = "Enable VFP3 instructions with only 16 d-registers and no double precision",
+ .llvm_name = "vfp3d16sp",
+ .subfeatures = &[_]*const Feature {
+ &feature_fpregs,
+ },
+};
+
+pub const feature_vfp3sp = Feature{
+ .name = "vfp3sp",
+ .description = "Enable VFP3 instructions with no double precision",
+ .llvm_name = "vfp3sp",
+ .subfeatures = &[_]*const Feature {
+ &feature_d32,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_vfp4 = Feature{
+ .name = "vfp4",
+ .description = "Enable VFP4 instructions",
+ .llvm_name = "vfp4",
+ .subfeatures = &[_]*const Feature {
+ &feature_fp16,
+ &feature_d32,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_vfp4d16 = Feature{
+ .name = "vfp4d16",
+ .description = "Enable VFP4 instructions with only 16 d-registers",
+ .llvm_name = "vfp4d16",
+ .subfeatures = &[_]*const Feature {
+ &feature_fp16,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_vfp4d16sp = Feature{
+ .name = "vfp4d16sp",
+ .description = "Enable VFP4 instructions with only 16 d-registers and no double precision",
+ .llvm_name = "vfp4d16sp",
+ .subfeatures = &[_]*const Feature {
+ &feature_fp16,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_vfp4sp = Feature{
+ .name = "vfp4sp",
+ .description = "Enable VFP4 instructions with no double precision",
+ .llvm_name = "vfp4sp",
+ .subfeatures = &[_]*const Feature {
+ &feature_fp16,
+ &feature_d32,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_vmlxForwarding = Feature{
+ .name = "vmlx-forwarding",
+ .description = "Has multiplier accumulator forwarding",
+ .llvm_name = "vmlx-forwarding",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_virtualization = Feature{
+ .name = "virtualization",
+ .description = "Supports Virtualization extension",
+ .llvm_name = "virtualization",
+ .subfeatures = &[_]*const Feature {
+ &feature_hwdiv,
+ &feature_hwdivArm,
+ },
+};
+
+pub const feature_zcz = Feature{
+ .name = "zcz",
+ .description = "Has zero-cycle zeroing instructions",
+ .llvm_name = "zcz",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mvefp = Feature{
+ .name = "mve.fp",
+ .description = "Support M-Class Vector Extension with integer and floating ops",
+ .llvm_name = "mve.fp",
+ .subfeatures = &[_]*const Feature {
+ &feature_v7clrex,
+ &feature_thumb2,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_dsp,
+ &feature_perfmon,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_mve = Feature{
+ .name = "mve",
+ .description = "Support M-Class Vector Extension with integer ops",
+ .llvm_name = "mve",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_dsp,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_v4t = Feature{
+ .name = "v4t",
+ .description = "Support ARM v4T instructions",
+ .llvm_name = "v4t",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_v5te = Feature{
+ .name = "v5te",
+ .description = "Support ARM v5TE, v5TEj, and v5TExp instructions",
+ .llvm_name = "v5te",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ },
+};
+
+pub const feature_v5t = Feature{
+ .name = "v5t",
+ .description = "Support ARM v5T instructions",
+ .llvm_name = "v5t",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ },
+};
+
+pub const feature_v6k = Feature{
+ .name = "v6k",
+ .description = "Support ARM v6k instructions",
+ .llvm_name = "v6k",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ },
+};
+
+pub const feature_v6m = Feature{
+ .name = "v6m",
+ .description = "Support ARM v6M instructions",
+ .llvm_name = "v6m",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ },
+};
+
+pub const feature_v6 = Feature{
+ .name = "v6",
+ .description = "Support ARM v6 instructions",
+ .llvm_name = "v6",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ },
+};
+
+pub const feature_v6t2 = Feature{
+ .name = "v6t2",
+ .description = "Support ARM v6t2 instructions",
+ .llvm_name = "v6t2",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_thumb2,
+ },
+};
+
+pub const feature_v7 = Feature{
+ .name = "v7",
+ .description = "Support ARM v7 instructions",
+ .llvm_name = "v7",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_v7clrex,
+ &feature_perfmon,
+ &feature_thumb2,
+ },
+};
+
+pub const feature_v8m = Feature{
+ .name = "v8m",
+ .description = "Support ARM v8M Baseline instructions",
+ .llvm_name = "v8m",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ },
+};
+
+pub const feature_v8mmain = Feature{
+ .name = "v8m.main",
+ .description = "Support ARM v8M Mainline instructions",
+ .llvm_name = "v8m.main",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_thumb2,
+ },
+};
+
+pub const feature_v8 = Feature{
+ .name = "v8",
+ .description = "Support ARM v8 instructions",
+ .llvm_name = "v8",
+ .subfeatures = &[_]*const Feature {
+ &feature_acquireRelease,
+ &feature_v7clrex,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_perfmon,
+ },
+};
+
+pub const feature_v81mmain = Feature{
+ .name = "v8.1m.main",
+ .description = "Support ARM v8-1M Mainline instructions",
+ .llvm_name = "v8.1m.main",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_v7clrex,
+ &feature_perfmon,
+ &feature_thumb2,
+ },
+};
+
+pub const feature_v81a = Feature{
+ .name = "v8.1a",
+ .description = "Support ARM v8.1a instructions",
+ .llvm_name = "v8.1a",
+ .subfeatures = &[_]*const Feature {
+ &feature_acquireRelease,
+ &feature_v7clrex,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_perfmon,
+ },
+};
+
+pub const feature_v82a = Feature{
+ .name = "v8.2a",
+ .description = "Support ARM v8.2a instructions",
+ .llvm_name = "v8.2a",
+ .subfeatures = &[_]*const Feature {
+ &feature_acquireRelease,
+ &feature_v7clrex,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_perfmon,
+ },
+};
+
+pub const feature_v83a = Feature{
+ .name = "v8.3a",
+ .description = "Support ARM v8.3a instructions",
+ .llvm_name = "v8.3a",
+ .subfeatures = &[_]*const Feature {
+ &feature_acquireRelease,
+ &feature_v7clrex,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_perfmon,
+ },
+};
+
+pub const feature_v84a = Feature{
+ .name = "v8.4a",
+ .description = "Support ARM v8.4a instructions",
+ .llvm_name = "v8.4a",
+ .subfeatures = &[_]*const Feature {
+ &feature_acquireRelease,
+ &feature_v7clrex,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_d32,
+ &feature_perfmon,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_v85a = Feature{
+ .name = "v8.5a",
+ .description = "Support ARM v8.5a instructions",
+ .llvm_name = "v8.5a",
+ .subfeatures = &[_]*const Feature {
+ &feature_acquireRelease,
+ &feature_v7clrex,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_d32,
+ &feature_sb,
+ &feature_perfmon,
+ &feature_fpregs,
+ },
+};
+
+pub const feature_iwmmxt = Feature{
+ .name = "iwmmxt",
+ .description = "ARMv5te architecture",
+ .llvm_name = "iwmmxt",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ },
+};
+
+pub const feature_iwmmxt2 = Feature{
+ .name = "iwmmxt2",
+ .description = "ARMv5te architecture",
+ .llvm_name = "iwmmxt2",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ },
+};
+
+pub const feature_softFloat = Feature{
+ .name = "soft-float",
+ .description = "Use software floating point features.",
+ .llvm_name = "soft-float",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_thumbMode = Feature{
+ .name = "thumb-mode",
+ .description = "Thumb mode",
+ .llvm_name = "thumb-mode",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_a5 = Feature{
+ .name = "a5",
+ .description = "Cortex-A5 ARM processors",
+ .llvm_name = "a5",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_a7 = Feature{
+ .name = "a7",
+ .description = "Cortex-A7 ARM processors",
+ .llvm_name = "a7",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_a8 = Feature{
+ .name = "a8",
+ .description = "Cortex-A8 ARM processors",
+ .llvm_name = "a8",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_a9 = Feature{
+ .name = "a9",
+ .description = "Cortex-A9 ARM processors",
+ .llvm_name = "a9",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_a12 = Feature{
+ .name = "a12",
+ .description = "Cortex-A12 ARM processors",
+ .llvm_name = "a12",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_a15 = Feature{
+ .name = "a15",
+ .description = "Cortex-A15 ARM processors",
+ .llvm_name = "a15",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_a17 = Feature{
+ .name = "a17",
+ .description = "Cortex-A17 ARM processors",
+ .llvm_name = "a17",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_a32 = Feature{
+ .name = "a32",
+ .description = "Cortex-A32 ARM processors",
+ .llvm_name = "a32",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_a35 = Feature{
+ .name = "a35",
+ .description = "Cortex-A35 ARM processors",
+ .llvm_name = "a35",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_a53 = Feature{
+ .name = "a53",
+ .description = "Cortex-A53 ARM processors",
+ .llvm_name = "a53",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_a55 = Feature{
+ .name = "a55",
+ .description = "Cortex-A55 ARM processors",
+ .llvm_name = "a55",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_a57 = Feature{
+ .name = "a57",
+ .description = "Cortex-A57 ARM processors",
+ .llvm_name = "a57",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_a72 = Feature{
+ .name = "a72",
+ .description = "Cortex-A72 ARM processors",
+ .llvm_name = "a72",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_a73 = Feature{
+ .name = "a73",
+ .description = "Cortex-A73 ARM processors",
+ .llvm_name = "a73",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_a75 = Feature{
+ .name = "a75",
+ .description = "Cortex-A75 ARM processors",
+ .llvm_name = "a75",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_a76 = Feature{
+ .name = "a76",
+ .description = "Cortex-A76 ARM processors",
+ .llvm_name = "a76",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_exynos = Feature{
+ .name = "exynos",
+ .description = "Samsung Exynos processors",
+ .llvm_name = "exynos",
+ .subfeatures = &[_]*const Feature {
+ &feature_slowFpBrcc,
+ &feature_slowfpvmlx,
+ &feature_hwdiv,
+ &feature_slowVdup32,
+ &feature_wideStrideVfp,
+ &feature_fuseAes,
+ &feature_slowVgetlni32,
+ &feature_zcz,
+ &feature_profUnpr,
+ &feature_d32,
+ &feature_hwdivArm,
+ &feature_retAddrStack,
+ &feature_crc,
+ &feature_expandFpMlx,
+ &feature_useAa,
+ &feature_dontWidenVmovs,
+ &feature_fpregs,
+ &feature_fuseLiterals,
+ },
+};
+
+pub const feature_krait = Feature{
+ .name = "krait",
+ .description = "Qualcomm Krait processors",
+ .llvm_name = "krait",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_kryo = Feature{
+ .name = "kryo",
+ .description = "Qualcomm Kryo processors",
+ .llvm_name = "kryo",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_m3 = Feature{
+ .name = "m3",
+ .description = "Cortex-M3 ARM processors",
+ .llvm_name = "m3",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_r4 = Feature{
+ .name = "r4",
+ .description = "Cortex-R4 ARM processors",
+ .llvm_name = "r4",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_r5 = Feature{
+ .name = "r5",
+ .description = "Cortex-R5 ARM processors",
+ .llvm_name = "r5",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_r7 = Feature{
+ .name = "r7",
+ .description = "Cortex-R7 ARM processors",
+ .llvm_name = "r7",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_r52 = Feature{
+ .name = "r52",
+ .description = "Cortex-R52 ARM processors",
+ .llvm_name = "r52",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_swift = Feature{
+ .name = "swift",
+ .description = "Swift ARM processors",
+ .llvm_name = "swift",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_xscale = Feature{
+ .name = "xscale",
+ .description = "ARMv5te architecture",
+ .llvm_name = "xscale",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ },
+};
+
+pub const features = &[_]*const Feature {
+ &feature_armv2,
+ &feature_armv2a,
+ &feature_armv3,
+ &feature_armv3m,
+ &feature_armv4,
+ &feature_armv4t,
+ &feature_armv5t,
+ &feature_armv5te,
+ &feature_armv5tej,
+ &feature_armv6,
+ &feature_armv6j,
+ &feature_armv6k,
+ &feature_armv6kz,
+ &feature_armv6M,
+ &feature_armv6sM,
+ &feature_armv6t2,
+ &feature_armv7A,
+ &feature_armv7eM,
+ &feature_armv7k,
+ &feature_armv7M,
+ &feature_armv7R,
+ &feature_armv7s,
+ &feature_armv7ve,
+ &feature_armv8A,
+ &feature_armv8Mbase,
+ &feature_armv8Mmain,
+ &feature_armv8R,
+ &feature_armv81A,
+ &feature_armv81Mmain,
+ &feature_armv82A,
+ &feature_armv83A,
+ &feature_armv84A,
+ &feature_armv85A,
+ &feature_msecext8,
+ &feature_aclass,
+ &feature_aes,
+ &feature_acquireRelease,
+ &feature_avoidMovsShop,
+ &feature_avoidPartialCpsr,
+ &feature_crc,
+ &feature_cheapPredicableCpsr,
+ &feature_vldnAlign,
+ &feature_crypto,
+ &feature_d32,
+ &feature_db,
+ &feature_dfb,
+ &feature_dsp,
+ &feature_dontWidenVmovs,
+ &feature_dotprod,
+ &feature_executeOnly,
+ &feature_expandFpMlx,
+ &feature_fp16,
+ &feature_fp16fml,
+ &feature_fp64,
+ &feature_fpao,
+ &feature_fpArmv8,
+ &feature_fpArmv8d16,
+ &feature_fpArmv8d16sp,
+ &feature_fpArmv8sp,
+ &feature_fpregs,
+ &feature_fpregs16,
+ &feature_fpregs64,
+ &feature_fullfp16,
+ &feature_fuseAes,
+ &feature_fuseLiterals,
+ &feature_hwdivArm,
+ &feature_hwdiv,
+ &feature_noBranchPredictor,
+ &feature_retAddrStack,
+ &feature_slowfpvmlx,
+ &feature_vmlxHazards,
+ &feature_lob,
+ &feature_longCalls,
+ &feature_mclass,
+ &feature_mp,
+ &feature_mve1beat,
+ &feature_mve2beat,
+ &feature_mve4beat,
+ &feature_muxedUnits,
+ &feature_neon,
+ &feature_neonfp,
+ &feature_neonFpmovs,
+ &feature_naclTrap,
+ &feature_noarm,
+ &feature_noMovt,
+ &feature_noNegImmediates,
+ &feature_disablePostraScheduler,
+ &feature_nonpipelinedVfp,
+ &feature_perfmon,
+ &feature_bit32,
+ &feature_preferIshst,
+ &feature_loopAlign,
+ &feature_preferVmovsr,
+ &feature_profUnpr,
+ &feature_ras,
+ &feature_rclass,
+ &feature_readTpHard,
+ &feature_reserveR9,
+ &feature_sb,
+ &feature_sha2,
+ &feature_slowFpBrcc,
+ &feature_slowLoadDSubreg,
+ &feature_slowOddReg,
+ &feature_slowVdup32,
+ &feature_slowVgetlni32,
+ &feature_splatVfpNeon,
+ &feature_strictAlign,
+ &feature_thumb2,
+ &feature_trustzone,
+ &feature_useAa,
+ &feature_useMisched,
+ &feature_wideStrideVfp,
+ &feature_v7clrex,
+ &feature_vfp2,
+ &feature_vfp2sp,
+ &feature_vfp3,
+ &feature_vfp3d16,
+ &feature_vfp3d16sp,
+ &feature_vfp3sp,
+ &feature_vfp4,
+ &feature_vfp4d16,
+ &feature_vfp4d16sp,
+ &feature_vfp4sp,
+ &feature_vmlxForwarding,
+ &feature_virtualization,
+ &feature_zcz,
+ &feature_mvefp,
+ &feature_mve,
+ &feature_v4t,
+ &feature_v5te,
+ &feature_v5t,
+ &feature_v6k,
+ &feature_v6m,
+ &feature_v6,
+ &feature_v6t2,
+ &feature_v7,
+ &feature_v8m,
+ &feature_v8mmain,
+ &feature_v8,
+ &feature_v81mmain,
+ &feature_v81a,
+ &feature_v82a,
+ &feature_v83a,
+ &feature_v84a,
+ &feature_v85a,
+ &feature_iwmmxt,
+ &feature_iwmmxt2,
+ &feature_softFloat,
+ &feature_thumbMode,
+ &feature_a5,
+ &feature_a7,
+ &feature_a8,
+ &feature_a9,
+ &feature_a12,
+ &feature_a15,
+ &feature_a17,
+ &feature_a32,
+ &feature_a35,
+ &feature_a53,
+ &feature_a55,
+ &feature_a57,
+ &feature_a72,
+ &feature_a73,
+ &feature_a75,
+ &feature_a76,
+ &feature_exynos,
+ &feature_krait,
+ &feature_kryo,
+ &feature_m3,
+ &feature_r4,
+ &feature_r5,
+ &feature_r7,
+ &feature_r52,
+ &feature_swift,
+ &feature_xscale,
+};
+
+pub const cpu_arm1020e = Cpu{
+ .name = "arm1020e",
+ .llvm_name = "arm1020e",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv5te,
+ },
+};
+
+pub const cpu_arm1020t = Cpu{
+ .name = "arm1020t",
+ .llvm_name = "arm1020t",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv5t,
+ },
+};
+
+pub const cpu_arm1022e = Cpu{
+ .name = "arm1022e",
+ .llvm_name = "arm1022e",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv5te,
+ },
+};
+
+pub const cpu_arm10e = Cpu{
+ .name = "arm10e",
+ .llvm_name = "arm10e",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv5te,
+ },
+};
+
+pub const cpu_arm10tdmi = Cpu{
+ .name = "arm10tdmi",
+ .llvm_name = "arm10tdmi",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv5t,
+ },
+};
+
+pub const cpu_arm1136jS = Cpu{
+ .name = "arm1136j-s",
+ .llvm_name = "arm1136j-s",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_dsp,
+ &feature_armv6,
+ },
+};
+
+pub const cpu_arm1136jfS = Cpu{
+ .name = "arm1136jf-s",
+ .llvm_name = "arm1136jf-s",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_dsp,
+ &feature_armv6,
+ &feature_slowfpvmlx,
+ &feature_fpregs,
+ &feature_vfp2,
+ },
+};
+
+pub const cpu_arm1156t2S = Cpu{
+ .name = "arm1156t2-s",
+ .llvm_name = "arm1156t2-s",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_dsp,
+ &feature_thumb2,
+ &feature_armv6t2,
+ },
+};
+
+pub const cpu_arm1156t2fS = Cpu{
+ .name = "arm1156t2f-s",
+ .llvm_name = "arm1156t2f-s",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_dsp,
+ &feature_thumb2,
+ &feature_armv6t2,
+ &feature_slowfpvmlx,
+ &feature_fpregs,
+ &feature_vfp2,
+ },
+};
+
+pub const cpu_arm1176jS = Cpu{
+ .name = "arm1176j-s",
+ .llvm_name = "arm1176j-s",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_trustzone,
+ &feature_armv6kz,
+ },
+};
+
+pub const cpu_arm1176jzS = Cpu{
+ .name = "arm1176jz-s",
+ .llvm_name = "arm1176jz-s",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_trustzone,
+ &feature_armv6kz,
+ },
+};
+
+pub const cpu_arm1176jzfS = Cpu{
+ .name = "arm1176jzf-s",
+ .llvm_name = "arm1176jzf-s",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_trustzone,
+ &feature_armv6kz,
+ &feature_slowfpvmlx,
+ &feature_fpregs,
+ &feature_vfp2,
+ },
+};
+
+pub const cpu_arm710t = Cpu{
+ .name = "arm710t",
+ .llvm_name = "arm710t",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv4t,
+ },
+};
+
+pub const cpu_arm720t = Cpu{
+ .name = "arm720t",
+ .llvm_name = "arm720t",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv4t,
+ },
+};
+
+pub const cpu_arm7tdmi = Cpu{
+ .name = "arm7tdmi",
+ .llvm_name = "arm7tdmi",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv4t,
+ },
+};
+
+pub const cpu_arm7tdmiS = Cpu{
+ .name = "arm7tdmi-s",
+ .llvm_name = "arm7tdmi-s",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv4t,
+ },
+};
+
+pub const cpu_arm8 = Cpu{
+ .name = "arm8",
+ .llvm_name = "arm8",
+ .subfeatures = &[_]*const Feature {
+ &feature_armv4,
+ },
+};
+
+pub const cpu_arm810 = Cpu{
+ .name = "arm810",
+ .llvm_name = "arm810",
+ .subfeatures = &[_]*const Feature {
+ &feature_armv4,
+ },
+};
+
+pub const cpu_arm9 = Cpu{
+ .name = "arm9",
+ .llvm_name = "arm9",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv4t,
+ },
+};
+
+pub const cpu_arm920 = Cpu{
+ .name = "arm920",
+ .llvm_name = "arm920",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv4t,
+ },
+};
+
+pub const cpu_arm920t = Cpu{
+ .name = "arm920t",
+ .llvm_name = "arm920t",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv4t,
+ },
+};
+
+pub const cpu_arm922t = Cpu{
+ .name = "arm922t",
+ .llvm_name = "arm922t",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv4t,
+ },
+};
+
+pub const cpu_arm926ejS = Cpu{
+ .name = "arm926ej-s",
+ .llvm_name = "arm926ej-s",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv5te,
+ },
+};
+
+pub const cpu_arm940t = Cpu{
+ .name = "arm940t",
+ .llvm_name = "arm940t",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv4t,
+ },
+};
+
+pub const cpu_arm946eS = Cpu{
+ .name = "arm946e-s",
+ .llvm_name = "arm946e-s",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv5te,
+ },
+};
+
+pub const cpu_arm966eS = Cpu{
+ .name = "arm966e-s",
+ .llvm_name = "arm966e-s",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv5te,
+ },
+};
+
+pub const cpu_arm968eS = Cpu{
+ .name = "arm968e-s",
+ .llvm_name = "arm968e-s",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv5te,
+ },
+};
+
+pub const cpu_arm9e = Cpu{
+ .name = "arm9e",
+ .llvm_name = "arm9e",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv5te,
+ },
+};
+
+pub const cpu_arm9tdmi = Cpu{
+ .name = "arm9tdmi",
+ .llvm_name = "arm9tdmi",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv4t,
+ },
+};
+
+pub const cpu_cortexA12 = Cpu{
+ .name = "cortex-a12",
+ .llvm_name = "cortex-a12",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv7A,
+ &feature_avoidPartialCpsr,
+ &feature_retAddrStack,
+ &feature_mp,
+ &feature_trustzone,
+ &feature_fp16,
+ &feature_vfp4,
+ &feature_vmlxForwarding,
+ &feature_hwdiv,
+ &feature_hwdivArm,
+ &feature_virtualization,
+ &feature_a12,
+ },
+};
+
+pub const cpu_cortexA15 = Cpu{
+ .name = "cortex-a15",
+ .llvm_name = "cortex-a15",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv7A,
+ &feature_avoidPartialCpsr,
+ &feature_vldnAlign,
+ &feature_dontWidenVmovs,
+ &feature_retAddrStack,
+ &feature_mp,
+ &feature_muxedUnits,
+ &feature_splatVfpNeon,
+ &feature_trustzone,
+ &feature_fp16,
+ &feature_vfp4,
+ &feature_hwdiv,
+ &feature_hwdivArm,
+ &feature_virtualization,
+ &feature_a15,
+ },
+};
+
+pub const cpu_cortexA17 = Cpu{
+ .name = "cortex-a17",
+ .llvm_name = "cortex-a17",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv7A,
+ &feature_avoidPartialCpsr,
+ &feature_retAddrStack,
+ &feature_mp,
+ &feature_trustzone,
+ &feature_fp16,
+ &feature_vfp4,
+ &feature_vmlxForwarding,
+ &feature_hwdiv,
+ &feature_hwdivArm,
+ &feature_virtualization,
+ &feature_a17,
+ },
+};
+
+pub const cpu_cortexA32 = Cpu{
+ .name = "cortex-a32",
+ .llvm_name = "cortex-a32",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv8A,
+ &feature_crypto,
+ },
+};
+
+pub const cpu_cortexA35 = Cpu{
+ .name = "cortex-a35",
+ .llvm_name = "cortex-a35",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv8A,
+ &feature_crypto,
+ &feature_a35,
+ },
+};
+
+pub const cpu_cortexA5 = Cpu{
+ .name = "cortex-a5",
+ .llvm_name = "cortex-a5",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv7A,
+ &feature_retAddrStack,
+ &feature_slowfpvmlx,
+ &feature_mp,
+ &feature_slowFpBrcc,
+ &feature_trustzone,
+ &feature_fp16,
+ &feature_vfp4,
+ &feature_vmlxForwarding,
+ &feature_a5,
+ },
+};
+
+pub const cpu_cortexA53 = Cpu{
+ .name = "cortex-a53",
+ .llvm_name = "cortex-a53",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv8A,
+ &feature_crypto,
+ &feature_fpao,
+ &feature_a53,
+ },
+};
+
+pub const cpu_cortexA55 = Cpu{
+ .name = "cortex-a55",
+ .llvm_name = "cortex-a55",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_ras,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv82A,
+ &feature_dotprod,
+ &feature_a55,
+ },
+};
+
+pub const cpu_cortexA57 = Cpu{
+ .name = "cortex-a57",
+ .llvm_name = "cortex-a57",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv8A,
+ &feature_avoidPartialCpsr,
+ &feature_cheapPredicableCpsr,
+ &feature_crypto,
+ &feature_fpao,
+ &feature_a57,
+ },
+};
+
+pub const cpu_cortexA7 = Cpu{
+ .name = "cortex-a7",
+ .llvm_name = "cortex-a7",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv7A,
+ &feature_retAddrStack,
+ &feature_slowfpvmlx,
+ &feature_vmlxHazards,
+ &feature_mp,
+ &feature_slowFpBrcc,
+ &feature_trustzone,
+ &feature_fp16,
+ &feature_vfp4,
+ &feature_vmlxForwarding,
+ &feature_hwdiv,
+ &feature_hwdivArm,
+ &feature_virtualization,
+ &feature_a7,
+ },
+};
+
+pub const cpu_cortexA72 = Cpu{
+ .name = "cortex-a72",
+ .llvm_name = "cortex-a72",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv8A,
+ &feature_crypto,
+ &feature_a72,
+ },
+};
+
+pub const cpu_cortexA73 = Cpu{
+ .name = "cortex-a73",
+ .llvm_name = "cortex-a73",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv8A,
+ &feature_crypto,
+ &feature_a73,
+ },
+};
+
+pub const cpu_cortexA75 = Cpu{
+ .name = "cortex-a75",
+ .llvm_name = "cortex-a75",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_ras,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv82A,
+ &feature_dotprod,
+ &feature_a75,
+ },
+};
+
+pub const cpu_cortexA76 = Cpu{
+ .name = "cortex-a76",
+ .llvm_name = "cortex-a76",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_ras,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv82A,
+ &feature_crypto,
+ &feature_dotprod,
+ &feature_fullfp16,
+ &feature_a76,
+ },
+};
+
+pub const cpu_cortexA76ae = Cpu{
+ .name = "cortex-a76ae",
+ .llvm_name = "cortex-a76ae",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_ras,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv82A,
+ &feature_crypto,
+ &feature_dotprod,
+ &feature_fullfp16,
+ &feature_a76,
+ },
+};
+
+pub const cpu_cortexA8 = Cpu{
+ .name = "cortex-a8",
+ .llvm_name = "cortex-a8",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv7A,
+ &feature_retAddrStack,
+ &feature_slowfpvmlx,
+ &feature_vmlxHazards,
+ &feature_nonpipelinedVfp,
+ &feature_slowFpBrcc,
+ &feature_trustzone,
+ &feature_vmlxForwarding,
+ &feature_a8,
+ },
+};
+
+pub const cpu_cortexA9 = Cpu{
+ .name = "cortex-a9",
+ .llvm_name = "cortex-a9",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv7A,
+ &feature_avoidPartialCpsr,
+ &feature_vldnAlign,
+ &feature_expandFpMlx,
+ &feature_fp16,
+ &feature_retAddrStack,
+ &feature_vmlxHazards,
+ &feature_mp,
+ &feature_muxedUnits,
+ &feature_neonFpmovs,
+ &feature_preferVmovsr,
+ &feature_trustzone,
+ &feature_vmlxForwarding,
+ &feature_a9,
+ },
+};
+
+pub const cpu_cortexM0 = Cpu{
+ .name = "cortex-m0",
+ .llvm_name = "cortex-m0",
+ .subfeatures = &[_]*const Feature {
+ &feature_db,
+ &feature_thumbMode,
+ &feature_mclass,
+ &feature_noarm,
+ &feature_v4t,
+ &feature_strictAlign,
+ &feature_armv6M,
+ },
+};
+
+pub const cpu_cortexM0plus = Cpu{
+ .name = "cortex-m0plus",
+ .llvm_name = "cortex-m0plus",
+ .subfeatures = &[_]*const Feature {
+ &feature_db,
+ &feature_thumbMode,
+ &feature_mclass,
+ &feature_noarm,
+ &feature_v4t,
+ &feature_strictAlign,
+ &feature_armv6M,
+ },
+};
+
+pub const cpu_cortexM1 = Cpu{
+ .name = "cortex-m1",
+ .llvm_name = "cortex-m1",
+ .subfeatures = &[_]*const Feature {
+ &feature_db,
+ &feature_thumbMode,
+ &feature_mclass,
+ &feature_noarm,
+ &feature_v4t,
+ &feature_strictAlign,
+ &feature_armv6M,
+ },
+};
+
+pub const cpu_cortexM23 = Cpu{
+ .name = "cortex-m23",
+ .llvm_name = "cortex-m23",
+ .subfeatures = &[_]*const Feature {
+ &feature_acquireRelease,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_msecext8,
+ &feature_thumbMode,
+ &feature_mclass,
+ &feature_noarm,
+ &feature_v4t,
+ &feature_strictAlign,
+ &feature_hwdiv,
+ &feature_armv8Mbase,
+ &feature_noMovt,
+ },
+};
+
+pub const cpu_cortexM3 = Cpu{
+ .name = "cortex-m3",
+ .llvm_name = "cortex-m3",
+ .subfeatures = &[_]*const Feature {
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_mclass,
+ &feature_thumbMode,
+ &feature_noarm,
+ &feature_v4t,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_armv7M,
+ &feature_noBranchPredictor,
+ &feature_loopAlign,
+ &feature_useAa,
+ &feature_useMisched,
+ &feature_m3,
+ },
+};
+
+pub const cpu_cortexM33 = Cpu{
+ .name = "cortex-m33",
+ .llvm_name = "cortex-m33",
+ .subfeatures = &[_]*const Feature {
+ &feature_acquireRelease,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_msecext8,
+ &feature_thumb2,
+ &feature_mclass,
+ &feature_thumbMode,
+ &feature_noarm,
+ &feature_v4t,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_armv8Mmain,
+ &feature_dsp,
+ &feature_fp16,
+ &feature_fpregs,
+ &feature_fpArmv8d16sp,
+ &feature_noBranchPredictor,
+ &feature_slowfpvmlx,
+ &feature_loopAlign,
+ &feature_useAa,
+ &feature_useMisched,
+ },
+};
+
+pub const cpu_cortexM35p = Cpu{
+ .name = "cortex-m35p",
+ .llvm_name = "cortex-m35p",
+ .subfeatures = &[_]*const Feature {
+ &feature_acquireRelease,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_msecext8,
+ &feature_thumb2,
+ &feature_mclass,
+ &feature_thumbMode,
+ &feature_noarm,
+ &feature_v4t,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_armv8Mmain,
+ &feature_dsp,
+ &feature_fp16,
+ &feature_fpregs,
+ &feature_fpArmv8d16sp,
+ &feature_noBranchPredictor,
+ &feature_slowfpvmlx,
+ &feature_loopAlign,
+ &feature_useAa,
+ &feature_useMisched,
+ },
+};
+
+pub const cpu_cortexM4 = Cpu{
+ .name = "cortex-m4",
+ .llvm_name = "cortex-m4",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_mclass,
+ &feature_thumbMode,
+ &feature_noarm,
+ &feature_v4t,
+ &feature_dsp,
+ &feature_hwdiv,
+ &feature_armv7eM,
+ &feature_noBranchPredictor,
+ &feature_slowfpvmlx,
+ &feature_loopAlign,
+ &feature_useAa,
+ &feature_useMisched,
+ &feature_fp16,
+ &feature_fpregs,
+ &feature_vfp4d16sp,
+ },
+};
+
+pub const cpu_cortexM7 = Cpu{
+ .name = "cortex-m7",
+ .llvm_name = "cortex-m7",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_mclass,
+ &feature_thumbMode,
+ &feature_noarm,
+ &feature_v4t,
+ &feature_dsp,
+ &feature_hwdiv,
+ &feature_armv7eM,
+ &feature_fp16,
+ &feature_fpregs,
+ &feature_fpArmv8d16,
+ },
+};
+
+pub const cpu_cortexR4 = Cpu{
+ .name = "cortex-r4",
+ .llvm_name = "cortex-r4",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_dsp,
+ &feature_hwdiv,
+ &feature_rclass,
+ &feature_armv7R,
+ &feature_avoidPartialCpsr,
+ &feature_retAddrStack,
+ &feature_r4,
+ },
+};
+
+pub const cpu_cortexR4f = Cpu{
+ .name = "cortex-r4f",
+ .llvm_name = "cortex-r4f",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_dsp,
+ &feature_hwdiv,
+ &feature_rclass,
+ &feature_armv7R,
+ &feature_avoidPartialCpsr,
+ &feature_retAddrStack,
+ &feature_slowfpvmlx,
+ &feature_slowFpBrcc,
+ &feature_fpregs,
+ &feature_vfp3d16,
+ &feature_r4,
+ },
+};
+
+pub const cpu_cortexR5 = Cpu{
+ .name = "cortex-r5",
+ .llvm_name = "cortex-r5",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_dsp,
+ &feature_hwdiv,
+ &feature_rclass,
+ &feature_armv7R,
+ &feature_avoidPartialCpsr,
+ &feature_hwdivArm,
+ &feature_retAddrStack,
+ &feature_slowfpvmlx,
+ &feature_slowFpBrcc,
+ &feature_fpregs,
+ &feature_vfp3d16,
+ &feature_r5,
+ },
+};
+
+pub const cpu_cortexR52 = Cpu{
+ .name = "cortex-r52",
+ .llvm_name = "cortex-r52",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_dfb,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_rclass,
+ &feature_armv8R,
+ &feature_fpao,
+ &feature_useAa,
+ &feature_useMisched,
+ &feature_r52,
+ },
+};
+
+pub const cpu_cortexR7 = Cpu{
+ .name = "cortex-r7",
+ .llvm_name = "cortex-r7",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_dsp,
+ &feature_hwdiv,
+ &feature_rclass,
+ &feature_armv7R,
+ &feature_avoidPartialCpsr,
+ &feature_fp16,
+ &feature_hwdivArm,
+ &feature_retAddrStack,
+ &feature_slowfpvmlx,
+ &feature_mp,
+ &feature_slowFpBrcc,
+ &feature_fpregs,
+ &feature_vfp3d16,
+ &feature_r7,
+ },
+};
+
+pub const cpu_cortexR8 = Cpu{
+ .name = "cortex-r8",
+ .llvm_name = "cortex-r8",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_dsp,
+ &feature_hwdiv,
+ &feature_rclass,
+ &feature_armv7R,
+ &feature_avoidPartialCpsr,
+ &feature_fp16,
+ &feature_hwdivArm,
+ &feature_retAddrStack,
+ &feature_slowfpvmlx,
+ &feature_mp,
+ &feature_slowFpBrcc,
+ &feature_fpregs,
+ &feature_vfp3d16,
+ },
+};
+
+pub const cpu_cyclone = Cpu{
+ .name = "cyclone",
+ .llvm_name = "cyclone",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv8A,
+ &feature_avoidMovsShop,
+ &feature_avoidPartialCpsr,
+ &feature_crypto,
+ &feature_retAddrStack,
+ &feature_slowfpvmlx,
+ &feature_neonfp,
+ &feature_disablePostraScheduler,
+ &feature_useMisched,
+ &feature_vfp4,
+ &feature_zcz,
+ &feature_swift,
+ },
+};
+
+pub const cpu_ep9312 = Cpu{
+ .name = "ep9312",
+ .llvm_name = "ep9312",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv4t,
+ },
+};
+
+pub const cpu_exynosM1 = Cpu{
+ .name = "exynos-m1",
+ .llvm_name = "exynos-m1",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv8A,
+ &feature_slowFpBrcc,
+ &feature_slowfpvmlx,
+ &feature_slowVdup32,
+ &feature_wideStrideVfp,
+ &feature_fuseAes,
+ &feature_slowVgetlni32,
+ &feature_zcz,
+ &feature_profUnpr,
+ &feature_retAddrStack,
+ &feature_expandFpMlx,
+ &feature_useAa,
+ &feature_dontWidenVmovs,
+ &feature_fuseLiterals,
+ &feature_exynos,
+ },
+};
+
+pub const cpu_exynosM2 = Cpu{
+ .name = "exynos-m2",
+ .llvm_name = "exynos-m2",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv8A,
+ &feature_slowFpBrcc,
+ &feature_slowfpvmlx,
+ &feature_slowVdup32,
+ &feature_wideStrideVfp,
+ &feature_fuseAes,
+ &feature_slowVgetlni32,
+ &feature_zcz,
+ &feature_profUnpr,
+ &feature_retAddrStack,
+ &feature_expandFpMlx,
+ &feature_useAa,
+ &feature_dontWidenVmovs,
+ &feature_fuseLiterals,
+ &feature_exynos,
+ },
+};
+
+pub const cpu_exynosM3 = Cpu{
+ .name = "exynos-m3",
+ .llvm_name = "exynos-m3",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv8A,
+ &feature_slowFpBrcc,
+ &feature_slowfpvmlx,
+ &feature_slowVdup32,
+ &feature_wideStrideVfp,
+ &feature_fuseAes,
+ &feature_slowVgetlni32,
+ &feature_zcz,
+ &feature_profUnpr,
+ &feature_retAddrStack,
+ &feature_expandFpMlx,
+ &feature_useAa,
+ &feature_dontWidenVmovs,
+ &feature_fuseLiterals,
+ &feature_exynos,
+ },
+};
+
+pub const cpu_exynosM4 = Cpu{
+ .name = "exynos-m4",
+ .llvm_name = "exynos-m4",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_ras,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv82A,
+ &feature_dotprod,
+ &feature_fullfp16,
+ &feature_slowFpBrcc,
+ &feature_slowfpvmlx,
+ &feature_slowVdup32,
+ &feature_wideStrideVfp,
+ &feature_fuseAes,
+ &feature_slowVgetlni32,
+ &feature_zcz,
+ &feature_profUnpr,
+ &feature_retAddrStack,
+ &feature_expandFpMlx,
+ &feature_useAa,
+ &feature_dontWidenVmovs,
+ &feature_fuseLiterals,
+ &feature_exynos,
+ },
+};
+
+pub const cpu_exynosM5 = Cpu{
+ .name = "exynos-m5",
+ .llvm_name = "exynos-m5",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_ras,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv82A,
+ &feature_dotprod,
+ &feature_fullfp16,
+ &feature_slowFpBrcc,
+ &feature_slowfpvmlx,
+ &feature_slowVdup32,
+ &feature_wideStrideVfp,
+ &feature_fuseAes,
+ &feature_slowVgetlni32,
+ &feature_zcz,
+ &feature_profUnpr,
+ &feature_retAddrStack,
+ &feature_expandFpMlx,
+ &feature_useAa,
+ &feature_dontWidenVmovs,
+ &feature_fuseLiterals,
+ &feature_exynos,
+ },
+};
+
+pub const cpu_generic = Cpu{
+ .name = "generic",
+ .llvm_name = "generic",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_iwmmxt = Cpu{
+ .name = "iwmmxt",
+ .llvm_name = "iwmmxt",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv5te,
+ },
+};
+
+pub const cpu_krait = Cpu{
+ .name = "krait",
+ .llvm_name = "krait",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv7A,
+ &feature_avoidPartialCpsr,
+ &feature_vldnAlign,
+ &feature_fp16,
+ &feature_hwdivArm,
+ &feature_hwdiv,
+ &feature_retAddrStack,
+ &feature_muxedUnits,
+ &feature_vfp4,
+ &feature_vmlxForwarding,
+ &feature_krait,
+ },
+};
+
+pub const cpu_kryo = Cpu{
+ .name = "kryo",
+ .llvm_name = "kryo",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv8A,
+ &feature_crypto,
+ &feature_kryo,
+ },
+};
+
+pub const cpu_mpcore = Cpu{
+ .name = "mpcore",
+ .llvm_name = "mpcore",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv6k,
+ &feature_slowfpvmlx,
+ &feature_fpregs,
+ &feature_vfp2,
+ },
+};
+
+pub const cpu_mpcorenovfp = Cpu{
+ .name = "mpcorenovfp",
+ .llvm_name = "mpcorenovfp",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv6k,
+ },
+};
+
+pub const cpu_neoverseN1 = Cpu{
+ .name = "neoverse-n1",
+ .llvm_name = "neoverse-n1",
+ .subfeatures = &[_]*const Feature {
+ &feature_mp,
+ &feature_acquireRelease,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_trustzone,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_ras,
+ &feature_fp16,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_hwdivArm,
+ &feature_crc,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv82A,
+ &feature_crypto,
+ &feature_dotprod,
+ },
+};
+
+pub const cpu_sc000 = Cpu{
+ .name = "sc000",
+ .llvm_name = "sc000",
+ .subfeatures = &[_]*const Feature {
+ &feature_db,
+ &feature_thumbMode,
+ &feature_mclass,
+ &feature_noarm,
+ &feature_v4t,
+ &feature_strictAlign,
+ &feature_armv6M,
+ },
+};
+
+pub const cpu_sc300 = Cpu{
+ .name = "sc300",
+ .llvm_name = "sc300",
+ .subfeatures = &[_]*const Feature {
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_mclass,
+ &feature_thumbMode,
+ &feature_noarm,
+ &feature_v4t,
+ &feature_perfmon,
+ &feature_hwdiv,
+ &feature_armv7M,
+ &feature_noBranchPredictor,
+ &feature_useAa,
+ &feature_useMisched,
+ &feature_m3,
+ },
+};
+
+pub const cpu_strongarm = Cpu{
+ .name = "strongarm",
+ .llvm_name = "strongarm",
+ .subfeatures = &[_]*const Feature {
+ &feature_armv4,
+ },
+};
+
+pub const cpu_strongarm110 = Cpu{
+ .name = "strongarm110",
+ .llvm_name = "strongarm110",
+ .subfeatures = &[_]*const Feature {
+ &feature_armv4,
+ },
+};
+
+pub const cpu_strongarm1100 = Cpu{
+ .name = "strongarm1100",
+ .llvm_name = "strongarm1100",
+ .subfeatures = &[_]*const Feature {
+ &feature_armv4,
+ },
+};
+
+pub const cpu_strongarm1110 = Cpu{
+ .name = "strongarm1110",
+ .llvm_name = "strongarm1110",
+ .subfeatures = &[_]*const Feature {
+ &feature_armv4,
+ },
+};
+
+pub const cpu_swift = Cpu{
+ .name = "swift",
+ .llvm_name = "swift",
+ .subfeatures = &[_]*const Feature {
+ &feature_perfmon,
+ &feature_v7clrex,
+ &feature_db,
+ &feature_thumb2,
+ &feature_v4t,
+ &feature_d32,
+ &feature_aclass,
+ &feature_dsp,
+ &feature_fpregs,
+ &feature_armv7A,
+ &feature_avoidMovsShop,
+ &feature_avoidPartialCpsr,
+ &feature_hwdivArm,
+ &feature_hwdiv,
+ &feature_retAddrStack,
+ &feature_slowfpvmlx,
+ &feature_vmlxHazards,
+ &feature_mp,
+ &feature_neonfp,
+ &feature_disablePostraScheduler,
+ &feature_preferIshst,
+ &feature_profUnpr,
+ &feature_slowLoadDSubreg,
+ &feature_slowOddReg,
+ &feature_slowVdup32,
+ &feature_slowVgetlni32,
+ &feature_useMisched,
+ &feature_wideStrideVfp,
+ &feature_fp16,
+ &feature_vfp4,
+ &feature_swift,
+ },
+};
+
+pub const cpu_xscale = Cpu{
+ .name = "xscale",
+ .llvm_name = "xscale",
+ .subfeatures = &[_]*const Feature {
+ &feature_v4t,
+ &feature_armv5te,
+ },
+};
+
+pub const cpus = &[_]*const Cpu {
+ &cpu_arm1020e,
+ &cpu_arm1020t,
+ &cpu_arm1022e,
+ &cpu_arm10e,
+ &cpu_arm10tdmi,
+ &cpu_arm1136jS,
+ &cpu_arm1136jfS,
+ &cpu_arm1156t2S,
+ &cpu_arm1156t2fS,
+ &cpu_arm1176jS,
+ &cpu_arm1176jzS,
+ &cpu_arm1176jzfS,
+ &cpu_arm710t,
+ &cpu_arm720t,
+ &cpu_arm7tdmi,
+ &cpu_arm7tdmiS,
+ &cpu_arm8,
+ &cpu_arm810,
+ &cpu_arm9,
+ &cpu_arm920,
+ &cpu_arm920t,
+ &cpu_arm922t,
+ &cpu_arm926ejS,
+ &cpu_arm940t,
+ &cpu_arm946eS,
+ &cpu_arm966eS,
+ &cpu_arm968eS,
+ &cpu_arm9e,
+ &cpu_arm9tdmi,
+ &cpu_cortexA12,
+ &cpu_cortexA15,
+ &cpu_cortexA17,
+ &cpu_cortexA32,
+ &cpu_cortexA35,
+ &cpu_cortexA5,
+ &cpu_cortexA53,
+ &cpu_cortexA55,
+ &cpu_cortexA57,
+ &cpu_cortexA7,
+ &cpu_cortexA72,
+ &cpu_cortexA73,
+ &cpu_cortexA75,
+ &cpu_cortexA76,
+ &cpu_cortexA76ae,
+ &cpu_cortexA8,
+ &cpu_cortexA9,
+ &cpu_cortexM0,
+ &cpu_cortexM0plus,
+ &cpu_cortexM1,
+ &cpu_cortexM23,
+ &cpu_cortexM3,
+ &cpu_cortexM33,
+ &cpu_cortexM35p,
+ &cpu_cortexM4,
+ &cpu_cortexM7,
+ &cpu_cortexR4,
+ &cpu_cortexR4f,
+ &cpu_cortexR5,
+ &cpu_cortexR52,
+ &cpu_cortexR7,
+ &cpu_cortexR8,
+ &cpu_cyclone,
+ &cpu_ep9312,
+ &cpu_exynosM1,
+ &cpu_exynosM2,
+ &cpu_exynosM3,
+ &cpu_exynosM4,
+ &cpu_exynosM5,
+ &cpu_generic,
+ &cpu_iwmmxt,
+ &cpu_krait,
+ &cpu_kryo,
+ &cpu_mpcore,
+ &cpu_mpcorenovfp,
+ &cpu_neoverseN1,
+ &cpu_sc000,
+ &cpu_sc300,
+ &cpu_strongarm,
+ &cpu_strongarm110,
+ &cpu_strongarm1100,
+ &cpu_strongarm1110,
+ &cpu_swift,
+ &cpu_xscale,
+};
lib/std/target/avr.zig
@@ -0,0 +1,5578 @@
+const Feature = @import("std").target.Feature;
+const Cpu = @import("std").target.Cpu;
+
+pub const feature_avr0 = Feature{
+ .name = "avr0",
+ .description = "The device is a part of the avr0 family",
+ .llvm_name = "avr0",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_avr1 = Feature{
+ .name = "avr1",
+ .description = "The device is a part of the avr1 family",
+ .llvm_name = "avr1",
+ .subfeatures = &[_]*const Feature {
+ &feature_avr0,
+ &feature_lpm,
+ },
+};
+
+pub const feature_avr2 = Feature{
+ .name = "avr2",
+ .description = "The device is a part of the avr2 family",
+ .llvm_name = "avr2",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ },
+};
+
+pub const feature_avr3 = Feature{
+ .name = "avr3",
+ .description = "The device is a part of the avr3 family",
+ .llvm_name = "avr3",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ },
+};
+
+pub const feature_avr4 = Feature{
+ .name = "avr4",
+ .description = "The device is a part of the avr4 family",
+ .llvm_name = "avr4",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ },
+};
+
+pub const feature_avr5 = Feature{
+ .name = "avr5",
+ .description = "The device is a part of the avr5 family",
+ .llvm_name = "avr5",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ },
+};
+
+pub const feature_avr6 = Feature{
+ .name = "avr6",
+ .description = "The device is a part of the avr6 family",
+ .llvm_name = "avr6",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ },
+};
+
+pub const feature_avr25 = Feature{
+ .name = "avr25",
+ .description = "The device is a part of the avr25 family",
+ .llvm_name = "avr25",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ },
+};
+
+pub const feature_avr31 = Feature{
+ .name = "avr31",
+ .description = "The device is a part of the avr31 family",
+ .llvm_name = "avr31",
+ .subfeatures = &[_]*const Feature {
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_elpm,
+ &feature_addsubiw,
+ },
+};
+
+pub const feature_avr35 = Feature{
+ .name = "avr35",
+ .description = "The device is a part of the avr35 family",
+ .llvm_name = "avr35",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ },
+};
+
+pub const feature_avr51 = Feature{
+ .name = "avr51",
+ .description = "The device is a part of the avr51 family",
+ .llvm_name = "avr51",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ },
+};
+
+pub const feature_avrtiny = Feature{
+ .name = "avrtiny",
+ .description = "The device is a part of the avrtiny family",
+ .llvm_name = "avrtiny",
+ .subfeatures = &[_]*const Feature {
+ &feature_tinyencoding,
+ &feature_sram,
+ &feature_break,
+ &feature_avr0,
+ },
+};
+
+pub const feature_xmega = Feature{
+ .name = "xmega",
+ .description = "The device is a part of the xmega family",
+ .llvm_name = "xmega",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ },
+};
+
+pub const feature_xmegau = Feature{
+ .name = "xmegau",
+ .description = "The device is a part of the xmegau family",
+ .llvm_name = "xmegau",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ },
+};
+
+pub const feature_addsubiw = Feature{
+ .name = "addsubiw",
+ .description = "Enable 16-bit register-immediate addition and subtraction instructions",
+ .llvm_name = "addsubiw",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_break = Feature{
+ .name = "break",
+ .description = "The device supports the `BREAK` debugging instruction",
+ .llvm_name = "break",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_des = Feature{
+ .name = "des",
+ .description = "The device supports the `DES k` encryption instruction",
+ .llvm_name = "des",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_eijmpcall = Feature{
+ .name = "eijmpcall",
+ .description = "The device supports the `EIJMP`/`EICALL` instructions",
+ .llvm_name = "eijmpcall",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_elpm = Feature{
+ .name = "elpm",
+ .description = "The device supports the ELPM instruction",
+ .llvm_name = "elpm",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_elpmx = Feature{
+ .name = "elpmx",
+ .description = "The device supports the `ELPM Rd, Z[+]` instructions",
+ .llvm_name = "elpmx",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ijmpcall = Feature{
+ .name = "ijmpcall",
+ .description = "The device supports `IJMP`/`ICALL`instructions",
+ .llvm_name = "ijmpcall",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_jmpcall = Feature{
+ .name = "jmpcall",
+ .description = "The device supports the `JMP` and `CALL` instructions",
+ .llvm_name = "jmpcall",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_lpm = Feature{
+ .name = "lpm",
+ .description = "The device supports the `LPM` instruction",
+ .llvm_name = "lpm",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_lpmx = Feature{
+ .name = "lpmx",
+ .description = "The device supports the `LPM Rd, Z[+]` instruction",
+ .llvm_name = "lpmx",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_movw = Feature{
+ .name = "movw",
+ .description = "The device supports the 16-bit MOVW instruction",
+ .llvm_name = "movw",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mul = Feature{
+ .name = "mul",
+ .description = "The device supports the multiplication instructions",
+ .llvm_name = "mul",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_rmw = Feature{
+ .name = "rmw",
+ .description = "The device supports the read-write-modify instructions: XCH, LAS, LAC, LAT",
+ .llvm_name = "rmw",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_spm = Feature{
+ .name = "spm",
+ .description = "The device supports the `SPM` instruction",
+ .llvm_name = "spm",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_spmx = Feature{
+ .name = "spmx",
+ .description = "The device supports the `SPM Z+` instruction",
+ .llvm_name = "spmx",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sram = Feature{
+ .name = "sram",
+ .description = "The device has random access memory",
+ .llvm_name = "sram",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_special = Feature{
+ .name = "special",
+ .description = "Enable use of the entire instruction set - used for debugging",
+ .llvm_name = "special",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_rmw,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ },
+};
+
+pub const feature_smallstack = Feature{
+ .name = "smallstack",
+ .description = "The device has an 8-bit stack pointer",
+ .llvm_name = "smallstack",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_tinyencoding = Feature{
+ .name = "tinyencoding",
+ .description = "The device has Tiny core specific instruction encodings",
+ .llvm_name = "tinyencoding",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const features = &[_]*const Feature {
+ &feature_avr0,
+ &feature_avr1,
+ &feature_avr2,
+ &feature_avr3,
+ &feature_avr4,
+ &feature_avr5,
+ &feature_avr6,
+ &feature_avr25,
+ &feature_avr31,
+ &feature_avr35,
+ &feature_avr51,
+ &feature_avrtiny,
+ &feature_xmega,
+ &feature_xmegau,
+ &feature_addsubiw,
+ &feature_break,
+ &feature_des,
+ &feature_eijmpcall,
+ &feature_elpm,
+ &feature_elpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_lpm,
+ &feature_lpmx,
+ &feature_movw,
+ &feature_mul,
+ &feature_rmw,
+ &feature_spm,
+ &feature_spmx,
+ &feature_sram,
+ &feature_special,
+ &feature_smallstack,
+ &feature_tinyencoding,
+};
+
+pub const cpu_at43usb320 = Cpu{
+ .name = "at43usb320",
+ .llvm_name = "at43usb320",
+ .subfeatures = &[_]*const Feature {
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr31,
+ },
+};
+
+pub const cpu_at43usb355 = Cpu{
+ .name = "at43usb355",
+ .llvm_name = "at43usb355",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr3,
+ },
+};
+
+pub const cpu_at76c711 = Cpu{
+ .name = "at76c711",
+ .llvm_name = "at76c711",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr3,
+ },
+};
+
+pub const cpu_at86rf401 = Cpu{
+ .name = "at86rf401",
+ .llvm_name = "at86rf401",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr2,
+ &feature_lpmx,
+ &feature_movw,
+ },
+};
+
+pub const cpu_at90c8534 = Cpu{
+ .name = "at90c8534",
+ .llvm_name = "at90c8534",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr2,
+ },
+};
+
+pub const cpu_at90can128 = Cpu{
+ .name = "at90can128",
+ .llvm_name = "at90can128",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr51,
+ },
+};
+
+pub const cpu_at90can32 = Cpu{
+ .name = "at90can32",
+ .llvm_name = "at90can32",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_at90can64 = Cpu{
+ .name = "at90can64",
+ .llvm_name = "at90can64",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_at90pwm1 = Cpu{
+ .name = "at90pwm1",
+ .llvm_name = "at90pwm1",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_at90pwm161 = Cpu{
+ .name = "at90pwm161",
+ .llvm_name = "at90pwm161",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_at90pwm2 = Cpu{
+ .name = "at90pwm2",
+ .llvm_name = "at90pwm2",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_at90pwm216 = Cpu{
+ .name = "at90pwm216",
+ .llvm_name = "at90pwm216",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_at90pwm2b = Cpu{
+ .name = "at90pwm2b",
+ .llvm_name = "at90pwm2b",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_at90pwm3 = Cpu{
+ .name = "at90pwm3",
+ .llvm_name = "at90pwm3",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_at90pwm316 = Cpu{
+ .name = "at90pwm316",
+ .llvm_name = "at90pwm316",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_at90pwm3b = Cpu{
+ .name = "at90pwm3b",
+ .llvm_name = "at90pwm3b",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_at90pwm81 = Cpu{
+ .name = "at90pwm81",
+ .llvm_name = "at90pwm81",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_at90s1200 = Cpu{
+ .name = "at90s1200",
+ .llvm_name = "at90s1200",
+ .subfeatures = &[_]*const Feature {
+ &feature_avr0,
+ },
+};
+
+pub const cpu_at90s2313 = Cpu{
+ .name = "at90s2313",
+ .llvm_name = "at90s2313",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr2,
+ },
+};
+
+pub const cpu_at90s2323 = Cpu{
+ .name = "at90s2323",
+ .llvm_name = "at90s2323",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr2,
+ },
+};
+
+pub const cpu_at90s2333 = Cpu{
+ .name = "at90s2333",
+ .llvm_name = "at90s2333",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr2,
+ },
+};
+
+pub const cpu_at90s2343 = Cpu{
+ .name = "at90s2343",
+ .llvm_name = "at90s2343",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr2,
+ },
+};
+
+pub const cpu_at90s4414 = Cpu{
+ .name = "at90s4414",
+ .llvm_name = "at90s4414",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr2,
+ },
+};
+
+pub const cpu_at90s4433 = Cpu{
+ .name = "at90s4433",
+ .llvm_name = "at90s4433",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr2,
+ },
+};
+
+pub const cpu_at90s4434 = Cpu{
+ .name = "at90s4434",
+ .llvm_name = "at90s4434",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr2,
+ },
+};
+
+pub const cpu_at90s8515 = Cpu{
+ .name = "at90s8515",
+ .llvm_name = "at90s8515",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr2,
+ },
+};
+
+pub const cpu_at90s8535 = Cpu{
+ .name = "at90s8535",
+ .llvm_name = "at90s8535",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr2,
+ },
+};
+
+pub const cpu_at90scr100 = Cpu{
+ .name = "at90scr100",
+ .llvm_name = "at90scr100",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_at90usb1286 = Cpu{
+ .name = "at90usb1286",
+ .llvm_name = "at90usb1286",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr51,
+ },
+};
+
+pub const cpu_at90usb1287 = Cpu{
+ .name = "at90usb1287",
+ .llvm_name = "at90usb1287",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr51,
+ },
+};
+
+pub const cpu_at90usb162 = Cpu{
+ .name = "at90usb162",
+ .llvm_name = "at90usb162",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr35,
+ },
+};
+
+pub const cpu_at90usb646 = Cpu{
+ .name = "at90usb646",
+ .llvm_name = "at90usb646",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_at90usb647 = Cpu{
+ .name = "at90usb647",
+ .llvm_name = "at90usb647",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_at90usb82 = Cpu{
+ .name = "at90usb82",
+ .llvm_name = "at90usb82",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr35,
+ },
+};
+
+pub const cpu_at94k = Cpu{
+ .name = "at94k",
+ .llvm_name = "at94k",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr3,
+ &feature_lpmx,
+ &feature_movw,
+ &feature_mul,
+ },
+};
+
+pub const cpu_ata5272 = Cpu{
+ .name = "ata5272",
+ .llvm_name = "ata5272",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_ata5505 = Cpu{
+ .name = "ata5505",
+ .llvm_name = "ata5505",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr35,
+ },
+};
+
+pub const cpu_ata5790 = Cpu{
+ .name = "ata5790",
+ .llvm_name = "ata5790",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_ata5795 = Cpu{
+ .name = "ata5795",
+ .llvm_name = "ata5795",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_ata6285 = Cpu{
+ .name = "ata6285",
+ .llvm_name = "ata6285",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_ata6286 = Cpu{
+ .name = "ata6286",
+ .llvm_name = "ata6286",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_ata6289 = Cpu{
+ .name = "ata6289",
+ .llvm_name = "ata6289",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_atmega103 = Cpu{
+ .name = "atmega103",
+ .llvm_name = "atmega103",
+ .subfeatures = &[_]*const Feature {
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr31,
+ },
+};
+
+pub const cpu_atmega128 = Cpu{
+ .name = "atmega128",
+ .llvm_name = "atmega128",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr51,
+ },
+};
+
+pub const cpu_atmega1280 = Cpu{
+ .name = "atmega1280",
+ .llvm_name = "atmega1280",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr51,
+ },
+};
+
+pub const cpu_atmega1281 = Cpu{
+ .name = "atmega1281",
+ .llvm_name = "atmega1281",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr51,
+ },
+};
+
+pub const cpu_atmega1284 = Cpu{
+ .name = "atmega1284",
+ .llvm_name = "atmega1284",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr51,
+ },
+};
+
+pub const cpu_atmega1284p = Cpu{
+ .name = "atmega1284p",
+ .llvm_name = "atmega1284p",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr51,
+ },
+};
+
+pub const cpu_atmega1284rfr2 = Cpu{
+ .name = "atmega1284rfr2",
+ .llvm_name = "atmega1284rfr2",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr51,
+ },
+};
+
+pub const cpu_atmega128a = Cpu{
+ .name = "atmega128a",
+ .llvm_name = "atmega128a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr51,
+ },
+};
+
+pub const cpu_atmega128rfa1 = Cpu{
+ .name = "atmega128rfa1",
+ .llvm_name = "atmega128rfa1",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr51,
+ },
+};
+
+pub const cpu_atmega128rfr2 = Cpu{
+ .name = "atmega128rfr2",
+ .llvm_name = "atmega128rfr2",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr51,
+ },
+};
+
+pub const cpu_atmega16 = Cpu{
+ .name = "atmega16",
+ .llvm_name = "atmega16",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega161 = Cpu{
+ .name = "atmega161",
+ .llvm_name = "atmega161",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr3,
+ &feature_lpmx,
+ &feature_movw,
+ &feature_mul,
+ &feature_spm,
+ },
+};
+
+pub const cpu_atmega162 = Cpu{
+ .name = "atmega162",
+ .llvm_name = "atmega162",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega163 = Cpu{
+ .name = "atmega163",
+ .llvm_name = "atmega163",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr3,
+ &feature_lpmx,
+ &feature_movw,
+ &feature_mul,
+ &feature_spm,
+ },
+};
+
+pub const cpu_atmega164a = Cpu{
+ .name = "atmega164a",
+ .llvm_name = "atmega164a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega164p = Cpu{
+ .name = "atmega164p",
+ .llvm_name = "atmega164p",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega164pa = Cpu{
+ .name = "atmega164pa",
+ .llvm_name = "atmega164pa",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega165 = Cpu{
+ .name = "atmega165",
+ .llvm_name = "atmega165",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega165a = Cpu{
+ .name = "atmega165a",
+ .llvm_name = "atmega165a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega165p = Cpu{
+ .name = "atmega165p",
+ .llvm_name = "atmega165p",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega165pa = Cpu{
+ .name = "atmega165pa",
+ .llvm_name = "atmega165pa",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega168 = Cpu{
+ .name = "atmega168",
+ .llvm_name = "atmega168",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega168a = Cpu{
+ .name = "atmega168a",
+ .llvm_name = "atmega168a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega168p = Cpu{
+ .name = "atmega168p",
+ .llvm_name = "atmega168p",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega168pa = Cpu{
+ .name = "atmega168pa",
+ .llvm_name = "atmega168pa",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega169 = Cpu{
+ .name = "atmega169",
+ .llvm_name = "atmega169",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega169a = Cpu{
+ .name = "atmega169a",
+ .llvm_name = "atmega169a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega169p = Cpu{
+ .name = "atmega169p",
+ .llvm_name = "atmega169p",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega169pa = Cpu{
+ .name = "atmega169pa",
+ .llvm_name = "atmega169pa",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega16a = Cpu{
+ .name = "atmega16a",
+ .llvm_name = "atmega16a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega16hva = Cpu{
+ .name = "atmega16hva",
+ .llvm_name = "atmega16hva",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega16hva2 = Cpu{
+ .name = "atmega16hva2",
+ .llvm_name = "atmega16hva2",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega16hvb = Cpu{
+ .name = "atmega16hvb",
+ .llvm_name = "atmega16hvb",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega16hvbrevb = Cpu{
+ .name = "atmega16hvbrevb",
+ .llvm_name = "atmega16hvbrevb",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega16m1 = Cpu{
+ .name = "atmega16m1",
+ .llvm_name = "atmega16m1",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega16u2 = Cpu{
+ .name = "atmega16u2",
+ .llvm_name = "atmega16u2",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr35,
+ },
+};
+
+pub const cpu_atmega16u4 = Cpu{
+ .name = "atmega16u4",
+ .llvm_name = "atmega16u4",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega2560 = Cpu{
+ .name = "atmega2560",
+ .llvm_name = "atmega2560",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr6,
+ },
+};
+
+pub const cpu_atmega2561 = Cpu{
+ .name = "atmega2561",
+ .llvm_name = "atmega2561",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr6,
+ },
+};
+
+pub const cpu_atmega2564rfr2 = Cpu{
+ .name = "atmega2564rfr2",
+ .llvm_name = "atmega2564rfr2",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr6,
+ },
+};
+
+pub const cpu_atmega256rfr2 = Cpu{
+ .name = "atmega256rfr2",
+ .llvm_name = "atmega256rfr2",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr6,
+ },
+};
+
+pub const cpu_atmega32 = Cpu{
+ .name = "atmega32",
+ .llvm_name = "atmega32",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega323 = Cpu{
+ .name = "atmega323",
+ .llvm_name = "atmega323",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega324a = Cpu{
+ .name = "atmega324a",
+ .llvm_name = "atmega324a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega324p = Cpu{
+ .name = "atmega324p",
+ .llvm_name = "atmega324p",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega324pa = Cpu{
+ .name = "atmega324pa",
+ .llvm_name = "atmega324pa",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega325 = Cpu{
+ .name = "atmega325",
+ .llvm_name = "atmega325",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega3250 = Cpu{
+ .name = "atmega3250",
+ .llvm_name = "atmega3250",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega3250a = Cpu{
+ .name = "atmega3250a",
+ .llvm_name = "atmega3250a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega3250p = Cpu{
+ .name = "atmega3250p",
+ .llvm_name = "atmega3250p",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega3250pa = Cpu{
+ .name = "atmega3250pa",
+ .llvm_name = "atmega3250pa",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega325a = Cpu{
+ .name = "atmega325a",
+ .llvm_name = "atmega325a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega325p = Cpu{
+ .name = "atmega325p",
+ .llvm_name = "atmega325p",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega325pa = Cpu{
+ .name = "atmega325pa",
+ .llvm_name = "atmega325pa",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega328 = Cpu{
+ .name = "atmega328",
+ .llvm_name = "atmega328",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega328p = Cpu{
+ .name = "atmega328p",
+ .llvm_name = "atmega328p",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega329 = Cpu{
+ .name = "atmega329",
+ .llvm_name = "atmega329",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega3290 = Cpu{
+ .name = "atmega3290",
+ .llvm_name = "atmega3290",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega3290a = Cpu{
+ .name = "atmega3290a",
+ .llvm_name = "atmega3290a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega3290p = Cpu{
+ .name = "atmega3290p",
+ .llvm_name = "atmega3290p",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega3290pa = Cpu{
+ .name = "atmega3290pa",
+ .llvm_name = "atmega3290pa",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega329a = Cpu{
+ .name = "atmega329a",
+ .llvm_name = "atmega329a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega329p = Cpu{
+ .name = "atmega329p",
+ .llvm_name = "atmega329p",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega329pa = Cpu{
+ .name = "atmega329pa",
+ .llvm_name = "atmega329pa",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega32a = Cpu{
+ .name = "atmega32a",
+ .llvm_name = "atmega32a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega32c1 = Cpu{
+ .name = "atmega32c1",
+ .llvm_name = "atmega32c1",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega32hvb = Cpu{
+ .name = "atmega32hvb",
+ .llvm_name = "atmega32hvb",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega32hvbrevb = Cpu{
+ .name = "atmega32hvbrevb",
+ .llvm_name = "atmega32hvbrevb",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega32m1 = Cpu{
+ .name = "atmega32m1",
+ .llvm_name = "atmega32m1",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega32u2 = Cpu{
+ .name = "atmega32u2",
+ .llvm_name = "atmega32u2",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr35,
+ },
+};
+
+pub const cpu_atmega32u4 = Cpu{
+ .name = "atmega32u4",
+ .llvm_name = "atmega32u4",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega32u6 = Cpu{
+ .name = "atmega32u6",
+ .llvm_name = "atmega32u6",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega406 = Cpu{
+ .name = "atmega406",
+ .llvm_name = "atmega406",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega48 = Cpu{
+ .name = "atmega48",
+ .llvm_name = "atmega48",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_atmega48a = Cpu{
+ .name = "atmega48a",
+ .llvm_name = "atmega48a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_atmega48p = Cpu{
+ .name = "atmega48p",
+ .llvm_name = "atmega48p",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_atmega48pa = Cpu{
+ .name = "atmega48pa",
+ .llvm_name = "atmega48pa",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_atmega64 = Cpu{
+ .name = "atmega64",
+ .llvm_name = "atmega64",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega640 = Cpu{
+ .name = "atmega640",
+ .llvm_name = "atmega640",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega644 = Cpu{
+ .name = "atmega644",
+ .llvm_name = "atmega644",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega644a = Cpu{
+ .name = "atmega644a",
+ .llvm_name = "atmega644a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega644p = Cpu{
+ .name = "atmega644p",
+ .llvm_name = "atmega644p",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega644pa = Cpu{
+ .name = "atmega644pa",
+ .llvm_name = "atmega644pa",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega644rfr2 = Cpu{
+ .name = "atmega644rfr2",
+ .llvm_name = "atmega644rfr2",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega645 = Cpu{
+ .name = "atmega645",
+ .llvm_name = "atmega645",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega6450 = Cpu{
+ .name = "atmega6450",
+ .llvm_name = "atmega6450",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega6450a = Cpu{
+ .name = "atmega6450a",
+ .llvm_name = "atmega6450a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega6450p = Cpu{
+ .name = "atmega6450p",
+ .llvm_name = "atmega6450p",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega645a = Cpu{
+ .name = "atmega645a",
+ .llvm_name = "atmega645a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega645p = Cpu{
+ .name = "atmega645p",
+ .llvm_name = "atmega645p",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega649 = Cpu{
+ .name = "atmega649",
+ .llvm_name = "atmega649",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega6490 = Cpu{
+ .name = "atmega6490",
+ .llvm_name = "atmega6490",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega6490a = Cpu{
+ .name = "atmega6490a",
+ .llvm_name = "atmega6490a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega6490p = Cpu{
+ .name = "atmega6490p",
+ .llvm_name = "atmega6490p",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega649a = Cpu{
+ .name = "atmega649a",
+ .llvm_name = "atmega649a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega649p = Cpu{
+ .name = "atmega649p",
+ .llvm_name = "atmega649p",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega64a = Cpu{
+ .name = "atmega64a",
+ .llvm_name = "atmega64a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega64c1 = Cpu{
+ .name = "atmega64c1",
+ .llvm_name = "atmega64c1",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega64hve = Cpu{
+ .name = "atmega64hve",
+ .llvm_name = "atmega64hve",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega64m1 = Cpu{
+ .name = "atmega64m1",
+ .llvm_name = "atmega64m1",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega64rfr2 = Cpu{
+ .name = "atmega64rfr2",
+ .llvm_name = "atmega64rfr2",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_atmega8 = Cpu{
+ .name = "atmega8",
+ .llvm_name = "atmega8",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_atmega8515 = Cpu{
+ .name = "atmega8515",
+ .llvm_name = "atmega8515",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr2,
+ &feature_lpmx,
+ &feature_movw,
+ &feature_mul,
+ &feature_spm,
+ },
+};
+
+pub const cpu_atmega8535 = Cpu{
+ .name = "atmega8535",
+ .llvm_name = "atmega8535",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr2,
+ &feature_lpmx,
+ &feature_movw,
+ &feature_mul,
+ &feature_spm,
+ },
+};
+
+pub const cpu_atmega88 = Cpu{
+ .name = "atmega88",
+ .llvm_name = "atmega88",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_atmega88a = Cpu{
+ .name = "atmega88a",
+ .llvm_name = "atmega88a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_atmega88p = Cpu{
+ .name = "atmega88p",
+ .llvm_name = "atmega88p",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_atmega88pa = Cpu{
+ .name = "atmega88pa",
+ .llvm_name = "atmega88pa",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_atmega8a = Cpu{
+ .name = "atmega8a",
+ .llvm_name = "atmega8a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_atmega8hva = Cpu{
+ .name = "atmega8hva",
+ .llvm_name = "atmega8hva",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_atmega8u2 = Cpu{
+ .name = "atmega8u2",
+ .llvm_name = "atmega8u2",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr35,
+ },
+};
+
+pub const cpu_attiny10 = Cpu{
+ .name = "attiny10",
+ .llvm_name = "attiny10",
+ .subfeatures = &[_]*const Feature {
+ &feature_tinyencoding,
+ &feature_sram,
+ &feature_break,
+ &feature_avr0,
+ &feature_avrtiny,
+ },
+};
+
+pub const cpu_attiny102 = Cpu{
+ .name = "attiny102",
+ .llvm_name = "attiny102",
+ .subfeatures = &[_]*const Feature {
+ &feature_tinyencoding,
+ &feature_sram,
+ &feature_break,
+ &feature_avr0,
+ &feature_avrtiny,
+ },
+};
+
+pub const cpu_attiny104 = Cpu{
+ .name = "attiny104",
+ .llvm_name = "attiny104",
+ .subfeatures = &[_]*const Feature {
+ &feature_tinyencoding,
+ &feature_sram,
+ &feature_break,
+ &feature_avr0,
+ &feature_avrtiny,
+ },
+};
+
+pub const cpu_attiny11 = Cpu{
+ .name = "attiny11",
+ .llvm_name = "attiny11",
+ .subfeatures = &[_]*const Feature {
+ &feature_avr0,
+ &feature_lpm,
+ &feature_avr1,
+ },
+};
+
+pub const cpu_attiny12 = Cpu{
+ .name = "attiny12",
+ .llvm_name = "attiny12",
+ .subfeatures = &[_]*const Feature {
+ &feature_avr0,
+ &feature_lpm,
+ &feature_avr1,
+ },
+};
+
+pub const cpu_attiny13 = Cpu{
+ .name = "attiny13",
+ .llvm_name = "attiny13",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny13a = Cpu{
+ .name = "attiny13a",
+ .llvm_name = "attiny13a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny15 = Cpu{
+ .name = "attiny15",
+ .llvm_name = "attiny15",
+ .subfeatures = &[_]*const Feature {
+ &feature_avr0,
+ &feature_lpm,
+ &feature_avr1,
+ },
+};
+
+pub const cpu_attiny1634 = Cpu{
+ .name = "attiny1634",
+ .llvm_name = "attiny1634",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr35,
+ },
+};
+
+pub const cpu_attiny167 = Cpu{
+ .name = "attiny167",
+ .llvm_name = "attiny167",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr35,
+ },
+};
+
+pub const cpu_attiny20 = Cpu{
+ .name = "attiny20",
+ .llvm_name = "attiny20",
+ .subfeatures = &[_]*const Feature {
+ &feature_tinyencoding,
+ &feature_sram,
+ &feature_break,
+ &feature_avr0,
+ &feature_avrtiny,
+ },
+};
+
+pub const cpu_attiny22 = Cpu{
+ .name = "attiny22",
+ .llvm_name = "attiny22",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr2,
+ },
+};
+
+pub const cpu_attiny2313 = Cpu{
+ .name = "attiny2313",
+ .llvm_name = "attiny2313",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny2313a = Cpu{
+ .name = "attiny2313a",
+ .llvm_name = "attiny2313a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny24 = Cpu{
+ .name = "attiny24",
+ .llvm_name = "attiny24",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny24a = Cpu{
+ .name = "attiny24a",
+ .llvm_name = "attiny24a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny25 = Cpu{
+ .name = "attiny25",
+ .llvm_name = "attiny25",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny26 = Cpu{
+ .name = "attiny26",
+ .llvm_name = "attiny26",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr2,
+ &feature_lpmx,
+ },
+};
+
+pub const cpu_attiny261 = Cpu{
+ .name = "attiny261",
+ .llvm_name = "attiny261",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny261a = Cpu{
+ .name = "attiny261a",
+ .llvm_name = "attiny261a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny28 = Cpu{
+ .name = "attiny28",
+ .llvm_name = "attiny28",
+ .subfeatures = &[_]*const Feature {
+ &feature_avr0,
+ &feature_lpm,
+ &feature_avr1,
+ },
+};
+
+pub const cpu_attiny4 = Cpu{
+ .name = "attiny4",
+ .llvm_name = "attiny4",
+ .subfeatures = &[_]*const Feature {
+ &feature_tinyencoding,
+ &feature_sram,
+ &feature_break,
+ &feature_avr0,
+ &feature_avrtiny,
+ },
+};
+
+pub const cpu_attiny40 = Cpu{
+ .name = "attiny40",
+ .llvm_name = "attiny40",
+ .subfeatures = &[_]*const Feature {
+ &feature_tinyencoding,
+ &feature_sram,
+ &feature_break,
+ &feature_avr0,
+ &feature_avrtiny,
+ },
+};
+
+pub const cpu_attiny4313 = Cpu{
+ .name = "attiny4313",
+ .llvm_name = "attiny4313",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny43u = Cpu{
+ .name = "attiny43u",
+ .llvm_name = "attiny43u",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny44 = Cpu{
+ .name = "attiny44",
+ .llvm_name = "attiny44",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny44a = Cpu{
+ .name = "attiny44a",
+ .llvm_name = "attiny44a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny45 = Cpu{
+ .name = "attiny45",
+ .llvm_name = "attiny45",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny461 = Cpu{
+ .name = "attiny461",
+ .llvm_name = "attiny461",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny461a = Cpu{
+ .name = "attiny461a",
+ .llvm_name = "attiny461a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny48 = Cpu{
+ .name = "attiny48",
+ .llvm_name = "attiny48",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny5 = Cpu{
+ .name = "attiny5",
+ .llvm_name = "attiny5",
+ .subfeatures = &[_]*const Feature {
+ &feature_tinyencoding,
+ &feature_sram,
+ &feature_break,
+ &feature_avr0,
+ &feature_avrtiny,
+ },
+};
+
+pub const cpu_attiny828 = Cpu{
+ .name = "attiny828",
+ .llvm_name = "attiny828",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny84 = Cpu{
+ .name = "attiny84",
+ .llvm_name = "attiny84",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny84a = Cpu{
+ .name = "attiny84a",
+ .llvm_name = "attiny84a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny85 = Cpu{
+ .name = "attiny85",
+ .llvm_name = "attiny85",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny861 = Cpu{
+ .name = "attiny861",
+ .llvm_name = "attiny861",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny861a = Cpu{
+ .name = "attiny861a",
+ .llvm_name = "attiny861a",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny87 = Cpu{
+ .name = "attiny87",
+ .llvm_name = "attiny87",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny88 = Cpu{
+ .name = "attiny88",
+ .llvm_name = "attiny88",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_attiny9 = Cpu{
+ .name = "attiny9",
+ .llvm_name = "attiny9",
+ .subfeatures = &[_]*const Feature {
+ &feature_tinyencoding,
+ &feature_sram,
+ &feature_break,
+ &feature_avr0,
+ &feature_avrtiny,
+ },
+};
+
+pub const cpu_atxmega128a1 = Cpu{
+ .name = "atxmega128a1",
+ .llvm_name = "atxmega128a1",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega128a1u = Cpu{
+ .name = "atxmega128a1u",
+ .llvm_name = "atxmega128a1u",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega128a3 = Cpu{
+ .name = "atxmega128a3",
+ .llvm_name = "atxmega128a3",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega128a3u = Cpu{
+ .name = "atxmega128a3u",
+ .llvm_name = "atxmega128a3u",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega128a4u = Cpu{
+ .name = "atxmega128a4u",
+ .llvm_name = "atxmega128a4u",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega128b1 = Cpu{
+ .name = "atxmega128b1",
+ .llvm_name = "atxmega128b1",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega128b3 = Cpu{
+ .name = "atxmega128b3",
+ .llvm_name = "atxmega128b3",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega128c3 = Cpu{
+ .name = "atxmega128c3",
+ .llvm_name = "atxmega128c3",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega128d3 = Cpu{
+ .name = "atxmega128d3",
+ .llvm_name = "atxmega128d3",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega128d4 = Cpu{
+ .name = "atxmega128d4",
+ .llvm_name = "atxmega128d4",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega16a4 = Cpu{
+ .name = "atxmega16a4",
+ .llvm_name = "atxmega16a4",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega16a4u = Cpu{
+ .name = "atxmega16a4u",
+ .llvm_name = "atxmega16a4u",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega16c4 = Cpu{
+ .name = "atxmega16c4",
+ .llvm_name = "atxmega16c4",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega16d4 = Cpu{
+ .name = "atxmega16d4",
+ .llvm_name = "atxmega16d4",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega16e5 = Cpu{
+ .name = "atxmega16e5",
+ .llvm_name = "atxmega16e5",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega192a3 = Cpu{
+ .name = "atxmega192a3",
+ .llvm_name = "atxmega192a3",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega192a3u = Cpu{
+ .name = "atxmega192a3u",
+ .llvm_name = "atxmega192a3u",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega192c3 = Cpu{
+ .name = "atxmega192c3",
+ .llvm_name = "atxmega192c3",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega192d3 = Cpu{
+ .name = "atxmega192d3",
+ .llvm_name = "atxmega192d3",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega256a3 = Cpu{
+ .name = "atxmega256a3",
+ .llvm_name = "atxmega256a3",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega256a3b = Cpu{
+ .name = "atxmega256a3b",
+ .llvm_name = "atxmega256a3b",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega256a3bu = Cpu{
+ .name = "atxmega256a3bu",
+ .llvm_name = "atxmega256a3bu",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega256a3u = Cpu{
+ .name = "atxmega256a3u",
+ .llvm_name = "atxmega256a3u",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega256c3 = Cpu{
+ .name = "atxmega256c3",
+ .llvm_name = "atxmega256c3",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega256d3 = Cpu{
+ .name = "atxmega256d3",
+ .llvm_name = "atxmega256d3",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega32a4 = Cpu{
+ .name = "atxmega32a4",
+ .llvm_name = "atxmega32a4",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega32a4u = Cpu{
+ .name = "atxmega32a4u",
+ .llvm_name = "atxmega32a4u",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega32c4 = Cpu{
+ .name = "atxmega32c4",
+ .llvm_name = "atxmega32c4",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega32d4 = Cpu{
+ .name = "atxmega32d4",
+ .llvm_name = "atxmega32d4",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega32e5 = Cpu{
+ .name = "atxmega32e5",
+ .llvm_name = "atxmega32e5",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega32x1 = Cpu{
+ .name = "atxmega32x1",
+ .llvm_name = "atxmega32x1",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega384c3 = Cpu{
+ .name = "atxmega384c3",
+ .llvm_name = "atxmega384c3",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega384d3 = Cpu{
+ .name = "atxmega384d3",
+ .llvm_name = "atxmega384d3",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega64a1 = Cpu{
+ .name = "atxmega64a1",
+ .llvm_name = "atxmega64a1",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega64a1u = Cpu{
+ .name = "atxmega64a1u",
+ .llvm_name = "atxmega64a1u",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega64a3 = Cpu{
+ .name = "atxmega64a3",
+ .llvm_name = "atxmega64a3",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega64a3u = Cpu{
+ .name = "atxmega64a3u",
+ .llvm_name = "atxmega64a3u",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega64a4u = Cpu{
+ .name = "atxmega64a4u",
+ .llvm_name = "atxmega64a4u",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega64b1 = Cpu{
+ .name = "atxmega64b1",
+ .llvm_name = "atxmega64b1",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega64b3 = Cpu{
+ .name = "atxmega64b3",
+ .llvm_name = "atxmega64b3",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega64c3 = Cpu{
+ .name = "atxmega64c3",
+ .llvm_name = "atxmega64c3",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_rmw,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmegau,
+ },
+};
+
+pub const cpu_atxmega64d3 = Cpu{
+ .name = "atxmega64d3",
+ .llvm_name = "atxmega64d3",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega64d4 = Cpu{
+ .name = "atxmega64d4",
+ .llvm_name = "atxmega64d4",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_atxmega8e5 = Cpu{
+ .name = "atxmega8e5",
+ .llvm_name = "atxmega8e5",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_avr1 = Cpu{
+ .name = "avr1",
+ .llvm_name = "avr1",
+ .subfeatures = &[_]*const Feature {
+ &feature_avr0,
+ &feature_lpm,
+ &feature_avr1,
+ },
+};
+
+pub const cpu_avr2 = Cpu{
+ .name = "avr2",
+ .llvm_name = "avr2",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr2,
+ },
+};
+
+pub const cpu_avr25 = Cpu{
+ .name = "avr25",
+ .llvm_name = "avr25",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr25,
+ },
+};
+
+pub const cpu_avr3 = Cpu{
+ .name = "avr3",
+ .llvm_name = "avr3",
+ .subfeatures = &[_]*const Feature {
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_addsubiw,
+ &feature_avr3,
+ },
+};
+
+pub const cpu_avr31 = Cpu{
+ .name = "avr31",
+ .llvm_name = "avr31",
+ .subfeatures = &[_]*const Feature {
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr31,
+ },
+};
+
+pub const cpu_avr35 = Cpu{
+ .name = "avr35",
+ .llvm_name = "avr35",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr35,
+ },
+};
+
+pub const cpu_avr4 = Cpu{
+ .name = "avr4",
+ .llvm_name = "avr4",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr4,
+ },
+};
+
+pub const cpu_avr5 = Cpu{
+ .name = "avr5",
+ .llvm_name = "avr5",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpu_avr51 = Cpu{
+ .name = "avr51",
+ .llvm_name = "avr51",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_ijmpcall,
+ &feature_jmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr51,
+ },
+};
+
+pub const cpu_avr6 = Cpu{
+ .name = "avr6",
+ .llvm_name = "avr6",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_avr6,
+ },
+};
+
+pub const cpu_avrtiny = Cpu{
+ .name = "avrtiny",
+ .llvm_name = "avrtiny",
+ .subfeatures = &[_]*const Feature {
+ &feature_tinyencoding,
+ &feature_sram,
+ &feature_break,
+ &feature_avr0,
+ &feature_avrtiny,
+ },
+};
+
+pub const cpu_avrxmega1 = Cpu{
+ .name = "avrxmega1",
+ .llvm_name = "avrxmega1",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_avrxmega2 = Cpu{
+ .name = "avrxmega2",
+ .llvm_name = "avrxmega2",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_avrxmega3 = Cpu{
+ .name = "avrxmega3",
+ .llvm_name = "avrxmega3",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_avrxmega4 = Cpu{
+ .name = "avrxmega4",
+ .llvm_name = "avrxmega4",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_avrxmega5 = Cpu{
+ .name = "avrxmega5",
+ .llvm_name = "avrxmega5",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_avrxmega6 = Cpu{
+ .name = "avrxmega6",
+ .llvm_name = "avrxmega6",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_avrxmega7 = Cpu{
+ .name = "avrxmega7",
+ .llvm_name = "avrxmega7",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_spmx,
+ &feature_lpm,
+ &feature_eijmpcall,
+ &feature_break,
+ &feature_spm,
+ &feature_elpmx,
+ &feature_elpm,
+ &feature_addsubiw,
+ &feature_des,
+ &feature_xmega,
+ },
+};
+
+pub const cpu_m3000 = Cpu{
+ .name = "m3000",
+ .llvm_name = "m3000",
+ .subfeatures = &[_]*const Feature {
+ &feature_lpmx,
+ &feature_jmpcall,
+ &feature_ijmpcall,
+ &feature_movw,
+ &feature_sram,
+ &feature_mul,
+ &feature_avr0,
+ &feature_lpm,
+ &feature_break,
+ &feature_spm,
+ &feature_addsubiw,
+ &feature_avr5,
+ },
+};
+
+pub const cpus = &[_]*const Cpu {
+ &cpu_at43usb320,
+ &cpu_at43usb355,
+ &cpu_at76c711,
+ &cpu_at86rf401,
+ &cpu_at90c8534,
+ &cpu_at90can128,
+ &cpu_at90can32,
+ &cpu_at90can64,
+ &cpu_at90pwm1,
+ &cpu_at90pwm161,
+ &cpu_at90pwm2,
+ &cpu_at90pwm216,
+ &cpu_at90pwm2b,
+ &cpu_at90pwm3,
+ &cpu_at90pwm316,
+ &cpu_at90pwm3b,
+ &cpu_at90pwm81,
+ &cpu_at90s1200,
+ &cpu_at90s2313,
+ &cpu_at90s2323,
+ &cpu_at90s2333,
+ &cpu_at90s2343,
+ &cpu_at90s4414,
+ &cpu_at90s4433,
+ &cpu_at90s4434,
+ &cpu_at90s8515,
+ &cpu_at90s8535,
+ &cpu_at90scr100,
+ &cpu_at90usb1286,
+ &cpu_at90usb1287,
+ &cpu_at90usb162,
+ &cpu_at90usb646,
+ &cpu_at90usb647,
+ &cpu_at90usb82,
+ &cpu_at94k,
+ &cpu_ata5272,
+ &cpu_ata5505,
+ &cpu_ata5790,
+ &cpu_ata5795,
+ &cpu_ata6285,
+ &cpu_ata6286,
+ &cpu_ata6289,
+ &cpu_atmega103,
+ &cpu_atmega128,
+ &cpu_atmega1280,
+ &cpu_atmega1281,
+ &cpu_atmega1284,
+ &cpu_atmega1284p,
+ &cpu_atmega1284rfr2,
+ &cpu_atmega128a,
+ &cpu_atmega128rfa1,
+ &cpu_atmega128rfr2,
+ &cpu_atmega16,
+ &cpu_atmega161,
+ &cpu_atmega162,
+ &cpu_atmega163,
+ &cpu_atmega164a,
+ &cpu_atmega164p,
+ &cpu_atmega164pa,
+ &cpu_atmega165,
+ &cpu_atmega165a,
+ &cpu_atmega165p,
+ &cpu_atmega165pa,
+ &cpu_atmega168,
+ &cpu_atmega168a,
+ &cpu_atmega168p,
+ &cpu_atmega168pa,
+ &cpu_atmega169,
+ &cpu_atmega169a,
+ &cpu_atmega169p,
+ &cpu_atmega169pa,
+ &cpu_atmega16a,
+ &cpu_atmega16hva,
+ &cpu_atmega16hva2,
+ &cpu_atmega16hvb,
+ &cpu_atmega16hvbrevb,
+ &cpu_atmega16m1,
+ &cpu_atmega16u2,
+ &cpu_atmega16u4,
+ &cpu_atmega2560,
+ &cpu_atmega2561,
+ &cpu_atmega2564rfr2,
+ &cpu_atmega256rfr2,
+ &cpu_atmega32,
+ &cpu_atmega323,
+ &cpu_atmega324a,
+ &cpu_atmega324p,
+ &cpu_atmega324pa,
+ &cpu_atmega325,
+ &cpu_atmega3250,
+ &cpu_atmega3250a,
+ &cpu_atmega3250p,
+ &cpu_atmega3250pa,
+ &cpu_atmega325a,
+ &cpu_atmega325p,
+ &cpu_atmega325pa,
+ &cpu_atmega328,
+ &cpu_atmega328p,
+ &cpu_atmega329,
+ &cpu_atmega3290,
+ &cpu_atmega3290a,
+ &cpu_atmega3290p,
+ &cpu_atmega3290pa,
+ &cpu_atmega329a,
+ &cpu_atmega329p,
+ &cpu_atmega329pa,
+ &cpu_atmega32a,
+ &cpu_atmega32c1,
+ &cpu_atmega32hvb,
+ &cpu_atmega32hvbrevb,
+ &cpu_atmega32m1,
+ &cpu_atmega32u2,
+ &cpu_atmega32u4,
+ &cpu_atmega32u6,
+ &cpu_atmega406,
+ &cpu_atmega48,
+ &cpu_atmega48a,
+ &cpu_atmega48p,
+ &cpu_atmega48pa,
+ &cpu_atmega64,
+ &cpu_atmega640,
+ &cpu_atmega644,
+ &cpu_atmega644a,
+ &cpu_atmega644p,
+ &cpu_atmega644pa,
+ &cpu_atmega644rfr2,
+ &cpu_atmega645,
+ &cpu_atmega6450,
+ &cpu_atmega6450a,
+ &cpu_atmega6450p,
+ &cpu_atmega645a,
+ &cpu_atmega645p,
+ &cpu_atmega649,
+ &cpu_atmega6490,
+ &cpu_atmega6490a,
+ &cpu_atmega6490p,
+ &cpu_atmega649a,
+ &cpu_atmega649p,
+ &cpu_atmega64a,
+ &cpu_atmega64c1,
+ &cpu_atmega64hve,
+ &cpu_atmega64m1,
+ &cpu_atmega64rfr2,
+ &cpu_atmega8,
+ &cpu_atmega8515,
+ &cpu_atmega8535,
+ &cpu_atmega88,
+ &cpu_atmega88a,
+ &cpu_atmega88p,
+ &cpu_atmega88pa,
+ &cpu_atmega8a,
+ &cpu_atmega8hva,
+ &cpu_atmega8u2,
+ &cpu_attiny10,
+ &cpu_attiny102,
+ &cpu_attiny104,
+ &cpu_attiny11,
+ &cpu_attiny12,
+ &cpu_attiny13,
+ &cpu_attiny13a,
+ &cpu_attiny15,
+ &cpu_attiny1634,
+ &cpu_attiny167,
+ &cpu_attiny20,
+ &cpu_attiny22,
+ &cpu_attiny2313,
+ &cpu_attiny2313a,
+ &cpu_attiny24,
+ &cpu_attiny24a,
+ &cpu_attiny25,
+ &cpu_attiny26,
+ &cpu_attiny261,
+ &cpu_attiny261a,
+ &cpu_attiny28,
+ &cpu_attiny4,
+ &cpu_attiny40,
+ &cpu_attiny4313,
+ &cpu_attiny43u,
+ &cpu_attiny44,
+ &cpu_attiny44a,
+ &cpu_attiny45,
+ &cpu_attiny461,
+ &cpu_attiny461a,
+ &cpu_attiny48,
+ &cpu_attiny5,
+ &cpu_attiny828,
+ &cpu_attiny84,
+ &cpu_attiny84a,
+ &cpu_attiny85,
+ &cpu_attiny861,
+ &cpu_attiny861a,
+ &cpu_attiny87,
+ &cpu_attiny88,
+ &cpu_attiny9,
+ &cpu_atxmega128a1,
+ &cpu_atxmega128a1u,
+ &cpu_atxmega128a3,
+ &cpu_atxmega128a3u,
+ &cpu_atxmega128a4u,
+ &cpu_atxmega128b1,
+ &cpu_atxmega128b3,
+ &cpu_atxmega128c3,
+ &cpu_atxmega128d3,
+ &cpu_atxmega128d4,
+ &cpu_atxmega16a4,
+ &cpu_atxmega16a4u,
+ &cpu_atxmega16c4,
+ &cpu_atxmega16d4,
+ &cpu_atxmega16e5,
+ &cpu_atxmega192a3,
+ &cpu_atxmega192a3u,
+ &cpu_atxmega192c3,
+ &cpu_atxmega192d3,
+ &cpu_atxmega256a3,
+ &cpu_atxmega256a3b,
+ &cpu_atxmega256a3bu,
+ &cpu_atxmega256a3u,
+ &cpu_atxmega256c3,
+ &cpu_atxmega256d3,
+ &cpu_atxmega32a4,
+ &cpu_atxmega32a4u,
+ &cpu_atxmega32c4,
+ &cpu_atxmega32d4,
+ &cpu_atxmega32e5,
+ &cpu_atxmega32x1,
+ &cpu_atxmega384c3,
+ &cpu_atxmega384d3,
+ &cpu_atxmega64a1,
+ &cpu_atxmega64a1u,
+ &cpu_atxmega64a3,
+ &cpu_atxmega64a3u,
+ &cpu_atxmega64a4u,
+ &cpu_atxmega64b1,
+ &cpu_atxmega64b3,
+ &cpu_atxmega64c3,
+ &cpu_atxmega64d3,
+ &cpu_atxmega64d4,
+ &cpu_atxmega8e5,
+ &cpu_avr1,
+ &cpu_avr2,
+ &cpu_avr25,
+ &cpu_avr3,
+ &cpu_avr31,
+ &cpu_avr35,
+ &cpu_avr4,
+ &cpu_avr5,
+ &cpu_avr51,
+ &cpu_avr6,
+ &cpu_avrtiny,
+ &cpu_avrxmega1,
+ &cpu_avrxmega2,
+ &cpu_avrxmega3,
+ &cpu_avrxmega4,
+ &cpu_avrxmega5,
+ &cpu_avrxmega6,
+ &cpu_avrxmega7,
+ &cpu_m3000,
+};
lib/std/target/bpf.zig
@@ -0,0 +1,75 @@
+const Feature = @import("std").target.Feature;
+const Cpu = @import("std").target.Cpu;
+
+pub const feature_alu32 = Feature{
+ .name = "alu32",
+ .description = "Enable ALU32 instructions",
+ .llvm_name = "alu32",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dummy = Feature{
+ .name = "dummy",
+ .description = "unused feature",
+ .llvm_name = "dummy",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dwarfris = Feature{
+ .name = "dwarfris",
+ .description = "Disable MCAsmInfo DwarfUsesRelocationsAcrossSections",
+ .llvm_name = "dwarfris",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const features = &[_]*const Feature {
+ &feature_alu32,
+ &feature_dummy,
+ &feature_dwarfris,
+};
+
+pub const cpu_generic = Cpu{
+ .name = "generic",
+ .llvm_name = "generic",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_probe = Cpu{
+ .name = "probe",
+ .llvm_name = "probe",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_v1 = Cpu{
+ .name = "v1",
+ .llvm_name = "v1",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_v2 = Cpu{
+ .name = "v2",
+ .llvm_name = "v2",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_v3 = Cpu{
+ .name = "v3",
+ .llvm_name = "v3",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpus = &[_]*const Cpu {
+ &cpu_generic,
+ &cpu_probe,
+ &cpu_v1,
+ &cpu_v2,
+ &cpu_v3,
+};
lib/std/target/cpu.zig
@@ -1,67 +0,0 @@
-const std = @import("std");
-
-const feature = @import("feature.zig");
-const Arch = std.Target.Arch;
-
-pub const AArch64Cpu = @import("cpu/AArch64Cpu.zig").AArch64Cpu;
-pub const AmdGpuCpu = @import("cpu/AmdGpuCpu.zig").AmdGpuCpu;
-pub const ArmCpu = @import("cpu/ArmCpu.zig").ArmCpu;
-pub const AvrCpu = @import("cpu/AvrCpu.zig").AvrCpu;
-pub const BpfCpu = @import("cpu/BpfCpu.zig").BpfCpu;
-pub const HexagonCpu = @import("cpu/HexagonCpu.zig").HexagonCpu;
-pub const MipsCpu = @import("cpu/MipsCpu.zig").MipsCpu;
-pub const Msp430Cpu = @import("cpu/Msp430Cpu.zig").Msp430Cpu;
-pub const NvptxCpu = @import("cpu/NvptxCpu.zig").NvptxCpu;
-pub const PowerPcCpu = @import("cpu/PowerPcCpu.zig").PowerPcCpu;
-pub const RiscVCpu = @import("cpu/RiscVCpu.zig").RiscVCpu;
-pub const SparcCpu = @import("cpu/SparcCpu.zig").SparcCpu;
-pub const SystemZCpu = @import("cpu/SystemZCpu.zig").SystemZCpu;
-pub const WebAssemblyCpu = @import("cpu/WebAssemblyCpu.zig").WebAssemblyCpu;
-pub const X86Cpu = @import("cpu/X86Cpu.zig").X86Cpu;
-
-pub const EmptyCpu = @import("cpu/empty.zig").EmptyCpu;
-
-pub fn ArchCpu(comptime arch: @TagType(Arch)) type {
- return switch (arch) {
- .arm, .armeb, .thumb, .thumbeb => ArmCpu,
- .aarch64, .aarch64_be, .aarch64_32 => AArch64Cpu,
- .avr => AvrCpu,
- .bpfel, .bpfeb => BpfCpu,
- .hexagon => HexagonCpu,
- .mips, .mipsel, .mips64, .mips64el => MipsCpu,
- .msp430 => Msp430Cpu,
- .powerpc, .powerpc64, .powerpc64le => PowerPcCpu,
- .amdgcn => AmdGpuCpu,
- .riscv32, .riscv64 => RiscVCpu,
- .sparc, .sparcv9, .sparcel => SparcCpu,
- .s390x => SystemZCpu,
- .i386, .x86_64 => X86Cpu,
- .nvptx, .nvptx64 => NvptxCpu,
- .wasm32, .wasm64 => WebAssemblyCpu,
-
- else => EmptyCpu,
- };
-}
-
-pub fn ArchCpuInfo(comptime arch: @TagType(Arch)) type {
- return CpuInfo(ArchCpu(arch), feature.ArchFeature(arch));
-}
-
-pub fn CpuInfo(comptime CpuType: type, comptime FeatureType: type) type {
- return struct {
- value: CpuType,
- name: []const u8,
-
- features: []const FeatureType,
-
- const Self = @This();
-
- pub fn create(value: CpuType, name: []const u8, features: []const FeatureType) Self {
- return Self {
- .value = value,
- .name = name,
- .features = features,
- };
- }
- };
-}
lib/std/target/feature.zig
@@ -1,81 +0,0 @@
-const builtin = @import("builtin");
-const std = @import("std");
-const Arch = std.Target.Arch;
-
-pub const AArch64Feature = @import("feature/AArch64Feature.zig").AArch64Feature;
-pub const AmdGpuFeature = @import("feature/AmdGpuFeature.zig").AmdGpuFeature;
-pub const ArmFeature = @import("feature/ArmFeature.zig").ArmFeature;
-pub const AvrFeature = @import("feature/AvrFeature.zig").AvrFeature;
-pub const BpfFeature = @import("feature/BpfFeature.zig").BpfFeature;
-pub const HexagonFeature = @import("feature/HexagonFeature.zig").HexagonFeature; pub const MipsFeature = @import("feature/MipsFeature.zig").MipsFeature;
-pub const Msp430Feature = @import("feature/Msp430Feature.zig").Msp430Feature;
-pub const NvptxFeature = @import("feature/NvptxFeature.zig").NvptxFeature;
-pub const PowerPcFeature = @import("feature/PowerPcFeature.zig").PowerPcFeature;
-pub const RiscVFeature = @import("feature/RiscVFeature.zig").RiscVFeature;
-pub const SparcFeature = @import("feature/SparcFeature.zig").SparcFeature;
-pub const SystemZFeature = @import("feature/SystemZFeature.zig").SystemZFeature;
-pub const WebAssemblyFeature = @import("feature/WebAssemblyFeature.zig").WebAssemblyFeature;
-pub const X86Feature = @import("feature/X86Feature.zig").X86Feature;
-
-pub const EmptyFeature = @import("feature/empty.zig").EmptyFeature;
-
-pub fn ArchFeature(comptime arch: @TagType(Arch)) type {
- return switch (arch) {
- .arm, .armeb, .thumb, .thumbeb => ArmFeature,
- .aarch64, .aarch64_be, .aarch64_32 => AArch64Feature,
- .avr => AvrFeature,
- .bpfel, .bpfeb => BpfFeature,
- .hexagon => HexagonFeature,
- .mips, .mipsel, .mips64, .mips64el => MipsFeature,
- .msp430 => Msp430Feature,
- .powerpc, .powerpc64, .powerpc64le => PowerPcFeature,
- .amdgcn => AmdGpuFeature,
- .riscv32, .riscv64 => RiscVFeature,
- .sparc, .sparcv9, .sparcel => SparcFeature,
- .s390x => SystemZFeature,
- .i386, .x86_64 => X86Feature,
- .nvptx, .nvptx64 => NvptxFeature,
- .wasm32, .wasm64 => WebAssemblyFeature,
-
- else => EmptyFeature,
- };
-}
-
-pub fn ArchFeatureInfo(comptime arch: @TagType(Arch)) type {
- return FeatureInfo(ArchFeature(arch));
-}
-
-pub fn FeatureInfo(comptime EnumType: type) type {
- return struct {
- value: EnumType,
- name: []const u8,
- description: []const u8,
- llvm_name: []const u8,
-
- subfeatures: []const EnumType,
-
- const Self = @This();
-
- pub fn create(value: EnumType, name: []const u8, description: []const u8, llvm_name: []const u8) Self {
- return Self {
- .value = value,
- .name = name,
- .description = description,
- .llvm_name = llvm_name,
-
- .subfeatures = &[_]EnumType{},
- };
- }
-
- pub fn createWithSubfeatures(value: EnumType, name: []const u8, description: []const u8, llvm_name: []const u8, subfeatures: []const EnumType) Self {
- return Self {
- .value = value,
- .name = name,
- .description = description,
- .llvm_name = llvm_name,
-
- .subfeatures = subfeatures,
- };
- }
- };
-}
lib/std/target/hexagon.zig
@@ -0,0 +1,357 @@
+const Feature = @import("std").target.Feature;
+const Cpu = @import("std").target.Cpu;
+
+pub const feature_v5 = Feature{
+ .name = "v5",
+ .description = "Enable Hexagon V5 architecture",
+ .llvm_name = "v5",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_v55 = Feature{
+ .name = "v55",
+ .description = "Enable Hexagon V55 architecture",
+ .llvm_name = "v55",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_v60 = Feature{
+ .name = "v60",
+ .description = "Enable Hexagon V60 architecture",
+ .llvm_name = "v60",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_v62 = Feature{
+ .name = "v62",
+ .description = "Enable Hexagon V62 architecture",
+ .llvm_name = "v62",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_v65 = Feature{
+ .name = "v65",
+ .description = "Enable Hexagon V65 architecture",
+ .llvm_name = "v65",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_v66 = Feature{
+ .name = "v66",
+ .description = "Enable Hexagon V66 architecture",
+ .llvm_name = "v66",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_hvx = Feature{
+ .name = "hvx",
+ .description = "Hexagon HVX instructions",
+ .llvm_name = "hvx",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_hvxLength64b = Feature{
+ .name = "hvx-length64b",
+ .description = "Hexagon HVX 64B instructions",
+ .llvm_name = "hvx-length64b",
+ .subfeatures = &[_]*const Feature {
+ &feature_hvx,
+ },
+};
+
+pub const feature_hvxLength128b = Feature{
+ .name = "hvx-length128b",
+ .description = "Hexagon HVX 128B instructions",
+ .llvm_name = "hvx-length128b",
+ .subfeatures = &[_]*const Feature {
+ &feature_hvx,
+ },
+};
+
+pub const feature_hvxv60 = Feature{
+ .name = "hvxv60",
+ .description = "Hexagon HVX instructions",
+ .llvm_name = "hvxv60",
+ .subfeatures = &[_]*const Feature {
+ &feature_hvx,
+ },
+};
+
+pub const feature_hvxv62 = Feature{
+ .name = "hvxv62",
+ .description = "Hexagon HVX instructions",
+ .llvm_name = "hvxv62",
+ .subfeatures = &[_]*const Feature {
+ &feature_hvx,
+ },
+};
+
+pub const feature_hvxv65 = Feature{
+ .name = "hvxv65",
+ .description = "Hexagon HVX instructions",
+ .llvm_name = "hvxv65",
+ .subfeatures = &[_]*const Feature {
+ &feature_hvx,
+ },
+};
+
+pub const feature_hvxv66 = Feature{
+ .name = "hvxv66",
+ .description = "Hexagon HVX instructions",
+ .llvm_name = "hvxv66",
+ .subfeatures = &[_]*const Feature {
+ &feature_zreg,
+ &feature_hvx,
+ },
+};
+
+pub const feature_zreg = Feature{
+ .name = "zreg",
+ .description = "Hexagon ZReg extension instructions",
+ .llvm_name = "zreg",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_duplex = Feature{
+ .name = "duplex",
+ .description = "Enable generation of duplex instruction",
+ .llvm_name = "duplex",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_longCalls = Feature{
+ .name = "long-calls",
+ .description = "Use constant-extended calls",
+ .llvm_name = "long-calls",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mem_noshuf = Feature{
+ .name = "mem_noshuf",
+ .description = "Supports mem_noshuf feature",
+ .llvm_name = "mem_noshuf",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_memops = Feature{
+ .name = "memops",
+ .description = "Use memop instructions",
+ .llvm_name = "memops",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_nvj = Feature{
+ .name = "nvj",
+ .description = "Support for new-value jumps",
+ .llvm_name = "nvj",
+ .subfeatures = &[_]*const Feature {
+ &feature_packets,
+ },
+};
+
+pub const feature_nvs = Feature{
+ .name = "nvs",
+ .description = "Support for new-value stores",
+ .llvm_name = "nvs",
+ .subfeatures = &[_]*const Feature {
+ &feature_packets,
+ },
+};
+
+pub const feature_noreturnStackElim = Feature{
+ .name = "noreturn-stack-elim",
+ .description = "Eliminate stack allocation in a noreturn function when possible",
+ .llvm_name = "noreturn-stack-elim",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_packets = Feature{
+ .name = "packets",
+ .description = "Support for instruction packets",
+ .llvm_name = "packets",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_reservedR19 = Feature{
+ .name = "reserved-r19",
+ .description = "Reserve register R19",
+ .llvm_name = "reserved-r19",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_smallData = Feature{
+ .name = "small-data",
+ .description = "Allow GP-relative addressing of global variables",
+ .llvm_name = "small-data",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const features = &[_]*const Feature {
+ &feature_v5,
+ &feature_v55,
+ &feature_v60,
+ &feature_v62,
+ &feature_v65,
+ &feature_v66,
+ &feature_hvx,
+ &feature_hvxLength64b,
+ &feature_hvxLength128b,
+ &feature_hvxv60,
+ &feature_hvxv62,
+ &feature_hvxv65,
+ &feature_hvxv66,
+ &feature_zreg,
+ &feature_duplex,
+ &feature_longCalls,
+ &feature_mem_noshuf,
+ &feature_memops,
+ &feature_nvj,
+ &feature_nvs,
+ &feature_noreturnStackElim,
+ &feature_packets,
+ &feature_reservedR19,
+ &feature_smallData,
+};
+
+pub const cpu_generic = Cpu{
+ .name = "generic",
+ .llvm_name = "generic",
+ .subfeatures = &[_]*const Feature {
+ &feature_v5,
+ &feature_v55,
+ &feature_v60,
+ &feature_duplex,
+ &feature_memops,
+ &feature_packets,
+ &feature_nvj,
+ &feature_nvs,
+ &feature_smallData,
+ },
+};
+
+pub const cpu_hexagonv5 = Cpu{
+ .name = "hexagonv5",
+ .llvm_name = "hexagonv5",
+ .subfeatures = &[_]*const Feature {
+ &feature_v5,
+ &feature_duplex,
+ &feature_memops,
+ &feature_packets,
+ &feature_nvj,
+ &feature_nvs,
+ &feature_smallData,
+ },
+};
+
+pub const cpu_hexagonv55 = Cpu{
+ .name = "hexagonv55",
+ .llvm_name = "hexagonv55",
+ .subfeatures = &[_]*const Feature {
+ &feature_v5,
+ &feature_v55,
+ &feature_duplex,
+ &feature_memops,
+ &feature_packets,
+ &feature_nvj,
+ &feature_nvs,
+ &feature_smallData,
+ },
+};
+
+pub const cpu_hexagonv60 = Cpu{
+ .name = "hexagonv60",
+ .llvm_name = "hexagonv60",
+ .subfeatures = &[_]*const Feature {
+ &feature_v5,
+ &feature_v55,
+ &feature_v60,
+ &feature_duplex,
+ &feature_memops,
+ &feature_packets,
+ &feature_nvj,
+ &feature_nvs,
+ &feature_smallData,
+ },
+};
+
+pub const cpu_hexagonv62 = Cpu{
+ .name = "hexagonv62",
+ .llvm_name = "hexagonv62",
+ .subfeatures = &[_]*const Feature {
+ &feature_v5,
+ &feature_v55,
+ &feature_v60,
+ &feature_v62,
+ &feature_duplex,
+ &feature_memops,
+ &feature_packets,
+ &feature_nvj,
+ &feature_nvs,
+ &feature_smallData,
+ },
+};
+
+pub const cpu_hexagonv65 = Cpu{
+ .name = "hexagonv65",
+ .llvm_name = "hexagonv65",
+ .subfeatures = &[_]*const Feature {
+ &feature_v5,
+ &feature_v55,
+ &feature_v60,
+ &feature_v62,
+ &feature_v65,
+ &feature_duplex,
+ &feature_mem_noshuf,
+ &feature_memops,
+ &feature_packets,
+ &feature_nvj,
+ &feature_nvs,
+ &feature_smallData,
+ },
+};
+
+pub const cpu_hexagonv66 = Cpu{
+ .name = "hexagonv66",
+ .llvm_name = "hexagonv66",
+ .subfeatures = &[_]*const Feature {
+ &feature_v5,
+ &feature_v55,
+ &feature_v60,
+ &feature_v62,
+ &feature_v65,
+ &feature_v66,
+ &feature_duplex,
+ &feature_mem_noshuf,
+ &feature_memops,
+ &feature_packets,
+ &feature_nvj,
+ &feature_nvs,
+ &feature_smallData,
+ },
+};
+
+pub const cpus = &[_]*const Cpu {
+ &cpu_generic,
+ &cpu_hexagonv5,
+ &cpu_hexagonv55,
+ &cpu_hexagonv60,
+ &cpu_hexagonv62,
+ &cpu_hexagonv65,
+ &cpu_hexagonv66,
+};
lib/std/target/mips.zig
@@ -0,0 +1,828 @@
+const Feature = @import("std").target.Feature;
+const Cpu = @import("std").target.Cpu;
+
+pub const feature_abs2008 = Feature{
+ .name = "abs2008",
+ .description = "Disable IEEE 754-2008 abs.fmt mode",
+ .llvm_name = "abs2008",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_crc = Feature{
+ .name = "crc",
+ .description = "Mips R6 CRC ASE",
+ .llvm_name = "crc",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_cnmips = Feature{
+ .name = "cnmips",
+ .description = "Octeon cnMIPS Support",
+ .llvm_name = "cnmips",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_gp64,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_fp64,
+ },
+};
+
+pub const feature_dsp = Feature{
+ .name = "dsp",
+ .description = "Mips DSP ASE",
+ .llvm_name = "dsp",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dspr2 = Feature{
+ .name = "dspr2",
+ .description = "Mips DSP-R2 ASE",
+ .llvm_name = "dspr2",
+ .subfeatures = &[_]*const Feature {
+ &feature_dsp,
+ },
+};
+
+pub const feature_dspr3 = Feature{
+ .name = "dspr3",
+ .description = "Mips DSP-R3 ASE",
+ .llvm_name = "dspr3",
+ .subfeatures = &[_]*const Feature {
+ &feature_dsp,
+ },
+};
+
+pub const feature_eva = Feature{
+ .name = "eva",
+ .description = "Mips EVA ASE",
+ .llvm_name = "eva",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fp64 = Feature{
+ .name = "fp64",
+ .description = "Support 64-bit FP registers",
+ .llvm_name = "fp64",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fpxx = Feature{
+ .name = "fpxx",
+ .description = "Support for FPXX",
+ .llvm_name = "fpxx",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ginv = Feature{
+ .name = "ginv",
+ .description = "Mips Global Invalidate ASE",
+ .llvm_name = "ginv",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_gp64 = Feature{
+ .name = "gp64",
+ .description = "General Purpose Registers are 64-bit wide",
+ .llvm_name = "gp64",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_longCalls = Feature{
+ .name = "long-calls",
+ .description = "Disable use of the jal instruction",
+ .llvm_name = "long-calls",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_msa = Feature{
+ .name = "msa",
+ .description = "Mips MSA ASE",
+ .llvm_name = "msa",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mt = Feature{
+ .name = "mt",
+ .description = "Mips MT ASE",
+ .llvm_name = "mt",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_nomadd4 = Feature{
+ .name = "nomadd4",
+ .description = "Disable 4-operand madd.fmt and related instructions",
+ .llvm_name = "nomadd4",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_micromips = Feature{
+ .name = "micromips",
+ .description = "microMips mode",
+ .llvm_name = "micromips",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mips1 = Feature{
+ .name = "mips1",
+ .description = "Mips I ISA Support [highly experimental]",
+ .llvm_name = "mips1",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mips2 = Feature{
+ .name = "mips2",
+ .description = "Mips II ISA Support [highly experimental]",
+ .llvm_name = "mips2",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips1,
+ },
+};
+
+pub const feature_mips3 = Feature{
+ .name = "mips3",
+ .description = "MIPS III ISA Support [highly experimental]",
+ .llvm_name = "mips3",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_gp64,
+ &feature_mips3_32,
+ &feature_fp64,
+ },
+};
+
+pub const feature_mips3_32 = Feature{
+ .name = "mips3_32",
+ .description = "Subset of MIPS-III that is also in MIPS32 [highly experimental]",
+ .llvm_name = "mips3_32",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mips3_32r2 = Feature{
+ .name = "mips3_32r2",
+ .description = "Subset of MIPS-III that is also in MIPS32r2 [highly experimental]",
+ .llvm_name = "mips3_32r2",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mips4 = Feature{
+ .name = "mips4",
+ .description = "MIPS IV ISA Support",
+ .llvm_name = "mips4",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_gp64,
+ &feature_mips4_32r2,
+ &feature_mips3_32,
+ &feature_fp64,
+ },
+};
+
+pub const feature_mips4_32 = Feature{
+ .name = "mips4_32",
+ .description = "Subset of MIPS-IV that is also in MIPS32 [highly experimental]",
+ .llvm_name = "mips4_32",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mips4_32r2 = Feature{
+ .name = "mips4_32r2",
+ .description = "Subset of MIPS-IV that is also in MIPS32r2 [highly experimental]",
+ .llvm_name = "mips4_32r2",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mips5 = Feature{
+ .name = "mips5",
+ .description = "MIPS V ISA Support [highly experimental]",
+ .llvm_name = "mips5",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_gp64,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_fp64,
+ },
+};
+
+pub const feature_mips5_32r2 = Feature{
+ .name = "mips5_32r2",
+ .description = "Subset of MIPS-V that is also in MIPS32r2 [highly experimental]",
+ .llvm_name = "mips5_32r2",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mips16 = Feature{
+ .name = "mips16",
+ .description = "Mips16 mode",
+ .llvm_name = "mips16",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mips32 = Feature{
+ .name = "mips32",
+ .description = "Mips32 ISA Support",
+ .llvm_name = "mips32",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32,
+ &feature_mips1,
+ },
+};
+
+pub const feature_mips32r2 = Feature{
+ .name = "mips32r2",
+ .description = "Mips32r2 ISA Support",
+ .llvm_name = "mips32r2",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ },
+};
+
+pub const feature_mips32r3 = Feature{
+ .name = "mips32r3",
+ .description = "Mips32r3 ISA Support",
+ .llvm_name = "mips32r3",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ },
+};
+
+pub const feature_mips32r5 = Feature{
+ .name = "mips32r5",
+ .description = "Mips32r5 ISA Support",
+ .llvm_name = "mips32r5",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ },
+};
+
+pub const feature_mips32r6 = Feature{
+ .name = "mips32r6",
+ .description = "Mips32r6 ISA Support [experimental]",
+ .llvm_name = "mips32r6",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_nan2008,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_abs2008,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_fp64,
+ },
+};
+
+pub const feature_mips64 = Feature{
+ .name = "mips64",
+ .description = "Mips64 ISA Support",
+ .llvm_name = "mips64",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_gp64,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_fp64,
+ },
+};
+
+pub const feature_mips64r2 = Feature{
+ .name = "mips64r2",
+ .description = "Mips64r2 ISA Support",
+ .llvm_name = "mips64r2",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_gp64,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_fp64,
+ },
+};
+
+pub const feature_mips64r3 = Feature{
+ .name = "mips64r3",
+ .description = "Mips64r3 ISA Support",
+ .llvm_name = "mips64r3",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_gp64,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_fp64,
+ },
+};
+
+pub const feature_mips64r5 = Feature{
+ .name = "mips64r5",
+ .description = "Mips64r5 ISA Support",
+ .llvm_name = "mips64r5",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_gp64,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_fp64,
+ },
+};
+
+pub const feature_mips64r6 = Feature{
+ .name = "mips64r6",
+ .description = "Mips64r6 ISA Support [experimental]",
+ .llvm_name = "mips64r6",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_nan2008,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_abs2008,
+ &feature_gp64,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_fp64,
+ },
+};
+
+pub const feature_nan2008 = Feature{
+ .name = "nan2008",
+ .description = "IEEE 754-2008 NaN encoding",
+ .llvm_name = "nan2008",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_noabicalls = Feature{
+ .name = "noabicalls",
+ .description = "Disable SVR4-style position-independent code",
+ .llvm_name = "noabicalls",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_nooddspreg = Feature{
+ .name = "nooddspreg",
+ .description = "Disable odd numbered single-precision registers",
+ .llvm_name = "nooddspreg",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ptr64 = Feature{
+ .name = "ptr64",
+ .description = "Pointers are 64-bit wide",
+ .llvm_name = "ptr64",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_singleFloat = Feature{
+ .name = "single-float",
+ .description = "Only supports single precision float",
+ .llvm_name = "single-float",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_softFloat = Feature{
+ .name = "soft-float",
+ .description = "Does not support floating point instructions",
+ .llvm_name = "soft-float",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sym32 = Feature{
+ .name = "sym32",
+ .description = "Symbols are 32 bit on Mips64",
+ .llvm_name = "sym32",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_useIndirectJumpHazard = Feature{
+ .name = "use-indirect-jump-hazard",
+ .description = "Use indirect jump guards to prevent certain speculation based attacks",
+ .llvm_name = "use-indirect-jump-hazard",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_useTccInDiv = Feature{
+ .name = "use-tcc-in-div",
+ .description = "Force the assembler to use trapping",
+ .llvm_name = "use-tcc-in-div",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vfpu = Feature{
+ .name = "vfpu",
+ .description = "Enable vector FPU instructions",
+ .llvm_name = "vfpu",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_virt = Feature{
+ .name = "virt",
+ .description = "Mips Virtualization ASE",
+ .llvm_name = "virt",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_xgot = Feature{
+ .name = "xgot",
+ .description = "Assume 32-bit GOT",
+ .llvm_name = "xgot",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_p5600 = Feature{
+ .name = "p5600",
+ .description = "The P5600 Processor",
+ .llvm_name = "p5600",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ },
+};
+
+pub const features = &[_]*const Feature {
+ &feature_abs2008,
+ &feature_crc,
+ &feature_cnmips,
+ &feature_dsp,
+ &feature_dspr2,
+ &feature_dspr3,
+ &feature_eva,
+ &feature_fp64,
+ &feature_fpxx,
+ &feature_ginv,
+ &feature_gp64,
+ &feature_longCalls,
+ &feature_msa,
+ &feature_mt,
+ &feature_nomadd4,
+ &feature_micromips,
+ &feature_mips1,
+ &feature_mips2,
+ &feature_mips3,
+ &feature_mips3_32,
+ &feature_mips3_32r2,
+ &feature_mips4,
+ &feature_mips4_32,
+ &feature_mips4_32r2,
+ &feature_mips5,
+ &feature_mips5_32r2,
+ &feature_mips16,
+ &feature_mips32,
+ &feature_mips32r2,
+ &feature_mips32r3,
+ &feature_mips32r5,
+ &feature_mips32r6,
+ &feature_mips64,
+ &feature_mips64r2,
+ &feature_mips64r3,
+ &feature_mips64r5,
+ &feature_mips64r6,
+ &feature_nan2008,
+ &feature_noabicalls,
+ &feature_nooddspreg,
+ &feature_ptr64,
+ &feature_singleFloat,
+ &feature_softFloat,
+ &feature_sym32,
+ &feature_useIndirectJumpHazard,
+ &feature_useTccInDiv,
+ &feature_vfpu,
+ &feature_virt,
+ &feature_xgot,
+ &feature_p5600,
+};
+
+pub const cpu_mips1 = Cpu{
+ .name = "mips1",
+ .llvm_name = "mips1",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips1,
+ },
+};
+
+pub const cpu_mips2 = Cpu{
+ .name = "mips2",
+ .llvm_name = "mips2",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips1,
+ &feature_mips2,
+ },
+};
+
+pub const cpu_mips3 = Cpu{
+ .name = "mips3",
+ .llvm_name = "mips3",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_gp64,
+ &feature_mips3_32,
+ &feature_fp64,
+ &feature_mips3,
+ },
+};
+
+pub const cpu_mips32 = Cpu{
+ .name = "mips32",
+ .llvm_name = "mips32",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32,
+ &feature_mips1,
+ &feature_mips32,
+ },
+};
+
+pub const cpu_mips32r2 = Cpu{
+ .name = "mips32r2",
+ .llvm_name = "mips32r2",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_mips32r2,
+ },
+};
+
+pub const cpu_mips32r3 = Cpu{
+ .name = "mips32r3",
+ .llvm_name = "mips32r3",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_mips32r3,
+ },
+};
+
+pub const cpu_mips32r5 = Cpu{
+ .name = "mips32r5",
+ .llvm_name = "mips32r5",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_mips32r5,
+ },
+};
+
+pub const cpu_mips32r6 = Cpu{
+ .name = "mips32r6",
+ .llvm_name = "mips32r6",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_nan2008,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_abs2008,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_fp64,
+ &feature_mips32r6,
+ },
+};
+
+pub const cpu_mips4 = Cpu{
+ .name = "mips4",
+ .llvm_name = "mips4",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_gp64,
+ &feature_mips4_32r2,
+ &feature_mips3_32,
+ &feature_fp64,
+ &feature_mips4,
+ },
+};
+
+pub const cpu_mips5 = Cpu{
+ .name = "mips5",
+ .llvm_name = "mips5",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_gp64,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_fp64,
+ &feature_mips5,
+ },
+};
+
+pub const cpu_mips64 = Cpu{
+ .name = "mips64",
+ .llvm_name = "mips64",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_gp64,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_fp64,
+ &feature_mips64,
+ },
+};
+
+pub const cpu_mips64r2 = Cpu{
+ .name = "mips64r2",
+ .llvm_name = "mips64r2",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_gp64,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_fp64,
+ &feature_mips64r2,
+ },
+};
+
+pub const cpu_mips64r3 = Cpu{
+ .name = "mips64r3",
+ .llvm_name = "mips64r3",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_gp64,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_fp64,
+ &feature_mips64r3,
+ },
+};
+
+pub const cpu_mips64r5 = Cpu{
+ .name = "mips64r5",
+ .llvm_name = "mips64r5",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_gp64,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_fp64,
+ &feature_mips64r5,
+ },
+};
+
+pub const cpu_mips64r6 = Cpu{
+ .name = "mips64r6",
+ .llvm_name = "mips64r6",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_nan2008,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_abs2008,
+ &feature_gp64,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_fp64,
+ &feature_mips64r6,
+ },
+};
+
+pub const cpu_octeon = Cpu{
+ .name = "octeon",
+ .llvm_name = "octeon",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_gp64,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_fp64,
+ &feature_cnmips,
+ &feature_mips64r2,
+ },
+};
+
+pub const cpu_p5600 = Cpu{
+ .name = "p5600",
+ .llvm_name = "p5600",
+ .subfeatures = &[_]*const Feature {
+ &feature_mips4_32,
+ &feature_mips3_32r2,
+ &feature_mips1,
+ &feature_mips4_32r2,
+ &feature_mips5_32r2,
+ &feature_mips3_32,
+ &feature_p5600,
+ },
+};
+
+pub const cpus = &[_]*const Cpu {
+ &cpu_mips1,
+ &cpu_mips2,
+ &cpu_mips3,
+ &cpu_mips32,
+ &cpu_mips32r2,
+ &cpu_mips32r3,
+ &cpu_mips32r5,
+ &cpu_mips32r6,
+ &cpu_mips4,
+ &cpu_mips5,
+ &cpu_mips64,
+ &cpu_mips64r2,
+ &cpu_mips64r3,
+ &cpu_mips64r5,
+ &cpu_mips64r6,
+ &cpu_octeon,
+ &cpu_p5600,
+};
lib/std/target/msp430.zig
@@ -0,0 +1,69 @@
+const Feature = @import("std").target.Feature;
+const Cpu = @import("std").target.Cpu;
+
+pub const feature_hwmult16 = Feature{
+ .name = "hwmult16",
+ .description = "Enable 16-bit hardware multiplier",
+ .llvm_name = "hwmult16",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_hwmult32 = Feature{
+ .name = "hwmult32",
+ .description = "Enable 32-bit hardware multiplier",
+ .llvm_name = "hwmult32",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_hwmultf5 = Feature{
+ .name = "hwmultf5",
+ .description = "Enable F5 series hardware multiplier",
+ .llvm_name = "hwmultf5",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ext = Feature{
+ .name = "ext",
+ .description = "Enable MSP430-X extensions",
+ .llvm_name = "ext",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const features = &[_]*const Feature {
+ &feature_hwmult16,
+ &feature_hwmult32,
+ &feature_hwmultf5,
+ &feature_ext,
+};
+
+pub const cpu_generic = Cpu{
+ .name = "generic",
+ .llvm_name = "generic",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_msp430 = Cpu{
+ .name = "msp430",
+ .llvm_name = "msp430",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_msp430x = Cpu{
+ .name = "msp430x",
+ .llvm_name = "msp430x",
+ .subfeatures = &[_]*const Feature {
+ &feature_ext,
+ },
+};
+
+pub const cpus = &[_]*const Cpu {
+ &cpu_generic,
+ &cpu_msp430,
+ &cpu_msp430x,
+};
lib/std/target/nvptx.zig
@@ -0,0 +1,379 @@
+const Feature = @import("std").target.Feature;
+const Cpu = @import("std").target.Cpu;
+
+pub const feature_ptx32 = Feature{
+ .name = "ptx32",
+ .description = "Use PTX version 3.2",
+ .llvm_name = "ptx32",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ptx40 = Feature{
+ .name = "ptx40",
+ .description = "Use PTX version 4.0",
+ .llvm_name = "ptx40",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ptx41 = Feature{
+ .name = "ptx41",
+ .description = "Use PTX version 4.1",
+ .llvm_name = "ptx41",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ptx42 = Feature{
+ .name = "ptx42",
+ .description = "Use PTX version 4.2",
+ .llvm_name = "ptx42",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ptx43 = Feature{
+ .name = "ptx43",
+ .description = "Use PTX version 4.3",
+ .llvm_name = "ptx43",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ptx50 = Feature{
+ .name = "ptx50",
+ .description = "Use PTX version 5.0",
+ .llvm_name = "ptx50",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ptx60 = Feature{
+ .name = "ptx60",
+ .description = "Use PTX version 6.0",
+ .llvm_name = "ptx60",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ptx61 = Feature{
+ .name = "ptx61",
+ .description = "Use PTX version 6.1",
+ .llvm_name = "ptx61",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ptx63 = Feature{
+ .name = "ptx63",
+ .description = "Use PTX version 6.3",
+ .llvm_name = "ptx63",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ptx64 = Feature{
+ .name = "ptx64",
+ .description = "Use PTX version 6.4",
+ .llvm_name = "ptx64",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sm_20 = Feature{
+ .name = "sm_20",
+ .description = "Target SM 2.0",
+ .llvm_name = "sm_20",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sm_21 = Feature{
+ .name = "sm_21",
+ .description = "Target SM 2.1",
+ .llvm_name = "sm_21",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sm_30 = Feature{
+ .name = "sm_30",
+ .description = "Target SM 3.0",
+ .llvm_name = "sm_30",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sm_32 = Feature{
+ .name = "sm_32",
+ .description = "Target SM 3.2",
+ .llvm_name = "sm_32",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sm_35 = Feature{
+ .name = "sm_35",
+ .description = "Target SM 3.5",
+ .llvm_name = "sm_35",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sm_37 = Feature{
+ .name = "sm_37",
+ .description = "Target SM 3.7",
+ .llvm_name = "sm_37",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sm_50 = Feature{
+ .name = "sm_50",
+ .description = "Target SM 5.0",
+ .llvm_name = "sm_50",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sm_52 = Feature{
+ .name = "sm_52",
+ .description = "Target SM 5.2",
+ .llvm_name = "sm_52",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sm_53 = Feature{
+ .name = "sm_53",
+ .description = "Target SM 5.3",
+ .llvm_name = "sm_53",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sm_60 = Feature{
+ .name = "sm_60",
+ .description = "Target SM 6.0",
+ .llvm_name = "sm_60",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sm_61 = Feature{
+ .name = "sm_61",
+ .description = "Target SM 6.1",
+ .llvm_name = "sm_61",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sm_62 = Feature{
+ .name = "sm_62",
+ .description = "Target SM 6.2",
+ .llvm_name = "sm_62",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sm_70 = Feature{
+ .name = "sm_70",
+ .description = "Target SM 7.0",
+ .llvm_name = "sm_70",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sm_72 = Feature{
+ .name = "sm_72",
+ .description = "Target SM 7.2",
+ .llvm_name = "sm_72",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sm_75 = Feature{
+ .name = "sm_75",
+ .description = "Target SM 7.5",
+ .llvm_name = "sm_75",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const features = &[_]*const Feature {
+ &feature_ptx32,
+ &feature_ptx40,
+ &feature_ptx41,
+ &feature_ptx42,
+ &feature_ptx43,
+ &feature_ptx50,
+ &feature_ptx60,
+ &feature_ptx61,
+ &feature_ptx63,
+ &feature_ptx64,
+ &feature_sm_20,
+ &feature_sm_21,
+ &feature_sm_30,
+ &feature_sm_32,
+ &feature_sm_35,
+ &feature_sm_37,
+ &feature_sm_50,
+ &feature_sm_52,
+ &feature_sm_53,
+ &feature_sm_60,
+ &feature_sm_61,
+ &feature_sm_62,
+ &feature_sm_70,
+ &feature_sm_72,
+ &feature_sm_75,
+};
+
+pub const cpu_sm_20 = Cpu{
+ .name = "sm_20",
+ .llvm_name = "sm_20",
+ .subfeatures = &[_]*const Feature {
+ &feature_sm_20,
+ },
+};
+
+pub const cpu_sm_21 = Cpu{
+ .name = "sm_21",
+ .llvm_name = "sm_21",
+ .subfeatures = &[_]*const Feature {
+ &feature_sm_21,
+ },
+};
+
+pub const cpu_sm_30 = Cpu{
+ .name = "sm_30",
+ .llvm_name = "sm_30",
+ .subfeatures = &[_]*const Feature {
+ &feature_sm_30,
+ },
+};
+
+pub const cpu_sm_32 = Cpu{
+ .name = "sm_32",
+ .llvm_name = "sm_32",
+ .subfeatures = &[_]*const Feature {
+ &feature_ptx40,
+ &feature_sm_32,
+ },
+};
+
+pub const cpu_sm_35 = Cpu{
+ .name = "sm_35",
+ .llvm_name = "sm_35",
+ .subfeatures = &[_]*const Feature {
+ &feature_sm_35,
+ },
+};
+
+pub const cpu_sm_37 = Cpu{
+ .name = "sm_37",
+ .llvm_name = "sm_37",
+ .subfeatures = &[_]*const Feature {
+ &feature_ptx41,
+ &feature_sm_37,
+ },
+};
+
+pub const cpu_sm_50 = Cpu{
+ .name = "sm_50",
+ .llvm_name = "sm_50",
+ .subfeatures = &[_]*const Feature {
+ &feature_ptx40,
+ &feature_sm_50,
+ },
+};
+
+pub const cpu_sm_52 = Cpu{
+ .name = "sm_52",
+ .llvm_name = "sm_52",
+ .subfeatures = &[_]*const Feature {
+ &feature_ptx41,
+ &feature_sm_52,
+ },
+};
+
+pub const cpu_sm_53 = Cpu{
+ .name = "sm_53",
+ .llvm_name = "sm_53",
+ .subfeatures = &[_]*const Feature {
+ &feature_ptx42,
+ &feature_sm_53,
+ },
+};
+
+pub const cpu_sm_60 = Cpu{
+ .name = "sm_60",
+ .llvm_name = "sm_60",
+ .subfeatures = &[_]*const Feature {
+ &feature_ptx50,
+ &feature_sm_60,
+ },
+};
+
+pub const cpu_sm_61 = Cpu{
+ .name = "sm_61",
+ .llvm_name = "sm_61",
+ .subfeatures = &[_]*const Feature {
+ &feature_ptx50,
+ &feature_sm_61,
+ },
+};
+
+pub const cpu_sm_62 = Cpu{
+ .name = "sm_62",
+ .llvm_name = "sm_62",
+ .subfeatures = &[_]*const Feature {
+ &feature_ptx50,
+ &feature_sm_62,
+ },
+};
+
+pub const cpu_sm_70 = Cpu{
+ .name = "sm_70",
+ .llvm_name = "sm_70",
+ .subfeatures = &[_]*const Feature {
+ &feature_ptx60,
+ &feature_sm_70,
+ },
+};
+
+pub const cpu_sm_72 = Cpu{
+ .name = "sm_72",
+ .llvm_name = "sm_72",
+ .subfeatures = &[_]*const Feature {
+ &feature_ptx61,
+ &feature_sm_72,
+ },
+};
+
+pub const cpu_sm_75 = Cpu{
+ .name = "sm_75",
+ .llvm_name = "sm_75",
+ .subfeatures = &[_]*const Feature {
+ &feature_ptx63,
+ &feature_sm_75,
+ },
+};
+
+pub const cpus = &[_]*const Cpu {
+ &cpu_sm_20,
+ &cpu_sm_21,
+ &cpu_sm_30,
+ &cpu_sm_32,
+ &cpu_sm_35,
+ &cpu_sm_37,
+ &cpu_sm_50,
+ &cpu_sm_52,
+ &cpu_sm_53,
+ &cpu_sm_60,
+ &cpu_sm_61,
+ &cpu_sm_62,
+ &cpu_sm_70,
+ &cpu_sm_72,
+ &cpu_sm_75,
+};
lib/std/target/powerpc.zig
@@ -0,0 +1,1115 @@
+const Feature = @import("std").target.Feature;
+const Cpu = @import("std").target.Cpu;
+
+pub const feature_bit64 = Feature{
+ .name = "64bit",
+ .description = "Enable 64-bit instructions",
+ .llvm_name = "64bit",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_bitregs64 = Feature{
+ .name = "64bitregs",
+ .description = "Enable 64-bit registers usage for ppc32 [beta]",
+ .llvm_name = "64bitregs",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_altivec = Feature{
+ .name = "altivec",
+ .description = "Enable Altivec instructions",
+ .llvm_name = "altivec",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_bpermd = Feature{
+ .name = "bpermd",
+ .description = "Enable the bpermd instruction",
+ .llvm_name = "bpermd",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_booke = Feature{
+ .name = "booke",
+ .description = "Enable Book E instructions",
+ .llvm_name = "booke",
+ .subfeatures = &[_]*const Feature {
+ &feature_icbt,
+ },
+};
+
+pub const feature_cmpb = Feature{
+ .name = "cmpb",
+ .description = "Enable the cmpb instruction",
+ .llvm_name = "cmpb",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_crbits = Feature{
+ .name = "crbits",
+ .description = "Use condition-register bits individually",
+ .llvm_name = "crbits",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_directMove = Feature{
+ .name = "direct-move",
+ .description = "Enable Power8 direct move instructions",
+ .llvm_name = "direct-move",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_e500 = Feature{
+ .name = "e500",
+ .description = "Enable E500/E500mc instructions",
+ .llvm_name = "e500",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_extdiv = Feature{
+ .name = "extdiv",
+ .description = "Enable extended divide instructions",
+ .llvm_name = "extdiv",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fcpsgn = Feature{
+ .name = "fcpsgn",
+ .description = "Enable the fcpsgn instruction",
+ .llvm_name = "fcpsgn",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_fpcvt = Feature{
+ .name = "fpcvt",
+ .description = "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
+ .llvm_name = "fpcvt",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_fprnd = Feature{
+ .name = "fprnd",
+ .description = "Enable the fri[mnpz] instructions",
+ .llvm_name = "fprnd",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_fpu = Feature{
+ .name = "fpu",
+ .description = "Enable classic FPU instructions",
+ .llvm_name = "fpu",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_fre = Feature{
+ .name = "fre",
+ .description = "Enable the fre instruction",
+ .llvm_name = "fre",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_fres = Feature{
+ .name = "fres",
+ .description = "Enable the fres instruction",
+ .llvm_name = "fres",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_frsqrte = Feature{
+ .name = "frsqrte",
+ .description = "Enable the frsqrte instruction",
+ .llvm_name = "frsqrte",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_frsqrtes = Feature{
+ .name = "frsqrtes",
+ .description = "Enable the frsqrtes instruction",
+ .llvm_name = "frsqrtes",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_fsqrt = Feature{
+ .name = "fsqrt",
+ .description = "Enable the fsqrt instruction",
+ .llvm_name = "fsqrt",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_float128 = Feature{
+ .name = "float128",
+ .description = "Enable the __float128 data type for IEEE-754R Binary128.",
+ .llvm_name = "float128",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_htm = Feature{
+ .name = "htm",
+ .description = "Enable Hardware Transactional Memory instructions",
+ .llvm_name = "htm",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_hardFloat = Feature{
+ .name = "hard-float",
+ .description = "Enable floating-point instructions",
+ .llvm_name = "hard-float",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_icbt = Feature{
+ .name = "icbt",
+ .description = "Enable icbt instruction",
+ .llvm_name = "icbt",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_isaV30Instructions = Feature{
+ .name = "isa-v30-instructions",
+ .description = "Enable instructions added in ISA 3.0.",
+ .llvm_name = "isa-v30-instructions",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_isel = Feature{
+ .name = "isel",
+ .description = "Enable the isel instruction",
+ .llvm_name = "isel",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_invariantFunctionDescriptors = Feature{
+ .name = "invariant-function-descriptors",
+ .description = "Assume function descriptors are invariant",
+ .llvm_name = "invariant-function-descriptors",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ldbrx = Feature{
+ .name = "ldbrx",
+ .description = "Enable the ldbrx instruction",
+ .llvm_name = "ldbrx",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_lfiwax = Feature{
+ .name = "lfiwax",
+ .description = "Enable the lfiwax instruction",
+ .llvm_name = "lfiwax",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_longcall = Feature{
+ .name = "longcall",
+ .description = "Always use indirect calls",
+ .llvm_name = "longcall",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mfocrf = Feature{
+ .name = "mfocrf",
+ .description = "Enable the MFOCRF instruction",
+ .llvm_name = "mfocrf",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_msync = Feature{
+ .name = "msync",
+ .description = "Has only the msync instruction instead of sync",
+ .llvm_name = "msync",
+ .subfeatures = &[_]*const Feature {
+ &feature_icbt,
+ },
+};
+
+pub const feature_power8Altivec = Feature{
+ .name = "power8-altivec",
+ .description = "Enable POWER8 Altivec instructions",
+ .llvm_name = "power8-altivec",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_crypto = Feature{
+ .name = "crypto",
+ .description = "Enable POWER8 Crypto instructions",
+ .llvm_name = "crypto",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_power8Vector = Feature{
+ .name = "power8-vector",
+ .description = "Enable POWER8 vector instructions",
+ .llvm_name = "power8-vector",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_power9Altivec = Feature{
+ .name = "power9-altivec",
+ .description = "Enable POWER9 Altivec instructions",
+ .llvm_name = "power9-altivec",
+ .subfeatures = &[_]*const Feature {
+ &feature_isaV30Instructions,
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_power9Vector = Feature{
+ .name = "power9-vector",
+ .description = "Enable POWER9 vector instructions",
+ .llvm_name = "power9-vector",
+ .subfeatures = &[_]*const Feature {
+ &feature_isaV30Instructions,
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_popcntd = Feature{
+ .name = "popcntd",
+ .description = "Enable the popcnt[dw] instructions",
+ .llvm_name = "popcntd",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ppc4xx = Feature{
+ .name = "ppc4xx",
+ .description = "Enable PPC 4xx instructions",
+ .llvm_name = "ppc4xx",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ppc6xx = Feature{
+ .name = "ppc6xx",
+ .description = "Enable PPC 6xx instructions",
+ .llvm_name = "ppc6xx",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ppcPostraSched = Feature{
+ .name = "ppc-postra-sched",
+ .description = "Use PowerPC post-RA scheduling strategy",
+ .llvm_name = "ppc-postra-sched",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ppcPreraSched = Feature{
+ .name = "ppc-prera-sched",
+ .description = "Use PowerPC pre-RA scheduling strategy",
+ .llvm_name = "ppc-prera-sched",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_partwordAtomics = Feature{
+ .name = "partword-atomics",
+ .description = "Enable l[bh]arx and st[bh]cx.",
+ .llvm_name = "partword-atomics",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_qpx = Feature{
+ .name = "qpx",
+ .description = "Enable QPX instructions",
+ .llvm_name = "qpx",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_recipprec = Feature{
+ .name = "recipprec",
+ .description = "Assume higher precision reciprocal estimates",
+ .llvm_name = "recipprec",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_spe = Feature{
+ .name = "spe",
+ .description = "Enable SPE instructions",
+ .llvm_name = "spe",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_stfiwx = Feature{
+ .name = "stfiwx",
+ .description = "Enable the stfiwx instruction",
+ .llvm_name = "stfiwx",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_securePlt = Feature{
+ .name = "secure-plt",
+ .description = "Enable secure plt mode",
+ .llvm_name = "secure-plt",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_slowPopcntd = Feature{
+ .name = "slow-popcntd",
+ .description = "Has slow popcnt[dw] instructions",
+ .llvm_name = "slow-popcntd",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_twoConstNr = Feature{
+ .name = "two-const-nr",
+ .description = "Requires two constant Newton-Raphson computation",
+ .llvm_name = "two-const-nr",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vsx = Feature{
+ .name = "vsx",
+ .description = "Enable VSX instructions",
+ .llvm_name = "vsx",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const feature_vectorsUseTwoUnits = Feature{
+ .name = "vectors-use-two-units",
+ .description = "Vectors use two units",
+ .llvm_name = "vectors-use-two-units",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const features = &[_]*const Feature {
+ &feature_bit64,
+ &feature_bitregs64,
+ &feature_altivec,
+ &feature_bpermd,
+ &feature_booke,
+ &feature_cmpb,
+ &feature_crbits,
+ &feature_directMove,
+ &feature_e500,
+ &feature_extdiv,
+ &feature_fcpsgn,
+ &feature_fpcvt,
+ &feature_fprnd,
+ &feature_fpu,
+ &feature_fre,
+ &feature_fres,
+ &feature_frsqrte,
+ &feature_frsqrtes,
+ &feature_fsqrt,
+ &feature_float128,
+ &feature_htm,
+ &feature_hardFloat,
+ &feature_icbt,
+ &feature_isaV30Instructions,
+ &feature_isel,
+ &feature_invariantFunctionDescriptors,
+ &feature_ldbrx,
+ &feature_lfiwax,
+ &feature_longcall,
+ &feature_mfocrf,
+ &feature_msync,
+ &feature_power8Altivec,
+ &feature_crypto,
+ &feature_power8Vector,
+ &feature_power9Altivec,
+ &feature_power9Vector,
+ &feature_popcntd,
+ &feature_ppc4xx,
+ &feature_ppc6xx,
+ &feature_ppcPostraSched,
+ &feature_ppcPreraSched,
+ &feature_partwordAtomics,
+ &feature_qpx,
+ &feature_recipprec,
+ &feature_spe,
+ &feature_stfiwx,
+ &feature_securePlt,
+ &feature_slowPopcntd,
+ &feature_twoConstNr,
+ &feature_vsx,
+ &feature_vectorsUseTwoUnits,
+};
+
+pub const cpu_440 = Cpu{
+ .name = "440",
+ .llvm_name = "440",
+ .subfeatures = &[_]*const Feature {
+ &feature_icbt,
+ &feature_booke,
+ &feature_hardFloat,
+ &feature_fres,
+ &feature_frsqrte,
+ &feature_isel,
+ &feature_msync,
+ },
+};
+
+pub const cpu_450 = Cpu{
+ .name = "450",
+ .llvm_name = "450",
+ .subfeatures = &[_]*const Feature {
+ &feature_icbt,
+ &feature_booke,
+ &feature_hardFloat,
+ &feature_fres,
+ &feature_frsqrte,
+ &feature_isel,
+ &feature_msync,
+ },
+};
+
+pub const cpu_601 = Cpu{
+ .name = "601",
+ .llvm_name = "601",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ &feature_fpu,
+ },
+};
+
+pub const cpu_602 = Cpu{
+ .name = "602",
+ .llvm_name = "602",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ &feature_fpu,
+ },
+};
+
+pub const cpu_603 = Cpu{
+ .name = "603",
+ .llvm_name = "603",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ &feature_fres,
+ &feature_frsqrte,
+ },
+};
+
+pub const cpu_e603 = Cpu{
+ .name = "603e",
+ .llvm_name = "603e",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ &feature_fres,
+ &feature_frsqrte,
+ },
+};
+
+pub const cpu_ev603 = Cpu{
+ .name = "603ev",
+ .llvm_name = "603ev",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ &feature_fres,
+ &feature_frsqrte,
+ },
+};
+
+pub const cpu_604 = Cpu{
+ .name = "604",
+ .llvm_name = "604",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ &feature_fres,
+ &feature_frsqrte,
+ },
+};
+
+pub const cpu_e604 = Cpu{
+ .name = "604e",
+ .llvm_name = "604e",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ &feature_fres,
+ &feature_frsqrte,
+ },
+};
+
+pub const cpu_620 = Cpu{
+ .name = "620",
+ .llvm_name = "620",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ &feature_fres,
+ &feature_frsqrte,
+ },
+};
+
+pub const cpu_7400 = Cpu{
+ .name = "7400",
+ .llvm_name = "7400",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ &feature_altivec,
+ &feature_fres,
+ &feature_frsqrte,
+ },
+};
+
+pub const cpu_7450 = Cpu{
+ .name = "7450",
+ .llvm_name = "7450",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ &feature_altivec,
+ &feature_fres,
+ &feature_frsqrte,
+ },
+};
+
+pub const cpu_750 = Cpu{
+ .name = "750",
+ .llvm_name = "750",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ &feature_fres,
+ &feature_frsqrte,
+ },
+};
+
+pub const cpu_970 = Cpu{
+ .name = "970",
+ .llvm_name = "970",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_hardFloat,
+ &feature_altivec,
+ &feature_fres,
+ &feature_frsqrte,
+ &feature_fsqrt,
+ &feature_mfocrf,
+ &feature_stfiwx,
+ },
+};
+
+pub const cpu_a2 = Cpu{
+ .name = "a2",
+ .llvm_name = "a2",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_icbt,
+ &feature_booke,
+ &feature_cmpb,
+ &feature_hardFloat,
+ &feature_fcpsgn,
+ &feature_fpcvt,
+ &feature_fprnd,
+ &feature_fre,
+ &feature_fres,
+ &feature_frsqrte,
+ &feature_frsqrtes,
+ &feature_fsqrt,
+ &feature_isel,
+ &feature_ldbrx,
+ &feature_lfiwax,
+ &feature_mfocrf,
+ &feature_recipprec,
+ &feature_stfiwx,
+ &feature_slowPopcntd,
+ },
+};
+
+pub const cpu_a2q = Cpu{
+ .name = "a2q",
+ .llvm_name = "a2q",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_icbt,
+ &feature_booke,
+ &feature_cmpb,
+ &feature_hardFloat,
+ &feature_fcpsgn,
+ &feature_fpcvt,
+ &feature_fprnd,
+ &feature_fre,
+ &feature_fres,
+ &feature_frsqrte,
+ &feature_frsqrtes,
+ &feature_fsqrt,
+ &feature_isel,
+ &feature_ldbrx,
+ &feature_lfiwax,
+ &feature_mfocrf,
+ &feature_qpx,
+ &feature_recipprec,
+ &feature_stfiwx,
+ &feature_slowPopcntd,
+ },
+};
+
+pub const cpu_e500 = Cpu{
+ .name = "e500",
+ .llvm_name = "e500",
+ .subfeatures = &[_]*const Feature {
+ &feature_icbt,
+ &feature_booke,
+ &feature_isel,
+ },
+};
+
+pub const cpu_e500mc = Cpu{
+ .name = "e500mc",
+ .llvm_name = "e500mc",
+ .subfeatures = &[_]*const Feature {
+ &feature_icbt,
+ &feature_booke,
+ &feature_isel,
+ &feature_hardFloat,
+ &feature_stfiwx,
+ },
+};
+
+pub const cpu_e5500 = Cpu{
+ .name = "e5500",
+ .llvm_name = "e5500",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_icbt,
+ &feature_booke,
+ &feature_isel,
+ &feature_mfocrf,
+ &feature_hardFloat,
+ &feature_stfiwx,
+ },
+};
+
+pub const cpu_g3 = Cpu{
+ .name = "g3",
+ .llvm_name = "g3",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ &feature_fres,
+ &feature_frsqrte,
+ },
+};
+
+pub const cpu_g4 = Cpu{
+ .name = "g4",
+ .llvm_name = "g4",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ &feature_altivec,
+ &feature_fres,
+ &feature_frsqrte,
+ },
+};
+
+pub const cpu_g4Plus = Cpu{
+ .name = "g4+",
+ .llvm_name = "g4+",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ &feature_altivec,
+ &feature_fres,
+ &feature_frsqrte,
+ },
+};
+
+pub const cpu_g5 = Cpu{
+ .name = "g5",
+ .llvm_name = "g5",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_hardFloat,
+ &feature_altivec,
+ &feature_fres,
+ &feature_frsqrte,
+ &feature_fsqrt,
+ &feature_mfocrf,
+ &feature_stfiwx,
+ },
+};
+
+pub const cpu_generic = Cpu{
+ .name = "generic",
+ .llvm_name = "generic",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const cpu_ppc = Cpu{
+ .name = "ppc",
+ .llvm_name = "ppc",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const cpu_ppc32 = Cpu{
+ .name = "ppc32",
+ .llvm_name = "ppc32",
+ .subfeatures = &[_]*const Feature {
+ &feature_hardFloat,
+ },
+};
+
+pub const cpu_ppc64 = Cpu{
+ .name = "ppc64",
+ .llvm_name = "ppc64",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_hardFloat,
+ &feature_altivec,
+ &feature_fres,
+ &feature_frsqrte,
+ &feature_fsqrt,
+ &feature_mfocrf,
+ &feature_stfiwx,
+ },
+};
+
+pub const cpu_ppc64le = Cpu{
+ .name = "ppc64le",
+ .llvm_name = "ppc64le",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_hardFloat,
+ &feature_altivec,
+ &feature_bpermd,
+ &feature_cmpb,
+ &feature_directMove,
+ &feature_extdiv,
+ &feature_fcpsgn,
+ &feature_fpcvt,
+ &feature_fprnd,
+ &feature_fre,
+ &feature_fres,
+ &feature_frsqrte,
+ &feature_frsqrtes,
+ &feature_fsqrt,
+ &feature_htm,
+ &feature_icbt,
+ &feature_isel,
+ &feature_ldbrx,
+ &feature_lfiwax,
+ &feature_mfocrf,
+ &feature_power8Altivec,
+ &feature_crypto,
+ &feature_power8Vector,
+ &feature_popcntd,
+ &feature_partwordAtomics,
+ &feature_recipprec,
+ &feature_stfiwx,
+ &feature_twoConstNr,
+ &feature_vsx,
+ },
+};
+
+pub const cpu_pwr3 = Cpu{
+ .name = "pwr3",
+ .llvm_name = "pwr3",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_hardFloat,
+ &feature_altivec,
+ &feature_fres,
+ &feature_frsqrte,
+ &feature_mfocrf,
+ &feature_stfiwx,
+ },
+};
+
+pub const cpu_pwr4 = Cpu{
+ .name = "pwr4",
+ .llvm_name = "pwr4",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_hardFloat,
+ &feature_altivec,
+ &feature_fres,
+ &feature_frsqrte,
+ &feature_fsqrt,
+ &feature_mfocrf,
+ &feature_stfiwx,
+ },
+};
+
+pub const cpu_pwr5 = Cpu{
+ .name = "pwr5",
+ .llvm_name = "pwr5",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_hardFloat,
+ &feature_altivec,
+ &feature_fre,
+ &feature_fres,
+ &feature_frsqrte,
+ &feature_frsqrtes,
+ &feature_fsqrt,
+ &feature_mfocrf,
+ &feature_stfiwx,
+ },
+};
+
+pub const cpu_pwr5x = Cpu{
+ .name = "pwr5x",
+ .llvm_name = "pwr5x",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_hardFloat,
+ &feature_altivec,
+ &feature_fprnd,
+ &feature_fre,
+ &feature_fres,
+ &feature_frsqrte,
+ &feature_frsqrtes,
+ &feature_fsqrt,
+ &feature_mfocrf,
+ &feature_stfiwx,
+ },
+};
+
+pub const cpu_pwr6 = Cpu{
+ .name = "pwr6",
+ .llvm_name = "pwr6",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_hardFloat,
+ &feature_altivec,
+ &feature_cmpb,
+ &feature_fcpsgn,
+ &feature_fprnd,
+ &feature_fre,
+ &feature_fres,
+ &feature_frsqrte,
+ &feature_frsqrtes,
+ &feature_fsqrt,
+ &feature_lfiwax,
+ &feature_mfocrf,
+ &feature_recipprec,
+ &feature_stfiwx,
+ },
+};
+
+pub const cpu_pwr6x = Cpu{
+ .name = "pwr6x",
+ .llvm_name = "pwr6x",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_hardFloat,
+ &feature_altivec,
+ &feature_cmpb,
+ &feature_fcpsgn,
+ &feature_fprnd,
+ &feature_fre,
+ &feature_fres,
+ &feature_frsqrte,
+ &feature_frsqrtes,
+ &feature_fsqrt,
+ &feature_lfiwax,
+ &feature_mfocrf,
+ &feature_recipprec,
+ &feature_stfiwx,
+ },
+};
+
+pub const cpu_pwr7 = Cpu{
+ .name = "pwr7",
+ .llvm_name = "pwr7",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_hardFloat,
+ &feature_altivec,
+ &feature_bpermd,
+ &feature_cmpb,
+ &feature_extdiv,
+ &feature_fcpsgn,
+ &feature_fpcvt,
+ &feature_fprnd,
+ &feature_fre,
+ &feature_fres,
+ &feature_frsqrte,
+ &feature_frsqrtes,
+ &feature_fsqrt,
+ &feature_isel,
+ &feature_ldbrx,
+ &feature_lfiwax,
+ &feature_mfocrf,
+ &feature_popcntd,
+ &feature_recipprec,
+ &feature_stfiwx,
+ &feature_twoConstNr,
+ &feature_vsx,
+ },
+};
+
+pub const cpu_pwr8 = Cpu{
+ .name = "pwr8",
+ .llvm_name = "pwr8",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_hardFloat,
+ &feature_altivec,
+ &feature_bpermd,
+ &feature_cmpb,
+ &feature_directMove,
+ &feature_extdiv,
+ &feature_fcpsgn,
+ &feature_fpcvt,
+ &feature_fprnd,
+ &feature_fre,
+ &feature_fres,
+ &feature_frsqrte,
+ &feature_frsqrtes,
+ &feature_fsqrt,
+ &feature_htm,
+ &feature_icbt,
+ &feature_isel,
+ &feature_ldbrx,
+ &feature_lfiwax,
+ &feature_mfocrf,
+ &feature_power8Altivec,
+ &feature_crypto,
+ &feature_power8Vector,
+ &feature_popcntd,
+ &feature_partwordAtomics,
+ &feature_recipprec,
+ &feature_stfiwx,
+ &feature_twoConstNr,
+ &feature_vsx,
+ },
+};
+
+pub const cpu_pwr9 = Cpu{
+ .name = "pwr9",
+ .llvm_name = "pwr9",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_hardFloat,
+ &feature_altivec,
+ &feature_bpermd,
+ &feature_cmpb,
+ &feature_directMove,
+ &feature_extdiv,
+ &feature_fcpsgn,
+ &feature_fpcvt,
+ &feature_fprnd,
+ &feature_fre,
+ &feature_fres,
+ &feature_frsqrte,
+ &feature_frsqrtes,
+ &feature_fsqrt,
+ &feature_htm,
+ &feature_icbt,
+ &feature_isaV30Instructions,
+ &feature_isel,
+ &feature_ldbrx,
+ &feature_lfiwax,
+ &feature_mfocrf,
+ &feature_power8Altivec,
+ &feature_crypto,
+ &feature_power8Vector,
+ &feature_power9Altivec,
+ &feature_power9Vector,
+ &feature_popcntd,
+ &feature_ppcPostraSched,
+ &feature_ppcPreraSched,
+ &feature_partwordAtomics,
+ &feature_recipprec,
+ &feature_stfiwx,
+ &feature_twoConstNr,
+ &feature_vsx,
+ &feature_vectorsUseTwoUnits,
+ },
+};
+
+pub const cpus = &[_]*const Cpu {
+ &cpu_440,
+ &cpu_450,
+ &cpu_601,
+ &cpu_602,
+ &cpu_603,
+ &cpu_e603,
+ &cpu_ev603,
+ &cpu_604,
+ &cpu_e604,
+ &cpu_620,
+ &cpu_7400,
+ &cpu_7450,
+ &cpu_750,
+ &cpu_970,
+ &cpu_a2,
+ &cpu_a2q,
+ &cpu_e500,
+ &cpu_e500mc,
+ &cpu_e5500,
+ &cpu_g3,
+ &cpu_g4,
+ &cpu_g4Plus,
+ &cpu_g5,
+ &cpu_generic,
+ &cpu_ppc,
+ &cpu_ppc32,
+ &cpu_ppc64,
+ &cpu_ppc64le,
+ &cpu_pwr3,
+ &cpu_pwr4,
+ &cpu_pwr5,
+ &cpu_pwr5x,
+ &cpu_pwr6,
+ &cpu_pwr6x,
+ &cpu_pwr7,
+ &cpu_pwr8,
+ &cpu_pwr9,
+};
lib/std/target/riscv.zig
@@ -0,0 +1,109 @@
+const Feature = @import("std").target.Feature;
+const Cpu = @import("std").target.Cpu;
+
+pub const feature_bit64 = Feature{
+ .name = "64bit",
+ .description = "Implements RV64",
+ .llvm_name = "64bit",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_e = Feature{
+ .name = "e",
+ .description = "Implements RV32E (provides 16 rather than 32 GPRs)",
+ .llvm_name = "e",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_rvcHints = Feature{
+ .name = "rvc-hints",
+ .description = "Enable RVC Hint Instructions.",
+ .llvm_name = "rvc-hints",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_relax = Feature{
+ .name = "relax",
+ .description = "Enable Linker relaxation.",
+ .llvm_name = "relax",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_a = Feature{
+ .name = "a",
+ .description = "'A' (Atomic Instructions)",
+ .llvm_name = "a",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_c = Feature{
+ .name = "c",
+ .description = "'C' (Compressed Instructions)",
+ .llvm_name = "c",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_d = Feature{
+ .name = "d",
+ .description = "'D' (Double-Precision Floating-Point)",
+ .llvm_name = "d",
+ .subfeatures = &[_]*const Feature {
+ &feature_f,
+ },
+};
+
+pub const feature_f = Feature{
+ .name = "f",
+ .description = "'F' (Single-Precision Floating-Point)",
+ .llvm_name = "f",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_m = Feature{
+ .name = "m",
+ .description = "'M' (Integer Multiplication and Division)",
+ .llvm_name = "m",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const features = &[_]*const Feature {
+ &feature_bit64,
+ &feature_e,
+ &feature_rvcHints,
+ &feature_relax,
+ &feature_a,
+ &feature_c,
+ &feature_d,
+ &feature_f,
+ &feature_m,
+};
+
+pub const cpu_genericRv32 = Cpu{
+ .name = "generic-rv32",
+ .llvm_name = "generic-rv32",
+ .subfeatures = &[_]*const Feature {
+ &feature_rvcHints,
+ },
+};
+
+pub const cpu_genericRv64 = Cpu{
+ .name = "generic-rv64",
+ .llvm_name = "generic-rv64",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_rvcHints,
+ },
+};
+
+pub const cpus = &[_]*const Cpu {
+ &cpu_genericRv32,
+ &cpu_genericRv64,
+};
lib/std/target/sparc.zig
@@ -0,0 +1,581 @@
+const Feature = @import("std").target.Feature;
+const Cpu = @import("std").target.Cpu;
+
+pub const feature_detectroundchange = Feature{
+ .name = "detectroundchange",
+ .description = "LEON3 erratum detection: Detects any rounding mode change request: use only the round-to-nearest rounding mode",
+ .llvm_name = "detectroundchange",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_hardQuadFloat = Feature{
+ .name = "hard-quad-float",
+ .description = "Enable quad-word floating point instructions",
+ .llvm_name = "hard-quad-float",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_leon = Feature{
+ .name = "leon",
+ .description = "Enable LEON extensions",
+ .llvm_name = "leon",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_noFmuls = Feature{
+ .name = "no-fmuls",
+ .description = "Disable the fmuls instruction.",
+ .llvm_name = "no-fmuls",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_noFsmuld = Feature{
+ .name = "no-fsmuld",
+ .description = "Disable the fsmuld instruction.",
+ .llvm_name = "no-fsmuld",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_leonpwrpsr = Feature{
+ .name = "leonpwrpsr",
+ .description = "Enable the PWRPSR instruction",
+ .llvm_name = "leonpwrpsr",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_softFloat = Feature{
+ .name = "soft-float",
+ .description = "Use software emulation for floating point",
+ .llvm_name = "soft-float",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_softMulDiv = Feature{
+ .name = "soft-mul-div",
+ .description = "Use software emulation for integer multiply and divide",
+ .llvm_name = "soft-mul-div",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_deprecatedV8 = Feature{
+ .name = "deprecated-v8",
+ .description = "Enable deprecated V8 instructions in V9 mode",
+ .llvm_name = "deprecated-v8",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_v9 = Feature{
+ .name = "v9",
+ .description = "Enable SPARC-V9 instructions",
+ .llvm_name = "v9",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vis = Feature{
+ .name = "vis",
+ .description = "Enable UltraSPARC Visual Instruction Set extensions",
+ .llvm_name = "vis",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vis2 = Feature{
+ .name = "vis2",
+ .description = "Enable Visual Instruction Set extensions II",
+ .llvm_name = "vis2",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vis3 = Feature{
+ .name = "vis3",
+ .description = "Enable Visual Instruction Set extensions III",
+ .llvm_name = "vis3",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fixallfdivsqrt = Feature{
+ .name = "fixallfdivsqrt",
+ .description = "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store",
+ .llvm_name = "fixallfdivsqrt",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_insertnopload = Feature{
+ .name = "insertnopload",
+ .description = "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction",
+ .llvm_name = "insertnopload",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_hasleoncasa = Feature{
+ .name = "hasleoncasa",
+ .description = "Enable CASA instruction for LEON3 and LEON4 processors",
+ .llvm_name = "hasleoncasa",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_leoncyclecounter = Feature{
+ .name = "leoncyclecounter",
+ .description = "Use the Leon cycle counter register",
+ .llvm_name = "leoncyclecounter",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_hasumacsmac = Feature{
+ .name = "hasumacsmac",
+ .description = "Enable UMAC and SMAC for LEON3 and LEON4 processors",
+ .llvm_name = "hasumacsmac",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_popc = Feature{
+ .name = "popc",
+ .description = "Use the popc (population count) instruction",
+ .llvm_name = "popc",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const features = &[_]*const Feature {
+ &feature_detectroundchange,
+ &feature_hardQuadFloat,
+ &feature_leon,
+ &feature_noFmuls,
+ &feature_noFsmuld,
+ &feature_leonpwrpsr,
+ &feature_softFloat,
+ &feature_softMulDiv,
+ &feature_deprecatedV8,
+ &feature_v9,
+ &feature_vis,
+ &feature_vis2,
+ &feature_vis3,
+ &feature_fixallfdivsqrt,
+ &feature_insertnopload,
+ &feature_hasleoncasa,
+ &feature_leoncyclecounter,
+ &feature_hasumacsmac,
+ &feature_popc,
+};
+
+pub const cpu_at697e = Cpu{
+ .name = "at697e",
+ .llvm_name = "at697e",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_insertnopload,
+ },
+};
+
+pub const cpu_at697f = Cpu{
+ .name = "at697f",
+ .llvm_name = "at697f",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_insertnopload,
+ },
+};
+
+pub const cpu_f934 = Cpu{
+ .name = "f934",
+ .llvm_name = "f934",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_generic = Cpu{
+ .name = "generic",
+ .llvm_name = "generic",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_gr712rc = Cpu{
+ .name = "gr712rc",
+ .llvm_name = "gr712rc",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_hasleoncasa,
+ },
+};
+
+pub const cpu_gr740 = Cpu{
+ .name = "gr740",
+ .llvm_name = "gr740",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_leonpwrpsr,
+ &feature_hasleoncasa,
+ &feature_leoncyclecounter,
+ &feature_hasumacsmac,
+ },
+};
+
+pub const cpu_hypersparc = Cpu{
+ .name = "hypersparc",
+ .llvm_name = "hypersparc",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_leon2 = Cpu{
+ .name = "leon2",
+ .llvm_name = "leon2",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ },
+};
+
+pub const cpu_leon3 = Cpu{
+ .name = "leon3",
+ .llvm_name = "leon3",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_hasumacsmac,
+ },
+};
+
+pub const cpu_leon4 = Cpu{
+ .name = "leon4",
+ .llvm_name = "leon4",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_hasleoncasa,
+ &feature_hasumacsmac,
+ },
+};
+
+pub const cpu_ma2080 = Cpu{
+ .name = "ma2080",
+ .llvm_name = "ma2080",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_hasleoncasa,
+ },
+};
+
+pub const cpu_ma2085 = Cpu{
+ .name = "ma2085",
+ .llvm_name = "ma2085",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_hasleoncasa,
+ },
+};
+
+pub const cpu_ma2100 = Cpu{
+ .name = "ma2100",
+ .llvm_name = "ma2100",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_hasleoncasa,
+ },
+};
+
+pub const cpu_ma2150 = Cpu{
+ .name = "ma2150",
+ .llvm_name = "ma2150",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_hasleoncasa,
+ },
+};
+
+pub const cpu_ma2155 = Cpu{
+ .name = "ma2155",
+ .llvm_name = "ma2155",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_hasleoncasa,
+ },
+};
+
+pub const cpu_ma2450 = Cpu{
+ .name = "ma2450",
+ .llvm_name = "ma2450",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_hasleoncasa,
+ },
+};
+
+pub const cpu_ma2455 = Cpu{
+ .name = "ma2455",
+ .llvm_name = "ma2455",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_hasleoncasa,
+ },
+};
+
+pub const cpu_ma2480 = Cpu{
+ .name = "ma2480",
+ .llvm_name = "ma2480",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_hasleoncasa,
+ },
+};
+
+pub const cpu_ma2485 = Cpu{
+ .name = "ma2485",
+ .llvm_name = "ma2485",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_hasleoncasa,
+ },
+};
+
+pub const cpu_ma2x5x = Cpu{
+ .name = "ma2x5x",
+ .llvm_name = "ma2x5x",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_hasleoncasa,
+ },
+};
+
+pub const cpu_ma2x8x = Cpu{
+ .name = "ma2x8x",
+ .llvm_name = "ma2x8x",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_hasleoncasa,
+ },
+};
+
+pub const cpu_myriad2 = Cpu{
+ .name = "myriad2",
+ .llvm_name = "myriad2",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_hasleoncasa,
+ },
+};
+
+pub const cpu_myriad21 = Cpu{
+ .name = "myriad2.1",
+ .llvm_name = "myriad2.1",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_hasleoncasa,
+ },
+};
+
+pub const cpu_myriad22 = Cpu{
+ .name = "myriad2.2",
+ .llvm_name = "myriad2.2",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_hasleoncasa,
+ },
+};
+
+pub const cpu_myriad23 = Cpu{
+ .name = "myriad2.3",
+ .llvm_name = "myriad2.3",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_hasleoncasa,
+ },
+};
+
+pub const cpu_niagara = Cpu{
+ .name = "niagara",
+ .llvm_name = "niagara",
+ .subfeatures = &[_]*const Feature {
+ &feature_deprecatedV8,
+ &feature_v9,
+ &feature_vis,
+ &feature_vis2,
+ },
+};
+
+pub const cpu_niagara2 = Cpu{
+ .name = "niagara2",
+ .llvm_name = "niagara2",
+ .subfeatures = &[_]*const Feature {
+ &feature_deprecatedV8,
+ &feature_v9,
+ &feature_vis,
+ &feature_vis2,
+ &feature_popc,
+ },
+};
+
+pub const cpu_niagara3 = Cpu{
+ .name = "niagara3",
+ .llvm_name = "niagara3",
+ .subfeatures = &[_]*const Feature {
+ &feature_deprecatedV8,
+ &feature_v9,
+ &feature_vis,
+ &feature_vis2,
+ &feature_popc,
+ },
+};
+
+pub const cpu_niagara4 = Cpu{
+ .name = "niagara4",
+ .llvm_name = "niagara4",
+ .subfeatures = &[_]*const Feature {
+ &feature_deprecatedV8,
+ &feature_v9,
+ &feature_vis,
+ &feature_vis2,
+ &feature_vis3,
+ &feature_popc,
+ },
+};
+
+pub const cpu_sparclet = Cpu{
+ .name = "sparclet",
+ .llvm_name = "sparclet",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_sparclite = Cpu{
+ .name = "sparclite",
+ .llvm_name = "sparclite",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_sparclite86x = Cpu{
+ .name = "sparclite86x",
+ .llvm_name = "sparclite86x",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_supersparc = Cpu{
+ .name = "supersparc",
+ .llvm_name = "supersparc",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_tsc701 = Cpu{
+ .name = "tsc701",
+ .llvm_name = "tsc701",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_ultrasparc = Cpu{
+ .name = "ultrasparc",
+ .llvm_name = "ultrasparc",
+ .subfeatures = &[_]*const Feature {
+ &feature_deprecatedV8,
+ &feature_v9,
+ &feature_vis,
+ },
+};
+
+pub const cpu_ultrasparc3 = Cpu{
+ .name = "ultrasparc3",
+ .llvm_name = "ultrasparc3",
+ .subfeatures = &[_]*const Feature {
+ &feature_deprecatedV8,
+ &feature_v9,
+ &feature_vis,
+ &feature_vis2,
+ },
+};
+
+pub const cpu_ut699 = Cpu{
+ .name = "ut699",
+ .llvm_name = "ut699",
+ .subfeatures = &[_]*const Feature {
+ &feature_leon,
+ &feature_noFmuls,
+ &feature_noFsmuld,
+ &feature_fixallfdivsqrt,
+ &feature_insertnopload,
+ },
+};
+
+pub const cpu_v7 = Cpu{
+ .name = "v7",
+ .llvm_name = "v7",
+ .subfeatures = &[_]*const Feature {
+ &feature_noFsmuld,
+ &feature_softMulDiv,
+ },
+};
+
+pub const cpu_v8 = Cpu{
+ .name = "v8",
+ .llvm_name = "v8",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_v9 = Cpu{
+ .name = "v9",
+ .llvm_name = "v9",
+ .subfeatures = &[_]*const Feature {
+ &feature_v9,
+ },
+};
+
+pub const cpus = &[_]*const Cpu {
+ &cpu_at697e,
+ &cpu_at697f,
+ &cpu_f934,
+ &cpu_generic,
+ &cpu_gr712rc,
+ &cpu_gr740,
+ &cpu_hypersparc,
+ &cpu_leon2,
+ &cpu_leon3,
+ &cpu_leon4,
+ &cpu_ma2080,
+ &cpu_ma2085,
+ &cpu_ma2100,
+ &cpu_ma2150,
+ &cpu_ma2155,
+ &cpu_ma2450,
+ &cpu_ma2455,
+ &cpu_ma2480,
+ &cpu_ma2485,
+ &cpu_ma2x5x,
+ &cpu_ma2x8x,
+ &cpu_myriad2,
+ &cpu_myriad21,
+ &cpu_myriad22,
+ &cpu_myriad23,
+ &cpu_niagara,
+ &cpu_niagara2,
+ &cpu_niagara3,
+ &cpu_niagara4,
+ &cpu_sparclet,
+ &cpu_sparclite,
+ &cpu_sparclite86x,
+ &cpu_supersparc,
+ &cpu_tsc701,
+ &cpu_ultrasparc,
+ &cpu_ultrasparc3,
+ &cpu_ut699,
+ &cpu_v7,
+ &cpu_v8,
+ &cpu_v9,
+};
lib/std/target/systemz.zig
@@ -0,0 +1,653 @@
+const Feature = @import("std").target.Feature;
+const Cpu = @import("std").target.Cpu;
+
+pub const feature_dfpPackedConversion = Feature{
+ .name = "dfp-packed-conversion",
+ .description = "Assume that the DFP packed-conversion facility is installed",
+ .llvm_name = "dfp-packed-conversion",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_dfpZonedConversion = Feature{
+ .name = "dfp-zoned-conversion",
+ .description = "Assume that the DFP zoned-conversion facility is installed",
+ .llvm_name = "dfp-zoned-conversion",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_deflateConversion = Feature{
+ .name = "deflate-conversion",
+ .description = "Assume that the deflate-conversion facility is installed",
+ .llvm_name = "deflate-conversion",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_distinctOps = Feature{
+ .name = "distinct-ops",
+ .description = "Assume that the distinct-operands facility is installed",
+ .llvm_name = "distinct-ops",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_enhancedDat2 = Feature{
+ .name = "enhanced-dat-2",
+ .description = "Assume that the enhanced-DAT facility 2 is installed",
+ .llvm_name = "enhanced-dat-2",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_enhancedSort = Feature{
+ .name = "enhanced-sort",
+ .description = "Assume that the enhanced-sort facility is installed",
+ .llvm_name = "enhanced-sort",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_executionHint = Feature{
+ .name = "execution-hint",
+ .description = "Assume that the execution-hint facility is installed",
+ .llvm_name = "execution-hint",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fpExtension = Feature{
+ .name = "fp-extension",
+ .description = "Assume that the floating-point extension facility is installed",
+ .llvm_name = "fp-extension",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fastSerialization = Feature{
+ .name = "fast-serialization",
+ .description = "Assume that the fast-serialization facility is installed",
+ .llvm_name = "fast-serialization",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_guardedStorage = Feature{
+ .name = "guarded-storage",
+ .description = "Assume that the guarded-storage facility is installed",
+ .llvm_name = "guarded-storage",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_highWord = Feature{
+ .name = "high-word",
+ .description = "Assume that the high-word facility is installed",
+ .llvm_name = "high-word",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_insertReferenceBitsMultiple = Feature{
+ .name = "insert-reference-bits-multiple",
+ .description = "Assume that the insert-reference-bits-multiple facility is installed",
+ .llvm_name = "insert-reference-bits-multiple",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_interlockedAccess1 = Feature{
+ .name = "interlocked-access1",
+ .description = "Assume that interlocked-access facility 1 is installed",
+ .llvm_name = "interlocked-access1",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_loadAndTrap = Feature{
+ .name = "load-and-trap",
+ .description = "Assume that the load-and-trap facility is installed",
+ .llvm_name = "load-and-trap",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_loadAndZeroRightmostByte = Feature{
+ .name = "load-and-zero-rightmost-byte",
+ .description = "Assume that the load-and-zero-rightmost-byte facility is installed",
+ .llvm_name = "load-and-zero-rightmost-byte",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_loadStoreOnCond = Feature{
+ .name = "load-store-on-cond",
+ .description = "Assume that the load/store-on-condition facility is installed",
+ .llvm_name = "load-store-on-cond",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_loadStoreOnCond2 = Feature{
+ .name = "load-store-on-cond-2",
+ .description = "Assume that the load/store-on-condition facility 2 is installed",
+ .llvm_name = "load-store-on-cond-2",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_messageSecurityAssistExtension3 = Feature{
+ .name = "message-security-assist-extension3",
+ .description = "Assume that the message-security-assist extension facility 3 is installed",
+ .llvm_name = "message-security-assist-extension3",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_messageSecurityAssistExtension4 = Feature{
+ .name = "message-security-assist-extension4",
+ .description = "Assume that the message-security-assist extension facility 4 is installed",
+ .llvm_name = "message-security-assist-extension4",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_messageSecurityAssistExtension5 = Feature{
+ .name = "message-security-assist-extension5",
+ .description = "Assume that the message-security-assist extension facility 5 is installed",
+ .llvm_name = "message-security-assist-extension5",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_messageSecurityAssistExtension7 = Feature{
+ .name = "message-security-assist-extension7",
+ .description = "Assume that the message-security-assist extension facility 7 is installed",
+ .llvm_name = "message-security-assist-extension7",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_messageSecurityAssistExtension8 = Feature{
+ .name = "message-security-assist-extension8",
+ .description = "Assume that the message-security-assist extension facility 8 is installed",
+ .llvm_name = "message-security-assist-extension8",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_messageSecurityAssistExtension9 = Feature{
+ .name = "message-security-assist-extension9",
+ .description = "Assume that the message-security-assist extension facility 9 is installed",
+ .llvm_name = "message-security-assist-extension9",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_miscellaneousExtensions = Feature{
+ .name = "miscellaneous-extensions",
+ .description = "Assume that the miscellaneous-extensions facility is installed",
+ .llvm_name = "miscellaneous-extensions",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_miscellaneousExtensions2 = Feature{
+ .name = "miscellaneous-extensions-2",
+ .description = "Assume that the miscellaneous-extensions facility 2 is installed",
+ .llvm_name = "miscellaneous-extensions-2",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_miscellaneousExtensions3 = Feature{
+ .name = "miscellaneous-extensions-3",
+ .description = "Assume that the miscellaneous-extensions facility 3 is installed",
+ .llvm_name = "miscellaneous-extensions-3",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_populationCount = Feature{
+ .name = "population-count",
+ .description = "Assume that the population-count facility is installed",
+ .llvm_name = "population-count",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_processorAssist = Feature{
+ .name = "processor-assist",
+ .description = "Assume that the processor-assist facility is installed",
+ .llvm_name = "processor-assist",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_resetReferenceBitsMultiple = Feature{
+ .name = "reset-reference-bits-multiple",
+ .description = "Assume that the reset-reference-bits-multiple facility is installed",
+ .llvm_name = "reset-reference-bits-multiple",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_transactionalExecution = Feature{
+ .name = "transactional-execution",
+ .description = "Assume that the transactional-execution facility is installed",
+ .llvm_name = "transactional-execution",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vector = Feature{
+ .name = "vector",
+ .description = "Assume that the vectory facility is installed",
+ .llvm_name = "vector",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vectorEnhancements1 = Feature{
+ .name = "vector-enhancements-1",
+ .description = "Assume that the vector enhancements facility 1 is installed",
+ .llvm_name = "vector-enhancements-1",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vectorEnhancements2 = Feature{
+ .name = "vector-enhancements-2",
+ .description = "Assume that the vector enhancements facility 2 is installed",
+ .llvm_name = "vector-enhancements-2",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vectorPackedDecimal = Feature{
+ .name = "vector-packed-decimal",
+ .description = "Assume that the vector packed decimal facility is installed",
+ .llvm_name = "vector-packed-decimal",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vectorPackedDecimalEnhancement = Feature{
+ .name = "vector-packed-decimal-enhancement",
+ .description = "Assume that the vector packed decimal enhancement facility is installed",
+ .llvm_name = "vector-packed-decimal-enhancement",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const features = &[_]*const Feature {
+ &feature_dfpPackedConversion,
+ &feature_dfpZonedConversion,
+ &feature_deflateConversion,
+ &feature_distinctOps,
+ &feature_enhancedDat2,
+ &feature_enhancedSort,
+ &feature_executionHint,
+ &feature_fpExtension,
+ &feature_fastSerialization,
+ &feature_guardedStorage,
+ &feature_highWord,
+ &feature_insertReferenceBitsMultiple,
+ &feature_interlockedAccess1,
+ &feature_loadAndTrap,
+ &feature_loadAndZeroRightmostByte,
+ &feature_loadStoreOnCond,
+ &feature_loadStoreOnCond2,
+ &feature_messageSecurityAssistExtension3,
+ &feature_messageSecurityAssistExtension4,
+ &feature_messageSecurityAssistExtension5,
+ &feature_messageSecurityAssistExtension7,
+ &feature_messageSecurityAssistExtension8,
+ &feature_messageSecurityAssistExtension9,
+ &feature_miscellaneousExtensions,
+ &feature_miscellaneousExtensions2,
+ &feature_miscellaneousExtensions3,
+ &feature_populationCount,
+ &feature_processorAssist,
+ &feature_resetReferenceBitsMultiple,
+ &feature_transactionalExecution,
+ &feature_vector,
+ &feature_vectorEnhancements1,
+ &feature_vectorEnhancements2,
+ &feature_vectorPackedDecimal,
+ &feature_vectorPackedDecimalEnhancement,
+};
+
+pub const cpu_arch10 = Cpu{
+ .name = "arch10",
+ .llvm_name = "arch10",
+ .subfeatures = &[_]*const Feature {
+ &feature_dfpZonedConversion,
+ &feature_distinctOps,
+ &feature_enhancedDat2,
+ &feature_executionHint,
+ &feature_fpExtension,
+ &feature_fastSerialization,
+ &feature_highWord,
+ &feature_interlockedAccess1,
+ &feature_loadAndTrap,
+ &feature_loadStoreOnCond,
+ &feature_messageSecurityAssistExtension3,
+ &feature_messageSecurityAssistExtension4,
+ &feature_miscellaneousExtensions,
+ &feature_populationCount,
+ &feature_processorAssist,
+ &feature_resetReferenceBitsMultiple,
+ &feature_transactionalExecution,
+ },
+};
+
+pub const cpu_arch11 = Cpu{
+ .name = "arch11",
+ .llvm_name = "arch11",
+ .subfeatures = &[_]*const Feature {
+ &feature_dfpPackedConversion,
+ &feature_dfpZonedConversion,
+ &feature_distinctOps,
+ &feature_enhancedDat2,
+ &feature_executionHint,
+ &feature_fpExtension,
+ &feature_fastSerialization,
+ &feature_highWord,
+ &feature_interlockedAccess1,
+ &feature_loadAndTrap,
+ &feature_loadAndZeroRightmostByte,
+ &feature_loadStoreOnCond,
+ &feature_loadStoreOnCond2,
+ &feature_messageSecurityAssistExtension3,
+ &feature_messageSecurityAssistExtension4,
+ &feature_messageSecurityAssistExtension5,
+ &feature_miscellaneousExtensions,
+ &feature_populationCount,
+ &feature_processorAssist,
+ &feature_resetReferenceBitsMultiple,
+ &feature_transactionalExecution,
+ &feature_vector,
+ },
+};
+
+pub const cpu_arch12 = Cpu{
+ .name = "arch12",
+ .llvm_name = "arch12",
+ .subfeatures = &[_]*const Feature {
+ &feature_dfpPackedConversion,
+ &feature_dfpZonedConversion,
+ &feature_distinctOps,
+ &feature_enhancedDat2,
+ &feature_executionHint,
+ &feature_fpExtension,
+ &feature_fastSerialization,
+ &feature_guardedStorage,
+ &feature_highWord,
+ &feature_insertReferenceBitsMultiple,
+ &feature_interlockedAccess1,
+ &feature_loadAndTrap,
+ &feature_loadAndZeroRightmostByte,
+ &feature_loadStoreOnCond,
+ &feature_loadStoreOnCond2,
+ &feature_messageSecurityAssistExtension3,
+ &feature_messageSecurityAssistExtension4,
+ &feature_messageSecurityAssistExtension5,
+ &feature_messageSecurityAssistExtension7,
+ &feature_messageSecurityAssistExtension8,
+ &feature_miscellaneousExtensions,
+ &feature_miscellaneousExtensions2,
+ &feature_populationCount,
+ &feature_processorAssist,
+ &feature_resetReferenceBitsMultiple,
+ &feature_transactionalExecution,
+ &feature_vector,
+ &feature_vectorEnhancements1,
+ &feature_vectorPackedDecimal,
+ },
+};
+
+pub const cpu_arch13 = Cpu{
+ .name = "arch13",
+ .llvm_name = "arch13",
+ .subfeatures = &[_]*const Feature {
+ &feature_dfpPackedConversion,
+ &feature_dfpZonedConversion,
+ &feature_deflateConversion,
+ &feature_distinctOps,
+ &feature_enhancedDat2,
+ &feature_enhancedSort,
+ &feature_executionHint,
+ &feature_fpExtension,
+ &feature_fastSerialization,
+ &feature_guardedStorage,
+ &feature_highWord,
+ &feature_insertReferenceBitsMultiple,
+ &feature_interlockedAccess1,
+ &feature_loadAndTrap,
+ &feature_loadAndZeroRightmostByte,
+ &feature_loadStoreOnCond,
+ &feature_loadStoreOnCond2,
+ &feature_messageSecurityAssistExtension3,
+ &feature_messageSecurityAssistExtension4,
+ &feature_messageSecurityAssistExtension5,
+ &feature_messageSecurityAssistExtension7,
+ &feature_messageSecurityAssistExtension8,
+ &feature_messageSecurityAssistExtension9,
+ &feature_miscellaneousExtensions,
+ &feature_miscellaneousExtensions2,
+ &feature_miscellaneousExtensions3,
+ &feature_populationCount,
+ &feature_processorAssist,
+ &feature_resetReferenceBitsMultiple,
+ &feature_transactionalExecution,
+ &feature_vector,
+ &feature_vectorEnhancements1,
+ &feature_vectorEnhancements2,
+ &feature_vectorPackedDecimal,
+ &feature_vectorPackedDecimalEnhancement,
+ },
+};
+
+pub const cpu_arch8 = Cpu{
+ .name = "arch8",
+ .llvm_name = "arch8",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_arch9 = Cpu{
+ .name = "arch9",
+ .llvm_name = "arch9",
+ .subfeatures = &[_]*const Feature {
+ &feature_distinctOps,
+ &feature_fpExtension,
+ &feature_fastSerialization,
+ &feature_highWord,
+ &feature_interlockedAccess1,
+ &feature_loadStoreOnCond,
+ &feature_messageSecurityAssistExtension3,
+ &feature_messageSecurityAssistExtension4,
+ &feature_populationCount,
+ &feature_resetReferenceBitsMultiple,
+ },
+};
+
+pub const cpu_generic = Cpu{
+ .name = "generic",
+ .llvm_name = "generic",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_z10 = Cpu{
+ .name = "z10",
+ .llvm_name = "z10",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_z13 = Cpu{
+ .name = "z13",
+ .llvm_name = "z13",
+ .subfeatures = &[_]*const Feature {
+ &feature_dfpPackedConversion,
+ &feature_dfpZonedConversion,
+ &feature_distinctOps,
+ &feature_enhancedDat2,
+ &feature_executionHint,
+ &feature_fpExtension,
+ &feature_fastSerialization,
+ &feature_highWord,
+ &feature_interlockedAccess1,
+ &feature_loadAndTrap,
+ &feature_loadAndZeroRightmostByte,
+ &feature_loadStoreOnCond,
+ &feature_loadStoreOnCond2,
+ &feature_messageSecurityAssistExtension3,
+ &feature_messageSecurityAssistExtension4,
+ &feature_messageSecurityAssistExtension5,
+ &feature_miscellaneousExtensions,
+ &feature_populationCount,
+ &feature_processorAssist,
+ &feature_resetReferenceBitsMultiple,
+ &feature_transactionalExecution,
+ &feature_vector,
+ },
+};
+
+pub const cpu_z14 = Cpu{
+ .name = "z14",
+ .llvm_name = "z14",
+ .subfeatures = &[_]*const Feature {
+ &feature_dfpPackedConversion,
+ &feature_dfpZonedConversion,
+ &feature_distinctOps,
+ &feature_enhancedDat2,
+ &feature_executionHint,
+ &feature_fpExtension,
+ &feature_fastSerialization,
+ &feature_guardedStorage,
+ &feature_highWord,
+ &feature_insertReferenceBitsMultiple,
+ &feature_interlockedAccess1,
+ &feature_loadAndTrap,
+ &feature_loadAndZeroRightmostByte,
+ &feature_loadStoreOnCond,
+ &feature_loadStoreOnCond2,
+ &feature_messageSecurityAssistExtension3,
+ &feature_messageSecurityAssistExtension4,
+ &feature_messageSecurityAssistExtension5,
+ &feature_messageSecurityAssistExtension7,
+ &feature_messageSecurityAssistExtension8,
+ &feature_miscellaneousExtensions,
+ &feature_miscellaneousExtensions2,
+ &feature_populationCount,
+ &feature_processorAssist,
+ &feature_resetReferenceBitsMultiple,
+ &feature_transactionalExecution,
+ &feature_vector,
+ &feature_vectorEnhancements1,
+ &feature_vectorPackedDecimal,
+ },
+};
+
+pub const cpu_z15 = Cpu{
+ .name = "z15",
+ .llvm_name = "z15",
+ .subfeatures = &[_]*const Feature {
+ &feature_dfpPackedConversion,
+ &feature_dfpZonedConversion,
+ &feature_deflateConversion,
+ &feature_distinctOps,
+ &feature_enhancedDat2,
+ &feature_enhancedSort,
+ &feature_executionHint,
+ &feature_fpExtension,
+ &feature_fastSerialization,
+ &feature_guardedStorage,
+ &feature_highWord,
+ &feature_insertReferenceBitsMultiple,
+ &feature_interlockedAccess1,
+ &feature_loadAndTrap,
+ &feature_loadAndZeroRightmostByte,
+ &feature_loadStoreOnCond,
+ &feature_loadStoreOnCond2,
+ &feature_messageSecurityAssistExtension3,
+ &feature_messageSecurityAssistExtension4,
+ &feature_messageSecurityAssistExtension5,
+ &feature_messageSecurityAssistExtension7,
+ &feature_messageSecurityAssistExtension8,
+ &feature_messageSecurityAssistExtension9,
+ &feature_miscellaneousExtensions,
+ &feature_miscellaneousExtensions2,
+ &feature_miscellaneousExtensions3,
+ &feature_populationCount,
+ &feature_processorAssist,
+ &feature_resetReferenceBitsMultiple,
+ &feature_transactionalExecution,
+ &feature_vector,
+ &feature_vectorEnhancements1,
+ &feature_vectorEnhancements2,
+ &feature_vectorPackedDecimal,
+ &feature_vectorPackedDecimalEnhancement,
+ },
+};
+
+pub const cpu_z196 = Cpu{
+ .name = "z196",
+ .llvm_name = "z196",
+ .subfeatures = &[_]*const Feature {
+ &feature_distinctOps,
+ &feature_fpExtension,
+ &feature_fastSerialization,
+ &feature_highWord,
+ &feature_interlockedAccess1,
+ &feature_loadStoreOnCond,
+ &feature_messageSecurityAssistExtension3,
+ &feature_messageSecurityAssistExtension4,
+ &feature_populationCount,
+ &feature_resetReferenceBitsMultiple,
+ },
+};
+
+pub const cpu_zEC12 = Cpu{
+ .name = "zEC12",
+ .llvm_name = "zEC12",
+ .subfeatures = &[_]*const Feature {
+ &feature_dfpZonedConversion,
+ &feature_distinctOps,
+ &feature_enhancedDat2,
+ &feature_executionHint,
+ &feature_fpExtension,
+ &feature_fastSerialization,
+ &feature_highWord,
+ &feature_interlockedAccess1,
+ &feature_loadAndTrap,
+ &feature_loadStoreOnCond,
+ &feature_messageSecurityAssistExtension3,
+ &feature_messageSecurityAssistExtension4,
+ &feature_miscellaneousExtensions,
+ &feature_populationCount,
+ &feature_processorAssist,
+ &feature_resetReferenceBitsMultiple,
+ &feature_transactionalExecution,
+ },
+};
+
+pub const cpus = &[_]*const Cpu {
+ &cpu_arch10,
+ &cpu_arch11,
+ &cpu_arch12,
+ &cpu_arch13,
+ &cpu_arch8,
+ &cpu_arch9,
+ &cpu_generic,
+ &cpu_z10,
+ &cpu_z13,
+ &cpu_z14,
+ &cpu_z15,
+ &cpu_z196,
+ &cpu_zEC12,
+};
lib/std/target/wasm.zig
@@ -0,0 +1,128 @@
+const Feature = @import("std").target.Feature;
+const Cpu = @import("std").target.Cpu;
+
+pub const feature_atomics = Feature{
+ .name = "atomics",
+ .description = "Enable Atomics",
+ .llvm_name = "atomics",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_bulkMemory = Feature{
+ .name = "bulk-memory",
+ .description = "Enable bulk memory operations",
+ .llvm_name = "bulk-memory",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_exceptionHandling = Feature{
+ .name = "exception-handling",
+ .description = "Enable Wasm exception handling",
+ .llvm_name = "exception-handling",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_multivalue = Feature{
+ .name = "multivalue",
+ .description = "Enable multivalue blocks, instructions, and functions",
+ .llvm_name = "multivalue",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mutableGlobals = Feature{
+ .name = "mutable-globals",
+ .description = "Enable mutable globals",
+ .llvm_name = "mutable-globals",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_nontrappingFptoint = Feature{
+ .name = "nontrapping-fptoint",
+ .description = "Enable non-trapping float-to-int conversion operators",
+ .llvm_name = "nontrapping-fptoint",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_simd128 = Feature{
+ .name = "simd128",
+ .description = "Enable 128-bit SIMD",
+ .llvm_name = "simd128",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_signExt = Feature{
+ .name = "sign-ext",
+ .description = "Enable sign extension operators",
+ .llvm_name = "sign-ext",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_tailCall = Feature{
+ .name = "tail-call",
+ .description = "Enable tail call instructions",
+ .llvm_name = "tail-call",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_unimplementedSimd128 = Feature{
+ .name = "unimplemented-simd128",
+ .description = "Enable 128-bit SIMD not yet implemented in engines",
+ .llvm_name = "unimplemented-simd128",
+ .subfeatures = &[_]*const Feature {
+ &feature_simd128,
+ },
+};
+
+pub const features = &[_]*const Feature {
+ &feature_atomics,
+ &feature_bulkMemory,
+ &feature_exceptionHandling,
+ &feature_multivalue,
+ &feature_mutableGlobals,
+ &feature_nontrappingFptoint,
+ &feature_simd128,
+ &feature_signExt,
+ &feature_tailCall,
+ &feature_unimplementedSimd128,
+};
+
+pub const cpu_bleedingEdge = Cpu{
+ .name = "bleeding-edge",
+ .llvm_name = "bleeding-edge",
+ .subfeatures = &[_]*const Feature {
+ &feature_atomics,
+ &feature_mutableGlobals,
+ &feature_nontrappingFptoint,
+ &feature_simd128,
+ &feature_signExt,
+ },
+};
+
+pub const cpu_generic = Cpu{
+ .name = "generic",
+ .llvm_name = "generic",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_mvp = Cpu{
+ .name = "mvp",
+ .llvm_name = "mvp",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpus = &[_]*const Cpu {
+ &cpu_bleedingEdge,
+ &cpu_generic,
+ &cpu_mvp,
+};
lib/std/target/x86.zig
@@ -0,0 +1,3427 @@
+const Feature = @import("std").target.Feature;
+const Cpu = @import("std").target.Cpu;
+
+pub const feature_dnow3 = Feature{
+ .name = "3dnow",
+ .description = "Enable 3DNow! instructions",
+ .llvm_name = "3dnow",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ },
+};
+
+pub const feature_dnowa3 = Feature{
+ .name = "3dnowa",
+ .description = "Enable 3DNow! Athlon instructions",
+ .llvm_name = "3dnowa",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ },
+};
+
+pub const feature_bit64 = Feature{
+ .name = "64bit",
+ .description = "Support 64-bit instructions",
+ .llvm_name = "64bit",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_adx = Feature{
+ .name = "adx",
+ .description = "Support ADX instructions",
+ .llvm_name = "adx",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_aes = Feature{
+ .name = "aes",
+ .description = "Enable AES instructions",
+ .llvm_name = "aes",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_avx = Feature{
+ .name = "avx",
+ .description = "Enable AVX instructions",
+ .llvm_name = "avx",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_avx2 = Feature{
+ .name = "avx2",
+ .description = "Enable AVX2 instructions",
+ .llvm_name = "avx2",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_avx512f = Feature{
+ .name = "avx512f",
+ .description = "Enable AVX-512 instructions",
+ .llvm_name = "avx512f",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_avx512bf16 = Feature{
+ .name = "avx512bf16",
+ .description = "Support bfloat16 floating point",
+ .llvm_name = "avx512bf16",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_avx512bitalg = Feature{
+ .name = "avx512bitalg",
+ .description = "Enable AVX-512 Bit Algorithms",
+ .llvm_name = "avx512bitalg",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_bmi = Feature{
+ .name = "bmi",
+ .description = "Support BMI instructions",
+ .llvm_name = "bmi",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_bmi2 = Feature{
+ .name = "bmi2",
+ .description = "Support BMI2 instructions",
+ .llvm_name = "bmi2",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_avx512bw = Feature{
+ .name = "avx512bw",
+ .description = "Enable AVX-512 Byte and Word Instructions",
+ .llvm_name = "avx512bw",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_branchfusion = Feature{
+ .name = "branchfusion",
+ .description = "CMP/TEST can be fused with conditional branches",
+ .llvm_name = "branchfusion",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_avx512cd = Feature{
+ .name = "avx512cd",
+ .description = "Enable AVX-512 Conflict Detection Instructions",
+ .llvm_name = "avx512cd",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_cldemote = Feature{
+ .name = "cldemote",
+ .description = "Enable Cache Demote",
+ .llvm_name = "cldemote",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_clflushopt = Feature{
+ .name = "clflushopt",
+ .description = "Flush A Cache Line Optimized",
+ .llvm_name = "clflushopt",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_clwb = Feature{
+ .name = "clwb",
+ .description = "Cache Line Write Back",
+ .llvm_name = "clwb",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_clzero = Feature{
+ .name = "clzero",
+ .description = "Enable Cache Line Zero",
+ .llvm_name = "clzero",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_cmov = Feature{
+ .name = "cmov",
+ .description = "Enable conditional move instructions",
+ .llvm_name = "cmov",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_cx8 = Feature{
+ .name = "cx8",
+ .description = "Support CMPXCHG8B instructions",
+ .llvm_name = "cx8",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_cx16 = Feature{
+ .name = "cx16",
+ .description = "64-bit with cmpxchg16b",
+ .llvm_name = "cx16",
+ .subfeatures = &[_]*const Feature {
+ &feature_cx8,
+ },
+};
+
+pub const feature_avx512dq = Feature{
+ .name = "avx512dq",
+ .description = "Enable AVX-512 Doubleword and Quadword Instructions",
+ .llvm_name = "avx512dq",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_mpx = Feature{
+ .name = "mpx",
+ .description = "Deprecated. Support MPX instructions",
+ .llvm_name = "mpx",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_enqcmd = Feature{
+ .name = "enqcmd",
+ .description = "Has ENQCMD instructions",
+ .llvm_name = "enqcmd",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_avx512er = Feature{
+ .name = "avx512er",
+ .description = "Enable AVX-512 Exponential and Reciprocal Instructions",
+ .llvm_name = "avx512er",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_ermsb = Feature{
+ .name = "ermsb",
+ .description = "REP MOVS/STOS are fast",
+ .llvm_name = "ermsb",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_f16c = Feature{
+ .name = "f16c",
+ .description = "Support 16-bit floating point conversion instructions",
+ .llvm_name = "f16c",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_fma = Feature{
+ .name = "fma",
+ .description = "Enable three-operand fused multiple-add",
+ .llvm_name = "fma",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_fma4 = Feature{
+ .name = "fma4",
+ .description = "Enable four-operand fused multiple-add",
+ .llvm_name = "fma4",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_fsgsbase = Feature{
+ .name = "fsgsbase",
+ .description = "Support FS/GS Base instructions",
+ .llvm_name = "fsgsbase",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fxsr = Feature{
+ .name = "fxsr",
+ .description = "Support fxsave/fxrestore instructions",
+ .llvm_name = "fxsr",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fast11bytenop = Feature{
+ .name = "fast-11bytenop",
+ .description = "Target can quickly decode up to 11 byte NOPs",
+ .llvm_name = "fast-11bytenop",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fast15bytenop = Feature{
+ .name = "fast-15bytenop",
+ .description = "Target can quickly decode up to 15 byte NOPs",
+ .llvm_name = "fast-15bytenop",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fastBextr = Feature{
+ .name = "fast-bextr",
+ .description = "Indicates that the BEXTR instruction is implemented as a single uop with good throughput",
+ .llvm_name = "fast-bextr",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fastHops = Feature{
+ .name = "fast-hops",
+ .description = "Prefer horizontal vector math instructions (haddp, phsub, etc.) over normal vector instructions with shuffles",
+ .llvm_name = "fast-hops",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_fastLzcnt = Feature{
+ .name = "fast-lzcnt",
+ .description = "LZCNT instructions are as fast as most simple integer ops",
+ .llvm_name = "fast-lzcnt",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fastPartialYmmOrZmmWrite = Feature{
+ .name = "fast-partial-ymm-or-zmm-write",
+ .description = "Partial writes to YMM/ZMM registers are fast",
+ .llvm_name = "fast-partial-ymm-or-zmm-write",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fastShldRotate = Feature{
+ .name = "fast-shld-rotate",
+ .description = "SHLD can be used as a faster rotate",
+ .llvm_name = "fast-shld-rotate",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fastScalarFsqrt = Feature{
+ .name = "fast-scalar-fsqrt",
+ .description = "Scalar SQRT is fast (disable Newton-Raphson)",
+ .llvm_name = "fast-scalar-fsqrt",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fastScalarShiftMasks = Feature{
+ .name = "fast-scalar-shift-masks",
+ .description = "Prefer a left/right scalar logical shift pair over a shift+and pair",
+ .llvm_name = "fast-scalar-shift-masks",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fastVariableShuffle = Feature{
+ .name = "fast-variable-shuffle",
+ .description = "Shuffles with variable masks are fast",
+ .llvm_name = "fast-variable-shuffle",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fastVectorFsqrt = Feature{
+ .name = "fast-vector-fsqrt",
+ .description = "Vector SQRT is fast (disable Newton-Raphson)",
+ .llvm_name = "fast-vector-fsqrt",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_fastVectorShiftMasks = Feature{
+ .name = "fast-vector-shift-masks",
+ .description = "Prefer a left/right vector logical shift pair over a shift+and pair",
+ .llvm_name = "fast-vector-shift-masks",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_gfni = Feature{
+ .name = "gfni",
+ .description = "Enable Galois Field Arithmetic Instructions",
+ .llvm_name = "gfni",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_fastGather = Feature{
+ .name = "fast-gather",
+ .description = "Indicates if gather is reasonably fast",
+ .llvm_name = "fast-gather",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_avx512ifma = Feature{
+ .name = "avx512ifma",
+ .description = "Enable AVX-512 Integer Fused Multiple-Add",
+ .llvm_name = "avx512ifma",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_invpcid = Feature{
+ .name = "invpcid",
+ .description = "Invalidate Process-Context Identifier",
+ .llvm_name = "invpcid",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sahf = Feature{
+ .name = "sahf",
+ .description = "Support LAHF and SAHF instructions",
+ .llvm_name = "sahf",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_leaSp = Feature{
+ .name = "lea-sp",
+ .description = "Use LEA for adjusting the stack pointer",
+ .llvm_name = "lea-sp",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_leaUsesAg = Feature{
+ .name = "lea-uses-ag",
+ .description = "LEA instruction needs inputs at AG stage",
+ .llvm_name = "lea-uses-ag",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_lwp = Feature{
+ .name = "lwp",
+ .description = "Enable LWP instructions",
+ .llvm_name = "lwp",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_lzcnt = Feature{
+ .name = "lzcnt",
+ .description = "Support LZCNT instruction",
+ .llvm_name = "lzcnt",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_falseDepsLzcntTzcnt = Feature{
+ .name = "false-deps-lzcnt-tzcnt",
+ .description = "LZCNT/TZCNT have a false dependency on dest register",
+ .llvm_name = "false-deps-lzcnt-tzcnt",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mmx = Feature{
+ .name = "mmx",
+ .description = "Enable MMX instructions",
+ .llvm_name = "mmx",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_movbe = Feature{
+ .name = "movbe",
+ .description = "Support MOVBE instruction",
+ .llvm_name = "movbe",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_movdir64b = Feature{
+ .name = "movdir64b",
+ .description = "Support movdir64b instruction",
+ .llvm_name = "movdir64b",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_movdiri = Feature{
+ .name = "movdiri",
+ .description = "Support movdiri instruction",
+ .llvm_name = "movdiri",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mwaitx = Feature{
+ .name = "mwaitx",
+ .description = "Enable MONITORX/MWAITX timer functionality",
+ .llvm_name = "mwaitx",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_macrofusion = Feature{
+ .name = "macrofusion",
+ .description = "Various instructions can be fused with conditional branches",
+ .llvm_name = "macrofusion",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_mergeToThreewayBranch = Feature{
+ .name = "merge-to-threeway-branch",
+ .description = "Merge branches to a three-way conditional branch",
+ .llvm_name = "merge-to-threeway-branch",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_nopl = Feature{
+ .name = "nopl",
+ .description = "Enable NOPL instruction",
+ .llvm_name = "nopl",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_pclmul = Feature{
+ .name = "pclmul",
+ .description = "Enable packed carry-less multiplication instructions",
+ .llvm_name = "pclmul",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_pconfig = Feature{
+ .name = "pconfig",
+ .description = "platform configuration instruction",
+ .llvm_name = "pconfig",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_avx512pf = Feature{
+ .name = "avx512pf",
+ .description = "Enable AVX-512 PreFetch Instructions",
+ .llvm_name = "avx512pf",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_pku = Feature{
+ .name = "pku",
+ .description = "Enable protection keys",
+ .llvm_name = "pku",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_popcnt = Feature{
+ .name = "popcnt",
+ .description = "Support POPCNT instruction",
+ .llvm_name = "popcnt",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_falseDepsPopcnt = Feature{
+ .name = "false-deps-popcnt",
+ .description = "POPCNT has a false dependency on dest register",
+ .llvm_name = "false-deps-popcnt",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_prefetchwt1 = Feature{
+ .name = "prefetchwt1",
+ .description = "Prefetch with Intent to Write and T1 Hint",
+ .llvm_name = "prefetchwt1",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_prfchw = Feature{
+ .name = "prfchw",
+ .description = "Support PRFCHW instructions",
+ .llvm_name = "prfchw",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ptwrite = Feature{
+ .name = "ptwrite",
+ .description = "Support ptwrite instruction",
+ .llvm_name = "ptwrite",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_padShortFunctions = Feature{
+ .name = "pad-short-functions",
+ .description = "Pad short functions",
+ .llvm_name = "pad-short-functions",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_prefer128Bit = Feature{
+ .name = "prefer-128-bit",
+ .description = "Prefer 128-bit AVX instructions",
+ .llvm_name = "prefer-128-bit",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_prefer256Bit = Feature{
+ .name = "prefer-256-bit",
+ .description = "Prefer 256-bit AVX instructions",
+ .llvm_name = "prefer-256-bit",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_rdpid = Feature{
+ .name = "rdpid",
+ .description = "Support RDPID instructions",
+ .llvm_name = "rdpid",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_rdrnd = Feature{
+ .name = "rdrnd",
+ .description = "Support RDRAND instruction",
+ .llvm_name = "rdrnd",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_rdseed = Feature{
+ .name = "rdseed",
+ .description = "Support RDSEED instruction",
+ .llvm_name = "rdseed",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_rtm = Feature{
+ .name = "rtm",
+ .description = "Support RTM instructions",
+ .llvm_name = "rtm",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_retpoline = Feature{
+ .name = "retpoline",
+ .description = "Remove speculation of indirect branches from the generated code, either by avoiding them entirely or lowering them with a speculation blocking construct",
+ .llvm_name = "retpoline",
+ .subfeatures = &[_]*const Feature {
+ &feature_retpolineIndirectCalls,
+ &feature_retpolineIndirectBranches,
+ },
+};
+
+pub const feature_retpolineExternalThunk = Feature{
+ .name = "retpoline-external-thunk",
+ .description = "When lowering an indirect call or branch using a `retpoline`, rely on the specified user provided thunk rather than emitting one ourselves. Only has effect when combined with some other retpoline feature",
+ .llvm_name = "retpoline-external-thunk",
+ .subfeatures = &[_]*const Feature {
+ &feature_retpolineIndirectCalls,
+ },
+};
+
+pub const feature_retpolineIndirectBranches = Feature{
+ .name = "retpoline-indirect-branches",
+ .description = "Remove speculation of indirect branches from the generated code",
+ .llvm_name = "retpoline-indirect-branches",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_retpolineIndirectCalls = Feature{
+ .name = "retpoline-indirect-calls",
+ .description = "Remove speculation of indirect calls from the generated code",
+ .llvm_name = "retpoline-indirect-calls",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sgx = Feature{
+ .name = "sgx",
+ .description = "Enable Software Guard Extensions",
+ .llvm_name = "sgx",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sha = Feature{
+ .name = "sha",
+ .description = "Enable SHA instructions",
+ .llvm_name = "sha",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_shstk = Feature{
+ .name = "shstk",
+ .description = "Support CET Shadow-Stack instructions",
+ .llvm_name = "shstk",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sse = Feature{
+ .name = "sse",
+ .description = "Enable SSE instructions",
+ .llvm_name = "sse",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_sse2 = Feature{
+ .name = "sse2",
+ .description = "Enable SSE2 instructions",
+ .llvm_name = "sse2",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_sse3 = Feature{
+ .name = "sse3",
+ .description = "Enable SSE3 instructions",
+ .llvm_name = "sse3",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_sse4a = Feature{
+ .name = "sse4a",
+ .description = "Support SSE 4a instructions",
+ .llvm_name = "sse4a",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_sse41 = Feature{
+ .name = "sse4.1",
+ .description = "Enable SSE 4.1 instructions",
+ .llvm_name = "sse4.1",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_sse42 = Feature{
+ .name = "sse4.2",
+ .description = "Enable SSE 4.2 instructions",
+ .llvm_name = "sse4.2",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_sseUnalignedMem = Feature{
+ .name = "sse-unaligned-mem",
+ .description = "Allow unaligned memory operands with SSE instructions",
+ .llvm_name = "sse-unaligned-mem",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_ssse3 = Feature{
+ .name = "ssse3",
+ .description = "Enable SSSE3 instructions",
+ .llvm_name = "ssse3",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_slow3opsLea = Feature{
+ .name = "slow-3ops-lea",
+ .description = "LEA instruction with 3 ops or certain registers is slow",
+ .llvm_name = "slow-3ops-lea",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_idivlToDivb = Feature{
+ .name = "idivl-to-divb",
+ .description = "Use 8-bit divide for positive values less than 256",
+ .llvm_name = "idivl-to-divb",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_idivqToDivl = Feature{
+ .name = "idivq-to-divl",
+ .description = "Use 32-bit divide for positive values less than 2^32",
+ .llvm_name = "idivq-to-divl",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_slowIncdec = Feature{
+ .name = "slow-incdec",
+ .description = "INC and DEC instructions are slower than ADD and SUB",
+ .llvm_name = "slow-incdec",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_slowLea = Feature{
+ .name = "slow-lea",
+ .description = "LEA instruction with certain arguments is slow",
+ .llvm_name = "slow-lea",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_slowPmaddwd = Feature{
+ .name = "slow-pmaddwd",
+ .description = "PMADDWD is slower than PMULLD",
+ .llvm_name = "slow-pmaddwd",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_slowPmulld = Feature{
+ .name = "slow-pmulld",
+ .description = "PMULLD instruction is slow",
+ .llvm_name = "slow-pmulld",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_slowShld = Feature{
+ .name = "slow-shld",
+ .description = "SHLD instruction is slow",
+ .llvm_name = "slow-shld",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_slowTwoMemOps = Feature{
+ .name = "slow-two-mem-ops",
+ .description = "Two memory operand instructions are slow",
+ .llvm_name = "slow-two-mem-ops",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_slowUnalignedMem16 = Feature{
+ .name = "slow-unaligned-mem-16",
+ .description = "Slow unaligned 16-byte memory access",
+ .llvm_name = "slow-unaligned-mem-16",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_slowUnalignedMem32 = Feature{
+ .name = "slow-unaligned-mem-32",
+ .description = "Slow unaligned 32-byte memory access",
+ .llvm_name = "slow-unaligned-mem-32",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_softFloat = Feature{
+ .name = "soft-float",
+ .description = "Use software floating point features",
+ .llvm_name = "soft-float",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_tbm = Feature{
+ .name = "tbm",
+ .description = "Enable TBM instructions",
+ .llvm_name = "tbm",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_useAa = Feature{
+ .name = "use-aa",
+ .description = "Use alias analysis during codegen",
+ .llvm_name = "use-aa",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_vaes = Feature{
+ .name = "vaes",
+ .description = "Promote selected AES instructions to AVX512/AVX registers",
+ .llvm_name = "vaes",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_avx512vbmi = Feature{
+ .name = "avx512vbmi",
+ .description = "Enable AVX-512 Vector Byte Manipulation Instructions",
+ .llvm_name = "avx512vbmi",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_avx512vbmi2 = Feature{
+ .name = "avx512vbmi2",
+ .description = "Enable AVX-512 further Vector Byte Manipulation Instructions",
+ .llvm_name = "avx512vbmi2",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_avx512vl = Feature{
+ .name = "avx512vl",
+ .description = "Enable AVX-512 Vector Length eXtensions",
+ .llvm_name = "avx512vl",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_avx512vnni = Feature{
+ .name = "avx512vnni",
+ .description = "Enable AVX-512 Vector Neural Network Instructions",
+ .llvm_name = "avx512vnni",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_avx512vp2intersect = Feature{
+ .name = "avx512vp2intersect",
+ .description = "Enable AVX-512 vp2intersect",
+ .llvm_name = "avx512vp2intersect",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_vpclmulqdq = Feature{
+ .name = "vpclmulqdq",
+ .description = "Enable vpclmulqdq instructions",
+ .llvm_name = "vpclmulqdq",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_avx512vpopcntdq = Feature{
+ .name = "avx512vpopcntdq",
+ .description = "Enable AVX-512 Population Count Instructions",
+ .llvm_name = "avx512vpopcntdq",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_waitpkg = Feature{
+ .name = "waitpkg",
+ .description = "Wait and pause enhancements",
+ .llvm_name = "waitpkg",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_wbnoinvd = Feature{
+ .name = "wbnoinvd",
+ .description = "Write Back No Invalidate",
+ .llvm_name = "wbnoinvd",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_x87 = Feature{
+ .name = "x87",
+ .description = "Enable X87 float instructions",
+ .llvm_name = "x87",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_xop = Feature{
+ .name = "xop",
+ .description = "Enable XOP instructions",
+ .llvm_name = "xop",
+ .subfeatures = &[_]*const Feature {
+ &feature_sse,
+ },
+};
+
+pub const feature_xsave = Feature{
+ .name = "xsave",
+ .description = "Support xsave instructions",
+ .llvm_name = "xsave",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_xsavec = Feature{
+ .name = "xsavec",
+ .description = "Support xsavec instructions",
+ .llvm_name = "xsavec",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_xsaveopt = Feature{
+ .name = "xsaveopt",
+ .description = "Support xsaveopt instructions",
+ .llvm_name = "xsaveopt",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_xsaves = Feature{
+ .name = "xsaves",
+ .description = "Support xsaves instructions",
+ .llvm_name = "xsaves",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_bitMode16 = Feature{
+ .name = "16bit-mode",
+ .description = "16-bit mode (i8086)",
+ .llvm_name = "16bit-mode",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_bitMode32 = Feature{
+ .name = "32bit-mode",
+ .description = "32-bit mode (80386)",
+ .llvm_name = "32bit-mode",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const feature_bitMode64 = Feature{
+ .name = "64bit-mode",
+ .description = "64-bit mode (x86_64)",
+ .llvm_name = "64bit-mode",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const features = &[_]*const Feature {
+ &feature_dnow3,
+ &feature_dnowa3,
+ &feature_bit64,
+ &feature_adx,
+ &feature_aes,
+ &feature_avx,
+ &feature_avx2,
+ &feature_avx512f,
+ &feature_avx512bf16,
+ &feature_avx512bitalg,
+ &feature_bmi,
+ &feature_bmi2,
+ &feature_avx512bw,
+ &feature_branchfusion,
+ &feature_avx512cd,
+ &feature_cldemote,
+ &feature_clflushopt,
+ &feature_clwb,
+ &feature_clzero,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_avx512dq,
+ &feature_mpx,
+ &feature_enqcmd,
+ &feature_avx512er,
+ &feature_ermsb,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fma4,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fast11bytenop,
+ &feature_fast15bytenop,
+ &feature_fastBextr,
+ &feature_fastHops,
+ &feature_fastLzcnt,
+ &feature_fastPartialYmmOrZmmWrite,
+ &feature_fastShldRotate,
+ &feature_fastScalarFsqrt,
+ &feature_fastScalarShiftMasks,
+ &feature_fastVariableShuffle,
+ &feature_fastVectorFsqrt,
+ &feature_fastVectorShiftMasks,
+ &feature_gfni,
+ &feature_fastGather,
+ &feature_avx512ifma,
+ &feature_invpcid,
+ &feature_sahf,
+ &feature_leaSp,
+ &feature_leaUsesAg,
+ &feature_lwp,
+ &feature_lzcnt,
+ &feature_falseDepsLzcntTzcnt,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_movdir64b,
+ &feature_movdiri,
+ &feature_mwaitx,
+ &feature_macrofusion,
+ &feature_mergeToThreewayBranch,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_pconfig,
+ &feature_avx512pf,
+ &feature_pku,
+ &feature_popcnt,
+ &feature_falseDepsPopcnt,
+ &feature_prefetchwt1,
+ &feature_prfchw,
+ &feature_ptwrite,
+ &feature_padShortFunctions,
+ &feature_prefer128Bit,
+ &feature_prefer256Bit,
+ &feature_rdpid,
+ &feature_rdrnd,
+ &feature_rdseed,
+ &feature_rtm,
+ &feature_retpoline,
+ &feature_retpolineExternalThunk,
+ &feature_retpolineIndirectBranches,
+ &feature_retpolineIndirectCalls,
+ &feature_sgx,
+ &feature_sha,
+ &feature_shstk,
+ &feature_sse,
+ &feature_sse2,
+ &feature_sse3,
+ &feature_sse4a,
+ &feature_sse41,
+ &feature_sse42,
+ &feature_sseUnalignedMem,
+ &feature_ssse3,
+ &feature_slow3opsLea,
+ &feature_idivlToDivb,
+ &feature_idivqToDivl,
+ &feature_slowIncdec,
+ &feature_slowLea,
+ &feature_slowPmaddwd,
+ &feature_slowPmulld,
+ &feature_slowShld,
+ &feature_slowTwoMemOps,
+ &feature_slowUnalignedMem16,
+ &feature_slowUnalignedMem32,
+ &feature_softFloat,
+ &feature_tbm,
+ &feature_useAa,
+ &feature_vaes,
+ &feature_avx512vbmi,
+ &feature_avx512vbmi2,
+ &feature_avx512vl,
+ &feature_avx512vnni,
+ &feature_avx512vp2intersect,
+ &feature_vpclmulqdq,
+ &feature_avx512vpopcntdq,
+ &feature_waitpkg,
+ &feature_wbnoinvd,
+ &feature_x87,
+ &feature_xop,
+ &feature_xsave,
+ &feature_xsavec,
+ &feature_xsaveopt,
+ &feature_xsaves,
+ &feature_bitMode16,
+ &feature_bitMode32,
+ &feature_bitMode64,
+};
+
+pub const cpu_amdfam10 = Cpu{
+ .name = "amdfam10",
+ .llvm_name = "amdfam10",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_dnowa3,
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fxsr,
+ &feature_fastScalarShiftMasks,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_nopl,
+ &feature_popcnt,
+ &feature_sse,
+ &feature_sse4a,
+ &feature_slowShld,
+ &feature_x87,
+ },
+};
+
+pub const cpu_athlon = Cpu{
+ .name = "athlon",
+ .llvm_name = "athlon",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_dnowa3,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_nopl,
+ &feature_slowShld,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_athlon4 = Cpu{
+ .name = "athlon-4",
+ .llvm_name = "athlon-4",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_dnowa3,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_fxsr,
+ &feature_nopl,
+ &feature_sse,
+ &feature_slowShld,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_athlonFx = Cpu{
+ .name = "athlon-fx",
+ .llvm_name = "athlon-fx",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_dnowa3,
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_fxsr,
+ &feature_fastScalarShiftMasks,
+ &feature_nopl,
+ &feature_sse,
+ &feature_sse2,
+ &feature_slowShld,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_athlonMp = Cpu{
+ .name = "athlon-mp",
+ .llvm_name = "athlon-mp",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_dnowa3,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_fxsr,
+ &feature_nopl,
+ &feature_sse,
+ &feature_slowShld,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_athlonTbird = Cpu{
+ .name = "athlon-tbird",
+ .llvm_name = "athlon-tbird",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_dnowa3,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_nopl,
+ &feature_slowShld,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_athlonXp = Cpu{
+ .name = "athlon-xp",
+ .llvm_name = "athlon-xp",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_dnowa3,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_fxsr,
+ &feature_nopl,
+ &feature_sse,
+ &feature_slowShld,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_athlon64 = Cpu{
+ .name = "athlon64",
+ .llvm_name = "athlon64",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_dnowa3,
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_fxsr,
+ &feature_fastScalarShiftMasks,
+ &feature_nopl,
+ &feature_sse,
+ &feature_sse2,
+ &feature_slowShld,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_athlon64Sse3 = Cpu{
+ .name = "athlon64-sse3",
+ .llvm_name = "athlon64-sse3",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_dnowa3,
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fxsr,
+ &feature_fastScalarShiftMasks,
+ &feature_nopl,
+ &feature_sse,
+ &feature_sse3,
+ &feature_slowShld,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_atom = Cpu{
+ .name = "atom",
+ .llvm_name = "atom",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fxsr,
+ &feature_sahf,
+ &feature_leaSp,
+ &feature_leaUsesAg,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_nopl,
+ &feature_padShortFunctions,
+ &feature_sse,
+ &feature_ssse3,
+ &feature_idivlToDivb,
+ &feature_idivqToDivl,
+ &feature_slowTwoMemOps,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_barcelona = Cpu{
+ .name = "barcelona",
+ .llvm_name = "barcelona",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_dnowa3,
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fxsr,
+ &feature_fastScalarShiftMasks,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_nopl,
+ &feature_popcnt,
+ &feature_sse,
+ &feature_sse4a,
+ &feature_slowShld,
+ &feature_x87,
+ },
+};
+
+pub const cpu_bdver1 = Cpu{
+ .name = "bdver1",
+ .llvm_name = "bdver1",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_sse,
+ &feature_aes,
+ &feature_branchfusion,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fxsr,
+ &feature_fast11bytenop,
+ &feature_fastScalarShiftMasks,
+ &feature_sahf,
+ &feature_lwp,
+ &feature_lzcnt,
+ &feature_mmx,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_prfchw,
+ &feature_slowShld,
+ &feature_x87,
+ &feature_xop,
+ &feature_xsave,
+ },
+};
+
+pub const cpu_bdver2 = Cpu{
+ .name = "bdver2",
+ .llvm_name = "bdver2",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_sse,
+ &feature_aes,
+ &feature_bmi,
+ &feature_branchfusion,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fxsr,
+ &feature_fast11bytenop,
+ &feature_fastBextr,
+ &feature_fastScalarShiftMasks,
+ &feature_sahf,
+ &feature_lwp,
+ &feature_lzcnt,
+ &feature_mmx,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_prfchw,
+ &feature_slowShld,
+ &feature_tbm,
+ &feature_x87,
+ &feature_xop,
+ &feature_xsave,
+ },
+};
+
+pub const cpu_bdver3 = Cpu{
+ .name = "bdver3",
+ .llvm_name = "bdver3",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_sse,
+ &feature_aes,
+ &feature_bmi,
+ &feature_branchfusion,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fast11bytenop,
+ &feature_fastBextr,
+ &feature_fastScalarShiftMasks,
+ &feature_sahf,
+ &feature_lwp,
+ &feature_lzcnt,
+ &feature_mmx,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_prfchw,
+ &feature_slowShld,
+ &feature_tbm,
+ &feature_x87,
+ &feature_xop,
+ &feature_xsave,
+ &feature_xsaveopt,
+ },
+};
+
+pub const cpu_bdver4 = Cpu{
+ .name = "bdver4",
+ .llvm_name = "bdver4",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_sse,
+ &feature_aes,
+ &feature_avx2,
+ &feature_bmi,
+ &feature_bmi2,
+ &feature_branchfusion,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fast11bytenop,
+ &feature_fastBextr,
+ &feature_fastScalarShiftMasks,
+ &feature_sahf,
+ &feature_lwp,
+ &feature_lzcnt,
+ &feature_mmx,
+ &feature_mwaitx,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_prfchw,
+ &feature_slowShld,
+ &feature_tbm,
+ &feature_x87,
+ &feature_xop,
+ &feature_xsave,
+ &feature_xsaveopt,
+ },
+};
+
+pub const cpu_bonnell = Cpu{
+ .name = "bonnell",
+ .llvm_name = "bonnell",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fxsr,
+ &feature_sahf,
+ &feature_leaSp,
+ &feature_leaUsesAg,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_nopl,
+ &feature_padShortFunctions,
+ &feature_sse,
+ &feature_ssse3,
+ &feature_idivlToDivb,
+ &feature_idivqToDivl,
+ &feature_slowTwoMemOps,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_broadwell = Cpu{
+ .name = "broadwell",
+ .llvm_name = "broadwell",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_adx,
+ &feature_sse,
+ &feature_avx,
+ &feature_avx2,
+ &feature_bmi,
+ &feature_bmi2,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_ermsb,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fastShldRotate,
+ &feature_fastScalarFsqrt,
+ &feature_fastVariableShuffle,
+ &feature_invpcid,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_falseDepsLzcntTzcnt,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_macrofusion,
+ &feature_mergeToThreewayBranch,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_falseDepsPopcnt,
+ &feature_prfchw,
+ &feature_rdrnd,
+ &feature_rdseed,
+ &feature_sse42,
+ &feature_slow3opsLea,
+ &feature_idivqToDivl,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsaveopt,
+ },
+};
+
+pub const cpu_btver1 = Cpu{
+ .name = "btver1",
+ .llvm_name = "btver1",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fxsr,
+ &feature_fast15bytenop,
+ &feature_fastScalarShiftMasks,
+ &feature_fastVectorShiftMasks,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_mmx,
+ &feature_nopl,
+ &feature_popcnt,
+ &feature_prfchw,
+ &feature_sse,
+ &feature_sse4a,
+ &feature_ssse3,
+ &feature_slowShld,
+ &feature_x87,
+ },
+};
+
+pub const cpu_btver2 = Cpu{
+ .name = "btver2",
+ .llvm_name = "btver2",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_sse,
+ &feature_aes,
+ &feature_avx,
+ &feature_bmi,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_f16c,
+ &feature_fxsr,
+ &feature_fast15bytenop,
+ &feature_fastBextr,
+ &feature_fastHops,
+ &feature_fastLzcnt,
+ &feature_fastPartialYmmOrZmmWrite,
+ &feature_fastScalarShiftMasks,
+ &feature_fastVectorShiftMasks,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_prfchw,
+ &feature_sse4a,
+ &feature_ssse3,
+ &feature_slowShld,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsaveopt,
+ },
+};
+
+pub const cpu_c3 = Cpu{
+ .name = "c3",
+ .llvm_name = "c3",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_dnow3,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_c32 = Cpu{
+ .name = "c3-2",
+ .llvm_name = "c3-2",
+ .subfeatures = &[_]*const Feature {
+ &feature_cmov,
+ &feature_cx8,
+ &feature_fxsr,
+ &feature_mmx,
+ &feature_sse,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_cannonlake = Cpu{
+ .name = "cannonlake",
+ .llvm_name = "cannonlake",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_adx,
+ &feature_sse,
+ &feature_aes,
+ &feature_avx,
+ &feature_avx2,
+ &feature_avx512f,
+ &feature_bmi,
+ &feature_bmi2,
+ &feature_avx512bw,
+ &feature_avx512cd,
+ &feature_clflushopt,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_avx512dq,
+ &feature_ermsb,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fastShldRotate,
+ &feature_fastScalarFsqrt,
+ &feature_fastVariableShuffle,
+ &feature_fastVectorFsqrt,
+ &feature_fastGather,
+ &feature_avx512ifma,
+ &feature_invpcid,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_macrofusion,
+ &feature_mergeToThreewayBranch,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_pku,
+ &feature_popcnt,
+ &feature_prfchw,
+ &feature_prefer256Bit,
+ &feature_rdrnd,
+ &feature_rdseed,
+ &feature_sgx,
+ &feature_sha,
+ &feature_sse42,
+ &feature_slow3opsLea,
+ &feature_idivqToDivl,
+ &feature_avx512vbmi,
+ &feature_avx512vl,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsavec,
+ &feature_xsaveopt,
+ &feature_xsaves,
+ },
+};
+
+pub const cpu_cascadelake = Cpu{
+ .name = "cascadelake",
+ .llvm_name = "cascadelake",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_adx,
+ &feature_sse,
+ &feature_aes,
+ &feature_avx,
+ &feature_avx2,
+ &feature_avx512f,
+ &feature_bmi,
+ &feature_bmi2,
+ &feature_avx512bw,
+ &feature_avx512cd,
+ &feature_clflushopt,
+ &feature_clwb,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_avx512dq,
+ &feature_ermsb,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fastShldRotate,
+ &feature_fastScalarFsqrt,
+ &feature_fastVariableShuffle,
+ &feature_fastVectorFsqrt,
+ &feature_fastGather,
+ &feature_invpcid,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_macrofusion,
+ &feature_mergeToThreewayBranch,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_pku,
+ &feature_popcnt,
+ &feature_falseDepsPopcnt,
+ &feature_prfchw,
+ &feature_prefer256Bit,
+ &feature_rdrnd,
+ &feature_rdseed,
+ &feature_sse42,
+ &feature_slow3opsLea,
+ &feature_idivqToDivl,
+ &feature_avx512vl,
+ &feature_avx512vnni,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsavec,
+ &feature_xsaveopt,
+ &feature_xsaves,
+ },
+};
+
+pub const cpu_cooperlake = Cpu{
+ .name = "cooperlake",
+ .llvm_name = "cooperlake",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_adx,
+ &feature_sse,
+ &feature_aes,
+ &feature_avx,
+ &feature_avx2,
+ &feature_avx512f,
+ &feature_avx512bf16,
+ &feature_bmi,
+ &feature_bmi2,
+ &feature_avx512bw,
+ &feature_avx512cd,
+ &feature_clflushopt,
+ &feature_clwb,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_avx512dq,
+ &feature_ermsb,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fastShldRotate,
+ &feature_fastScalarFsqrt,
+ &feature_fastVariableShuffle,
+ &feature_fastVectorFsqrt,
+ &feature_fastGather,
+ &feature_invpcid,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_macrofusion,
+ &feature_mergeToThreewayBranch,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_pku,
+ &feature_popcnt,
+ &feature_falseDepsPopcnt,
+ &feature_prfchw,
+ &feature_prefer256Bit,
+ &feature_rdrnd,
+ &feature_rdseed,
+ &feature_sse42,
+ &feature_slow3opsLea,
+ &feature_idivqToDivl,
+ &feature_avx512vl,
+ &feature_avx512vnni,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsavec,
+ &feature_xsaveopt,
+ &feature_xsaves,
+ },
+};
+
+pub const cpu_coreAvxI = Cpu{
+ .name = "core-avx-i",
+ .llvm_name = "core-avx-i",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_sse,
+ &feature_avx,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_f16c,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fastShldRotate,
+ &feature_fastScalarFsqrt,
+ &feature_sahf,
+ &feature_mmx,
+ &feature_macrofusion,
+ &feature_mergeToThreewayBranch,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_falseDepsPopcnt,
+ &feature_rdrnd,
+ &feature_sse42,
+ &feature_slow3opsLea,
+ &feature_idivqToDivl,
+ &feature_slowUnalignedMem32,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsaveopt,
+ },
+};
+
+pub const cpu_coreAvx2 = Cpu{
+ .name = "core-avx2",
+ .llvm_name = "core-avx2",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_sse,
+ &feature_avx,
+ &feature_avx2,
+ &feature_bmi,
+ &feature_bmi2,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_ermsb,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fastShldRotate,
+ &feature_fastScalarFsqrt,
+ &feature_fastVariableShuffle,
+ &feature_invpcid,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_falseDepsLzcntTzcnt,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_macrofusion,
+ &feature_mergeToThreewayBranch,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_falseDepsPopcnt,
+ &feature_rdrnd,
+ &feature_sse42,
+ &feature_slow3opsLea,
+ &feature_idivqToDivl,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsaveopt,
+ },
+};
+
+pub const cpu_core2 = Cpu{
+ .name = "core2",
+ .llvm_name = "core2",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fxsr,
+ &feature_sahf,
+ &feature_mmx,
+ &feature_macrofusion,
+ &feature_nopl,
+ &feature_sse,
+ &feature_ssse3,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_corei7 = Cpu{
+ .name = "corei7",
+ .llvm_name = "corei7",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fxsr,
+ &feature_sahf,
+ &feature_mmx,
+ &feature_macrofusion,
+ &feature_nopl,
+ &feature_popcnt,
+ &feature_sse,
+ &feature_sse42,
+ &feature_x87,
+ },
+};
+
+pub const cpu_corei7Avx = Cpu{
+ .name = "corei7-avx",
+ .llvm_name = "corei7-avx",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_sse,
+ &feature_avx,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fxsr,
+ &feature_fastShldRotate,
+ &feature_fastScalarFsqrt,
+ &feature_sahf,
+ &feature_mmx,
+ &feature_macrofusion,
+ &feature_mergeToThreewayBranch,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_falseDepsPopcnt,
+ &feature_sse42,
+ &feature_slow3opsLea,
+ &feature_idivqToDivl,
+ &feature_slowUnalignedMem32,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsaveopt,
+ },
+};
+
+pub const cpu_generic = Cpu{
+ .name = "generic",
+ .llvm_name = "generic",
+ .subfeatures = &[_]*const Feature {
+ &feature_cx8,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_geode = Cpu{
+ .name = "geode",
+ .llvm_name = "geode",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_dnowa3,
+ &feature_cx8,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_goldmont = Cpu{
+ .name = "goldmont",
+ .llvm_name = "goldmont",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_sse,
+ &feature_aes,
+ &feature_clflushopt,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_sahf,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_falseDepsPopcnt,
+ &feature_prfchw,
+ &feature_rdrnd,
+ &feature_rdseed,
+ &feature_sha,
+ &feature_sse42,
+ &feature_ssse3,
+ &feature_slowIncdec,
+ &feature_slowLea,
+ &feature_slowTwoMemOps,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsavec,
+ &feature_xsaveopt,
+ &feature_xsaves,
+ },
+};
+
+pub const cpu_goldmontPlus = Cpu{
+ .name = "goldmont-plus",
+ .llvm_name = "goldmont-plus",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_sse,
+ &feature_aes,
+ &feature_clflushopt,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_sahf,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_prfchw,
+ &feature_ptwrite,
+ &feature_rdpid,
+ &feature_rdrnd,
+ &feature_rdseed,
+ &feature_sgx,
+ &feature_sha,
+ &feature_sse42,
+ &feature_ssse3,
+ &feature_slowIncdec,
+ &feature_slowLea,
+ &feature_slowTwoMemOps,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsavec,
+ &feature_xsaveopt,
+ &feature_xsaves,
+ },
+};
+
+pub const cpu_haswell = Cpu{
+ .name = "haswell",
+ .llvm_name = "haswell",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_sse,
+ &feature_avx,
+ &feature_avx2,
+ &feature_bmi,
+ &feature_bmi2,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_ermsb,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fastShldRotate,
+ &feature_fastScalarFsqrt,
+ &feature_fastVariableShuffle,
+ &feature_invpcid,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_falseDepsLzcntTzcnt,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_macrofusion,
+ &feature_mergeToThreewayBranch,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_falseDepsPopcnt,
+ &feature_rdrnd,
+ &feature_sse42,
+ &feature_slow3opsLea,
+ &feature_idivqToDivl,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsaveopt,
+ },
+};
+
+pub const cpu_i386 = Cpu{
+ .name = "i386",
+ .llvm_name = "i386",
+ .subfeatures = &[_]*const Feature {
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_i486 = Cpu{
+ .name = "i486",
+ .llvm_name = "i486",
+ .subfeatures = &[_]*const Feature {
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_i586 = Cpu{
+ .name = "i586",
+ .llvm_name = "i586",
+ .subfeatures = &[_]*const Feature {
+ &feature_cx8,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_i686 = Cpu{
+ .name = "i686",
+ .llvm_name = "i686",
+ .subfeatures = &[_]*const Feature {
+ &feature_cmov,
+ &feature_cx8,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_icelakeClient = Cpu{
+ .name = "icelake-client",
+ .llvm_name = "icelake-client",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_adx,
+ &feature_sse,
+ &feature_aes,
+ &feature_avx,
+ &feature_avx2,
+ &feature_avx512f,
+ &feature_avx512bitalg,
+ &feature_bmi,
+ &feature_bmi2,
+ &feature_avx512bw,
+ &feature_avx512cd,
+ &feature_clflushopt,
+ &feature_clwb,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_avx512dq,
+ &feature_ermsb,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fastShldRotate,
+ &feature_fastScalarFsqrt,
+ &feature_fastVariableShuffle,
+ &feature_fastVectorFsqrt,
+ &feature_gfni,
+ &feature_fastGather,
+ &feature_avx512ifma,
+ &feature_invpcid,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_macrofusion,
+ &feature_mergeToThreewayBranch,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_pku,
+ &feature_popcnt,
+ &feature_prfchw,
+ &feature_prefer256Bit,
+ &feature_rdpid,
+ &feature_rdrnd,
+ &feature_rdseed,
+ &feature_sgx,
+ &feature_sha,
+ &feature_sse42,
+ &feature_slow3opsLea,
+ &feature_idivqToDivl,
+ &feature_vaes,
+ &feature_avx512vbmi,
+ &feature_avx512vbmi2,
+ &feature_avx512vl,
+ &feature_avx512vnni,
+ &feature_vpclmulqdq,
+ &feature_avx512vpopcntdq,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsavec,
+ &feature_xsaveopt,
+ &feature_xsaves,
+ },
+};
+
+pub const cpu_icelakeServer = Cpu{
+ .name = "icelake-server",
+ .llvm_name = "icelake-server",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_adx,
+ &feature_sse,
+ &feature_aes,
+ &feature_avx,
+ &feature_avx2,
+ &feature_avx512f,
+ &feature_avx512bitalg,
+ &feature_bmi,
+ &feature_bmi2,
+ &feature_avx512bw,
+ &feature_avx512cd,
+ &feature_clflushopt,
+ &feature_clwb,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_avx512dq,
+ &feature_ermsb,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fastShldRotate,
+ &feature_fastScalarFsqrt,
+ &feature_fastVariableShuffle,
+ &feature_fastVectorFsqrt,
+ &feature_gfni,
+ &feature_fastGather,
+ &feature_avx512ifma,
+ &feature_invpcid,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_macrofusion,
+ &feature_mergeToThreewayBranch,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_pconfig,
+ &feature_pku,
+ &feature_popcnt,
+ &feature_prfchw,
+ &feature_prefer256Bit,
+ &feature_rdpid,
+ &feature_rdrnd,
+ &feature_rdseed,
+ &feature_sgx,
+ &feature_sha,
+ &feature_sse42,
+ &feature_slow3opsLea,
+ &feature_idivqToDivl,
+ &feature_vaes,
+ &feature_avx512vbmi,
+ &feature_avx512vbmi2,
+ &feature_avx512vl,
+ &feature_avx512vnni,
+ &feature_vpclmulqdq,
+ &feature_avx512vpopcntdq,
+ &feature_wbnoinvd,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsavec,
+ &feature_xsaveopt,
+ &feature_xsaves,
+ },
+};
+
+pub const cpu_ivybridge = Cpu{
+ .name = "ivybridge",
+ .llvm_name = "ivybridge",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_sse,
+ &feature_avx,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_f16c,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fastShldRotate,
+ &feature_fastScalarFsqrt,
+ &feature_sahf,
+ &feature_mmx,
+ &feature_macrofusion,
+ &feature_mergeToThreewayBranch,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_falseDepsPopcnt,
+ &feature_rdrnd,
+ &feature_sse42,
+ &feature_slow3opsLea,
+ &feature_idivqToDivl,
+ &feature_slowUnalignedMem32,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsaveopt,
+ },
+};
+
+pub const cpu_k6 = Cpu{
+ .name = "k6",
+ .llvm_name = "k6",
+ .subfeatures = &[_]*const Feature {
+ &feature_cx8,
+ &feature_mmx,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_k62 = Cpu{
+ .name = "k6-2",
+ .llvm_name = "k6-2",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_dnow3,
+ &feature_cx8,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_k63 = Cpu{
+ .name = "k6-3",
+ .llvm_name = "k6-3",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_dnow3,
+ &feature_cx8,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_k8 = Cpu{
+ .name = "k8",
+ .llvm_name = "k8",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_dnowa3,
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_fxsr,
+ &feature_fastScalarShiftMasks,
+ &feature_nopl,
+ &feature_sse,
+ &feature_sse2,
+ &feature_slowShld,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_k8Sse3 = Cpu{
+ .name = "k8-sse3",
+ .llvm_name = "k8-sse3",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_dnowa3,
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fxsr,
+ &feature_fastScalarShiftMasks,
+ &feature_nopl,
+ &feature_sse,
+ &feature_sse3,
+ &feature_slowShld,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_knl = Cpu{
+ .name = "knl",
+ .llvm_name = "knl",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_adx,
+ &feature_sse,
+ &feature_aes,
+ &feature_avx512f,
+ &feature_bmi,
+ &feature_bmi2,
+ &feature_avx512cd,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_avx512er,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fastPartialYmmOrZmmWrite,
+ &feature_fastGather,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_avx512pf,
+ &feature_popcnt,
+ &feature_prefetchwt1,
+ &feature_prfchw,
+ &feature_rdrnd,
+ &feature_rdseed,
+ &feature_slow3opsLea,
+ &feature_idivqToDivl,
+ &feature_slowIncdec,
+ &feature_slowPmaddwd,
+ &feature_slowTwoMemOps,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsaveopt,
+ },
+};
+
+pub const cpu_knm = Cpu{
+ .name = "knm",
+ .llvm_name = "knm",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_adx,
+ &feature_sse,
+ &feature_aes,
+ &feature_avx512f,
+ &feature_bmi,
+ &feature_bmi2,
+ &feature_avx512cd,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_avx512er,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fastPartialYmmOrZmmWrite,
+ &feature_fastGather,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_avx512pf,
+ &feature_popcnt,
+ &feature_prefetchwt1,
+ &feature_prfchw,
+ &feature_rdrnd,
+ &feature_rdseed,
+ &feature_slow3opsLea,
+ &feature_idivqToDivl,
+ &feature_slowIncdec,
+ &feature_slowPmaddwd,
+ &feature_slowTwoMemOps,
+ &feature_avx512vpopcntdq,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsaveopt,
+ },
+};
+
+pub const cpu_lakemont = Cpu{
+ .name = "lakemont",
+ .llvm_name = "lakemont",
+ .subfeatures = &[_]*const Feature {
+ },
+};
+
+pub const cpu_nehalem = Cpu{
+ .name = "nehalem",
+ .llvm_name = "nehalem",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fxsr,
+ &feature_sahf,
+ &feature_mmx,
+ &feature_macrofusion,
+ &feature_nopl,
+ &feature_popcnt,
+ &feature_sse,
+ &feature_sse42,
+ &feature_x87,
+ },
+};
+
+pub const cpu_nocona = Cpu{
+ .name = "nocona",
+ .llvm_name = "nocona",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fxsr,
+ &feature_mmx,
+ &feature_nopl,
+ &feature_sse,
+ &feature_sse3,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_opteron = Cpu{
+ .name = "opteron",
+ .llvm_name = "opteron",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_dnowa3,
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_fxsr,
+ &feature_fastScalarShiftMasks,
+ &feature_nopl,
+ &feature_sse,
+ &feature_sse2,
+ &feature_slowShld,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_opteronSse3 = Cpu{
+ .name = "opteron-sse3",
+ .llvm_name = "opteron-sse3",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_dnowa3,
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fxsr,
+ &feature_fastScalarShiftMasks,
+ &feature_nopl,
+ &feature_sse,
+ &feature_sse3,
+ &feature_slowShld,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_penryn = Cpu{
+ .name = "penryn",
+ .llvm_name = "penryn",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fxsr,
+ &feature_sahf,
+ &feature_mmx,
+ &feature_macrofusion,
+ &feature_nopl,
+ &feature_sse,
+ &feature_sse41,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_pentium = Cpu{
+ .name = "pentium",
+ .llvm_name = "pentium",
+ .subfeatures = &[_]*const Feature {
+ &feature_cx8,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_pentiumM = Cpu{
+ .name = "pentium-m",
+ .llvm_name = "pentium-m",
+ .subfeatures = &[_]*const Feature {
+ &feature_cmov,
+ &feature_cx8,
+ &feature_fxsr,
+ &feature_mmx,
+ &feature_nopl,
+ &feature_sse,
+ &feature_sse2,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_pentiumMmx = Cpu{
+ .name = "pentium-mmx",
+ .llvm_name = "pentium-mmx",
+ .subfeatures = &[_]*const Feature {
+ &feature_cx8,
+ &feature_mmx,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_pentium2 = Cpu{
+ .name = "pentium2",
+ .llvm_name = "pentium2",
+ .subfeatures = &[_]*const Feature {
+ &feature_cmov,
+ &feature_cx8,
+ &feature_fxsr,
+ &feature_mmx,
+ &feature_nopl,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_pentium3 = Cpu{
+ .name = "pentium3",
+ .llvm_name = "pentium3",
+ .subfeatures = &[_]*const Feature {
+ &feature_cmov,
+ &feature_cx8,
+ &feature_fxsr,
+ &feature_mmx,
+ &feature_nopl,
+ &feature_sse,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_pentium3m = Cpu{
+ .name = "pentium3m",
+ .llvm_name = "pentium3m",
+ .subfeatures = &[_]*const Feature {
+ &feature_cmov,
+ &feature_cx8,
+ &feature_fxsr,
+ &feature_mmx,
+ &feature_nopl,
+ &feature_sse,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_pentium4 = Cpu{
+ .name = "pentium4",
+ .llvm_name = "pentium4",
+ .subfeatures = &[_]*const Feature {
+ &feature_cmov,
+ &feature_cx8,
+ &feature_fxsr,
+ &feature_mmx,
+ &feature_nopl,
+ &feature_sse,
+ &feature_sse2,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_pentium4m = Cpu{
+ .name = "pentium4m",
+ .llvm_name = "pentium4m",
+ .subfeatures = &[_]*const Feature {
+ &feature_cmov,
+ &feature_cx8,
+ &feature_fxsr,
+ &feature_mmx,
+ &feature_nopl,
+ &feature_sse,
+ &feature_sse2,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_pentiumpro = Cpu{
+ .name = "pentiumpro",
+ .llvm_name = "pentiumpro",
+ .subfeatures = &[_]*const Feature {
+ &feature_cmov,
+ &feature_cx8,
+ &feature_nopl,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_prescott = Cpu{
+ .name = "prescott",
+ .llvm_name = "prescott",
+ .subfeatures = &[_]*const Feature {
+ &feature_cmov,
+ &feature_cx8,
+ &feature_fxsr,
+ &feature_mmx,
+ &feature_nopl,
+ &feature_sse,
+ &feature_sse3,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_sandybridge = Cpu{
+ .name = "sandybridge",
+ .llvm_name = "sandybridge",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_sse,
+ &feature_avx,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fxsr,
+ &feature_fastShldRotate,
+ &feature_fastScalarFsqrt,
+ &feature_sahf,
+ &feature_mmx,
+ &feature_macrofusion,
+ &feature_mergeToThreewayBranch,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_falseDepsPopcnt,
+ &feature_sse42,
+ &feature_slow3opsLea,
+ &feature_idivqToDivl,
+ &feature_slowUnalignedMem32,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsaveopt,
+ },
+};
+
+pub const cpu_silvermont = Cpu{
+ .name = "silvermont",
+ .llvm_name = "silvermont",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fxsr,
+ &feature_sahf,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_nopl,
+ &feature_sse,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_falseDepsPopcnt,
+ &feature_prfchw,
+ &feature_rdrnd,
+ &feature_sse42,
+ &feature_ssse3,
+ &feature_idivqToDivl,
+ &feature_slowIncdec,
+ &feature_slowLea,
+ &feature_slowPmulld,
+ &feature_slowTwoMemOps,
+ &feature_x87,
+ },
+};
+
+pub const cpu_skx = Cpu{
+ .name = "skx",
+ .llvm_name = "skx",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_adx,
+ &feature_sse,
+ &feature_aes,
+ &feature_avx,
+ &feature_avx2,
+ &feature_avx512f,
+ &feature_bmi,
+ &feature_bmi2,
+ &feature_avx512bw,
+ &feature_avx512cd,
+ &feature_clflushopt,
+ &feature_clwb,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_avx512dq,
+ &feature_ermsb,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fastShldRotate,
+ &feature_fastScalarFsqrt,
+ &feature_fastVariableShuffle,
+ &feature_fastVectorFsqrt,
+ &feature_fastGather,
+ &feature_invpcid,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_macrofusion,
+ &feature_mergeToThreewayBranch,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_pku,
+ &feature_popcnt,
+ &feature_falseDepsPopcnt,
+ &feature_prfchw,
+ &feature_prefer256Bit,
+ &feature_rdrnd,
+ &feature_rdseed,
+ &feature_sse42,
+ &feature_slow3opsLea,
+ &feature_idivqToDivl,
+ &feature_avx512vl,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsavec,
+ &feature_xsaveopt,
+ &feature_xsaves,
+ },
+};
+
+pub const cpu_skylake = Cpu{
+ .name = "skylake",
+ .llvm_name = "skylake",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_adx,
+ &feature_sse,
+ &feature_aes,
+ &feature_avx,
+ &feature_avx2,
+ &feature_bmi,
+ &feature_bmi2,
+ &feature_clflushopt,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_ermsb,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fastShldRotate,
+ &feature_fastScalarFsqrt,
+ &feature_fastVariableShuffle,
+ &feature_fastVectorFsqrt,
+ &feature_fastGather,
+ &feature_invpcid,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_macrofusion,
+ &feature_mergeToThreewayBranch,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_falseDepsPopcnt,
+ &feature_prfchw,
+ &feature_rdrnd,
+ &feature_rdseed,
+ &feature_sgx,
+ &feature_sse42,
+ &feature_slow3opsLea,
+ &feature_idivqToDivl,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsavec,
+ &feature_xsaveopt,
+ &feature_xsaves,
+ },
+};
+
+pub const cpu_skylakeAvx512 = Cpu{
+ .name = "skylake-avx512",
+ .llvm_name = "skylake-avx512",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_adx,
+ &feature_sse,
+ &feature_aes,
+ &feature_avx,
+ &feature_avx2,
+ &feature_avx512f,
+ &feature_bmi,
+ &feature_bmi2,
+ &feature_avx512bw,
+ &feature_avx512cd,
+ &feature_clflushopt,
+ &feature_clwb,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_avx512dq,
+ &feature_ermsb,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fastShldRotate,
+ &feature_fastScalarFsqrt,
+ &feature_fastVariableShuffle,
+ &feature_fastVectorFsqrt,
+ &feature_fastGather,
+ &feature_invpcid,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_macrofusion,
+ &feature_mergeToThreewayBranch,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_pku,
+ &feature_popcnt,
+ &feature_falseDepsPopcnt,
+ &feature_prfchw,
+ &feature_prefer256Bit,
+ &feature_rdrnd,
+ &feature_rdseed,
+ &feature_sse42,
+ &feature_slow3opsLea,
+ &feature_idivqToDivl,
+ &feature_avx512vl,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsavec,
+ &feature_xsaveopt,
+ &feature_xsaves,
+ },
+};
+
+pub const cpu_slm = Cpu{
+ .name = "slm",
+ .llvm_name = "slm",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fxsr,
+ &feature_sahf,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_nopl,
+ &feature_sse,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_falseDepsPopcnt,
+ &feature_prfchw,
+ &feature_rdrnd,
+ &feature_sse42,
+ &feature_ssse3,
+ &feature_idivqToDivl,
+ &feature_slowIncdec,
+ &feature_slowLea,
+ &feature_slowPmulld,
+ &feature_slowTwoMemOps,
+ &feature_x87,
+ },
+};
+
+pub const cpu_tigerlake = Cpu{
+ .name = "tigerlake",
+ .llvm_name = "tigerlake",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_adx,
+ &feature_sse,
+ &feature_aes,
+ &feature_avx,
+ &feature_avx2,
+ &feature_avx512f,
+ &feature_avx512bitalg,
+ &feature_bmi,
+ &feature_bmi2,
+ &feature_avx512bw,
+ &feature_avx512cd,
+ &feature_clflushopt,
+ &feature_clwb,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_avx512dq,
+ &feature_ermsb,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fastShldRotate,
+ &feature_fastScalarFsqrt,
+ &feature_fastVariableShuffle,
+ &feature_fastVectorFsqrt,
+ &feature_gfni,
+ &feature_fastGather,
+ &feature_avx512ifma,
+ &feature_invpcid,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_movdir64b,
+ &feature_movdiri,
+ &feature_macrofusion,
+ &feature_mergeToThreewayBranch,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_pku,
+ &feature_popcnt,
+ &feature_prfchw,
+ &feature_prefer256Bit,
+ &feature_rdpid,
+ &feature_rdrnd,
+ &feature_rdseed,
+ &feature_sgx,
+ &feature_sha,
+ &feature_shstk,
+ &feature_sse42,
+ &feature_slow3opsLea,
+ &feature_idivqToDivl,
+ &feature_vaes,
+ &feature_avx512vbmi,
+ &feature_avx512vbmi2,
+ &feature_avx512vl,
+ &feature_avx512vnni,
+ &feature_avx512vp2intersect,
+ &feature_vpclmulqdq,
+ &feature_avx512vpopcntdq,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsavec,
+ &feature_xsaveopt,
+ &feature_xsaves,
+ },
+};
+
+pub const cpu_tremont = Cpu{
+ .name = "tremont",
+ .llvm_name = "tremont",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_sse,
+ &feature_aes,
+ &feature_cldemote,
+ &feature_clflushopt,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_gfni,
+ &feature_sahf,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_movdir64b,
+ &feature_movdiri,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_prfchw,
+ &feature_ptwrite,
+ &feature_rdpid,
+ &feature_rdrnd,
+ &feature_rdseed,
+ &feature_sgx,
+ &feature_sha,
+ &feature_sse42,
+ &feature_ssse3,
+ &feature_slowIncdec,
+ &feature_slowLea,
+ &feature_slowTwoMemOps,
+ &feature_waitpkg,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsavec,
+ &feature_xsaveopt,
+ &feature_xsaves,
+ },
+};
+
+pub const cpu_westmere = Cpu{
+ .name = "westmere",
+ .llvm_name = "westmere",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_fxsr,
+ &feature_sahf,
+ &feature_mmx,
+ &feature_macrofusion,
+ &feature_nopl,
+ &feature_sse,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_sse42,
+ &feature_x87,
+ },
+};
+
+pub const cpu_winchipC6 = Cpu{
+ .name = "winchip-c6",
+ .llvm_name = "winchip-c6",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_winchip2 = Cpu{
+ .name = "winchip2",
+ .llvm_name = "winchip2",
+ .subfeatures = &[_]*const Feature {
+ &feature_mmx,
+ &feature_dnow3,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_x8664 = Cpu{
+ .name = "x86-64",
+ .llvm_name = "x86-64",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_fxsr,
+ &feature_mmx,
+ &feature_macrofusion,
+ &feature_nopl,
+ &feature_sse,
+ &feature_sse2,
+ &feature_slow3opsLea,
+ &feature_slowIncdec,
+ &feature_x87,
+ },
+};
+
+pub const cpu_yonah = Cpu{
+ .name = "yonah",
+ .llvm_name = "yonah",
+ .subfeatures = &[_]*const Feature {
+ &feature_cmov,
+ &feature_cx8,
+ &feature_fxsr,
+ &feature_mmx,
+ &feature_nopl,
+ &feature_sse,
+ &feature_sse3,
+ &feature_slowUnalignedMem16,
+ &feature_x87,
+ },
+};
+
+pub const cpu_znver1 = Cpu{
+ .name = "znver1",
+ .llvm_name = "znver1",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_adx,
+ &feature_sse,
+ &feature_aes,
+ &feature_avx2,
+ &feature_bmi,
+ &feature_bmi2,
+ &feature_branchfusion,
+ &feature_clflushopt,
+ &feature_clzero,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fast15bytenop,
+ &feature_fastBextr,
+ &feature_fastLzcnt,
+ &feature_fastScalarShiftMasks,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_mwaitx,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_prfchw,
+ &feature_rdrnd,
+ &feature_rdseed,
+ &feature_sha,
+ &feature_sse4a,
+ &feature_slowShld,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsavec,
+ &feature_xsaveopt,
+ &feature_xsaves,
+ },
+};
+
+pub const cpu_znver2 = Cpu{
+ .name = "znver2",
+ .llvm_name = "znver2",
+ .subfeatures = &[_]*const Feature {
+ &feature_bit64,
+ &feature_adx,
+ &feature_sse,
+ &feature_aes,
+ &feature_avx2,
+ &feature_bmi,
+ &feature_bmi2,
+ &feature_branchfusion,
+ &feature_clflushopt,
+ &feature_clwb,
+ &feature_clzero,
+ &feature_cmov,
+ &feature_cx8,
+ &feature_cx16,
+ &feature_f16c,
+ &feature_fma,
+ &feature_fsgsbase,
+ &feature_fxsr,
+ &feature_fast15bytenop,
+ &feature_fastBextr,
+ &feature_fastLzcnt,
+ &feature_fastScalarShiftMasks,
+ &feature_sahf,
+ &feature_lzcnt,
+ &feature_mmx,
+ &feature_movbe,
+ &feature_mwaitx,
+ &feature_nopl,
+ &feature_pclmul,
+ &feature_popcnt,
+ &feature_prfchw,
+ &feature_rdpid,
+ &feature_rdrnd,
+ &feature_rdseed,
+ &feature_sha,
+ &feature_sse4a,
+ &feature_slowShld,
+ &feature_wbnoinvd,
+ &feature_x87,
+ &feature_xsave,
+ &feature_xsavec,
+ &feature_xsaveopt,
+ &feature_xsaves,
+ },
+};
+
+pub const cpus = &[_]*const Cpu {
+ &cpu_amdfam10,
+ &cpu_athlon,
+ &cpu_athlon4,
+ &cpu_athlonFx,
+ &cpu_athlonMp,
+ &cpu_athlonTbird,
+ &cpu_athlonXp,
+ &cpu_athlon64,
+ &cpu_athlon64Sse3,
+ &cpu_atom,
+ &cpu_barcelona,
+ &cpu_bdver1,
+ &cpu_bdver2,
+ &cpu_bdver3,
+ &cpu_bdver4,
+ &cpu_bonnell,
+ &cpu_broadwell,
+ &cpu_btver1,
+ &cpu_btver2,
+ &cpu_c3,
+ &cpu_c32,
+ &cpu_cannonlake,
+ &cpu_cascadelake,
+ &cpu_cooperlake,
+ &cpu_coreAvxI,
+ &cpu_coreAvx2,
+ &cpu_core2,
+ &cpu_corei7,
+ &cpu_corei7Avx,
+ &cpu_generic,
+ &cpu_geode,
+ &cpu_goldmont,
+ &cpu_goldmontPlus,
+ &cpu_haswell,
+ &cpu_i386,
+ &cpu_i486,
+ &cpu_i586,
+ &cpu_i686,
+ &cpu_icelakeClient,
+ &cpu_icelakeServer,
+ &cpu_ivybridge,
+ &cpu_k6,
+ &cpu_k62,
+ &cpu_k63,
+ &cpu_k8,
+ &cpu_k8Sse3,
+ &cpu_knl,
+ &cpu_knm,
+ &cpu_lakemont,
+ &cpu_nehalem,
+ &cpu_nocona,
+ &cpu_opteron,
+ &cpu_opteronSse3,
+ &cpu_penryn,
+ &cpu_pentium,
+ &cpu_pentiumM,
+ &cpu_pentiumMmx,
+ &cpu_pentium2,
+ &cpu_pentium3,
+ &cpu_pentium3m,
+ &cpu_pentium4,
+ &cpu_pentium4m,
+ &cpu_pentiumpro,
+ &cpu_prescott,
+ &cpu_sandybridge,
+ &cpu_silvermont,
+ &cpu_skx,
+ &cpu_skylake,
+ &cpu_skylakeAvx512,
+ &cpu_slm,
+ &cpu_tigerlake,
+ &cpu_tremont,
+ &cpu_westmere,
+ &cpu_winchipC6,
+ &cpu_winchip2,
+ &cpu_x8664,
+ &cpu_yonah,
+ &cpu_znver1,
+ &cpu_znver2,
+};
lib/std/target.zig
@@ -2,9 +2,6 @@ const std = @import("std.zig");
const mem = std.mem;
const builtin = std.builtin;
-pub const feature = @import("target/feature.zig");
-pub const cpu = @import("target/cpu.zig");
-
/// TODO Nearly all the functions in this namespace would be
/// better off if https://github.com/ziglang/zig/issues/425
/// was solved.
@@ -844,3 +841,78 @@ pub const Target = union(enum) {
return .unavailable;
}
};
+
+pub const aarch64 = @import("target/aarch64.zig");
+pub const amdgpu = @import("target/amdgpu.zig");
+pub const arm = @import("target/arm.zig");
+pub const avr = @import("target/avr.zig");
+pub const bpf = @import("target/bpf.zig");
+pub const hexagon = @import("target/hexagon.zig");
+pub const mips = @import("target/mips.zig");
+pub const msp430 = @import("target/msp430.zig");
+pub const nvptx = @import("target/nvptx.zig");
+pub const powerpc = @import("target/powerpc.zig");
+pub const riscv = @import("target/riscv.zig");
+pub const sparc = @import("target/sparc.zig");
+pub const systemz = @import("target/systemz.zig");
+pub const wasm = @import("target/wasm.zig");
+pub const x86 = @import("target/x86.zig");
+
+pub const Feature = struct {
+ name: []const u8,
+ description: []const u8,
+ llvm_name: []const u8,
+
+ subfeatures: []*const Feature,
+};
+
+pub const Cpu = struct {
+ name: []const u8,
+ llvm_name: []const u8,
+
+ subfeatures: []*const Feature,
+};
+
+pub fn getFeaturesForArch(arch: @TagType(Target.Arch)) []*const Feature {
+ return switch (arch) {
+ .arm, .armeb, .thumb, .thumbeb => arm.features,
+ .aarch64, .aarch64_be, .aarch64_32 => aarch64.features,
+ .avr => avr.features,
+ .bpfel, .bpfeb => bpf.features,
+ .hexagon => hexagon.features,
+ .mips, .mipsel, .mips64, .mips64el => mips.features,
+ .msp430 => msp430.features,
+ .powerpc, .powerpc64, .powerpc64le => powerpc.features,
+ .amdgcn => amdgpu.features,
+ .riscv32, .riscv64 => riscv.features,
+ .sparc, .sparcv9, .sparcel => sparc.features,
+ .s390x => systemz.features,
+ .i386, .x86_64 => x86.features,
+ .nvptx, .nvptx64 => nvptx.features,
+ .wasm32, .wasm64 => wasm.features,
+
+ else => &[_]*const Feature{},
+ };
+}
+
+pub fn getCpusForArch(arch: @TagType(Target.Arch)) []*const Cpu {
+ return switch (arch) {
+ .arm, .armeb, .thumb, .thumbeb => arm.cpus,
+ .aarch64, .aarch64_be, .aarch64_32 => aarch64.cpus,
+ .avr => avr.cpus,
+ .bpfel, .bpfeb => bpf.cpus,
+ .hexagon => hexagon.cpus,
+ .mips, .mipsel, .mips64, .mips64el => mips.cpus,
+ .msp430 => msp430.cpus,
+ .powerpc, .powerpc64, .powerpc64le => powerpc.cpus,
+ .amdgcn => amdgpu.cpus,
+ .riscv32, .riscv64 => riscv.cpus,
+ .sparc, .sparcv9, .sparcel => sparc.cpus,
+ .s390x => systemz.cpus,
+ .i386, .x86_64 => x86.cpus,
+ .nvptx, .nvptx64 => nvptx.cpus,
+ .wasm32, .wasm64 => wasm.cpus,
+
+ else => &[_]*const Cpu{},
+ };
+}
src-self-hosted/stage1.zig
@@ -6,8 +6,6 @@ const io = std.io;
const mem = std.mem;
const fs = std.fs;
const process = std.process;
-const feature = std.target.feature;
-const cpu = std.target.cpu;
const Allocator = mem.Allocator;
const ArrayList = std.ArrayList;
const Buffer = std.Buffer;
@@ -546,34 +544,30 @@ fn print_features_for_arch(arch_name: []const u8, show_subfeatures: bool) !void
return;
};
- inline for (@typeInfo(@TagType(Target.Arch)).Enum.fields) |arch_enum_field| {
- if (@enumToInt(arch) == arch_enum_field.value) {
- const enum_arch = @intToEnum(@TagType(Target.Arch), arch_enum_field.value);
+ try stdout_stream.print("Available features for {}:\n", .{ @tagName(arch) });
- const feature_infos = feature.ArchFeature(enum_arch).feature_infos;
+ const features = std.target.getFeaturesForArch(arch);
- try stdout_stream.print("Available features for {}:\n", .{ arch_enum_field.name });
-
- var longest_len: usize = 0;
- for (feature_infos) |feature_info| {
- if (feature_info.name.len > longest_len) longest_len = feature_info.name.len;
- }
+ var longest_len: usize = 0;
+ for (features) |feature| {
+ if (feature.name.len > longest_len) {
+ longest_len = feature.name.len;
+ }
+ }
- for (feature_infos) |feature_info| {
- try stdout_stream.print(" {}", .{ feature_info.name });
-
- var i: usize = 0;
- while (i < longest_len - feature_info.name.len) : (i += 1) {
- try stdout_stream.write(" ");
- }
+ for (features) |feature| {
+ try stdout_stream.print(" {}", .{ feature.name });
+
+ var i: usize = 0;
+ while (i < longest_len - feature.name.len) : (i += 1) {
+ try stdout_stream.write(" ");
+ }
- try stdout_stream.print(" - {}\n", .{ feature_info.description });
+ try stdout_stream.print(" - {}\n", .{ feature.description });
- if (show_subfeatures and feature_info.subfeatures.len > 0) {
- for (feature_info.subfeatures) |subfeature| {
- try stdout_stream.print(" {}\n", .{ subfeature.getInfo().name });
- }
- }
+ if (show_subfeatures and feature.subfeatures.len > 0) {
+ for (feature.subfeatures) |subfeature| {
+ try stdout_stream.print(" {}\n", .{ subfeature.name });
}
}
}
@@ -594,35 +588,33 @@ fn print_cpus_for_arch(arch_name: []const u8, show_subfeatures: bool) !void {
return;
};
- inline for (@typeInfo(@TagType(Target.Arch)).Enum.fields) |arch_enum_field| {
- if (@enumToInt(arch) == arch_enum_field.value) {
- const enum_arch = @intToEnum(@TagType(Target.Arch), arch_enum_field.value);
-
- const cpu_infos = cpu.ArchCpu(enum_arch).cpu_infos;
+ const cpus = std.target.getCpusForArch(arch);
- try stdout_stream.print("Available cpus for {}:\n", .{ arch_enum_field.name });
+ try stdout_stream.print("Available cpus for {}:\n", .{ @tagName(arch) });
- var longest_len: usize = 0;
- for (cpu_infos) |cpu_info| {
- if (cpu_info.name.len > longest_len) longest_len = cpu_info.name.len;
- }
+ var longest_len: usize = 0;
+ for (cpus) |cpu| {
+ if (cpu.name.len > longest_len) {
+ longest_len = cpu.name.len;
+ }
+ }
- for (cpu_infos) |cpu_info| {
- try stdout_stream.print(" {}", .{ cpu_info.name });
-
- var i: usize = 0;
- while (i < longest_len - cpu_info.name.len) : (i += 1) {
- try stdout_stream.write(" ");
- }
+ for (cpus) |cpu| {
+ try stdout_stream.print(" {}", .{ cpu.name });
+
+ var i: usize = 0;
+ while (i < longest_len - cpu.name.len) : (i += 1) {
+ try stdout_stream.write(" ");
+ }
- try stdout_stream.write("\n");
+ try stdout_stream.write("\n");
- if (show_subfeatures and cpu_info.features.len > 0) {
- for (cpu_info.features) |subfeature| {
- try stdout_stream.print(" {}\n", .{ subfeature.getInfo().name });
- }
- }
+ if (show_subfeatures and cpu.subfeatures.len > 0) {
+ for (cpu.subfeatures) |subfeature| {
+ try stdout_stream.print(" {}\n", .{ subfeature.name });
}
}
}
}
+
+// use target_arch_name(ZigLLVM_ArchType) to get name from main.cpp 'target'.