Commit b07958e6b7

@@ -1,70 +0,0 @@
-#if __ARM_PCS_VFP
-
-.syntax unified
-.fpu vfp
-
-.global fegetround
-.type fegetround,%function
-fegetround:
-	fmrx r0, fpscr
-	and r0, r0, #0xc00000
-	bx lr
-
-.global __fesetround
-.hidden __fesetround
-.type __fesetround,%function
-__fesetround:
-	fmrx r3, fpscr
-	bic r3, r3, #0xc00000
-	orr r3, r3, r0
-	fmxr fpscr, r3
-	mov r0, #0
-	bx lr
-
-.global fetestexcept
-.type fetestexcept,%function
-fetestexcept:
-	and r0, r0, #0x1f
-	fmrx r3, fpscr
-	and r0, r0, r3
-	bx lr
-
-.global feclearexcept
-.type feclearexcept,%function
-feclearexcept:
-	and r0, r0, #0x1f
-	fmrx r3, fpscr
-	bic r3, r3, r0
-	fmxr fpscr, r3
-	mov r0, #0
-	bx lr
-
-.global feraiseexcept
-.type feraiseexcept,%function
-feraiseexcept:
-	and r0, r0, #0x1f
-	fmrx r3, fpscr
-	orr r3, r3, r0
-	fmxr fpscr, r3
-	mov r0, #0
-	bx lr
-
-.global fegetenv
-.type fegetenv,%function
-fegetenv:
-	fmrx r3, fpscr
-	str r3, [r0]
-	mov r0, #0
-	bx lr
-
-.global fesetenv
-.type fesetenv,%function
-fesetenv:
-	cmn r0, #1
-	moveq r3, #0
-	ldrne r3, [r0]
-	fmxr fpscr, r3
-	mov r0, #0
-	bx lr
-
-#endif

@@ -1,72 +0,0 @@
-#ifndef __mips_soft_float
-
-.set noreorder
-
-.global feclearexcept
-.type  feclearexcept,@function
-feclearexcept:
-	and     $4, $4, 0x7c
-	cfc1    $5, $31
-	or      $5, $5, $4
-	xor     $5, $5, $4
-	ctc1    $5, $31
-	jr      $ra
-	li      $2, 0
-
-.global feraiseexcept
-.type  feraiseexcept,@function
-feraiseexcept:
-	and     $4, $4, 0x7c
-	cfc1    $5, $31
-	or      $5, $5, $4
-	ctc1    $5, $31
-	jr      $ra
-	li      $2, 0
-
-.global fetestexcept
-.type  fetestexcept,@function
-fetestexcept:
-	and     $4, $4, 0x7c
-	cfc1    $2, $31
-	jr      $ra
-	and     $2, $2, $4
-
-.global fegetround
-.type  fegetround,@function
-fegetround:
-	cfc1    $2, $31
-	jr      $ra
-	andi    $2, $2, 3
-
-.global __fesetround
-.hidden __fesetround
-.type __fesetround,@function
-__fesetround:
-	cfc1    $5, $31
-	li      $6, -4
-	and     $5, $5, $6
-	or      $5, $5, $4
-	ctc1    $5, $31
-	jr      $ra
-	li      $2, 0
-
-.global fegetenv
-.type  fegetenv,@function
-fegetenv:
-	cfc1    $5, $31
-	sw      $5, 0($4)
-	jr      $ra
-	li      $2, 0
-
-.global fesetenv
-.type  fesetenv,@function
-fesetenv:
-	addiu   $5, $4, 1
-	beq     $5, $0, 1f
-	 nop
-	lw      $5, 0($4)
-1:	ctc1    $5, $31
-	jr      $ra
-	li      $2, 0
-
-#endif

@@ -1,72 +0,0 @@
-#ifndef __mips_soft_float
-
-.set	noreorder
-
-.global	feclearexcept
-.type	feclearexcept,@function
-feclearexcept:
-	and	$4, $4, 0x7c
-	cfc1	$5, $31
-	or	$5, $5, $4
-	xor	$5, $5, $4
-	ctc1	$5, $31
-	jr	$ra
-	li	$2, 0
-
-.global	feraiseexcept
-.type	feraiseexcept,@function
-feraiseexcept:
-	and	$4, $4, 0x7c
-	cfc1	$5, $31
-	or	$5, $5, $4
-	ctc1	$5, $31
-	jr	$ra
-	li	$2, 0
-
-.global	fetestexcept
-.type	fetestexcept,@function
-fetestexcept:
-	and	$4, $4, 0x7c
-	cfc1	$2, $31
-	jr	$ra
-	and	$2, $2, $4
-
-.global	fegetround
-.type	fegetround,@function
-fegetround:
-	cfc1	$2, $31
-	jr	$ra
-	andi	$2, $2, 3
-
-.global	__fesetround
-.hidden __fesetround
-.type	__fesetround,@function
-__fesetround:
-	cfc1	$5, $31
-	li	$6, -4
-	and	$5, $5, $6
-	or	$5, $5, $4
-	ctc1	$5, $31
-	jr	$ra
-	li	$2, 0
-
-.global	fegetenv
-.type	fegetenv,@function
-fegetenv:
-	cfc1	$5, $31
-	sw	$5, 0($4)
-	jr	$ra
-	li	$2, 0
-
-.global	fesetenv
-.type	fesetenv,@function
-fesetenv:
-	daddiu	$5, $4, 1
-	beq	$5, $0, 1f
-	nop
-	lw	$5, 0($4)
-1:	ctc1	$5, $31
-	jr	$ra
-	li	$2, 0
-
-#endif

@@ -1,71 +0,0 @@
-#ifndef __mips_soft_float
-
-.set	noreorder
-.global	feclearexcept
-.type	feclearexcept,@function
-feclearexcept:
-	and	$4, $4, 0x7c
-	cfc1	$5, $31
-	or	$5, $5, $4
-	xor	$5, $5, $4
-	ctc1	$5, $31
-	jr	$ra
-	li	$2, 0
-
-.global feraiseexcept
-.type  feraiseexcept,@function
-feraiseexcept:
-	and	$4, $4, 0x7c
-	cfc1	$5, $31
-	or	$5, $5, $4
-	ctc1	$5, $31
-	jr	$ra
-	li	$2, 0
-
-.global fetestexcept
-.type  fetestexcept,@function
-fetestexcept:
-	and	$4, $4, 0x7c
-	cfc1	$2, $31
-	jr	$ra
-	and	$2, $2, $4
-
-.global fegetround
-.type  fegetround,@function
-fegetround:
-	cfc1	$2, $31
-	jr	$ra
-	andi	$2, $2, 3
-
-.global __fesetround
-.hidden __fesetround
-.type __fesetround,@function
-__fesetround:
-	cfc1	$5, $31
-	li	$6, -4
-	and	$5, $5, $6
-	or	$5, $5, $4
-	ctc1	$5, $31
-	jr	$ra
-	li	$2, 0
-
-.global fegetenv
-.type  fegetenv,@function
-fegetenv:
-	cfc1	$5, $31
-	sw	$5, 0($4)
-	jr	$ra
-	li	$2, 0
-
-.global fesetenv
-.type  fesetenv,@function
-fesetenv:
-	addiu   $5, $4, 1
-	beq	$5, $0, 1f
-	nop
-	lw	$5, 0($4)
-1:	ctc1	$5, $31
-	jr	$ra
-	li	$2, 0
-
-#endif

@@ -1,130 +0,0 @@
-#if !defined(_SOFT_FLOAT) && !defined(__NO_FPRS__)
-.global feclearexcept
-.type feclearexcept,@function
-feclearexcept:
-	andis. 3,3,0x3e00
-	/* if (r3 & FE_INVALID) r3 |= all_invalid_flags */
-	andis. 0,3,0x2000
-	stwu 1,-16(1)
-	beq- 0,1f
-	oris 3,3,0x01f8
-	ori  3,3,0x0700
-1:
-	/*
-	 * note: fpscr contains various fpu status and control
-	 * flags and we dont check if r3 may alter other flags
-	 * than the exception related ones
-	 * ufpscr &= ~r3
-	 */
-	mffs 0
-	stfd 0,8(1)
-	lwz 9,12(1)
-	andc 9,9,3
-	stw 9,12(1)
-	lfd 0,8(1)
-	mtfsf 255,0
-
-	/* return 0 */
-	li 3,0
-	addi 1,1,16
-	blr
-
-.global feraiseexcept
-.type feraiseexcept,@function
-feraiseexcept:
-	andis. 3,3,0x3e00
-	/* if (r3 & FE_INVALID) r3 |= software_invalid_flag */
-	andis. 0,3,0x2000
-	stwu 1,-16(1)
-	beq- 0,1f
-	ori 3,3,0x0400
-1:
-	/* fpscr |= r3 */
-	mffs 0
-	stfd 0,8(1)
-	lwz 9,12(1)
-	or 9,9,3
-	stw 9,12(1)
-	lfd 0,8(1)
-	mtfsf 255,0
-
-	/* return 0 */
-	li 3,0
-	addi 1,1,16
-	blr
-
-.global fetestexcept
-.type fetestexcept,@function
-fetestexcept:
-	andis. 3,3,0x3e00
-	/* return r3 & fpscr */
-	stwu 1,-16(1)
-	mffs 0
-	stfd 0,8(1)
-	lwz 9,12(1)
-	addi 1,1,16
-	and 3,3,9
-	blr
-
-.global fegetround
-.type fegetround,@function
-fegetround:
-	/* return fpscr & 3 */
-	stwu 1,-16(1)
-	mffs 0
-	stfd 0,8(1)
-	lwz 3,12(1)
-	addi 1,1,16
-	clrlwi 3,3,30
-	blr
-
-.global __fesetround
-.hidden __fesetround
-.type __fesetround,@function
-__fesetround:
-	/*
-	 * note: invalid input is not checked, r3 < 4 must hold
-	 * fpscr = (fpscr & -4U) | r3
-	 */
-	stwu 1,-16(1)
-	mffs 0
-	stfd 0,8(1)
-	lwz 9,12(1)
-	clrrwi 9,9,2
-	or 9,9,3
-	stw 9,12(1)
-	lfd 0,8(1)
-	mtfsf 255,0
-
-	/* return 0 */
-	li 3,0
-	addi 1,1,16
-	blr
-
-.global fegetenv
-.type fegetenv,@function
-fegetenv:
-	/* *r3 = fpscr */
-	mffs 0
-	stfd 0,0(3)
-	/* return 0 */
-	li 3,0
-	blr
-
-.global fesetenv
-.type fesetenv,@function
-fesetenv:
-	cmpwi 3, -1
-	bne 1f
-	mflr 4
-	bl 2f
-	.zero 8
-2:	mflr 3
-	mtlr 4
-1:	/* fpscr = *r3 */
-	lfd 0,0(3)
-	mtfsf 255,0
-	/* return 0 */
-	li 3,0
-	blr
-#endif

@@ -1,56 +0,0 @@
-#ifdef __riscv_flen
-
-.global feclearexcept
-.type feclearexcept, %function
-feclearexcept:
-	csrc fflags, a0
-	li a0, 0
-	ret
-
-.global feraiseexcept
-.type feraiseexcept, %function
-feraiseexcept:
-	csrs fflags, a0
-	li a0, 0
-	ret
-
-.global fetestexcept
-.type fetestexcept, %function
-fetestexcept:
-	frflags t0
-	and a0, t0, a0
-	ret
-
-.global fegetround
-.type fegetround, %function
-fegetround:
-	frrm a0
-	ret
-
-.global __fesetround
-.type __fesetround, %function
-__fesetround:
-	fsrm t0, a0
-	li a0, 0
-	ret
-
-.global fegetenv
-.type fegetenv, %function
-fegetenv:
-	frcsr t0
-	sw t0, 0(a0)
-	li a0, 0
-	ret
-
-.global fesetenv
-.type fesetenv, %function
-fesetenv:
-	li t2, -1
-	li t1, 0
-	beq a0, t2, 1f
-	lw t1, 0(a0)
-1:	fscsr t1
-	li a0, 0
-	ret
-
-#endif

@@ -1,81 +0,0 @@
-#if __SH_FPU_ANY__ || __SH4__
-
-.global fegetround
-.type   fegetround, @function
-fegetround:
-	sts fpscr, r0
-	rts
-	 and #3, r0
-
-.global __fesetround
-.hidden __fesetround
-.type   __fesetround, @function
-__fesetround:
-	sts fpscr, r0
-	mov #-4, r1
-	and r1, r0
-	or  r4, r0
-	lds r0, fpscr
-	rts
-	 mov #0, r0
-
-.global fetestexcept
-.type   fetestexcept, @function
-fetestexcept:
-	sts fpscr, r0
-	and r4, r0
-	rts
-	 and #0x7c, r0
-
-.global feclearexcept
-.type   feclearexcept, @function
-feclearexcept:
-	mov r4, r0
-	and #0x7c, r0
-	not r0, r4
-	sts fpscr, r0
-	and r4, r0
-	lds r0, fpscr
-	rts
-	 mov #0, r0
-
-.global feraiseexcept
-.type   feraiseexcept, @function
-feraiseexcept:
-	mov r4, r0
-	and #0x7c, r0
-	sts fpscr, r4
-	or  r4, r0
-	lds r0, fpscr
-	rts
-	 mov #0, r0
-
-.global fegetenv
-.type   fegetenv, @function
-fegetenv:
-	sts fpscr, r0
-	mov.l r0, @r4
-	rts
-	 mov #0, r0
-
-.global fesetenv
-.type   fesetenv, @function
-fesetenv:
-	mov r4, r0
-	cmp/eq #-1, r0
-	bf 1f
-
-	! the default environment is complicated by the fact that we need to
-	! preserve the current precision bit, which we do not know a priori
-	sts fpscr, r0
-	mov #8, r1
-	swap.w r1, r1
-	bra 2f
-	 and r1, r0
-
-1:	mov.l @r4, r0      ! non-default environment
-2:	lds r0, fpscr
-	rts
-	 mov #0, r0
-
-#endif

@@ -1,3 +0,0 @@
-#define __dlsym __dlsym_redir_time64
-#define dlsym __dlsym_time64
-#include "dlsym.s"

@@ -1,55 +0,0 @@
-.syntax unified
-
-.text
-.global __tlsdesc_static
-.hidden __tlsdesc_static
-.type __tlsdesc_static,%function
-__tlsdesc_static:
-	ldr r0,[r0]
-	bx lr
-
-.global __tlsdesc_dynamic
-.hidden __tlsdesc_dynamic
-.type __tlsdesc_dynamic,%function
-__tlsdesc_dynamic:
-	push {r2,r3,ip,lr}
-	ldr r1,[r0]
-	ldr r2,[r1,#4]  // r2 = offset
-	ldr r1,[r1]     // r1 = modid
-
-#if ((__ARM_ARCH_6K__ || __ARM_ARCH_6KZ__ || __ARM_ARCH_6ZK__) && !__thumb__) \
- || __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
-	mrc p15,0,r0,c13,c0,3
-#else
-	ldr r0,1f
-	add r0,r0,pc
-	ldr r0,[r0]
-2:
-#if __ARM_ARCH >= 5
-	blx r0          // r0 = tp
-#else
-#if __thumb__
-	add lr,pc,#1
-#else
-	mov lr,pc
-#endif
-	bx r0
-#endif
-#endif
-	ldr r3,[r0,#-4] // r3 = dtv
-	ldr ip,[r3,r1,LSL #2]
-	sub r0,ip,r0
-	add r0,r0,r2    // r0 = r3[r1]-r0+r2
-#if __ARM_ARCH >= 5
-	pop {r2,r3,ip,pc}
-#else
-	pop {r2,r3,ip,lr}
-	bx lr
-#endif
-
-#if ((__ARM_ARCH_6K__ || __ARM_ARCH_6KZ__ || __ARM_ARCH_6ZK__) && !__thumb__) \
- || __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
-#else
-	.align 2
-1:	.word __a_gettp_ptr - 2b
-#endif

@@ -1,3 +0,0 @@
-#define __dlsym __dlsym_redir_time64
-#define dlsym __dlsym_time64
-#include "dlsym.s"

@@ -1,3 +0,0 @@
-#define __dlsym __dlsym_redir_time64
-#define dlsym __dlsym_time64
-#include "dlsym.s"

@@ -1,3 +0,0 @@
-#define __dlsym __dlsym_redir_time64
-#define dlsym __dlsym_time64
-#include "dlsym.s"

@@ -1,3 +0,0 @@
-#define __dlsym __dlsym_redir_time64
-#define dlsym __dlsym_time64
-#include "dlsym.s"

@@ -1,3 +0,0 @@
-#define __dlsym __dlsym_redir_time64
-#define dlsym __dlsym_time64
-#include "dlsym.s"

@@ -1,3 +0,0 @@
-#define __dlsym __dlsym_redir_time64
-#define dlsym __dlsym_time64
-#include "dlsym.s"

@@ -1,3 +0,0 @@
-#define __dlsym __dlsym_redir_time64
-#define dlsym __dlsym_time64
-#include "dlsym.s"

@@ -1,3 +0,0 @@
-#define __dlsym __dlsym_redir_time64
-#define dlsym __dlsym_time64
-#include "dlsym.s"

@@ -1,50 +0,0 @@
-.syntax unified
-.global _longjmp
-.global longjmp
-.type _longjmp,%function
-.type longjmp,%function
-_longjmp:
-longjmp:
-	mov ip,r0
-	movs r0,r1
-	moveq r0,#1
-	ldmia ip!, {v1,v2,v3,v4,v5,v6,sl,fp}
-	ldmia ip!, {r2,lr}
-	mov sp,r2
-
-	adr r1,1f
-	ldr r2,1f
-	ldr r1,[r1,r2]
-
-#if __ARM_ARCH < 8
-	tst r1,#0x260
-	beq 3f
-	// HWCAP_ARM_FPA
-	tst r1,#0x20
-	beq 2f
-	ldc p2, cr4, [ip], #48
-#endif
-2:	tst r1,#0x40
-	beq 2f
-	.fpu vfp
-	vldmia ip!, {d8-d15}
-	.fpu softvfp
-	.eabi_attribute 10, 0
-	.eabi_attribute 27, 0
-#if __ARM_ARCH < 8
-	// HWCAP_ARM_IWMMXT
-2:	tst r1,#0x200
-	beq 3f
-	ldcl p1, cr10, [ip], #8
-	ldcl p1, cr11, [ip], #8
-	ldcl p1, cr12, [ip], #8
-	ldcl p1, cr13, [ip], #8
-	ldcl p1, cr14, [ip], #8
-	ldcl p1, cr15, [ip], #8
-#endif
-2:
-3:	bx lr
-
-.hidden __hwcap
-.align 2
-1:	.word __hwcap-1b

@@ -1,52 +0,0 @@
-.syntax unified
-.global __setjmp
-.global _setjmp
-.global setjmp
-.type __setjmp,%function
-.type _setjmp,%function
-.type setjmp,%function
-__setjmp:
-_setjmp:
-setjmp:
-	mov ip,r0
-	stmia ip!,{v1,v2,v3,v4,v5,v6,sl,fp}
-	mov r2,sp
-	stmia ip!,{r2,lr}
-	mov r0,#0
-
-	adr r1,1f
-	ldr r2,1f
-	ldr r1,[r1,r2]
-
-#if __ARM_ARCH < 8
-	tst r1,#0x260
-	beq 3f
-	// HWCAP_ARM_FPA
-	tst r1,#0x20
-	beq 2f
-	stc p2, cr4, [ip], #48
-#endif
-2:	tst r1,#0x40
-	beq 2f
-	.fpu vfp
-	vstmia ip!, {d8-d15}
-	.fpu softvfp
-	.eabi_attribute 10, 0
-	.eabi_attribute 27, 0
-#if __ARM_ARCH < 8
-	// HWCAP_ARM_IWMMXT
-2:	tst r1,#0x200
-	beq 3f
-	stcl p1, cr10, [ip], #8
-	stcl p1, cr11, [ip], #8
-	stcl p1, cr12, [ip], #8
-	stcl p1, cr13, [ip], #8
-	stcl p1, cr14, [ip], #8
-	stcl p1, cr15, [ip], #8
-#endif
-2:
-3:	bx lr
-
-.hidden __hwcap
-.align 2
-1:	.word __hwcap-1b

@@ -1,34 +0,0 @@
-.set noreorder
-
-.global _longjmp
-.global longjmp
-.type   _longjmp,@function
-.type   longjmp,@function
-_longjmp:
-longjmp:
-	move    $2, $5
-	bne     $2, $0, 1f
-	nop
-	addu    $2, $2, 1
-1:
-#ifndef __mips_soft_float
-	l.d     $f20, 56($4)
-	l.d     $f22, 64($4)
-	l.d     $f24, 72($4)
-	l.d     $f26, 80($4)
-	l.d     $f28, 88($4)
-	l.d     $f30, 96($4)
-#endif
-	lw      $ra,  0($4)
-	lw      $sp,  4($4)
-	lw      $16,  8($4)
-	lw      $17, 12($4)
-	lw      $18, 16($4)
-	lw      $19, 20($4)
-	lw      $20, 24($4)
-	lw      $21, 28($4)
-	lw      $22, 32($4)
-	lw      $23, 36($4)
-	lw      $30, 40($4)
-	jr      $ra
-	lw      $28, 44($4)

@@ -1,33 +0,0 @@
-.set noreorder
-
-.global __setjmp
-.global _setjmp
-.global setjmp
-.type   __setjmp,@function
-.type   _setjmp,@function
-.type   setjmp,@function
-__setjmp:
-_setjmp:
-setjmp:
-	sw      $ra,  0($4)
-	sw      $sp,  4($4)
-	sw      $16,  8($4)
-	sw      $17, 12($4)
-	sw      $18, 16($4)
-	sw      $19, 20($4)
-	sw      $20, 24($4)
-	sw      $21, 28($4)
-	sw      $22, 32($4)
-	sw      $23, 36($4)
-	sw      $30, 40($4)
-	sw      $28, 44($4)
-#ifndef __mips_soft_float
-	s.d     $f20, 56($4)
-	s.d     $f22, 64($4)
-	s.d     $f24, 72($4)
-	s.d     $f26, 80($4)
-	s.d     $f28, 88($4)
-	s.d     $f30, 96($4)
-#endif
-	jr      $ra
-	li      $2, 0

@@ -1,37 +0,0 @@
-.set	noreorder
-.global	_longjmp
-.global	longjmp
-.type	_longjmp,@function
-.type	longjmp,@function
-_longjmp:
-longjmp:
-	move	$2, $5
-
-	bne	$2, $0, 1f
-	nop
-	daddu	$2, $2, 1
-1:
-#ifndef __mips_soft_float
-	ldc1	$24, 96($4)
-	ldc1	$25, 104($4)
-	ldc1	$26, 112($4)
-	ldc1	$27, 120($4)
-	ldc1	$28, 128($4)
-	ldc1	$29, 136($4)
-	ldc1	$30, 144($4)
-	ldc1	$31, 152($4)
-#endif
-	ld	$ra, 0($4)
-	ld	$sp, 8($4)
-	ld	$gp, 16($4)
-	ld	$16, 24($4)
-	ld	$17, 32($4)
-	ld	$18, 40($4)
-	ld	$19, 48($4)
-	ld	$20, 56($4)
-	ld	$21, 64($4)
-	ld	$22, 72($4)
-	ld	$23, 80($4)
-	ld	$30, 88($4)
-	jr	$ra
-	nop

@@ -1,34 +0,0 @@
-.set	noreorder
-.global	__setjmp
-.global	_setjmp
-.global	setjmp
-.type	__setjmp,@function
-.type	_setjmp,@function
-.type	setjmp,@function
-__setjmp:
-_setjmp:
-setjmp:
-	sd	$ra, 0($4)
-	sd	$sp, 8($4)
-	sd	$gp, 16($4)
-	sd	$16, 24($4)
-	sd	$17, 32($4)
-	sd	$18, 40($4)
-	sd	$19, 48($4)
-	sd	$20, 56($4)
-	sd	$21, 64($4)
-	sd	$22, 72($4)
-	sd	$23, 80($4)
-	sd	$30, 88($4)
-#ifndef __mips_soft_float
-	sdc1	$24, 96($4)
-	sdc1	$25, 104($4)
-	sdc1	$26, 112($4)
-	sdc1	$27, 120($4)
-	sdc1	$28, 128($4)
-	sdc1	$29, 136($4)
-	sdc1	$30, 144($4)
-	sdc1	$31, 152($4)
-#endif
-	jr	$ra
-	li	$2, 0

@@ -1,36 +0,0 @@
-.set	noreorder
-.global	_longjmp
-.global	longjmp
-.type	_longjmp,@function
-.type	longjmp,@function
-_longjmp:
-longjmp:
-	move	$2, $5
-	bne	$2, $0, 1f
-	nop
-	addu	$2, $2, 1
-1:
-#ifndef __mips_soft_float
-	ldc1	$24, 96($4)
-	ldc1	$25, 104($4)
-	ldc1	$26, 112($4)
-	ldc1	$27, 120($4)
-	ldc1	$28, 128($4)
-	ldc1	$29, 136($4)
-	ldc1	$30, 144($4)
-	ldc1	$31, 152($4)
-#endif
-	ld	$ra, 0($4)
-	ld	$sp, 8($4)
-	ld	$gp, 16($4)
-	ld	$16, 24($4)
-	ld	$17, 32($4)
-	ld	$18, 40($4)
-	ld	$19, 48($4)
-	ld	$20, 56($4)
-	ld	$21, 64($4)
-	ld	$22, 72($4)
-	ld	$23, 80($4)
-	ld	$30, 88($4)
-	jr	$ra
-	nop

@@ -1,34 +0,0 @@
-.set	noreorder
-.global	__setjmp
-.global	_setjmp
-.global	setjmp
-.type	__setjmp,@function
-.type	_setjmp,@function
-.type	setjmp,@function
-__setjmp:
-_setjmp:
-setjmp:
-	sd	$ra, 0($4)
-	sd	$sp, 8($4)
-	sd	$gp, 16($4)
-	sd	$16, 24($4)
-	sd	$17, 32($4)
-	sd	$18, 40($4)
-	sd	$19, 48($4)
-	sd	$20, 56($4)
-	sd	$21, 64($4)
-	sd	$22, 72($4)
-	sd	$23, 80($4)
-	sd	$30, 88($4)
-#ifndef __mips_soft_float
-	sdc1	$24, 96($4)
-	sdc1	$25, 104($4)
-	sdc1	$26, 112($4)
-	sdc1	$27, 120($4)
-	sdc1	$28, 128($4)
-	sdc1	$29, 136($4)
-	sdc1	$30, 144($4)
-	sdc1	$31, 152($4)
-#endif
-	jr	$ra
-	li	$2, 0

@@ -1,99 +0,0 @@
-	.global _longjmp
-	.global longjmp
-	.type   _longjmp,@function
-	.type   longjmp,@function
-_longjmp:
-longjmp:
-	/*
-	 * void longjmp(jmp_buf env, int val);
-	 * put val into return register and restore the env saved in setjmp
-	 * if val(r4) is 0, put 1 there.
-	 */
-	/* 0) move old return address into r0 */
-	lwz 0, 0(3)
-	/* 1) put it into link reg */
-	mtlr 0
-	/* 2 ) restore stack ptr */
-	lwz 1, 4(3)
-	/* 3) restore control reg */
-	lwz 0, 8(3)
-	mtcr 0
-	/* 4) restore r14-r31 */
-	lwz 14, 12(3)
-	lwz 15, 16(3)
-	lwz 16, 20(3)
-	lwz 17, 24(3)
-	lwz 18, 28(3)
-	lwz 19, 32(3)
-	lwz 20, 36(3)
-	lwz 21, 40(3)
-	lwz 22, 44(3)
-	lwz 23, 48(3)
-	lwz 24, 52(3)
-	lwz 25, 56(3)
-	lwz 26, 60(3)
-	lwz 27, 64(3)
-	lwz 28, 68(3)
-	lwz 29, 72(3)
-	lwz 30, 76(3)
-	lwz 31, 80(3)
-#if defined(_SOFT_FLOAT) || defined(__NO_FPRS__)
-	mflr 0
-	bl 1f
-	.hidden __hwcap
-	.long __hwcap-.
-1:	mflr 4
-	lwz 5, 0(4)
-	lwzx 4, 4, 5
-	andis. 4, 4, 0x80
-	beq 1f
-	.long 0x11c35b01 /* evldd 14,88(3) */
-	.long 0x11e36301 /* ... */
-	.long 0x12036b01
-	.long 0x12237301
-	.long 0x12437b01
-	.long 0x12638301
-	.long 0x12838b01
-	.long 0x12a39301
-	.long 0x12c39b01
-	.long 0x12e3a301
-	.long 0x1303ab01
-	.long 0x1323b301
-	.long 0x1343bb01
-	.long 0x1363c301
-	.long 0x1383cb01
-	.long 0x13a3d301
-	.long 0x13c3db01
-	.long 0x13e3e301 /* evldd 31,224(3) */
-	.long 0x11a3eb01 /* evldd 13,232(3) */
-1:	mtlr 0
-#else
-	lfd 14,88(3)
-	lfd 15,96(3)
-	lfd 16,104(3)
-	lfd 17,112(3)
-	lfd 18,120(3)
-	lfd 19,128(3)
-	lfd 20,136(3)
-	lfd 21,144(3)
-	lfd 22,152(3)
-	lfd 23,160(3)
-	lfd 24,168(3)
-	lfd 25,176(3)
-	lfd 26,184(3)
-	lfd 27,192(3)
-	lfd 28,200(3)
-	lfd 29,208(3)
-	lfd 30,216(3)
-	lfd 31,224(3)
-#endif
-	/* 5) put val into return reg r3 */
-	mr 3, 4
-
-	/* 6) check if return value is 0, make it 1 in that case */
-	cmpwi cr7, 4, 0
-	bne cr7, 1f
-	li 3, 1
-1:
-	blr
-

@@ -1,93 +0,0 @@
-	.global ___setjmp
-	.hidden ___setjmp
-	.global __setjmp
-	.global _setjmp
-	.global setjmp
-	.type   __setjmp,@function
-	.type   _setjmp,@function
-	.type   setjmp,@function
-___setjmp:
-__setjmp:
-_setjmp:
-setjmp:
-	/* 0) store IP int 0, then into the jmpbuf pointed to by r3 (first arg) */
-	mflr 0
-	stw 0, 0(3)
-	/* 1) store reg1 (SP) */
-	stw 1, 4(3)
-	/* 2) store cr */
-	mfcr 0
-	stw 0, 8(3)
-	/* 3) store r14-31 */
-	stw 14, 12(3)
-	stw 15, 16(3)
-	stw 16, 20(3)
-	stw 17, 24(3)
-	stw 18, 28(3)
-	stw 19, 32(3)
-	stw 20, 36(3)
-	stw 21, 40(3)
-	stw 22, 44(3)
-	stw 23, 48(3)
-	stw 24, 52(3)
-	stw 25, 56(3)
-	stw 26, 60(3)
-	stw 27, 64(3)
-	stw 28, 68(3)
-	stw 29, 72(3)
-	stw 30, 76(3)
-	stw 31, 80(3)
-#if defined(_SOFT_FLOAT) || defined(__NO_FPRS__)
-	mflr 0
-	bl 1f
-	.hidden __hwcap
-	.long __hwcap-.
-1:	mflr 4
-	lwz 5, 0(4)
-	lwzx 4, 4, 5
-	andis. 4, 4, 0x80
-	beq 1f
-	.long 0x11c35b21 /* evstdd 14,88(3) */
-	.long 0x11e36321 /* ... */
-	.long 0x12036b21
-	.long 0x12237321
-	.long 0x12437b21
-	.long 0x12638321
-	.long 0x12838b21
-	.long 0x12a39321
-	.long 0x12c39b21
-	.long 0x12e3a321
-	.long 0x1303ab21
-	.long 0x1323b321
-	.long 0x1343bb21
-	.long 0x1363c321
-	.long 0x1383cb21
-	.long 0x13a3d321
-	.long 0x13c3db21
-	.long 0x13e3e321 /* evstdd 31,224(3) */
-	.long 0x11a3eb21 /* evstdd 13,232(3) */
-1:	mtlr 0
-#else
-	stfd 14,88(3)
-	stfd 15,96(3)
-	stfd 16,104(3)
-	stfd 17,112(3)
-	stfd 18,120(3)
-	stfd 19,128(3)
-	stfd 20,136(3)
-	stfd 21,144(3)
-	stfd 22,152(3)
-	stfd 23,160(3)
-	stfd 24,168(3)
-	stfd 25,176(3)
-	stfd 26,184(3)
-	stfd 27,192(3)
-	stfd 28,200(3)
-	stfd 29,208(3)
-	stfd 30,216(3)
-	stfd 31,224(3)
-#endif
-	/* 4) set return value to 0 */
-	li 3, 0
-	/* 5) return */
-	blr

@@ -1,42 +0,0 @@
-.global __longjmp
-.global _longjmp
-.global longjmp
-.type __longjmp, %function
-.type _longjmp,  %function
-.type longjmp,   %function
-__longjmp:
-_longjmp:
-longjmp:
-	ld s0,    0(a0)
-	ld s1,    8(a0)
-	ld s2,    16(a0)
-	ld s3,    24(a0)
-	ld s4,    32(a0)
-	ld s5,    40(a0)
-	ld s6,    48(a0)
-	ld s7,    56(a0)
-	ld s8,    64(a0)
-	ld s9,    72(a0)
-	ld s10,   80(a0)
-	ld s11,   88(a0)
-	ld sp,    96(a0)
-	ld ra,    104(a0)
-
-#ifndef __riscv_float_abi_soft
-	fld fs0,  112(a0)
-	fld fs1,  120(a0)
-	fld fs2,  128(a0)
-	fld fs3,  136(a0)
-	fld fs4,  144(a0)
-	fld fs5,  152(a0)
-	fld fs6,  160(a0)
-	fld fs7,  168(a0)
-	fld fs8,  176(a0)
-	fld fs9,  184(a0)
-	fld fs10, 192(a0)
-	fld fs11, 200(a0)
-#endif
-
-	seqz a0, a1
-	add a0, a0, a1
-	ret

@@ -1,41 +0,0 @@
-.global __setjmp
-.global _setjmp
-.global setjmp
-.type __setjmp, %function
-.type _setjmp,  %function
-.type setjmp,   %function
-__setjmp:
-_setjmp:
-setjmp:
-	sd s0,    0(a0)
-	sd s1,    8(a0)
-	sd s2,    16(a0)
-	sd s3,    24(a0)
-	sd s4,    32(a0)
-	sd s5,    40(a0)
-	sd s6,    48(a0)
-	sd s7,    56(a0)
-	sd s8,    64(a0)
-	sd s9,    72(a0)
-	sd s10,   80(a0)
-	sd s11,   88(a0)
-	sd sp,    96(a0)
-	sd ra,    104(a0)
-
-#ifndef __riscv_float_abi_soft
-	fsd fs0,  112(a0)
-	fsd fs1,  120(a0)
-	fsd fs2,  128(a0)
-	fsd fs3,  136(a0)
-	fsd fs4,  144(a0)
-	fsd fs5,  152(a0)
-	fsd fs6,  160(a0)
-	fsd fs7,  168(a0)
-	fsd fs8,  176(a0)
-	fsd fs9,  184(a0)
-	fsd fs10, 192(a0)
-	fsd fs11, 200(a0)
-#endif
-
-	li a0, 0
-	ret

@@ -1,28 +0,0 @@
-.global _longjmp
-.global longjmp
-.type   _longjmp, @function
-.type   longjmp,  @function
-_longjmp:
-longjmp:
-	mov.l  @r4+, r8
-	mov.l  @r4+, r9
-	mov.l  @r4+, r10
-	mov.l  @r4+, r11
-	mov.l  @r4+, r12
-	mov.l  @r4+, r13
-	mov.l  @r4+, r14
-	mov.l  @r4+, r15
-	lds.l  @r4+, pr
-#if __SH_FPU_ANY__ || __SH4__
-	fmov.s @r4+, fr12
-	fmov.s @r4+, fr13
-	fmov.s @r4+, fr14
-	fmov.s @r4+, fr15
-#endif
-
-	tst  r5, r5
-	movt r0
-	add  r5, r0
-
-	rts
-	 nop

@@ -1,32 +0,0 @@
-.global ___setjmp
-.hidden ___setjmp
-.global __setjmp
-.global _setjmp
-.global setjmp
-.type   __setjmp, @function
-.type   _setjmp,  @function
-.type   setjmp,   @function
-___setjmp:
-__setjmp:
-_setjmp:
-setjmp:
-#if __SH_FPU_ANY__ || __SH4__
-	add   #52, r4
-	fmov.s fr15, @-r4
-	fmov.s fr14, @-r4
-	fmov.s fr13, @-r4
-	fmov.s fr12, @-r4
-#else
-	add   #36, r4
-#endif
-	sts.l  pr,   @-r4
-	mov.l  r15,  @-r4
-	mov.l  r14,  @-r4
-	mov.l  r13,  @-r4
-	mov.l  r12,  @-r4
-	mov.l  r11,  @-r4
-	mov.l  r10,  @-r4
-	mov.l  r9,   @-r4
-	mov.l  r8,   @-r4
-	rts
-	 mov  #0, r0

@@ -1,115 +0,0 @@
-/*
- * memset - fill memory with a constant byte
- *
- * Copyright (c) 2012-2020, Arm Limited.
- * SPDX-License-Identifier: MIT
- */
-
-/* Assumptions:
- *
- * ARMv8-a, AArch64, Advanced SIMD, unaligned accesses.
- *
- */
-
-#define dstin   x0
-#define val     x1
-#define valw    w1
-#define count   x2
-#define dst     x3
-#define dstend  x4
-#define zva_val x5
-
-.global memset
-.type memset,%function
-memset:
-
-	dup     v0.16B, valw
-	add     dstend, dstin, count
-
-	cmp     count, 96
-	b.hi    .Lset_long
-	cmp     count, 16
-	b.hs    .Lset_medium
-	mov     val, v0.D[0]
-
-	/* Set 0..15 bytes.  */
-	tbz     count, 3, 1f
-	str     val, [dstin]
-	str     val, [dstend, -8]
-	ret
-	nop
-1:      tbz     count, 2, 2f
-	str     valw, [dstin]
-	str     valw, [dstend, -4]
-	ret
-2:      cbz     count, 3f
-	strb    valw, [dstin]
-	tbz     count, 1, 3f
-	strh    valw, [dstend, -2]
-3:      ret
-
-	/* Set 17..96 bytes.  */
-.Lset_medium:
-	str     q0, [dstin]
-	tbnz    count, 6, .Lset96
-	str     q0, [dstend, -16]
-	tbz     count, 5, 1f
-	str     q0, [dstin, 16]
-	str     q0, [dstend, -32]
-1:      ret
-
-	.p2align 4
-	/* Set 64..96 bytes.  Write 64 bytes from the start and
-	   32 bytes from the end.  */
-.Lset96:
-	str     q0, [dstin, 16]
-	stp     q0, q0, [dstin, 32]
-	stp     q0, q0, [dstend, -32]
-	ret
-
-	.p2align 4
-.Lset_long:
-	and     valw, valw, 255
-	bic     dst, dstin, 15
-	str     q0, [dstin]
-	cmp     count, 160
-	ccmp    valw, 0, 0, hs
-	b.ne    .Lno_zva
-
-#ifndef SKIP_ZVA_CHECK
-	mrs     zva_val, dczid_el0
-	and     zva_val, zva_val, 31
-	cmp     zva_val, 4              /* ZVA size is 64 bytes.  */
-	b.ne    .Lno_zva
-#endif
-	str     q0, [dst, 16]
-	stp     q0, q0, [dst, 32]
-	bic     dst, dst, 63
-	sub     count, dstend, dst      /* Count is now 64 too large.  */
-	sub     count, count, 128       /* Adjust count and bias for loop.  */
-
-	.p2align 4
-.Lzva_loop:
-	add     dst, dst, 64
-	dc      zva, dst
-	subs    count, count, 64
-	b.hi    .Lzva_loop
-	stp     q0, q0, [dstend, -64]
-	stp     q0, q0, [dstend, -32]
-	ret
-
-.Lno_zva:
-	sub     count, dstend, dst      /* Count is 16 too large.  */
-	sub     dst, dst, 16            /* Dst is biased by -32.  */
-	sub     count, count, 64 + 16   /* Adjust count and bias for loop.  */
-.Lno_zva_loop:
-	stp     q0, q0, [dst, 32]
-	stp     q0, q0, [dst, 64]!
-	subs    count, count, 64
-	b.hi    .Lno_zva_loop
-	stp     q0, q0, [dstend, -64]
-	stp     q0, q0, [dstend, -32]
-	ret
-
-.size memset,.-memset
-