Commit af78c55676

@@ -34,6 +34,7 @@ test isSignalNan {
         //       See https://github.com/ziglang/zig/issues/14366
         if (!builtin.cpu.arch.isArm() and
             !builtin.cpu.arch.isAARCH64() and
+            builtin.cpu.arch != .hexagon and
             !builtin.cpu.arch.isMIPS32() and
             !builtin.cpu.arch.isPowerPC() and
             builtin.zig_backend != .stage2_c)

@@ -135,6 +135,7 @@ test log10_int {
     if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_llvm and comptime builtin.target.cpu.arch.isWasm()) return error.SkipZigTest; // TODO
+    if (builtin.zig_backend == .stage2_llvm and comptime builtin.target.cpu.arch == .hexagon) return error.SkipZigTest;
 
     inline for (
         .{ u8, u16, u32, u64, u128, u256, u512 },

@@ -636,6 +636,7 @@ test shl {
 
     try testing.expect(shl(i8, -1, -100) == -1);
     try testing.expect(shl(i8, -1, 100) == 0);
+    if (builtin.cpu.arch == .hexagon and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
     try testing.expect(@reduce(.And, shl(@Vector(2, i8), .{ -1, 1 }, -100) == @Vector(2, i8){ -1, 0 }));
     try testing.expect(@reduce(.And, shl(@Vector(2, i8), .{ -1, 1 }, 100) == @Vector(2, i8){ 0, 0 }));
 }
@@ -684,6 +685,7 @@ test shr {
 
     try testing.expect(shr(i8, -1, -100) == 0);
     try testing.expect(shr(i8, -1, 100) == -1);
+    if (builtin.cpu.arch == .hexagon and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
     try testing.expect(@reduce(.And, shr(@Vector(2, i8), .{ -1, 1 }, -100) == @Vector(2, i8){ 0, 0 }));
     try testing.expect(@reduce(.And, shr(@Vector(2, i8), .{ -1, 1 }, 100) == @Vector(2, i8){ -1, 0 }));
 }