Commit aac800ec65
Changed files (13)
lib
compiler
aro_translate_c
src
arch
x86_64
link
doc/langref.html.in
@@ -3679,22 +3679,22 @@ void do_a_thing(struct Foo *foo) {
<tr>
<th scope="row">{#syntax#}.{x}{#endsyntax#}</th>
<td>{#syntax#}T{#endsyntax#}</td>
- <td>{#syntax#}x{#endsyntax#} is a {#syntax#}std.meta.FieldType(T, .@"0"){#endsyntax#}</td>
+ <td>{#syntax#}x{#endsyntax#} is a {#syntax#}@FieldType(T, "0"){#endsyntax#}</td>
</tr>
<tr>
<th scope="row">{#syntax#}.{ .a = x }{#endsyntax#}</th>
<td>{#syntax#}T{#endsyntax#}</td>
- <td>{#syntax#}x{#endsyntax#} is a {#syntax#}std.meta.FieldType(T, .a){#endsyntax#}</td>
+ <td>{#syntax#}x{#endsyntax#} is a {#syntax#}@FieldType(T, "a"){#endsyntax#}</td>
</tr>
<tr>
<th scope="row">{#syntax#}T{x}{#endsyntax#}</th>
<td>-</td>
- <td>{#syntax#}x{#endsyntax#} is a {#syntax#}std.meta.FieldType(T, .@"0"){#endsyntax#}</td>
+ <td>{#syntax#}x{#endsyntax#} is a {#syntax#}@FieldType(T, "0"){#endsyntax#}</td>
</tr>
<tr>
<th scope="row">{#syntax#}T{ .a = x }{#endsyntax#}</th>
<td>-</td>
- <td>{#syntax#}x{#endsyntax#} is a {#syntax#}std.meta.FieldType(T, .a){#endsyntax#}</td>
+ <td>{#syntax#}x{#endsyntax#} is a {#syntax#}@FieldType(T, "a"){#endsyntax#}</td>
</tr>
<tr>
<th scope="row">{#syntax#}@Type(x){#endsyntax#}</th>
lib/compiler/aro_translate_c/ast.zig
@@ -394,7 +394,7 @@ pub const Node = extern union {
}
pub fn Data(comptime t: Tag) type {
- return std.meta.fieldInfo(t.Type(), .data).type;
+ return @FieldType(t.Type(), "data");
}
};
lib/std/zig/llvm/Builder.zig
@@ -7526,9 +7526,9 @@ pub const Constant = enum(u32) {
};
}
};
- const Mantissa64 = std.meta.FieldType(Float.Repr(f64), .mantissa);
- const Exponent32 = std.meta.FieldType(Float.Repr(f32), .exponent);
- const Exponent64 = std.meta.FieldType(Float.Repr(f64), .exponent);
+ const Mantissa64 = @FieldType(Float.Repr(f64), "mantissa");
+ const Exponent32 = @FieldType(Float.Repr(f32), "exponent");
+ const Exponent64 = @FieldType(Float.Repr(f64), "exponent");
const repr: Float.Repr(f32) = @bitCast(item.data);
const denormal_shift = switch (repr.exponent) {
lib/std/array_hash_map.zig
@@ -2486,13 +2486,13 @@ test "reIndex" {
test "auto store_hash" {
const HasCheapEql = AutoArrayHashMap(i32, i32);
const HasExpensiveEql = AutoArrayHashMap([32]i32, i32);
- try testing.expect(std.meta.fieldInfo(HasCheapEql.Data, .hash).type == void);
- try testing.expect(std.meta.fieldInfo(HasExpensiveEql.Data, .hash).type != void);
+ try testing.expect(@FieldType(HasCheapEql.Data, "hash") == void);
+ try testing.expect(@FieldType(HasExpensiveEql.Data, "hash") != void);
const HasCheapEqlUn = AutoArrayHashMapUnmanaged(i32, i32);
const HasExpensiveEqlUn = AutoArrayHashMapUnmanaged([32]i32, i32);
- try testing.expect(std.meta.fieldInfo(HasCheapEqlUn.Data, .hash).type == void);
- try testing.expect(std.meta.fieldInfo(HasExpensiveEqlUn.Data, .hash).type != void);
+ try testing.expect(@FieldType(HasCheapEqlUn.Data, "hash") == void);
+ try testing.expect(@FieldType(HasExpensiveEqlUn.Data, "hash") != void);
}
test "sort" {
lib/std/multi_array_list.zig
@@ -565,7 +565,7 @@ pub fn MultiArrayList(comptime T: type) type {
}
fn FieldType(comptime field: Field) type {
- return meta.fieldInfo(Elem, field).type;
+ return @FieldType(Elem, @tagName(field));
}
const Entry = entry: {
src/arch/x86_64/Encoding.zig
@@ -1030,8 +1030,8 @@ const mnemonic_to_encodings_map = init: {
storage_i += value.len;
}
var mnemonic_i: [mnemonic_count]usize = @splat(0);
- const ops_len = @typeInfo(std.meta.FieldType(Data, .ops)).array.len;
- const opc_len = @typeInfo(std.meta.FieldType(Data, .opc)).array.len;
+ const ops_len = @typeInfo(@FieldType(Data, "ops")).array.len;
+ const opc_len = @typeInfo(@FieldType(Data, "opc")).array.len;
for (encodings) |entry| {
const i = &mnemonic_i[@intFromEnum(entry[0])];
mnemonic_map[@intFromEnum(entry[0])][i.*] = .{
src/link/Elf/Atom.zig
@@ -1783,9 +1783,9 @@ const aarch64 = struct {
aarch64_util.writeAddImmInst(off, code);
} else {
const old_inst: Instruction = .{
- .add_subtract_immediate = mem.bytesToValue(std.meta.TagPayload(
+ .add_subtract_immediate = mem.bytesToValue(@FieldType(
Instruction,
- Instruction.add_subtract_immediate,
+ @tagName(Instruction.add_subtract_immediate),
), code),
};
const rd: Register = @enumFromInt(old_inst.add_subtract_immediate.rd);
@@ -1797,9 +1797,9 @@ const aarch64 = struct {
.TLSDESC_CALL => if (!target.flags.has_tlsdesc) {
const old_inst: Instruction = .{
- .unconditional_branch_register = mem.bytesToValue(std.meta.TagPayload(
+ .unconditional_branch_register = mem.bytesToValue(@FieldType(
Instruction,
- Instruction.unconditional_branch_register,
+ @tagName(Instruction.unconditional_branch_register),
), code),
};
const rn: Register = @enumFromInt(old_inst.unconditional_branch_register.rn);
src/link/MachO/Atom.zig
@@ -794,9 +794,9 @@ fn resolveRelocInner(
aarch64.writeAddImmInst(@truncate(target), inst_code);
} else {
var inst = aarch64.Instruction{
- .load_store_register = mem.bytesToValue(std.meta.TagPayload(
+ .load_store_register = mem.bytesToValue(@FieldType(
aarch64.Instruction,
- aarch64.Instruction.load_store_register,
+ @tagName(aarch64.Instruction.load_store_register),
), inst_code),
};
inst.load_store_register.offset = switch (inst.load_store_register.size) {
@@ -843,9 +843,9 @@ fn resolveRelocInner(
const inst_code = code[rel_offset..][0..4];
const reg_info: RegInfo = blk: {
if (aarch64.isArithmeticOp(inst_code)) {
- const inst = mem.bytesToValue(std.meta.TagPayload(
+ const inst = mem.bytesToValue(@FieldType(
aarch64.Instruction,
- aarch64.Instruction.add_subtract_immediate,
+ @tagName(aarch64.Instruction.add_subtract_immediate),
), inst_code);
break :blk .{
.rd = inst.rd,
@@ -853,9 +853,9 @@ fn resolveRelocInner(
.size = inst.sf,
};
} else {
- const inst = mem.bytesToValue(std.meta.TagPayload(
+ const inst = mem.bytesToValue(@FieldType(
aarch64.Instruction,
- aarch64.Instruction.load_store_register,
+ @tagName(aarch64.Instruction.load_store_register),
), inst_code);
break :blk .{
.rd = inst.rt,
src/link/aarch64.zig
@@ -5,9 +5,9 @@ pub inline fn isArithmeticOp(inst: *const [4]u8) bool {
pub fn writeAddImmInst(value: u12, code: *[4]u8) void {
var inst = Instruction{
- .add_subtract_immediate = mem.bytesToValue(std.meta.TagPayload(
+ .add_subtract_immediate = mem.bytesToValue(@FieldType(
Instruction,
- Instruction.add_subtract_immediate,
+ @tagName(Instruction.add_subtract_immediate),
), code),
};
inst.add_subtract_immediate.imm12 = value;
@@ -16,9 +16,9 @@ pub fn writeAddImmInst(value: u12, code: *[4]u8) void {
pub fn writeLoadStoreRegInst(value: u12, code: *[4]u8) void {
var inst: Instruction = .{
- .load_store_register = mem.bytesToValue(std.meta.TagPayload(
+ .load_store_register = mem.bytesToValue(@FieldType(
Instruction,
- Instruction.load_store_register,
+ @tagName(Instruction.load_store_register),
), code),
};
inst.load_store_register.offset = value;
@@ -34,9 +34,9 @@ pub fn calcNumberOfPages(saddr: i64, taddr: i64) error{Overflow}!i21 {
pub fn writeAdrpInst(pages: u21, code: *[4]u8) void {
var inst = Instruction{
- .pc_relative_address = mem.bytesToValue(std.meta.TagPayload(
+ .pc_relative_address = mem.bytesToValue(@FieldType(
Instruction,
- Instruction.pc_relative_address,
+ @tagName(Instruction.pc_relative_address),
), code),
};
inst.pc_relative_address.immhi = @as(u19, @truncate(pages >> 2));
@@ -46,9 +46,9 @@ pub fn writeAdrpInst(pages: u21, code: *[4]u8) void {
pub fn writeBranchImm(disp: i28, code: *[4]u8) void {
var inst = Instruction{
- .unconditional_branch_immediate = mem.bytesToValue(std.meta.TagPayload(
+ .unconditional_branch_immediate = mem.bytesToValue(@FieldType(
Instruction,
- Instruction.unconditional_branch_immediate,
+ @tagName(Instruction.unconditional_branch_immediate),
), code),
};
inst.unconditional_branch_immediate.imm26 = @as(u26, @truncate(@as(u28, @bitCast(disp >> 2))));
src/link/Coff.zig
@@ -3497,9 +3497,9 @@ pub const Relocation = struct {
const target_page = @as(i32, @intCast(ctx.target_vaddr >> 12));
const pages = @as(u21, @bitCast(@as(i21, @intCast(target_page - source_page))));
var inst = aarch64_util.Instruction{
- .pc_relative_address = mem.bytesToValue(std.meta.TagPayload(
+ .pc_relative_address = mem.bytesToValue(@FieldType(
aarch64_util.Instruction,
- aarch64_util.Instruction.pc_relative_address,
+ @tagName(aarch64_util.Instruction.pc_relative_address),
), buffer[0..4]),
};
inst.pc_relative_address.immhi = @as(u19, @truncate(pages >> 2));
@@ -3512,18 +3512,18 @@ pub const Relocation = struct {
const narrowed = @as(u12, @truncate(@as(u64, @intCast(ctx.target_vaddr))));
if (isArithmeticOp(buffer[0..4])) {
var inst = aarch64_util.Instruction{
- .add_subtract_immediate = mem.bytesToValue(std.meta.TagPayload(
+ .add_subtract_immediate = mem.bytesToValue(@FieldType(
aarch64_util.Instruction,
- aarch64_util.Instruction.add_subtract_immediate,
+ @tagName(aarch64_util.Instruction.add_subtract_immediate),
), buffer[0..4]),
};
inst.add_subtract_immediate.imm12 = narrowed;
mem.writeInt(u32, buffer[0..4], inst.toU32(), .little);
} else {
var inst = aarch64_util.Instruction{
- .load_store_register = mem.bytesToValue(std.meta.TagPayload(
+ .load_store_register = mem.bytesToValue(@FieldType(
aarch64_util.Instruction,
- aarch64_util.Instruction.load_store_register,
+ @tagName(aarch64_util.Instruction.load_store_register),
), buffer[0..4]),
};
const offset: u12 = blk: {
src/link/riscv.zig
@@ -50,27 +50,27 @@ pub fn writeAddend(
}
pub fn writeInstU(code: *[4]u8, value: u32) void {
- var data: Instruction = .{ .U = mem.bytesToValue(std.meta.TagPayload(Instruction, .U), code) };
+ var data: Instruction = .{ .U = mem.bytesToValue(@FieldType(Instruction, "U"), code) };
const compensated: u32 = @bitCast(@as(i32, @bitCast(value)) + 0x800);
data.U.imm12_31 = bitSlice(compensated, 31, 12);
mem.writeInt(u32, code, data.toU32(), .little);
}
pub fn writeInstI(code: *[4]u8, value: u32) void {
- var data: Instruction = .{ .I = mem.bytesToValue(std.meta.TagPayload(Instruction, .I), code) };
+ var data: Instruction = .{ .I = mem.bytesToValue(@FieldType(Instruction, "I"), code) };
data.I.imm0_11 = bitSlice(value, 11, 0);
mem.writeInt(u32, code, data.toU32(), .little);
}
pub fn writeInstS(code: *[4]u8, value: u32) void {
- var data: Instruction = .{ .S = mem.bytesToValue(std.meta.TagPayload(Instruction, .S), code) };
+ var data: Instruction = .{ .S = mem.bytesToValue(@FieldType(Instruction, "S"), code) };
data.S.imm0_4 = bitSlice(value, 4, 0);
data.S.imm5_11 = bitSlice(value, 11, 5);
mem.writeInt(u32, code, data.toU32(), .little);
}
pub fn writeInstJ(code: *[4]u8, value: u32) void {
- var data: Instruction = .{ .J = mem.bytesToValue(std.meta.TagPayload(Instruction, .J), code) };
+ var data: Instruction = .{ .J = mem.bytesToValue(@FieldType(Instruction, "J"), code) };
data.J.imm1_10 = bitSlice(value, 10, 1);
data.J.imm11 = bitSlice(value, 11, 11);
data.J.imm12_19 = bitSlice(value, 19, 12);
@@ -79,7 +79,7 @@ pub fn writeInstJ(code: *[4]u8, value: u32) void {
}
pub fn writeInstB(code: *[4]u8, value: u32) void {
- var data: Instruction = .{ .B = mem.bytesToValue(std.meta.TagPayload(Instruction, .B), code) };
+ var data: Instruction = .{ .B = mem.bytesToValue(@FieldType(Instruction, "B"), code) };
data.B.imm1_4 = bitSlice(value, 4, 1);
data.B.imm5_10 = bitSlice(value, 10, 5);
data.B.imm11 = bitSlice(value, 11, 11);
src/Compilation.zig
@@ -1512,7 +1512,7 @@ pub fn create(gpa: Allocator, arena: Allocator, options: CreateOptions) !*Compil
.emit_asm = options.emit_asm,
.emit_llvm_ir = options.emit_llvm_ir,
.emit_llvm_bc = options.emit_llvm_bc,
- .work_queues = .{std.fifo.LinearFifo(Job, .Dynamic).init(gpa)} ** @typeInfo(std.meta.FieldType(Compilation, .work_queues)).array.len,
+ .work_queues = @splat(.init(gpa)),
.c_object_work_queue = std.fifo.LinearFifo(*CObject, .Dynamic).init(gpa),
.win32_resource_work_queue = if (dev.env.supports(.win32_resource)) std.fifo.LinearFifo(*Win32Resource, .Dynamic).init(gpa) else .{},
.astgen_work_queue = std.fifo.LinearFifo(Zcu.File.Index, .Dynamic).init(gpa),
src/Sema.zig
@@ -13519,7 +13519,7 @@ fn validateErrSetSwitch(
seen_errors: *SwitchErrorSet,
case_vals: *std.ArrayListUnmanaged(Air.Inst.Ref),
operand_ty: Type,
- inst_data: std.meta.FieldType(Zir.Inst.Data, .pl_node),
+ inst_data: @FieldType(Zir.Inst.Data, "pl_node"),
scalar_cases_len: u32,
multi_cases_len: u32,
else_case: struct { body: []const Zir.Inst.Index, end: usize, src: LazySrcLoc },