Commit 9fc9235ac8

Jacob Young <jacobly0@users.noreply.github.com>
2023-10-08 07:28:17
x86_64: fix undersized vector binary operations
master
1 parent f6e027d
Changed files (2)
src
arch
x86_64
CodeGen.zig
test
behavior
maximum_minimum.zig
src/arch/x86_64/CodeGen.zig
@@ -7733,7 +7733,10 @@ fn genBinOp(
             mir_tag,
             dst_reg,
             lhs_reg,
-            src_mcv.mem(Memory.PtrSize.fromSize(abi_size)),
+            src_mcv.mem(switch (lhs_ty.zigTypeTag(mod)) {
+                else => Memory.PtrSize.fromSize(abi_size),
+                .Vector => Memory.PtrSize.fromBitSize(dst_reg.bitSize()),
+            }),
         ) else try self.asmRegisterRegisterRegister(
             mir_tag,
             dst_reg,
@@ -7748,7 +7751,10 @@ fn genBinOp(
         if (src_mcv.isMemory()) try self.asmRegisterMemory(
             mir_tag,
             dst_reg,
-            src_mcv.mem(Memory.PtrSize.fromSize(abi_size)),
+            src_mcv.mem(switch (lhs_ty.zigTypeTag(mod)) {
+                else => Memory.PtrSize.fromSize(abi_size),
+                .Vector => Memory.PtrSize.fromBitSize(dst_reg.bitSize()),
+            }),
         ) else try self.asmRegisterRegister(
             mir_tag,
             dst_reg,
test/behavior/maximum_minimum.zig
@@ -276,7 +276,8 @@ test "@min/@max notices bounds from vector types when element of comptime-known
     if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
-    if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
+    if (builtin.zig_backend == .stage2_x86_64 and
+        !comptime std.Target.x86.featureSetHas(builtin.cpu.features, .sse4_1)) return error.SkipZigTest;
 
     var x: @Vector(2, u32) = .{ 1_000_000, 12345 };
     const y: @Vector(2, u16) = .{ 10, undefined };