Commit 9d23e711ef

@@ -378,21 +378,33 @@ pub inline fn spinLoopHint() void {
         // No-op instruction that can hint to save (or share with a hardware-thread)
         // pipelining/power resources
         // https://software.intel.com/content/www/us/en/develop/articles/benefitting-power-and-performance-sleep-loops.html
-        .x86, .x86_64 => asm volatile ("pause" ::: "memory"),
+        .x86,
+        .x86_64,
+        => asm volatile ("pause" ::: "memory"),
 
         // No-op instruction that serves as a hardware-thread resource yield hint.
         // https://stackoverflow.com/a/7588941
-        .powerpc64, .powerpc64le => asm volatile ("or 27, 27, 27" ::: "memory"),
+        .powerpc,
+        .powerpcle,
+        .powerpc64,
+        .powerpc64le,
+        => asm volatile ("or 27, 27, 27" ::: "memory"),
 
         // `isb` appears more reliable for releasing execution resources than `yield`
         // on common aarch64 CPUs.
         // https://bugs.java.com/bugdatabase/view_bug.do?bug_id=8258604
         // https://bugs.mysql.com/bug.php?id=100664
-        .aarch64, .aarch64_be => asm volatile ("isb" ::: "memory"),
+        .aarch64,
+        .aarch64_be,
+        => asm volatile ("isb" ::: "memory"),
 
         // `yield` was introduced in v6k but is also available on v6m.
         // https://www.keil.com/support/man/docs/armasm/armasm_dom1361289926796.htm
-        .arm, .armeb, .thumb, .thumbeb => {
+        .arm,
+        .armeb,
+        .thumb,
+        .thumbeb,
+        => {
             const can_yield = comptime std.Target.arm.featureSetHasAny(builtin.target.cpu.features, .{
                 .has_v6k, .has_v6m,
             });
@@ -402,6 +414,22 @@ pub inline fn spinLoopHint() void {
                 asm volatile ("" ::: "memory");
             }
         },
+
+        // The 8-bit immediate specifies the amount of cycles to pause for. We can't really be too
+        // opinionated here.
+        .hexagon,
+        => asm volatile ("pause(#1)" ::: "memory"),
+
+        .riscv32,
+        .riscv64,
+        => {
+            if (comptime std.Target.riscv.featureSetHas(builtin.target.cpu.features, .zihintpause)) {
+                asm volatile ("pause" ::: "memory");
+            } else {
+                asm volatile ("" ::: "memory");
+            }
+        },
+
         // Memory barrier to prevent the compiler from optimizing away the spin-loop
         // even if no hint_instruction was provided.
         else => asm volatile ("" ::: "memory"),