Commit `9542ee9bf8`

Jakub Konka <kubkon@jakubkonka.com>

2024-02-17 11:43:18

elf: create Zig specific reloc type shared across ISAs

master

1 parent ace1a69

Changed files (4)

src

arch

x86_64

Emit.zig

link

Elf

Atom.zig

relocation.zig

Elf.zig

@@ -120,7 +120,7 @@ pub fn emitMir(emit: *Emit) Error!void {
                     }
                     if (emit.lower.pic) {
                         const r_type: u32 = if (sym.flags.needs_zig_got and !is_obj_or_static_lib)
-                            link.File.Elf.R_X86_64_ZIG_GOTPCREL
+                            link.File.Elf.R_ZIG_GOTPCREL
                         else if (sym.flags.needs_got)
                             @intFromEnum(std.elf.R_X86_64.R_X86_64_GOTPCREL)
                         else
@@ -140,7 +140,7 @@ pub fn emitMir(emit: *Emit) Error!void {
                             });
                         } else {
                             const r_type: u32 = if (sym.flags.needs_zig_got and !is_obj_or_static_lib)
-                                link.File.Elf.R_X86_64_ZIG_GOT32
+                                link.File.Elf.R_ZIG_GOT32
                             else if (sym.flags.needs_got)
                                 @intFromEnum(std.elf.R_X86_64.R_X86_64_GOT32)
                             else if (sym.flags.is_tls)

@@ -968,8 +968,8 @@ const x86_64 = struct {
 
                 else => |x| switch (@intFromEnum(x)) {
                     // Zig custom relocations
-                    Elf.R_X86_64_ZIG_GOT32,
-                    Elf.R_X86_64_ZIG_GOTPCREL,
+                    Elf.R_ZIG_GOT32,
+                    Elf.R_ZIG_GOTPCREL,
                     => {
                         assert(symbol.flags.has_zig_got);
                     },
@@ -1153,8 +1153,8 @@ const x86_64 = struct {
 
                 else => |x| switch (@intFromEnum(x)) {
                     // Zig custom relocations
-                    Elf.R_X86_64_ZIG_GOT32 => try cwriter.writeInt(u32, @as(u32, @intCast(ZIG_GOT + A)), .little),
-                    Elf.R_X86_64_ZIG_GOTPCREL => try cwriter.writeInt(i32, @as(i32, @intCast(ZIG_GOT + A - P)), .little),
+                    Elf.R_ZIG_GOT32 => try cwriter.writeInt(u32, @as(u32, @intCast(ZIG_GOT + A)), .little),
+                    Elf.R_ZIG_GOTPCREL => try cwriter.writeInt(i32, @as(i32, @intCast(ZIG_GOT + A - P)), .little),
 
                     else => {},
                 },

@@ -55,7 +55,7 @@ const aarch64_relocs = Table(10, elf.R_AARCH64, .{
     .{ .tlsdesc, .R_AARCH64_TLSDESC },
 });
 
-const riscv64_relocs = Table(8, elf.R_RISCV, .{
+const riscv64_relocs = Table(9, elf.R_RISCV, .{
     .{ .abs, .R_RISCV_64 },
     .{ .copy, .R_RISCV_COPY },
     .{ .rel, .R_RISCV_RELATIVE },

@@ -6065,8 +6065,9 @@ const RelaSection = struct {
 };
 const RelaSectionTable = std.AutoArrayHashMapUnmanaged(u32, RelaSection);
 
-pub const R_X86_64_ZIG_GOT32: u32 = 0xff00;
-pub const R_X86_64_ZIG_GOTPCREL: u32 = 0xff01;
+// TODO: add comptime check we don't clobber any reloc for any ISA
+pub const R_ZIG_GOT32: u32 = 0xff00;
+pub const R_ZIG_GOTPCREL: u32 = 0xff01;
 
 fn defaultEntrySymbolName(cpu_arch: std.Target.Cpu.Arch) []const u8 {
     return switch (cpu_arch) {

Commit 9542ee9bf8

Commit `9542ee9bf8`