Commit 927706e6d0
Changed files (1)
src
arch
sparcv9
src/arch/sparcv9/Emit.zig
@@ -7,6 +7,7 @@ const Module = @import("../../Module.zig");
const ErrorMsg = Module.ErrorMsg;
const Liveness = @import("../../Liveness.zig");
const DebugInfoOutput = @import("../../codegen.zig").DebugInfoOutput;
+const DW = std.dwarf;
const Emit = @This();
const Mir = @import("Mir.zig");
@@ -33,11 +34,60 @@ const InnerError = error{
pub fn emitMir(
emit: *Emit,
) InnerError!void {
- _ = emit;
+ const mir_tags = emit.mir.instructions.items(.tag);
- @panic("TODO implement emitMir");
+ // Emit machine code
+ for (mir_tags) |tag, index| {
+ const inst = @intCast(u32, index);
+ switch (tag) {
+ .dbg_line => try emit.mirDbgLine(inst),
+
+ .dbg_prologue_end => try emit.mirDebugPrologueEnd(),
+ .dbg_epilogue_begin => try emit.mirDebugEpilogueBegin(),
+ }
+ }
}
pub fn deinit(emit: *Emit) void {
emit.* = undefined;
}
+
+fn dbgAdvancePCAndLine(self: *Emit, line: u32, column: u32) !void {
+ _ = self;
+ _ = line;
+ _ = column;
+
+ @panic("TODO implement dbgAdvancePCAndLine");
+}
+
+fn mirDbgLine(emit: *Emit, inst: Mir.Inst.Index) !void {
+ const tag = emit.mir.instructions.items(.tag)[inst];
+ const dbg_line_column = emit.mir.instructions.items(.data)[inst].dbg_line_column;
+
+ switch (tag) {
+ .dbg_line => try emit.dbgAdvancePCAndLine(dbg_line_column.line, dbg_line_column.column),
+ else => unreachable,
+ }
+}
+
+fn mirDebugPrologueEnd(self: *Emit) !void {
+ switch (self.debug_output) {
+ .dwarf => |dbg_out| {
+ try dbg_out.dbg_line.append(DW.LNS.set_prologue_end);
+ try self.dbgAdvancePCAndLine(self.prev_di_line, self.prev_di_column);
+ },
+ .plan9 => {},
+ .none => {},
+ }
+}
+
+fn mirDebugEpilogueBegin(self: *Emit) !void {
+ switch (self.debug_output) {
+ .dwarf => |dbg_out| {
+ try dbg_out.dbg_line.append(DW.LNS.set_epilogue_begin);
+ try self.dbgAdvancePCAndLine(self.prev_di_line, self.prev_di_column);
+ },
+ .plan9 => {},
+ .none => {},
+ }
+}