Commit 88b49ed00d

Ivan Velickovic <i.velickovic@unsw.edu.au>
2022-12-15 09:16:32
std.leb128: Re-enable test for riscv64
These were previously disabled due to a LLVM 14 regression, see https://github.com/ziglang/zig/issues/12031 for more details. This has been fixed in LLVM 15.
master
1 parent 077b003
Changed files (1)
lib
std
leb128.zig
lib/std/leb128.zig
@@ -347,11 +347,6 @@ fn test_write_leb128(value: anytype) !void {
 }
 
 test "serialize unsigned LEB128" {
-    if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .riscv64) {
-        // https://github.com/ziglang/zig/issues/12031
-        return error.SkipZigTest;
-    }
-
     const max_bits = 18;
 
     comptime var t = 0;
@@ -366,11 +361,6 @@ test "serialize unsigned LEB128" {
 }
 
 test "serialize signed LEB128" {
-    if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .riscv64) {
-        // https://github.com/ziglang/zig/issues/12031
-        return error.SkipZigTest;
-    }
-
     // explicitly test i0 because starting `t` at 0
     // will break the while loop
     try test_write_leb128(@as(i0, 0));