Commit 86077fe6bd

@@ -21,11 +21,11 @@ const Air = @import("../Air.zig");
 const Value = @import("../Value.zig");
 const Type = @import("../Type.zig");
 const codegen = @import("../codegen.zig");
-const x86_64_abi = @import("../arch/x86_64/abi.zig");
+const x86_64_abi = @import("x86_64/abi.zig");
 const wasm_c_abi = @import("wasm/abi.zig");
 const aarch64_c_abi = @import("aarch64/abi.zig");
 const arm_c_abi = @import("arm/abi.zig");
-const riscv_c_abi = @import("../arch/riscv64/abi.zig");
+const riscv_c_abi = @import("riscv64/abi.zig");
 const mips_c_abi = @import("mips/abi.zig");
 const dev = @import("../dev.zig");
 

@@ -1473,9 +1473,9 @@ const x86_64 = struct {
         for (insts) |inst| try inst.encode(&writer, .{});
     }
 
-    const bits = @import("../../arch/x86_64/bits.zig");
-    const encoder = @import("../../arch/x86_64/encoder.zig");
-    const Disassembler = @import("../../arch/x86_64/Disassembler.zig");
+    const bits = @import("../../codegen/x86_64/bits.zig");
+    const encoder = @import("../../codegen/x86_64/encoder.zig");
+    const Disassembler = @import("../../codegen/x86_64/Disassembler.zig");
     const Immediate = Instruction.Immediate;
     const Instruction = encoder.Instruction;
 };

@@ -901,9 +901,9 @@ const x86_64 = struct {
         for (insts) |inst| try inst.encode(&stream, .{});
     }
 
-    const bits = @import("../../arch/x86_64/bits.zig");
-    const encoder = @import("../../arch/x86_64/encoder.zig");
-    const Disassembler = @import("../../arch/x86_64/Disassembler.zig");
+    const bits = @import("../../codegen/x86_64/bits.zig");
+    const encoder = @import("../../codegen/x86_64/encoder.zig");
+    const Disassembler = @import("../../codegen/x86_64/Disassembler.zig");
     const Immediate = bits.Immediate;
     const Instruction = encoder.Instruction;
 };

@@ -9,7 +9,7 @@ const Alignment = Wasm.Alignment;
 const String = Wasm.String;
 const Relocation = Wasm.Relocation;
 const InternPool = @import("../../InternPool.zig");
-const Mir = @import("../../arch/wasm/Mir.zig");
+const Mir = @import("../../codegen/wasm/Mir.zig");
 
 const build_options = @import("build_options");
 

@@ -102,7 +102,7 @@ const DebugFrame = struct {
         } + switch (target.cpu.arch) {
             .x86_64 => len: {
                 dev.check(.x86_64_backend);
-                const Register = @import("../arch/x86_64/bits.zig").Register;
+                const Register = @import("../codegen/x86_64/bits.zig").Register;
                 break :len uleb128Bytes(1) + sleb128Bytes(-8) + uleb128Bytes(Register.rip.dwarfNum()) +
                     1 + uleb128Bytes(Register.rsp.dwarfNum()) + sleb128Bytes(-1) +
                     1 + uleb128Bytes(1);
@@ -2349,7 +2349,7 @@ pub fn init(lf: *link.File, format: DW.Format) Dwarf {
         .debug_aranges = .{ .section = Section.init },
         .debug_frame = .{
             .header = if (target.cpu.arch == .x86_64 and target.ofmt == .elf) header: {
-                const Register = @import("../arch/x86_64/bits.zig").Register;
+                const Register = @import("../codegen/x86_64/bits.zig").Register;
                 break :header comptime .{
                     .format = .eh_frame,
                     .code_alignment_factor = 1,
@@ -4833,7 +4833,7 @@ fn flushWriterError(dwarf: *Dwarf, pt: Zcu.PerThread) (FlushError || Writer.Erro
             .eh_frame => switch (target.cpu.arch) {
                 .x86_64 => {
                     dev.check(.x86_64_backend);
-                    const Register = @import("../arch/x86_64/bits.zig").Register;
+                    const Register = @import("../codegen/x86_64/bits.zig").Register;
                     for (dwarf.debug_frame.section.units.items) |*unit| {
                         header_aw.clearRetainingCapacity();
                         try header_aw.ensureTotalCapacity(unit.header_len);

@@ -113,5 +113,5 @@ pub const Eflags = packed struct(u32) {
 const mem = std.mem;
 const std = @import("std");
 
-const encoding = @import("../arch/riscv64/encoding.zig");
+const encoding = @import("../codegen/riscv64/encoding.zig");
 const Instruction = encoding.Instruction;

@@ -29,8 +29,8 @@ const leb = std.leb;
 const log = std.log.scoped(.link);
 const mem = std.mem;
 
-const Mir = @import("../arch/wasm/Mir.zig");
-const CodeGen = @import("../arch/wasm/CodeGen.zig");
+const Mir = @import("../codegen/wasm/Mir.zig");
+const CodeGen = @import("../codegen/wasm/CodeGen.zig");
 const abi = @import("../codegen/wasm/abi.zig");
 const Compilation = @import("../Compilation.zig");
 const Dwarf = @import("Dwarf.zig");

@@ -55,11 +55,11 @@ fn importBackend(comptime backend: std.builtin.CompilerBackend) type {
         .stage2_c => @import("codegen/c.zig"),
         .stage2_llvm => @import("codegen/llvm.zig"),
         .stage2_powerpc => unreachable,
-        .stage2_riscv64 => @import("arch/riscv64/CodeGen.zig"),
-        .stage2_sparc64 => @import("arch/sparc64/CodeGen.zig"),
+        .stage2_riscv64 => @import("codegen/riscv64/CodeGen.zig"),
+        .stage2_sparc64 => @import("codegen/sparc64/CodeGen.zig"),
         .stage2_spirv => @import("codegen/spirv/CodeGen.zig"),
-        .stage2_wasm => @import("arch/wasm/CodeGen.zig"),
-        .stage2_x86, .stage2_x86_64 => @import("arch/x86_64/CodeGen.zig"),
+        .stage2_wasm => @import("codegen/wasm/CodeGen.zig"),
+        .stage2_x86, .stage2_x86_64 => @import("codegen/x86_64/CodeGen.zig"),
         _ => unreachable,
     };
 }
@@ -99,10 +99,10 @@ pub fn wantsLiveness(pt: Zcu.PerThread, nav_index: InternPool.Nav.Index) bool {
 /// union of all MIR types. The active tag is known from the backend in use; see `AnyMir.tag`.
 pub const AnyMir = union {
     aarch64: if (dev.env.supports(.aarch64_backend)) @import("codegen/aarch64/Mir.zig") else noreturn,
-    riscv64: if (dev.env.supports(.riscv64_backend)) @import("arch/riscv64/Mir.zig") else noreturn,
-    sparc64: if (dev.env.supports(.sparc64_backend)) @import("arch/sparc64/Mir.zig") else noreturn,
-    x86_64: if (dev.env.supports(.x86_64_backend)) @import("arch/x86_64/Mir.zig") else noreturn,
-    wasm: if (dev.env.supports(.wasm_backend)) @import("arch/wasm/Mir.zig") else noreturn,
+    riscv64: if (dev.env.supports(.riscv64_backend)) @import("codegen/riscv64/Mir.zig") else noreturn,
+    sparc64: if (dev.env.supports(.sparc64_backend)) @import("codegen/sparc64/Mir.zig") else noreturn,
+    x86_64: if (dev.env.supports(.x86_64_backend)) @import("codegen/x86_64/Mir.zig") else noreturn,
+    wasm: if (dev.env.supports(.wasm_backend)) @import("codegen/wasm/Mir.zig") else noreturn,
     c: if (dev.env.supports(.c_backend)) @import("codegen/c.zig").Mir else noreturn,
 
     pub inline fn tag(comptime backend: std.builtin.CompilerBackend) []const u8 {