Commit 7e17cbbda5

@@ -0,0 +1,21 @@
+pub fn main() void {
+    print();
+}
+
+fn print() void {
+    asm volatile ("ecall"
+        :
+        : [number] "{a7}" (64),
+          [arg1] "{a0}" (1),
+          [arg2] "{a1}" (@ptrToInt("Hello, World!\n")),
+          [arg3] "{a2}" ("Hello, World!\n".len),
+        : "rcx", "r11", "memory"
+    );
+    return;
+}
+
+// run
+// target=riscv64-linux
+//
+// Hello, World!
+//

@@ -0,0 +1,27 @@
+pub fn main() void {
+    print();
+    print();
+    print();
+    print();
+}
+
+fn print() void {
+    asm volatile ("ecall"
+        :
+        : [number] "{a7}" (64),
+          [arg1] "{a0}" (1),
+          [arg2] "{a1}" (@ptrToInt("Hello, World!\n")),
+          [arg3] "{a2}" ("Hello, World!\n".len),
+        : "rcx", "r11", "memory"
+    );
+    return;
+}
+
+// run
+// target=riscv64-linux
+//
+// Hello, World!
+// Hello, World!
+// Hello, World!
+// Hello, World!
+//

@@ -1,33 +0,0 @@
-const std = @import("std");
-const TestContext = @import("../../src/test.zig").TestContext;
-
-const linux_riscv64 = std.zig.CrossTarget{
-    .cpu_arch = .riscv64,
-    .os_tag = .linux,
-};
-
-pub fn addCases(ctx: *TestContext) !void {
-    {
-        var case = ctx.exe("riscv64 hello world", linux_riscv64);
-        // Regular old hello world
-        case.addCompareOutput(
-            \\pub fn main() void {
-            \\    print();
-            \\}
-            \\
-            \\fn print() void {
-            \\    asm volatile ("ecall"
-            \\        :
-            \\        : [number] "{a7}" (64),
-            \\          [arg1] "{a0}" (1),
-            \\          [arg2] "{a1}" (@ptrToInt("Hello, World!\n")),
-            \\          [arg3] "{a2}" ("Hello, World!\n".len)
-            \\        : "rcx", "r11", "memory"
-            \\    );
-            \\    return;
-            \\}
-        ,
-            "Hello, World!\n",
-        );
-    }
-}

@@ -12,7 +12,6 @@ pub fn addCases(ctx: *TestContext) !void {
     try @import("stage2/arm.zig").addCases(ctx);
     try @import("stage2/aarch64.zig").addCases(ctx);
     try @import("stage2/llvm.zig").addCases(ctx);
-    try @import("stage2/riscv64.zig").addCases(ctx);
     try @import("stage2/plan9.zig").addCases(ctx);
     try @import("stage2/x86_64.zig").addCases(ctx);
     try @import("stage2/sparcv9.zig").addCases(ctx);