Commit 76558f8c6b
Changed files (1)
src
codegen
src/codegen/llvm.zig
@@ -12578,7 +12578,7 @@ fn ccAbiPromoteInt(
else => null,
},
else => switch (target.cpu.arch) {
- .riscv64 => switch (int_info.bits) {
+ .loongarch64, .riscv64 => switch (int_info.bits) {
0...16 => int_info.signedness,
32 => .signed, // LLVM always signextends 32 bit ints, unsure if bug.
17...31, 33...63 => int_info.signedness,