Commit 71c5eebd32
Changed files (3)
src
arch
src/arch/x86_64/CodeGen.zig
@@ -2968,9 +2968,8 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
_ = try self.addInst(.{
.tag = .mov,
.ops = (Mir.Ops{
- .reg1 = reg,
+ .reg1 = registerAlias(reg, @divExact(src_reg.size(), 8)),
.reg2 = src_reg,
- .flags = 0b11,
}).encode(),
.data = undefined,
});
src/arch/x86_64/Emit.zig
@@ -1119,17 +1119,7 @@ fn mirMovImpl(
encoder.imm32(imm_op);
break :blk;
}
- // mov reg1, reg2
- // RM
- const opc: u8 = if (ops.reg1.size() == 8) 0x8a else 0x8b;
- const encoder = try Encoder.init(code, 3);
- encoder.rex(.{
- .w = ops.reg1.size() == 64 and ops.reg2.size() == 64,
- .r = ops.reg1.isExtended(),
- .b = ops.reg2.isExtended(),
- });
- encoder.opcode_1byte(opc);
- encoder.modRm_direct(ops.reg1.lowId(), ops.reg2.lowId());
+ return EmitResult.err(allocator, src_loc, "TODO unused variant: mov reg1, reg2, 0b11", .{});
},
}
return EmitResult.ok();
src/arch/x86_64/Mir.zig
@@ -145,7 +145,7 @@ pub const Inst = struct {
/// 0b10 [reg1 + imm32], reg2
/// 0b10 [reg1 + 0], imm32
/// 0b11 [reg1 + imm32], imm32
- /// 0b11 reg1, reg2 (RM)
+ /// 0b11 AVAILABLE
/// Notes:
/// * If reg2 is `none` then it means Data field `imm` is used as the immediate.
/// * When two imm32 values are required, Data field `payload` points at `ImmPair`.