Commit 6f3ed2f71f
Changed files (15)
lib/std/target/aarch64.zig
@@ -8,9 +8,18 @@ const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;
pub const Feature = enum {
- a34,
+ CONTEXTIDREL2,
+ a35,
+ a53,
+ a55,
+ a57,
+ a64fx,
a65,
+ a72,
+ a73,
+ a75,
a76,
+ a77,
aes,
aggressive_fma,
alternate_sextload_cvt_f32_pattern,
@@ -36,10 +45,14 @@ pub const Feature = enum {
call_saved_x18,
call_saved_x8,
call_saved_x9,
+ carmel,
ccdp,
ccidx,
ccpp,
complxnum,
+ cortex_a78,
+ cortex_r82,
+ cortex_x1,
crc,
crypto,
custom_cheap_as_move,
@@ -49,9 +62,11 @@ pub const Feature = enum {
ecv,
ete,
exynos_cheap_as_move,
+ exynosm3,
exynosm4,
f32mm,
f64mm,
+ falkor,
fgt,
fmi,
force_32bit_jump_tables,
@@ -67,8 +82,9 @@ pub const Feature = enum {
fuse_literals,
harden_sls_blr,
harden_sls_retbr,
- i8mm,
+ _i8mm,
jsconv,
+ kryo,
lor,
lse,
lsl_fast,
@@ -77,8 +93,11 @@ pub const Feature = enum {
neon,
neoversee1,
neoversen1,
+ neoversen2,
+ neoversev1,
no_neg_immediates,
nv,
+ outline_atomics,
pa,
pan,
pan_rwv,
@@ -88,7 +107,6 @@ pub const Feature = enum {
predres,
rand,
ras,
- rasv8_4,
rcpc,
rcpc_immo,
rdm,
@@ -117,6 +135,7 @@ pub const Feature = enum {
reserve_x6,
reserve_x7,
reserve_x9,
+ saphira,
sb,
sel2,
sha2,
@@ -136,6 +155,12 @@ pub const Feature = enum {
sve2_sha3,
sve2_sm4,
tagged_globals,
+ thunderx,
+ thunderx2t99,
+ thunderx3t110,
+ thunderxt81,
+ thunderxt83,
+ thunderxt88,
tlb_rmi,
tme,
tpidr_el1,
@@ -143,18 +168,19 @@ pub const Feature = enum {
tpidr_el3,
tracev8_4,
trbe,
+ tsv110,
uaops,
use_aa,
use_experimental_zeroing_pseudos,
use_postra_scheduler,
use_reciprocal_square_root,
- v8a,
v8_1a,
v8_2a,
v8_3a,
v8_4a,
v8_5a,
v8_6a,
+ v8r,
vh,
zcm,
zcz,
@@ -166,18 +192,87 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
- @setEvalBranchQuota(2000);
+ @setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
- result[@enumToInt(Feature.a34)] = .{
+ result[@enumToInt(Feature.CONTEXTIDREL2)] = .{
+ .llvm_name = "CONTEXTIDREL2",
+ .description = "Enable RW operand CONTEXTIDR_EL2",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.a35)] = .{
.llvm_name = "a35",
- .description = "Cortex-A34 ARM processors",
+ .description = "Cortex-A35 ARM processors",
+ .dependencies = featureSet(&[_]Feature{
+ .crc,
+ .crypto,
+ .fp_armv8,
+ .neon,
+ .perfmon,
+ }),
+ };
+ result[@enumToInt(Feature.a53)] = .{
+ .llvm_name = "a53",
+ .description = "Cortex-A53 ARM processors",
+ .dependencies = featureSet(&[_]Feature{
+ .balance_fp_ops,
+ .crc,
+ .crypto,
+ .custom_cheap_as_move,
+ .fp_armv8,
+ .fuse_aes,
+ .neon,
+ .perfmon,
+ .use_aa,
+ .use_postra_scheduler,
+ }),
+ };
+ result[@enumToInt(Feature.a55)] = .{
+ .llvm_name = "a55",
+ .description = "Cortex-A55 ARM processors",
+ .dependencies = featureSet(&[_]Feature{
+ .crypto,
+ .dotprod,
+ .fp_armv8,
+ .fullfp16,
+ .fuse_aes,
+ .neon,
+ .perfmon,
+ .rcpc,
+ .v8_2a,
+ }),
+ };
+ result[@enumToInt(Feature.a57)] = .{
+ .llvm_name = "a57",
+ .description = "Cortex-A57 ARM processors",
.dependencies = featureSet(&[_]Feature{
+ .balance_fp_ops,
.crc,
.crypto,
+ .custom_cheap_as_move,
+ .fp_armv8,
+ .fuse_aes,
+ .fuse_literals,
+ .neon,
+ .perfmon,
+ .predictable_select_expensive,
+ .use_postra_scheduler,
+ }),
+ };
+ result[@enumToInt(Feature.a64fx)] = .{
+ .llvm_name = "a64fx",
+ .description = "Fujitsu A64FX processors",
+ .dependencies = featureSet(&[_]Feature{
+ .complxnum,
+ .fp_armv8,
+ .fullfp16,
+ .neon,
.perfmon,
- .v8a,
+ .sha2,
+ .sve,
+ .use_postra_scheduler,
+ .v8_2a,
}),
};
result[@enumToInt(Feature.a65)] = .{
@@ -195,18 +290,72 @@ pub const all_features = blk: {
.v8_2a,
}),
};
+ result[@enumToInt(Feature.a72)] = .{
+ .llvm_name = "a72",
+ .description = "Cortex-A72 ARM processors",
+ .dependencies = featureSet(&[_]Feature{
+ .crc,
+ .crypto,
+ .fp_armv8,
+ .fuse_aes,
+ .neon,
+ .perfmon,
+ }),
+ };
+ result[@enumToInt(Feature.a73)] = .{
+ .llvm_name = "a73",
+ .description = "Cortex-A73 ARM processors",
+ .dependencies = featureSet(&[_]Feature{
+ .crc,
+ .crypto,
+ .fp_armv8,
+ .fuse_aes,
+ .neon,
+ .perfmon,
+ }),
+ };
+ result[@enumToInt(Feature.a75)] = .{
+ .llvm_name = "a75",
+ .description = "Cortex-A75 ARM processors",
+ .dependencies = featureSet(&[_]Feature{
+ .crypto,
+ .dotprod,
+ .fp_armv8,
+ .fullfp16,
+ .fuse_aes,
+ .neon,
+ .perfmon,
+ .rcpc,
+ .v8_2a,
+ }),
+ };
result[@enumToInt(Feature.a76)] = .{
.llvm_name = "a76",
.description = "Cortex-A76 ARM processors",
.dependencies = featureSet(&[_]Feature{
.crypto,
.dotprod,
+ .fp_armv8,
.fullfp16,
+ .neon,
.rcpc,
.ssbs,
.v8_2a,
}),
};
+ result[@enumToInt(Feature.a77)] = .{
+ .llvm_name = "a77",
+ .description = "Cortex-A77 ARM processors",
+ .dependencies = featureSet(&[_]Feature{
+ .crypto,
+ .dotprod,
+ .fp_armv8,
+ .fullfp16,
+ .neon,
+ .rcpc,
+ .v8_2a,
+ }),
+ };
result[@enumToInt(Feature.aes)] = .{
.llvm_name = "aes",
.description = "Enable AES support",
@@ -415,6 +564,16 @@ pub const all_features = blk: {
.description = "Make X9 callee saved.",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.carmel)] = .{
+ .llvm_name = "carmel",
+ .description = "Nvidia Carmel processors",
+ .dependencies = featureSet(&[_]Feature{
+ .crypto,
+ .fullfp16,
+ .neon,
+ .v8_2a,
+ }),
+ };
result[@enumToInt(Feature.ccdp)] = .{
.llvm_name = "ccdp",
.description = "Enable v8.5 Cache Clean to Point of Deep Persistence",
@@ -437,6 +596,49 @@ pub const all_features = blk: {
.neon,
}),
};
+ result[@enumToInt(Feature.cortex_a78)] = .{
+ .llvm_name = "cortex-a78",
+ .description = "Cortex-A78 ARM processors",
+ .dependencies = featureSet(&[_]Feature{
+ .crypto,
+ .dotprod,
+ .fp_armv8,
+ .fullfp16,
+ .fuse_aes,
+ .neon,
+ .perfmon,
+ .rcpc,
+ .spe,
+ .ssbs,
+ .use_postra_scheduler,
+ .v8_2a,
+ }),
+ };
+ result[@enumToInt(Feature.cortex_r82)] = .{
+ .llvm_name = "cortex-r82",
+ .description = "Cortex-R82 ARM Processors",
+ .dependencies = featureSet(&[_]Feature{
+ .use_postra_scheduler,
+ .v8r,
+ }),
+ };
+ result[@enumToInt(Feature.cortex_x1)] = .{
+ .llvm_name = "cortex-x1",
+ .description = "Cortex-X1 ARM processors",
+ .dependencies = featureSet(&[_]Feature{
+ .crypto,
+ .dotprod,
+ .fp_armv8,
+ .fullfp16,
+ .fuse_aes,
+ .neon,
+ .perfmon,
+ .rcpc,
+ .spe,
+ .use_postra_scheduler,
+ .v8_2a,
+ }),
+ };
result[@enumToInt(Feature.crc)] = .{
.llvm_name = "crc",
.description = "Enable ARMv8 CRC-32 checksum instructions",
@@ -490,6 +692,25 @@ pub const all_features = blk: {
.custom_cheap_as_move,
}),
};
+ result[@enumToInt(Feature.exynosm3)] = .{
+ .llvm_name = "exynosm3",
+ .description = "Samsung Exynos-M3 processors",
+ .dependencies = featureSet(&[_]Feature{
+ .crc,
+ .crypto,
+ .exynos_cheap_as_move,
+ .force_32bit_jump_tables,
+ .fuse_address,
+ .fuse_aes,
+ .fuse_csel,
+ .fuse_literals,
+ .lsl_fast,
+ .perfmon,
+ .predictable_select_expensive,
+ .use_postra_scheduler,
+ .zcz_fp,
+ }),
+ };
result[@enumToInt(Feature.exynosm4)] = .{
.llvm_name = "exynosm4",
.description = "Samsung Exynos-M4 processors",
@@ -527,6 +748,24 @@ pub const all_features = blk: {
.sve,
}),
};
+ result[@enumToInt(Feature.falkor)] = .{
+ .llvm_name = "falkor",
+ .description = "Qualcomm Falkor processors",
+ .dependencies = featureSet(&[_]Feature{
+ .crc,
+ .crypto,
+ .custom_cheap_as_move,
+ .fp_armv8,
+ .lsl_fast,
+ .neon,
+ .perfmon,
+ .predictable_select_expensive,
+ .rdm,
+ .slow_strqro_store,
+ .use_postra_scheduler,
+ .zcz,
+ }),
+ };
result[@enumToInt(Feature.fgt)] = .{
.llvm_name = "fgt",
.description = "Enable fine grained virtualization traps extension",
@@ -606,7 +845,7 @@ pub const all_features = blk: {
.description = "Harden against straight line speculation across RET and BR instructions",
.dependencies = featureSet(&[_]Feature{}),
};
- result[@enumToInt(Feature.i8mm)] = .{
+ result[@enumToInt(Feature._i8mm)] = .{
.llvm_name = "i8mm",
.description = "Enable Matrix Multiply Int8 Extension",
.dependencies = featureSet(&[_]Feature{}),
@@ -618,6 +857,22 @@ pub const all_features = blk: {
.fp_armv8,
}),
};
+ result[@enumToInt(Feature.kryo)] = .{
+ .llvm_name = "kryo",
+ .description = "Qualcomm Kryo processors",
+ .dependencies = featureSet(&[_]Feature{
+ .crc,
+ .crypto,
+ .custom_cheap_as_move,
+ .fp_armv8,
+ .lsl_fast,
+ .neon,
+ .perfmon,
+ .predictable_select_expensive,
+ .use_postra_scheduler,
+ .zcz,
+ }),
+ };
result[@enumToInt(Feature.lor)] = .{
.llvm_name = "lor",
.description = "Enables ARM v8.1 Limited Ordering Regions extension",
@@ -679,6 +934,42 @@ pub const all_features = blk: {
.v8_2a,
}),
};
+ result[@enumToInt(Feature.neoversen2)] = .{
+ .llvm_name = "neoversen2",
+ .description = "Neoverse N2 ARM processors",
+ .dependencies = featureSet(&[_]Feature{
+ .bf16,
+ .ete,
+ ._i8mm,
+ .mte,
+ .sve2,
+ .sve2_bitperm,
+ .trbe,
+ .v8_5a,
+ }),
+ };
+ result[@enumToInt(Feature.neoversev1)] = .{
+ .llvm_name = "neoversev1",
+ .description = "Neoverse V1 ARM processors",
+ .dependencies = featureSet(&[_]Feature{
+ .bf16,
+ .ccdp,
+ .crypto,
+ .fp_armv8,
+ .fp16fml,
+ .fullfp16,
+ .fuse_aes,
+ ._i8mm,
+ .neon,
+ .perfmon,
+ .rand,
+ .spe,
+ .ssbs,
+ .sve,
+ .use_postra_scheduler,
+ .v8_4a,
+ }),
+ };
result[@enumToInt(Feature.no_neg_immediates)] = .{
.llvm_name = "no-neg-immediates",
.description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.",
@@ -686,7 +977,12 @@ pub const all_features = blk: {
};
result[@enumToInt(Feature.nv)] = .{
.llvm_name = "nv",
- .description = "Enable v8.4-A Nested Virtualization extension",
+ .description = "Enable v8.4-A Nested Virtualization Enchancement",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.outline_atomics)] = .{
+ .llvm_name = "outline-atomics",
+ .description = "Enable out of line atomics to support LSE instructions",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.pa)] = .{
@@ -736,13 +1032,6 @@ pub const all_features = blk: {
.description = "Enable ARMv8 Reliability, Availability and Serviceability Extensions",
.dependencies = featureSet(&[_]Feature{}),
};
- result[@enumToInt(Feature.rasv8_4)] = .{
- .llvm_name = "rasv8_4",
- .description = "Enable v8.4-A Reliability, Availability and Serviceability extension",
- .dependencies = featureSet(&[_]Feature{
- .ras,
- }),
- };
result[@enumToInt(Feature.rcpc)] = .{
.llvm_name = "rcpc",
.description = "Enable support for RCPC extension",
@@ -885,6 +1174,23 @@ pub const all_features = blk: {
.description = "Reserve X9, making it unavailable as a GPR",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.saphira)] = .{
+ .llvm_name = "saphira",
+ .description = "Qualcomm Saphira processors",
+ .dependencies = featureSet(&[_]Feature{
+ .crypto,
+ .custom_cheap_as_move,
+ .fp_armv8,
+ .lsl_fast,
+ .neon,
+ .perfmon,
+ .predictable_select_expensive,
+ .spe,
+ .use_postra_scheduler,
+ .v8_4a,
+ .zcz,
+ }),
+ };
result[@enumToInt(Feature.sb)] = .{
.llvm_name = "sb",
.description = "Enable v8.5 Speculation Barrier",
@@ -955,7 +1261,9 @@ pub const all_features = blk: {
result[@enumToInt(Feature.sve)] = .{
.llvm_name = "sve",
.description = "Enable Scalable Vector Extension (SVE) instructions",
- .dependencies = featureSet(&[_]Feature{}),
+ .dependencies = featureSet(&[_]Feature{
+ .fullfp16,
+ }),
};
result[@enumToInt(Feature.sve2)] = .{
.llvm_name = "sve2",
@@ -1000,15 +1308,104 @@ pub const all_features = blk: {
.description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits",
.dependencies = featureSet(&[_]Feature{}),
};
- result[@enumToInt(Feature.tlb_rmi)] = .{
- .llvm_name = "tlb-rmi",
- .description = "Enable v8.4-A TLB Range and Maintenance Instructions",
- .dependencies = featureSet(&[_]Feature{}),
- };
- result[@enumToInt(Feature.tme)] = .{
- .llvm_name = "tme",
- .description = "Enable Transactional Memory Extension",
- .dependencies = featureSet(&[_]Feature{}),
+ result[@enumToInt(Feature.thunderx)] = .{
+ .llvm_name = "thunderx",
+ .description = "Cavium ThunderX processors",
+ .dependencies = featureSet(&[_]Feature{
+ .crc,
+ .crypto,
+ .fp_armv8,
+ .neon,
+ .perfmon,
+ .predictable_select_expensive,
+ .use_postra_scheduler,
+ }),
+ };
+ result[@enumToInt(Feature.thunderx2t99)] = .{
+ .llvm_name = "thunderx2t99",
+ .description = "Cavium ThunderX2 processors",
+ .dependencies = featureSet(&[_]Feature{
+ .aggressive_fma,
+ .arith_bcc_fusion,
+ .crc,
+ .crypto,
+ .fp_armv8,
+ .lse,
+ .neon,
+ .predictable_select_expensive,
+ .use_postra_scheduler,
+ .v8_1a,
+ }),
+ };
+ result[@enumToInt(Feature.thunderx3t110)] = .{
+ .llvm_name = "thunderx3t110",
+ .description = "Marvell ThunderX3 processors",
+ .dependencies = featureSet(&[_]Feature{
+ .aggressive_fma,
+ .arith_bcc_fusion,
+ .balance_fp_ops,
+ .crc,
+ .crypto,
+ .fp_armv8,
+ .lse,
+ .neon,
+ .pa,
+ .perfmon,
+ .predictable_select_expensive,
+ .strict_align,
+ .use_aa,
+ .use_postra_scheduler,
+ .v8_3a,
+ }),
+ };
+ result[@enumToInt(Feature.thunderxt81)] = .{
+ .llvm_name = "thunderxt81",
+ .description = "Cavium ThunderX processors",
+ .dependencies = featureSet(&[_]Feature{
+ .crc,
+ .crypto,
+ .fp_armv8,
+ .neon,
+ .perfmon,
+ .predictable_select_expensive,
+ .use_postra_scheduler,
+ }),
+ };
+ result[@enumToInt(Feature.thunderxt83)] = .{
+ .llvm_name = "thunderxt83",
+ .description = "Cavium ThunderX processors",
+ .dependencies = featureSet(&[_]Feature{
+ .crc,
+ .crypto,
+ .fp_armv8,
+ .neon,
+ .perfmon,
+ .predictable_select_expensive,
+ .use_postra_scheduler,
+ }),
+ };
+ result[@enumToInt(Feature.thunderxt88)] = .{
+ .llvm_name = "thunderxt88",
+ .description = "Cavium ThunderX processors",
+ .dependencies = featureSet(&[_]Feature{
+ .crc,
+ .crypto,
+ .fp_armv8,
+ .neon,
+ .perfmon,
+ .predictable_select_expensive,
+ .use_postra_scheduler,
+ }),
+ };
+ result[@enumToInt(Feature.tlb_rmi)] = .{
+ .llvm_name = "tlb-rmi",
+ .description = "Enable v8.4-A TLB Range and Maintenance Instructions",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.tme)] = .{
+ .llvm_name = "tme",
+ .description = "Enable Transactional Memory Extension",
+ .dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.tpidr_el1)] = .{
.llvm_name = "tpidr-el1",
@@ -1035,6 +1432,24 @@ pub const all_features = blk: {
.description = "Enable Trace Buffer Extension",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.tsv110)] = .{
+ .llvm_name = "tsv110",
+ .description = "HiSilicon TS-V110 processors",
+ .dependencies = featureSet(&[_]Feature{
+ .crypto,
+ .custom_cheap_as_move,
+ .dotprod,
+ .fp_armv8,
+ .fp16fml,
+ .fullfp16,
+ .fuse_aes,
+ .neon,
+ .perfmon,
+ .spe,
+ .use_postra_scheduler,
+ .v8_2a,
+ }),
+ };
result[@enumToInt(Feature.uaops)] = .{
.llvm_name = "uaops",
.description = "Enable v8.2 UAO PState",
@@ -1060,14 +1475,6 @@ pub const all_features = blk: {
.description = "Use the reciprocal square root approximation",
.dependencies = featureSet(&[_]Feature{}),
};
- result[@enumToInt(Feature.v8a)] = .{
- .llvm_name = null,
- .description = "Support ARM v8a instructions",
- .dependencies = featureSet(&[_]Feature{
- .fp_armv8,
- .neon,
- }),
- };
result[@enumToInt(Feature.v8_1a)] = .{
.llvm_name = "v8.1a",
.description = "Support ARM v8.1a instructions",
@@ -1078,7 +1485,6 @@ pub const all_features = blk: {
.pan,
.rdm,
.vh,
- .v8a,
}),
};
result[@enumToInt(Feature.v8_2a)] = .{
@@ -1115,7 +1521,6 @@ pub const all_features = blk: {
.mpam,
.nv,
.pmu,
- .rasv8_4,
.rcpc_immo,
.sel2,
.tlb_rmi,
@@ -1146,14 +1551,52 @@ pub const all_features = blk: {
.bf16,
.ecv,
.fgt,
- .i8mm,
+ ._i8mm,
.v8_5a,
}),
};
+ result[@enumToInt(Feature.v8r)] = .{
+ .llvm_name = "v8r",
+ .description = "Support ARM v8r instructions",
+ .dependencies = featureSet(&[_]Feature{
+ .CONTEXTIDREL2,
+ .ccidx,
+ .ccpp,
+ .complxnum,
+ .crc,
+ .dit,
+ .dotprod,
+ .fmi,
+ .fp16fml,
+ .fullfp16,
+ .jsconv,
+ .lse,
+ .pa,
+ .pan,
+ .pan_rwv,
+ .perfmon,
+ .predres,
+ .ras,
+ .rcpc,
+ .rcpc_immo,
+ .rdm,
+ .sb,
+ .sel2,
+ .sha3,
+ .sm4,
+ .specrestrict,
+ .ssbs,
+ .tlb_rmi,
+ .tracev8_4,
+ .uaops,
+ }),
+ };
result[@enumToInt(Feature.vh)] = .{
.llvm_name = "vh",
.description = "Enables ARM v8.1 Virtual Host extension",
- .dependencies = featureSet(&[_]Feature{}),
+ .dependencies = featureSet(&[_]Feature{
+ .CONTEXTIDREL2,
+ }),
};
result[@enumToInt(Feature.zcm)] = .{
.llvm_name = "zcm",
@@ -1196,15 +1639,7 @@ pub const cpu = struct {
.name = "a64fx",
.llvm_name = "a64fx",
.features = featureSet(&[_]Feature{
- .complxnum,
- .fp_armv8,
- .fullfp16,
- .neon,
- .perfmon,
- .sha2,
- .sve,
- .use_postra_scheduler,
- .v8_2a,
+ .a64fx,
}),
};
pub const apple_a10 = CpuModel{
@@ -1281,68 +1716,42 @@ pub const cpu = struct {
.name = "carmel",
.llvm_name = "carmel",
.features = featureSet(&[_]Feature{
- .crypto,
- .fullfp16,
- .neon,
- .v8_2a,
+ .carmel,
}),
};
pub const cortex_a34 = CpuModel{
.name = "cortex_a34",
.llvm_name = "cortex-a34",
.features = featureSet(&[_]Feature{
- .a34,
+ .a35,
}),
};
pub const cortex_a35 = CpuModel{
.name = "cortex_a35",
.llvm_name = "cortex-a35",
.features = featureSet(&[_]Feature{
- .a34,
+ .a35,
}),
};
pub const cortex_a53 = CpuModel{
.name = "cortex_a53",
.llvm_name = "cortex-a53",
.features = featureSet(&[_]Feature{
- .balance_fp_ops,
- .crc,
- .crypto,
- .custom_cheap_as_move,
- .fuse_aes,
- .perfmon,
- .use_aa,
- .use_postra_scheduler,
- .v8a,
+ .a53,
}),
};
pub const cortex_a55 = CpuModel{
.name = "cortex_a55",
.llvm_name = "cortex-a55",
.features = featureSet(&[_]Feature{
- .crypto,
- .dotprod,
- .fullfp16,
- .fuse_aes,
- .perfmon,
- .rcpc,
- .v8_2a,
+ .a55,
}),
};
pub const cortex_a57 = CpuModel{
.name = "cortex_a57",
.llvm_name = "cortex-a57",
.features = featureSet(&[_]Feature{
- .balance_fp_ops,
- .crc,
- .crypto,
- .custom_cheap_as_move,
- .fuse_aes,
- .fuse_literals,
- .perfmon,
- .predictable_select_expensive,
- .use_postra_scheduler,
- .v8a,
+ .a57,
}),
};
pub const cortex_a65 = CpuModel{
@@ -1363,35 +1772,21 @@ pub const cpu = struct {
.name = "cortex_a72",
.llvm_name = "cortex-a72",
.features = featureSet(&[_]Feature{
- .crc,
- .crypto,
- .fuse_aes,
- .perfmon,
- .v8a,
+ .a72,
}),
};
pub const cortex_a73 = CpuModel{
.name = "cortex_a73",
.llvm_name = "cortex-a73",
.features = featureSet(&[_]Feature{
- .crc,
- .crypto,
- .fuse_aes,
- .perfmon,
- .v8a,
+ .a73,
}),
};
pub const cortex_a75 = CpuModel{
.name = "cortex_a75",
.llvm_name = "cortex-a75",
.features = featureSet(&[_]Feature{
- .crypto,
- .dotprod,
- .fullfp16,
- .fuse_aes,
- .perfmon,
- .rcpc,
- .v8_2a,
+ .a75,
}),
};
pub const cortex_a76 = CpuModel{
@@ -1412,48 +1807,28 @@ pub const cpu = struct {
.name = "cortex_a77",
.llvm_name = "cortex-a77",
.features = featureSet(&[_]Feature{
- .crypto,
- .dotprod,
- .fp_armv8,
- .fullfp16,
- .neon,
- .rcpc,
- .v8_2a,
+ .a77,
}),
};
pub const cortex_a78 = CpuModel{
.name = "cortex_a78",
.llvm_name = "cortex-a78",
.features = featureSet(&[_]Feature{
- .crypto,
- .dotprod,
- .fp_armv8,
- .fullfp16,
- .fuse_aes,
- .neon,
- .perfmon,
- .rcpc,
- .spe,
- .ssbs,
- .use_postra_scheduler,
- .v8_2a,
+ .cortex_a78,
+ }),
+ };
+ pub const cortex_r82 = CpuModel{
+ .name = "cortex_r82",
+ .llvm_name = "cortex-r82",
+ .features = featureSet(&[_]Feature{
+ .cortex_r82,
}),
};
pub const cortex_x1 = CpuModel{
.name = "cortex_x1",
.llvm_name = "cortex-x1",
.features = featureSet(&[_]Feature{
- .crypto,
- .dotprod,
- .fp_armv8,
- .fullfp16,
- .fuse_aes,
- .neon,
- .perfmon,
- .rcpc,
- .spe,
- .use_postra_scheduler,
- .v8_2a,
+ .cortex_x1,
}),
};
pub const cyclone = CpuModel{
@@ -1463,59 +1838,11 @@ pub const cpu = struct {
.apple_a7,
}),
};
- pub const exynos_m1 = CpuModel{
- .name = "exynos_m1",
- .llvm_name = null,
- .features = featureSet(&[_]Feature{
- .crc,
- .crypto,
- .exynos_cheap_as_move,
- .force_32bit_jump_tables,
- .fuse_aes,
- .perfmon,
- .slow_misaligned_128store,
- .slow_paired_128,
- .use_postra_scheduler,
- .use_reciprocal_square_root,
- .v8a,
- .zcz_fp,
- }),
- };
- pub const exynos_m2 = CpuModel{
- .name = "exynos_m2",
- .llvm_name = null,
- .features = featureSet(&[_]Feature{
- .crc,
- .crypto,
- .exynos_cheap_as_move,
- .force_32bit_jump_tables,
- .fuse_aes,
- .perfmon,
- .slow_misaligned_128store,
- .slow_paired_128,
- .use_postra_scheduler,
- .v8a,
- .zcz_fp,
- }),
- };
pub const exynos_m3 = CpuModel{
.name = "exynos_m3",
.llvm_name = "exynos-m3",
.features = featureSet(&[_]Feature{
- .crc,
- .crypto,
- .exynos_cheap_as_move,
- .force_32bit_jump_tables,
- .fuse_address,
- .fuse_aes,
- .fuse_csel,
- .fuse_literals,
- .lsl_fast,
- .perfmon,
- .predictable_select_expensive,
- .use_postra_scheduler,
- .v8a,
- .zcz_fp,
+ .exynosm3,
}),
};
pub const exynos_m4 = CpuModel{
@@ -1536,17 +1863,7 @@ pub const cpu = struct {
.name = "falkor",
.llvm_name = "falkor",
.features = featureSet(&[_]Feature{
- .crc,
- .crypto,
- .custom_cheap_as_move,
- .lsl_fast,
- .perfmon,
- .predictable_select_expensive,
- .rdm,
- .slow_strqro_store,
- .use_postra_scheduler,
- .v8a,
- .zcz,
+ .falkor,
}),
};
pub const generic = CpuModel{
@@ -1554,25 +1871,18 @@ pub const cpu = struct {
.llvm_name = "generic",
.features = featureSet(&[_]Feature{
.ete,
+ .fp_armv8,
.fuse_aes,
+ .neon,
.perfmon,
.use_postra_scheduler,
- .v8a,
}),
};
pub const kryo = CpuModel{
.name = "kryo",
.llvm_name = "kryo",
.features = featureSet(&[_]Feature{
- .crc,
- .crypto,
- .custom_cheap_as_move,
- .lsl_fast,
- .perfmon,
- .predictable_select_expensive,
- .use_postra_scheduler,
- .zcz,
- .v8a,
+ .kryo,
}),
};
pub const neoverse_e1 = CpuModel{
@@ -1589,118 +1899,74 @@ pub const cpu = struct {
.neoversen1,
}),
};
+ pub const neoverse_n2 = CpuModel{
+ .name = "neoverse_n2",
+ .llvm_name = "neoverse-n2",
+ .features = featureSet(&[_]Feature{
+ .neoversen2,
+ }),
+ };
+ pub const neoverse_v1 = CpuModel{
+ .name = "neoverse_v1",
+ .llvm_name = "neoverse-v1",
+ .features = featureSet(&[_]Feature{
+ .neoversev1,
+ }),
+ };
pub const saphira = CpuModel{
.name = "saphira",
.llvm_name = "saphira",
.features = featureSet(&[_]Feature{
- .crypto,
- .custom_cheap_as_move,
- .lsl_fast,
- .perfmon,
- .predictable_select_expensive,
- .spe,
- .use_postra_scheduler,
- .v8_4a,
- .zcz,
+ .saphira,
}),
};
pub const thunderx = CpuModel{
.name = "thunderx",
.llvm_name = "thunderx",
.features = featureSet(&[_]Feature{
- .crc,
- .crypto,
- .perfmon,
- .predictable_select_expensive,
- .use_postra_scheduler,
- .v8a,
+ .thunderx,
}),
};
pub const thunderx2t99 = CpuModel{
.name = "thunderx2t99",
.llvm_name = "thunderx2t99",
.features = featureSet(&[_]Feature{
- .aggressive_fma,
- .arith_bcc_fusion,
- .crc,
- .crypto,
- .lse,
- .predictable_select_expensive,
- .use_postra_scheduler,
- .v8_1a,
+ .thunderx2t99,
}),
};
pub const thunderx3t110 = CpuModel{
.name = "thunderx3t110",
.llvm_name = "thunderx3t110",
.features = featureSet(&[_]Feature{
- .aggressive_fma,
- .arith_bcc_fusion,
- .balance_fp_ops,
- .crc,
- .crypto,
- .fp_armv8,
- .lse,
- .neon,
- .pa,
- .perfmon,
- .predictable_select_expensive,
- .strict_align,
- .use_aa,
- .use_postra_scheduler,
- .v8_3a,
+ .thunderx3t110,
}),
};
pub const thunderxt81 = CpuModel{
.name = "thunderxt81",
.llvm_name = "thunderxt81",
.features = featureSet(&[_]Feature{
- .crc,
- .crypto,
- .perfmon,
- .predictable_select_expensive,
- .use_postra_scheduler,
- .v8a,
+ .thunderxt81,
}),
};
pub const thunderxt83 = CpuModel{
.name = "thunderxt83",
.llvm_name = "thunderxt83",
.features = featureSet(&[_]Feature{
- .crc,
- .crypto,
- .perfmon,
- .predictable_select_expensive,
- .use_postra_scheduler,
- .v8a,
+ .thunderxt83,
}),
};
pub const thunderxt88 = CpuModel{
.name = "thunderxt88",
.llvm_name = "thunderxt88",
.features = featureSet(&[_]Feature{
- .crc,
- .crypto,
- .perfmon,
- .predictable_select_expensive,
- .use_postra_scheduler,
- .v8a,
+ .thunderxt88,
}),
};
pub const tsv110 = CpuModel{
.name = "tsv110",
.llvm_name = "tsv110",
.features = featureSet(&[_]Feature{
- .crypto,
- .custom_cheap_as_move,
- .dotprod,
- .fp16fml,
- .fullfp16,
- .fuse_aes,
- .perfmon,
- .spe,
- .use_postra_scheduler,
- .v8_2a,
+ .tsv110,
}),
};
};
lib/std/target/amdgpu.zig
@@ -16,7 +16,6 @@ pub const Feature = enum {
atomic_fadd_insts,
auto_waitcnt_before_barrier,
ci_insts,
- code_object_v3,
cumode,
dl_insts,
dot1_insts,
@@ -54,6 +53,8 @@ pub const Feature = enum {
gfx9,
gfx9_insts,
half_rate_64_ops,
+ image_gather4_d16_bug,
+ image_store_d16_bug,
inst_fwd_prefetch_bug,
int_clamp_insts,
inv_2pi_inline_imm,
@@ -104,7 +105,9 @@ pub const Feature = enum {
sram_ecc,
trap_handler,
trig_reduced_range,
+ unaligned_access_mode,
unaligned_buffer_access,
+ unaligned_ds_access,
unaligned_scratch_access,
unpacked_d16_vmem,
unsafe_ds_offset_folding,
@@ -125,6 +128,7 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
+ @setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
@@ -170,11 +174,6 @@ pub const all_features = blk: {
.description = "Additional instructions for CI+",
.dependencies = featureSet(&[_]Feature{}),
};
- result[@enumToInt(Feature.code_object_v3)] = .{
- .llvm_name = "code-object-v3",
- .description = "Generate code object version 3",
- .dependencies = featureSet(&[_]Feature{}),
- };
result[@enumToInt(Feature.cumode)] = .{
.llvm_name = "cumode",
.description = "Enable CU wavefront execution mode",
@@ -353,6 +352,8 @@ pub const all_features = blk: {
.sdwa_omod,
.sdwa_scalar,
.sdwa_sdst,
+ .unaligned_buffer_access,
+ .unaligned_ds_access,
.vop3_literal,
.vop3p,
.vscnt,
@@ -418,6 +419,8 @@ pub const all_features = blk: {
.sdwa_omod,
.sdwa_scalar,
.sdwa_sdst,
+ .unaligned_buffer_access,
+ .unaligned_ds_access,
.vgpr_index_mode,
.vop3p,
.wavefrontsize64,
@@ -433,6 +436,16 @@ pub const all_features = blk: {
.description = "Most fp64 instructions are half rate instead of quarter",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.image_gather4_d16_bug)] = .{
+ .llvm_name = "image-gather4-d16-bug",
+ .description = "Image Gather4 D16 hardware bug",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.image_store_d16_bug)] = .{
+ .llvm_name = "image-store-d16-bug",
+ .description = "Image Store D16 hardware bug",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
result[@enumToInt(Feature.inst_fwd_prefetch_bug)] = .{
.llvm_name = "inst-fwd-prefetch-bug",
.description = "S_INST_PREFETCH instruction causes shader to hang",
@@ -455,7 +468,7 @@ pub const all_features = blk: {
};
result[@enumToInt(Feature.lds_misaligned_bug)] = .{
.llvm_name = "lds-misaligned-bug",
- .description = "Some GFX10 bug with misaligned multi-dword LDS access in WGP mode",
+ .description = "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.ldsbankcount16)] = .{
@@ -659,6 +672,7 @@ pub const all_features = blk: {
.no_sram_ecc_support,
.s_memtime_inst,
.trig_reduced_range,
+ .unaligned_buffer_access,
.wavefrontsize64,
}),
};
@@ -710,9 +724,19 @@ pub const all_features = blk: {
.description = "Requires use of fract on arguments to trig instructions",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.unaligned_access_mode)] = .{
+ .llvm_name = "unaligned-access-mode",
+ .description = "Enable unaligned global, local and region loads and stores if the hardware supports it",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
result[@enumToInt(Feature.unaligned_buffer_access)] = .{
.llvm_name = "unaligned-buffer-access",
- .description = "Support unaligned global loads and stores",
+ .description = "Hardware supports unaligned global loads and stores",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.unaligned_ds_access)] = .{
+ .llvm_name = "unaligned-ds-access",
+ .description = "Hardware supports unaligned local and region loads and stores",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.unaligned_scratch_access)] = .{
@@ -778,6 +802,7 @@ pub const all_features = blk: {
.sdwa_mav,
.sdwa_out_mods_vopc,
.trig_reduced_range,
+ .unaligned_buffer_access,
.vgpr_index_mode,
.wavefrontsize64,
}),
@@ -830,7 +855,6 @@ pub const cpu = struct {
.name = "bonaire",
.llvm_name = "bonaire",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.ldsbankcount32,
.no_xnack_support,
.sea_islands,
@@ -840,7 +864,6 @@ pub const cpu = struct {
.name = "carrizo",
.llvm_name = "carrizo",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.fast_fmaf,
.half_rate_64_ops,
.ldsbankcount32,
@@ -853,7 +876,6 @@ pub const cpu = struct {
.name = "fiji",
.llvm_name = "fiji",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.ldsbankcount32,
.no_xnack_support,
.unpacked_d16_vmem,
@@ -879,7 +901,6 @@ pub const cpu = struct {
.name = "gfx1010",
.llvm_name = "gfx1010",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.dl_insts,
.ds_src2_insts,
.flat_segment_offset_bug,
@@ -909,7 +930,6 @@ pub const cpu = struct {
.name = "gfx1011",
.llvm_name = "gfx1011",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.dl_insts,
.dot1_insts,
.dot2_insts,
@@ -921,6 +941,7 @@ pub const cpu = struct {
.gfx10,
.inst_fwd_prefetch_bug,
.lds_branch_vmem_war_hazard,
+ .lds_misaligned_bug,
.ldsbankcount32,
.mad_mac_f32_insts,
.no_xnack_support,
@@ -942,7 +963,6 @@ pub const cpu = struct {
.name = "gfx1012",
.llvm_name = "gfx1012",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.dl_insts,
.dot1_insts,
.dot2_insts,
@@ -976,7 +996,60 @@ pub const cpu = struct {
.name = "gfx1030",
.llvm_name = "gfx1030",
.features = featureSet(&[_]Feature{
- .code_object_v3,
+ .dl_insts,
+ .dot1_insts,
+ .dot2_insts,
+ .dot5_insts,
+ .dot6_insts,
+ .gfx10,
+ .gfx10_3_insts,
+ .gfx10_b_encoding,
+ .ldsbankcount32,
+ .no_xnack_support,
+ .nsa_encoding,
+ .wavefrontsize32,
+ }),
+ };
+ pub const gfx1031 = CpuModel{
+ .name = "gfx1031",
+ .llvm_name = "gfx1031",
+ .features = featureSet(&[_]Feature{
+ .dl_insts,
+ .dot1_insts,
+ .dot2_insts,
+ .dot5_insts,
+ .dot6_insts,
+ .gfx10,
+ .gfx10_3_insts,
+ .gfx10_b_encoding,
+ .ldsbankcount32,
+ .no_xnack_support,
+ .nsa_encoding,
+ .wavefrontsize32,
+ }),
+ };
+ pub const gfx1032 = CpuModel{
+ .name = "gfx1032",
+ .llvm_name = "gfx1032",
+ .features = featureSet(&[_]Feature{
+ .dl_insts,
+ .dot1_insts,
+ .dot2_insts,
+ .dot5_insts,
+ .dot6_insts,
+ .gfx10,
+ .gfx10_3_insts,
+ .gfx10_b_encoding,
+ .ldsbankcount32,
+ .no_xnack_support,
+ .nsa_encoding,
+ .wavefrontsize32,
+ }),
+ };
+ pub const gfx1033 = CpuModel{
+ .name = "gfx1033",
+ .llvm_name = "gfx1033",
+ .features = featureSet(&[_]Feature{
.dl_insts,
.dot1_insts,
.dot2_insts,
@@ -995,7 +1068,6 @@ pub const cpu = struct {
.name = "gfx600",
.llvm_name = "gfx600",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.fast_fmaf,
.half_rate_64_ops,
.ldsbankcount32,
@@ -1007,7 +1079,15 @@ pub const cpu = struct {
.name = "gfx601",
.llvm_name = "gfx601",
.features = featureSet(&[_]Feature{
- .code_object_v3,
+ .ldsbankcount32,
+ .no_xnack_support,
+ .southern_islands,
+ }),
+ };
+ pub const gfx602 = CpuModel{
+ .name = "gfx602",
+ .llvm_name = "gfx602",
+ .features = featureSet(&[_]Feature{
.ldsbankcount32,
.no_xnack_support,
.southern_islands,
@@ -1017,7 +1097,6 @@ pub const cpu = struct {
.name = "gfx700",
.llvm_name = "gfx700",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.ldsbankcount32,
.no_xnack_support,
.sea_islands,
@@ -1027,7 +1106,6 @@ pub const cpu = struct {
.name = "gfx701",
.llvm_name = "gfx701",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.fast_fmaf,
.half_rate_64_ops,
.ldsbankcount32,
@@ -1039,7 +1117,6 @@ pub const cpu = struct {
.name = "gfx702",
.llvm_name = "gfx702",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.fast_fmaf,
.ldsbankcount16,
.no_xnack_support,
@@ -1050,7 +1127,6 @@ pub const cpu = struct {
.name = "gfx703",
.llvm_name = "gfx703",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.ldsbankcount16,
.no_xnack_support,
.sea_islands,
@@ -1060,17 +1136,24 @@ pub const cpu = struct {
.name = "gfx704",
.llvm_name = "gfx704",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.ldsbankcount32,
.no_xnack_support,
.sea_islands,
}),
};
+ pub const gfx705 = CpuModel{
+ .name = "gfx705",
+ .llvm_name = "gfx705",
+ .features = featureSet(&[_]Feature{
+ .ldsbankcount16,
+ .no_xnack_support,
+ .sea_islands,
+ }),
+ };
pub const gfx801 = CpuModel{
.name = "gfx801",
.llvm_name = "gfx801",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.fast_fmaf,
.half_rate_64_ops,
.ldsbankcount32,
@@ -1083,7 +1166,6 @@ pub const cpu = struct {
.name = "gfx802",
.llvm_name = "gfx802",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.ldsbankcount32,
.no_xnack_support,
.sgpr_init_bug,
@@ -1095,18 +1177,29 @@ pub const cpu = struct {
.name = "gfx803",
.llvm_name = "gfx803",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.ldsbankcount32,
.no_xnack_support,
.unpacked_d16_vmem,
.volcanic_islands,
}),
};
+ pub const gfx805 = CpuModel{
+ .name = "gfx805",
+ .llvm_name = "gfx805",
+ .features = featureSet(&[_]Feature{
+ .ldsbankcount32,
+ .no_xnack_support,
+ .sgpr_init_bug,
+ .unpacked_d16_vmem,
+ .volcanic_islands,
+ }),
+ };
pub const gfx810 = CpuModel{
.name = "gfx810",
.llvm_name = "gfx810",
.features = featureSet(&[_]Feature{
- .code_object_v3,
+ .image_gather4_d16_bug,
+ .image_store_d16_bug,
.ldsbankcount16,
.volcanic_islands,
.xnack,
@@ -1116,8 +1209,8 @@ pub const cpu = struct {
.name = "gfx900",
.llvm_name = "gfx900",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.gfx9,
+ .image_gather4_d16_bug,
.ldsbankcount32,
.mad_mix_insts,
.no_sram_ecc_support,
@@ -1128,8 +1221,8 @@ pub const cpu = struct {
.name = "gfx902",
.llvm_name = "gfx902",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.gfx9,
+ .image_gather4_d16_bug,
.ldsbankcount32,
.mad_mix_insts,
.no_sram_ecc_support,
@@ -1140,9 +1233,9 @@ pub const cpu = struct {
.name = "gfx904",
.llvm_name = "gfx904",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.fma_mix_insts,
.gfx9,
+ .image_gather4_d16_bug,
.ldsbankcount32,
.no_sram_ecc_support,
.no_xnack_support,
@@ -1152,13 +1245,13 @@ pub const cpu = struct {
.name = "gfx906",
.llvm_name = "gfx906",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.dl_insts,
.dot1_insts,
.dot2_insts,
.fma_mix_insts,
.gfx9,
.half_rate_64_ops,
+ .image_gather4_d16_bug,
.ldsbankcount32,
.no_xnack_support,
}),
@@ -1168,7 +1261,6 @@ pub const cpu = struct {
.llvm_name = "gfx908",
.features = featureSet(&[_]Feature{
.atomic_fadd_insts,
- .code_object_v3,
.dl_insts,
.dot1_insts,
.dot2_insts,
@@ -1179,6 +1271,7 @@ pub const cpu = struct {
.fma_mix_insts,
.gfx9,
.half_rate_64_ops,
+ .image_gather4_d16_bug,
.ldsbankcount32,
.mai_insts,
.mfma_inline_literal_bug,
@@ -1190,8 +1283,19 @@ pub const cpu = struct {
.name = "gfx909",
.llvm_name = "gfx909",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.gfx9,
+ .image_gather4_d16_bug,
+ .ldsbankcount32,
+ .mad_mix_insts,
+ .xnack,
+ }),
+ };
+ pub const gfx90c = CpuModel{
+ .name = "gfx90c",
+ .llvm_name = "gfx90c",
+ .features = featureSet(&[_]Feature{
+ .gfx9,
+ .image_gather4_d16_bug,
.ldsbankcount32,
.mad_mix_insts,
.xnack,
@@ -1201,7 +1305,6 @@ pub const cpu = struct {
.name = "hainan",
.llvm_name = "hainan",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.ldsbankcount32,
.no_xnack_support,
.southern_islands,
@@ -1211,7 +1314,6 @@ pub const cpu = struct {
.name = "hawaii",
.llvm_name = "hawaii",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.fast_fmaf,
.half_rate_64_ops,
.ldsbankcount32,
@@ -1223,7 +1325,6 @@ pub const cpu = struct {
.name = "iceland",
.llvm_name = "iceland",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.ldsbankcount32,
.no_xnack_support,
.sgpr_init_bug,
@@ -1235,7 +1336,6 @@ pub const cpu = struct {
.name = "kabini",
.llvm_name = "kabini",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.ldsbankcount16,
.no_xnack_support,
.sea_islands,
@@ -1245,7 +1345,6 @@ pub const cpu = struct {
.name = "kaveri",
.llvm_name = "kaveri",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.ldsbankcount32,
.no_xnack_support,
.sea_islands,
@@ -1255,7 +1354,6 @@ pub const cpu = struct {
.name = "mullins",
.llvm_name = "mullins",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.ldsbankcount16,
.no_xnack_support,
.sea_islands,
@@ -1265,7 +1363,6 @@ pub const cpu = struct {
.name = "oland",
.llvm_name = "oland",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.ldsbankcount32,
.no_xnack_support,
.southern_islands,
@@ -1275,7 +1372,6 @@ pub const cpu = struct {
.name = "pitcairn",
.llvm_name = "pitcairn",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.ldsbankcount32,
.no_xnack_support,
.southern_islands,
@@ -1285,7 +1381,6 @@ pub const cpu = struct {
.name = "polaris10",
.llvm_name = "polaris10",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.ldsbankcount32,
.no_xnack_support,
.unpacked_d16_vmem,
@@ -1296,7 +1391,6 @@ pub const cpu = struct {
.name = "polaris11",
.llvm_name = "polaris11",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.ldsbankcount32,
.no_xnack_support,
.unpacked_d16_vmem,
@@ -1307,7 +1401,8 @@ pub const cpu = struct {
.name = "stoney",
.llvm_name = "stoney",
.features = featureSet(&[_]Feature{
- .code_object_v3,
+ .image_gather4_d16_bug,
+ .image_store_d16_bug,
.ldsbankcount16,
.volcanic_islands,
.xnack,
@@ -1317,7 +1412,6 @@ pub const cpu = struct {
.name = "tahiti",
.llvm_name = "tahiti",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.fast_fmaf,
.half_rate_64_ops,
.ldsbankcount32,
@@ -1329,7 +1423,17 @@ pub const cpu = struct {
.name = "tonga",
.llvm_name = "tonga",
.features = featureSet(&[_]Feature{
- .code_object_v3,
+ .ldsbankcount32,
+ .no_xnack_support,
+ .sgpr_init_bug,
+ .unpacked_d16_vmem,
+ .volcanic_islands,
+ }),
+ };
+ pub const tongapro = CpuModel{
+ .name = "tongapro",
+ .llvm_name = "tongapro",
+ .features = featureSet(&[_]Feature{
.ldsbankcount32,
.no_xnack_support,
.sgpr_init_bug,
@@ -1341,7 +1445,6 @@ pub const cpu = struct {
.name = "verde",
.llvm_name = "verde",
.features = featureSet(&[_]Feature{
- .code_object_v3,
.ldsbankcount32,
.no_xnack_support,
.southern_islands,
lib/std/target/arm.zig
@@ -10,10 +10,60 @@ const CpuModel = std.Target.Cpu.Model;
pub const Feature = enum {
@"32bit",
@"8msecext",
+ a12,
+ a15,
+ a17,
+ a32,
+ a35,
+ a5,
+ a53,
+ a55,
+ a57,
+ a7,
+ a72,
+ a73,
+ a75,
a76,
+ a77,
+ a8,
+ a9,
aclass,
acquire_release,
aes,
+ armv2,
+ armv2a,
+ armv3,
+ armv3m,
+ armv4,
+ armv4t,
+ armv5t,
+ armv5te,
+ armv5tej,
+ armv6,
+ armv6_m,
+ armv6j,
+ armv6k,
+ armv6kz,
+ armv6s_m,
+ armv6t2,
+ armv7_a,
+ armv7_m,
+ armv7_r,
+ armv7e_m,
+ armv7k,
+ armv7s,
+ armv7ve,
+ armv8_a,
+ armv8_m_base,
+ armv8_m_main,
+ armv8_r,
+ armv8_1_a,
+ armv8_1_m_main,
+ armv8_2_a,
+ armv8_3_a,
+ armv8_4_a,
+ armv8_5_a,
+ armv8_6_a,
avoid_movs_shop,
avoid_partial_cpsr,
bf16,
@@ -27,6 +77,8 @@ pub const Feature = enum {
cdecp6,
cdecp7,
cheap_predicable_cpsr,
+ cortex_a78,
+ cortex_x1,
crc,
crypto,
d32,
@@ -39,13 +91,13 @@ pub const Feature = enum {
execute_only,
expand_fp_mlx,
exynos,
- fp16,
- fp16fml,
- fp64,
fp_armv8,
fp_armv8d16,
fp_armv8d16sp,
fp_armv8sp,
+ fp16,
+ fp16fml,
+ fp64,
fpao,
fpregs,
fpregs16,
@@ -53,30 +105,13 @@ pub const Feature = enum {
fullfp16,
fuse_aes,
fuse_literals,
- has_v4t,
- has_v5t,
- has_v5te,
- has_v6,
- has_v6k,
- has_v6m,
- has_v6t2,
- has_v7,
- has_v7clrex,
- has_v8_1a,
- has_v8_1m_main,
- has_v8_2a,
- has_v8_3a,
- has_v8_4a,
- has_v8_5a,
- has_v8_6a,
- has_v8,
- has_v8m,
- has_v8m_main,
hwdiv,
hwdiv_arm,
- i8mm,
+ _i8mm,
iwmmxt,
iwmmxt2,
+ krait,
+ kryo,
lob,
long_calls,
loop_align,
@@ -93,6 +128,7 @@ pub const Feature = enum {
neon,
neon_fpmovs,
neonfp,
+ neoverse_v1,
no_branch_predictor,
no_movt,
no_neg_immediates,
@@ -103,6 +139,9 @@ pub const Feature = enum {
prefer_vmovsr,
prof_unpr,
r4,
+ r5,
+ r52,
+ r7,
ras,
rclass,
read_tp_hard,
@@ -121,37 +160,20 @@ pub const Feature = enum {
splat_vfp_neon,
strict_align,
swift,
- thumb2,
thumb_mode,
+ thumb2,
trustzone,
use_misched,
- v2,
- v2a,
- v3,
- v3m,
- v4,
v4t,
v5t,
v5te,
- v5tej,
v6,
- v6j,
v6k,
- v6kz,
v6m,
- v6sm,
v6t2,
- v7a,
- v7em,
- v7k,
- v7m,
- v7r,
- v7s,
- v7ve,
- v8a,
- v8m,
- v8m_main,
- v8r,
+ v7,
+ v7clrex,
+ v8,
v8_1a,
v8_1m_main,
v8_2a,
@@ -159,6 +181,8 @@ pub const Feature = enum {
v8_4a,
v8_5a,
v8_6a,
+ v8m,
+ v8m_main,
vfp2,
vfp2sp,
vfp3,
@@ -195,11 +219,91 @@ pub const all_features = blk: {
.description = "Enable support for ARMv8-M Security Extensions",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.a12)] = .{
+ .llvm_name = "a12",
+ .description = "Cortex-A12 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.a15)] = .{
+ .llvm_name = "a15",
+ .description = "Cortex-A15 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.a17)] = .{
+ .llvm_name = "a17",
+ .description = "Cortex-A17 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.a32)] = .{
+ .llvm_name = "a32",
+ .description = "Cortex-A32 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.a35)] = .{
+ .llvm_name = "a35",
+ .description = "Cortex-A35 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.a5)] = .{
+ .llvm_name = "a5",
+ .description = "Cortex-A5 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.a53)] = .{
+ .llvm_name = "a53",
+ .description = "Cortex-A53 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.a55)] = .{
+ .llvm_name = "a55",
+ .description = "Cortex-A55 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.a57)] = .{
+ .llvm_name = "a57",
+ .description = "Cortex-A57 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.a7)] = .{
+ .llvm_name = "a7",
+ .description = "Cortex-A7 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.a72)] = .{
+ .llvm_name = "a72",
+ .description = "Cortex-A72 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.a73)] = .{
+ .llvm_name = "a73",
+ .description = "Cortex-A73 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.a75)] = .{
+ .llvm_name = "a75",
+ .description = "Cortex-A75 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
result[@enumToInt(Feature.a76)] = .{
.llvm_name = "a76",
.description = "Cortex-A76 ARM processors",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.a77)] = .{
+ .llvm_name = "a77",
+ .description = "Cortex-A77 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.a8)] = .{
+ .llvm_name = "a8",
+ .description = "Cortex-A8 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.a9)] = .{
+ .llvm_name = "a9",
+ .description = "Cortex-A9 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
result[@enumToInt(Feature.aclass)] = .{
.llvm_name = "aclass",
.description = "Is application profile ('A' series)",
@@ -217,6 +321,387 @@ pub const all_features = blk: {
.neon,
}),
};
+ result[@enumToInt(Feature.armv2)] = .{
+ .llvm_name = "armv2",
+ .description = "ARMv2 architecture",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.armv2a)] = .{
+ .llvm_name = "armv2a",
+ .description = "ARMv2a architecture",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.armv3)] = .{
+ .llvm_name = "armv3",
+ .description = "ARMv3 architecture",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.armv3m)] = .{
+ .llvm_name = "armv3m",
+ .description = "ARMv3m architecture",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.armv4)] = .{
+ .llvm_name = "armv4",
+ .description = "ARMv4 architecture",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.armv4t)] = .{
+ .llvm_name = "armv4t",
+ .description = "ARMv4t architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .v4t,
+ }),
+ };
+ result[@enumToInt(Feature.armv5t)] = .{
+ .llvm_name = "armv5t",
+ .description = "ARMv5t architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .v5t,
+ }),
+ };
+ result[@enumToInt(Feature.armv5te)] = .{
+ .llvm_name = "armv5te",
+ .description = "ARMv5te architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .v5te,
+ }),
+ };
+ result[@enumToInt(Feature.armv5tej)] = .{
+ .llvm_name = "armv5tej",
+ .description = "ARMv5tej architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .v5te,
+ }),
+ };
+ result[@enumToInt(Feature.armv6)] = .{
+ .llvm_name = "armv6",
+ .description = "ARMv6 architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .dsp,
+ .v6,
+ }),
+ };
+ result[@enumToInt(Feature.armv6_m)] = .{
+ .llvm_name = "armv6-m",
+ .description = "ARMv6m architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .db,
+ .mclass,
+ .noarm,
+ .strict_align,
+ .thumb_mode,
+ .v6m,
+ }),
+ };
+ result[@enumToInt(Feature.armv6j)] = .{
+ .llvm_name = "armv6j",
+ .description = "ARMv7a architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .armv6,
+ }),
+ };
+ result[@enumToInt(Feature.armv6k)] = .{
+ .llvm_name = "armv6k",
+ .description = "ARMv6k architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .v6k,
+ }),
+ };
+ result[@enumToInt(Feature.armv6kz)] = .{
+ .llvm_name = "armv6kz",
+ .description = "ARMv6kz architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .trustzone,
+ .v6k,
+ }),
+ };
+ result[@enumToInt(Feature.armv6s_m)] = .{
+ .llvm_name = "armv6s-m",
+ .description = "ARMv6sm architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .db,
+ .mclass,
+ .noarm,
+ .strict_align,
+ .thumb_mode,
+ .v6m,
+ }),
+ };
+ result[@enumToInt(Feature.armv6t2)] = .{
+ .llvm_name = "armv6t2",
+ .description = "ARMv6t2 architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .dsp,
+ .v6t2,
+ }),
+ };
+ result[@enumToInt(Feature.armv7_a)] = .{
+ .llvm_name = "armv7-a",
+ .description = "ARMv7a architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .aclass,
+ .db,
+ .dsp,
+ .neon,
+ .v7,
+ }),
+ };
+ result[@enumToInt(Feature.armv7_m)] = .{
+ .llvm_name = "armv7-m",
+ .description = "ARMv7m architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .db,
+ .hwdiv,
+ .mclass,
+ .noarm,
+ .thumb_mode,
+ .thumb2,
+ .v7,
+ }),
+ };
+ result[@enumToInt(Feature.armv7_r)] = .{
+ .llvm_name = "armv7-r",
+ .description = "ARMv7r architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .db,
+ .dsp,
+ .hwdiv,
+ .rclass,
+ .v7,
+ }),
+ };
+ result[@enumToInt(Feature.armv7e_m)] = .{
+ .llvm_name = "armv7e-m",
+ .description = "ARMv7em architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .db,
+ .dsp,
+ .hwdiv,
+ .mclass,
+ .noarm,
+ .thumb_mode,
+ .thumb2,
+ .v7,
+ }),
+ };
+ result[@enumToInt(Feature.armv7k)] = .{
+ .llvm_name = "armv7k",
+ .description = "ARMv7a architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .armv7_a,
+ }),
+ };
+ result[@enumToInt(Feature.armv7s)] = .{
+ .llvm_name = "armv7s",
+ .description = "ARMv7a architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .armv7_a,
+ }),
+ };
+ result[@enumToInt(Feature.armv7ve)] = .{
+ .llvm_name = "armv7ve",
+ .description = "ARMv7ve architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .aclass,
+ .db,
+ .dsp,
+ .mp,
+ .neon,
+ .trustzone,
+ .v7,
+ .virtualization,
+ }),
+ };
+ result[@enumToInt(Feature.armv8_a)] = .{
+ .llvm_name = "armv8-a",
+ .description = "ARMv8a architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .aclass,
+ .crc,
+ .crypto,
+ .db,
+ .dsp,
+ .fp_armv8,
+ .mp,
+ .neon,
+ .trustzone,
+ .v8,
+ .virtualization,
+ }),
+ };
+ result[@enumToInt(Feature.armv8_m_base)] = .{
+ .llvm_name = "armv8-m.base",
+ .description = "ARMv8mBaseline architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .@"8msecext",
+ .acquire_release,
+ .db,
+ .hwdiv,
+ .mclass,
+ .noarm,
+ .strict_align,
+ .thumb_mode,
+ .v7clrex,
+ .v8m,
+ }),
+ };
+ result[@enumToInt(Feature.armv8_m_main)] = .{
+ .llvm_name = "armv8-m.main",
+ .description = "ARMv8mMainline architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .@"8msecext",
+ .acquire_release,
+ .db,
+ .hwdiv,
+ .mclass,
+ .noarm,
+ .thumb_mode,
+ .v8m_main,
+ }),
+ };
+ result[@enumToInt(Feature.armv8_r)] = .{
+ .llvm_name = "armv8-r",
+ .description = "ARMv8r architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .crc,
+ .db,
+ .dfb,
+ .dsp,
+ .fp_armv8,
+ .mp,
+ .neon,
+ .rclass,
+ .v8,
+ .virtualization,
+ }),
+ };
+ result[@enumToInt(Feature.armv8_1_a)] = .{
+ .llvm_name = "armv8.1-a",
+ .description = "ARMv81a architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .aclass,
+ .crc,
+ .crypto,
+ .db,
+ .dsp,
+ .fp_armv8,
+ .mp,
+ .neon,
+ .trustzone,
+ .v8_1a,
+ .virtualization,
+ }),
+ };
+ result[@enumToInt(Feature.armv8_1_m_main)] = .{
+ .llvm_name = "armv8.1-m.main",
+ .description = "ARMv81mMainline architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .@"8msecext",
+ .acquire_release,
+ .db,
+ .hwdiv,
+ .lob,
+ .mclass,
+ .noarm,
+ .ras,
+ .thumb_mode,
+ .v8_1m_main,
+ }),
+ };
+ result[@enumToInt(Feature.armv8_2_a)] = .{
+ .llvm_name = "armv8.2-a",
+ .description = "ARMv82a architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .aclass,
+ .crc,
+ .crypto,
+ .db,
+ .dsp,
+ .fp_armv8,
+ .mp,
+ .neon,
+ .ras,
+ .trustzone,
+ .v8_2a,
+ .virtualization,
+ }),
+ };
+ result[@enumToInt(Feature.armv8_3_a)] = .{
+ .llvm_name = "armv8.3-a",
+ .description = "ARMv83a architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .aclass,
+ .crc,
+ .crypto,
+ .db,
+ .dsp,
+ .fp_armv8,
+ .mp,
+ .neon,
+ .ras,
+ .trustzone,
+ .v8_3a,
+ .virtualization,
+ }),
+ };
+ result[@enumToInt(Feature.armv8_4_a)] = .{
+ .llvm_name = "armv8.4-a",
+ .description = "ARMv84a architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .aclass,
+ .crc,
+ .crypto,
+ .db,
+ .dotprod,
+ .dsp,
+ .fp_armv8,
+ .mp,
+ .neon,
+ .ras,
+ .trustzone,
+ .v8_4a,
+ .virtualization,
+ }),
+ };
+ result[@enumToInt(Feature.armv8_5_a)] = .{
+ .llvm_name = "armv8.5-a",
+ .description = "ARMv85a architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .aclass,
+ .crc,
+ .crypto,
+ .db,
+ .dotprod,
+ .dsp,
+ .fp_armv8,
+ .mp,
+ .neon,
+ .ras,
+ .trustzone,
+ .v8_5a,
+ .virtualization,
+ }),
+ };
+ result[@enumToInt(Feature.armv8_6_a)] = .{
+ .llvm_name = "armv8.6-a",
+ .description = "ARMv86a architecture",
+ .dependencies = featureSet(&[_]Feature{
+ .aclass,
+ .crc,
+ .crypto,
+ .db,
+ .dotprod,
+ .dsp,
+ .fp_armv8,
+ .mp,
+ .neon,
+ .ras,
+ .trustzone,
+ .v8_6a,
+ .virtualization,
+ }),
+ };
result[@enumToInt(Feature.avoid_movs_shop)] = .{
.llvm_name = "avoid-movs-shop",
.description = "Avoid movs instructions with shifter operand",
@@ -302,6 +787,16 @@ pub const all_features = blk: {
.description = "Disable +1 predication cost for instructions updating CPSR",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.cortex_a78)] = .{
+ .llvm_name = "cortex-a78",
+ .description = "Cortex-A78 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.cortex_x1)] = .{
+ .llvm_name = "cortex-x1",
+ .description = "Cortex-X1 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
result[@enumToInt(Feature.crc)] = .{
.llvm_name = "crc",
.description = "Enable support for CRC instructions",
@@ -386,25 +881,6 @@ pub const all_features = blk: {
.zcz,
}),
};
- result[@enumToInt(Feature.fp16)] = .{
- .llvm_name = "fp16",
- .description = "Enable half-precision floating point",
- .dependencies = featureSet(&[_]Feature{}),
- };
- result[@enumToInt(Feature.fp16fml)] = .{
- .llvm_name = "fp16fml",
- .description = "Enable full half-precision floating point fml instructions",
- .dependencies = featureSet(&[_]Feature{
- .fullfp16,
- }),
- };
- result[@enumToInt(Feature.fp64)] = .{
- .llvm_name = "fp64",
- .description = "Floating point unit supports double precision",
- .dependencies = featureSet(&[_]Feature{
- .fpregs64,
- }),
- };
result[@enumToInt(Feature.fp_armv8)] = .{
.llvm_name = "fp-armv8",
.description = "Enable ARMv8 FP",
@@ -439,186 +915,67 @@ pub const all_features = blk: {
.vfp4sp,
}),
};
- result[@enumToInt(Feature.fpao)] = .{
- .llvm_name = "fpao",
- .description = "Enable fast computation of positive address offsets",
- .dependencies = featureSet(&[_]Feature{}),
- };
- result[@enumToInt(Feature.fpregs)] = .{
- .llvm_name = "fpregs",
- .description = "Enable FP registers",
- .dependencies = featureSet(&[_]Feature{}),
- };
- result[@enumToInt(Feature.fpregs16)] = .{
- .llvm_name = "fpregs16",
- .description = "Enable 16-bit FP registers",
- .dependencies = featureSet(&[_]Feature{
- .fpregs,
- }),
- };
- result[@enumToInt(Feature.fpregs64)] = .{
- .llvm_name = "fpregs64",
- .description = "Enable 64-bit FP registers",
- .dependencies = featureSet(&[_]Feature{
- .fpregs,
- }),
- };
- result[@enumToInt(Feature.fullfp16)] = .{
- .llvm_name = "fullfp16",
- .description = "Enable full half-precision floating point",
- .dependencies = featureSet(&[_]Feature{
- .fp_armv8d16sp,
- .fpregs16,
- }),
- };
- result[@enumToInt(Feature.fuse_aes)] = .{
- .llvm_name = "fuse-aes",
- .description = "CPU fuses AES crypto operations",
- .dependencies = featureSet(&[_]Feature{}),
- };
- result[@enumToInt(Feature.fuse_literals)] = .{
- .llvm_name = "fuse-literals",
- .description = "CPU fuses literal generation operations",
- .dependencies = featureSet(&[_]Feature{}),
- };
- result[@enumToInt(Feature.has_v4t)] = .{
- .llvm_name = "v4t",
- .description = "Support ARM v4T instructions",
- .dependencies = featureSet(&[_]Feature{}),
- };
- result[@enumToInt(Feature.has_v5t)] = .{
- .llvm_name = "v5t",
- .description = "Support ARM v5T instructions",
- .dependencies = featureSet(&[_]Feature{
- .has_v4t,
- }),
- };
- result[@enumToInt(Feature.has_v5te)] = .{
- .llvm_name = "v5te",
- .description = "Support ARM v5TE, v5TEj, and v5TExp instructions",
- .dependencies = featureSet(&[_]Feature{
- .has_v5t,
- }),
- };
- result[@enumToInt(Feature.has_v6)] = .{
- .llvm_name = "v6",
- .description = "Support ARM v6 instructions",
- .dependencies = featureSet(&[_]Feature{
- .has_v5te,
- }),
- };
- result[@enumToInt(Feature.has_v6k)] = .{
- .llvm_name = "v6k",
- .description = "Support ARM v6k instructions",
- .dependencies = featureSet(&[_]Feature{
- .has_v6,
- }),
- };
- result[@enumToInt(Feature.has_v6m)] = .{
- .llvm_name = "v6m",
- .description = "Support ARM v6M instructions",
- .dependencies = featureSet(&[_]Feature{
- .has_v6,
- }),
- };
- result[@enumToInt(Feature.has_v6t2)] = .{
- .llvm_name = "v6t2",
- .description = "Support ARM v6t2 instructions",
- .dependencies = featureSet(&[_]Feature{
- .thumb2,
- .has_v6k,
- .has_v8m,
- }),
- };
- result[@enumToInt(Feature.has_v7)] = .{
- .llvm_name = "v7",
- .description = "Support ARM v7 instructions",
- .dependencies = featureSet(&[_]Feature{
- .perfmon,
- .has_v6t2,
- .has_v7clrex,
- }),
- };
- result[@enumToInt(Feature.has_v7clrex)] = .{
- .llvm_name = "v7clrex",
- .description = "Has v7 clrex instruction",
+ result[@enumToInt(Feature.fp16)] = .{
+ .llvm_name = "fp16",
+ .description = "Enable half-precision floating point",
.dependencies = featureSet(&[_]Feature{}),
};
- result[@enumToInt(Feature.has_v8)] = .{
- .llvm_name = "v8",
- .description = "Support ARM v8 instructions",
- .dependencies = featureSet(&[_]Feature{
- .acquire_release,
- .has_v7,
- }),
- };
- result[@enumToInt(Feature.has_v8_1a)] = .{
- .llvm_name = "v8.1a",
- .description = "Support ARM v8.1a instructions",
- .dependencies = featureSet(&[_]Feature{
- .has_v8,
- }),
- };
- result[@enumToInt(Feature.has_v8_1m_main)] = .{
- .llvm_name = "v8.1m.main",
- .description = "Support ARM v8-1M Mainline instructions",
- .dependencies = featureSet(&[_]Feature{
- .has_v8m_main,
- }),
- };
- result[@enumToInt(Feature.has_v8_2a)] = .{
- .llvm_name = "v8.2a",
- .description = "Support ARM v8.2a instructions",
+ result[@enumToInt(Feature.fp16fml)] = .{
+ .llvm_name = "fp16fml",
+ .description = "Enable full half-precision floating point fml instructions",
.dependencies = featureSet(&[_]Feature{
- .has_v8_1a,
+ .fullfp16,
}),
};
- result[@enumToInt(Feature.has_v8_3a)] = .{
- .llvm_name = "v8.3a",
- .description = "Support ARM v8.3a instructions",
+ result[@enumToInt(Feature.fp64)] = .{
+ .llvm_name = "fp64",
+ .description = "Floating point unit supports double precision",
.dependencies = featureSet(&[_]Feature{
- .has_v8_2a,
+ .fpregs64,
}),
};
- result[@enumToInt(Feature.has_v8_4a)] = .{
- .llvm_name = "v8.4a",
- .description = "Support ARM v8.4a instructions",
- .dependencies = featureSet(&[_]Feature{
- .dotprod,
- .has_v8_3a,
- }),
+ result[@enumToInt(Feature.fpao)] = .{
+ .llvm_name = "fpao",
+ .description = "Enable fast computation of positive address offsets",
+ .dependencies = featureSet(&[_]Feature{}),
};
- result[@enumToInt(Feature.has_v8_5a)] = .{
- .llvm_name = "v8.5a",
- .description = "Support ARM v8.5a instructions",
- .dependencies = featureSet(&[_]Feature{
- .sb,
- .has_v8_4a,
- }),
+ result[@enumToInt(Feature.fpregs)] = .{
+ .llvm_name = "fpregs",
+ .description = "Enable FP registers",
+ .dependencies = featureSet(&[_]Feature{}),
};
- result[@enumToInt(Feature.has_v8_6a)] = .{
- .llvm_name = "v8.6a",
- .description = "Support ARM v8.6a instructions",
+ result[@enumToInt(Feature.fpregs16)] = .{
+ .llvm_name = "fpregs16",
+ .description = "Enable 16-bit FP registers",
.dependencies = featureSet(&[_]Feature{
- .bf16,
- .i8mm,
- .has_v8_5a,
+ .fpregs,
}),
};
- result[@enumToInt(Feature.has_v8m)] = .{
- .llvm_name = "v8m",
- .description = "Support ARM v8M Baseline instructions",
+ result[@enumToInt(Feature.fpregs64)] = .{
+ .llvm_name = "fpregs64",
+ .description = "Enable 64-bit FP registers",
.dependencies = featureSet(&[_]Feature{
- .has_v6m,
+ .fpregs,
}),
};
- result[@enumToInt(Feature.has_v8m_main)] = .{
- .llvm_name = "v8m.main",
- .description = "Support ARM v8M Mainline instructions",
+ result[@enumToInt(Feature.fullfp16)] = .{
+ .llvm_name = "fullfp16",
+ .description = "Enable full half-precision floating point",
.dependencies = featureSet(&[_]Feature{
- .has_v7,
+ .fp_armv8d16sp,
+ .fpregs16,
}),
};
+ result[@enumToInt(Feature.fuse_aes)] = .{
+ .llvm_name = "fuse-aes",
+ .description = "CPU fuses AES crypto operations",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.fuse_literals)] = .{
+ .llvm_name = "fuse-literals",
+ .description = "CPU fuses literal generation operations",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
result[@enumToInt(Feature.hwdiv)] = .{
.llvm_name = "hwdiv",
.description = "Enable divide instructions in Thumb",
@@ -629,7 +986,7 @@ pub const all_features = blk: {
.description = "Enable divide instructions in ARM mode",
.dependencies = featureSet(&[_]Feature{}),
};
- result[@enumToInt(Feature.i8mm)] = .{
+ result[@enumToInt(Feature._i8mm)] = .{
.llvm_name = "i8mm",
.description = "Enable Matrix Multiply Int8 Extension",
.dependencies = featureSet(&[_]Feature{
@@ -640,16 +997,26 @@ pub const all_features = blk: {
.llvm_name = "iwmmxt",
.description = "ARMv5te architecture",
.dependencies = featureSet(&[_]Feature{
- .has_v5te,
+ .armv5te,
}),
};
result[@enumToInt(Feature.iwmmxt2)] = .{
.llvm_name = "iwmmxt2",
.description = "ARMv5te architecture",
.dependencies = featureSet(&[_]Feature{
- .has_v5te,
+ .armv5te,
}),
};
+ result[@enumToInt(Feature.krait)] = .{
+ .llvm_name = "krait",
+ .description = "Qualcomm Krait processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.kryo)] = .{
+ .llvm_name = "kryo",
+ .description = "Qualcomm Kryo processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
result[@enumToInt(Feature.lob)] = .{
.llvm_name = "lob",
.description = "Enable Low Overhead Branch extensions",
@@ -692,7 +1059,7 @@ pub const all_features = blk: {
.dsp,
.fpregs16,
.fpregs64,
- .has_v8_1m_main,
+ .v8_1m_main,
}),
};
result[@enumToInt(Feature.mve_fp)] = .{
@@ -741,6 +1108,11 @@ pub const all_features = blk: {
.description = "Use NEON for single precision FP",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.neoverse_v1)] = .{
+ .llvm_name = "neoverse-v1",
+ .description = "Neoverse-V1 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
result[@enumToInt(Feature.no_branch_predictor)] = .{
.llvm_name = "no-branch-predictor",
.description = "Has no branch predictor",
@@ -791,6 +1163,21 @@ pub const all_features = blk: {
.description = "Cortex-R4 ARM processors",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.r5)] = .{
+ .llvm_name = "r5",
+ .description = "Cortex-R5 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.r52)] = .{
+ .llvm_name = "r52",
+ .description = "Cortex-R52 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.r7)] = .{
+ .llvm_name = "r7",
+ .description = "Cortex-R7 ARM processors",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
result[@enumToInt(Feature.ras)] = .{
.llvm_name = "ras",
.description = "Enable Reliability, Availability and Serviceability extensions",
@@ -885,16 +1272,16 @@ pub const all_features = blk: {
.description = "Swift ARM processors",
.dependencies = featureSet(&[_]Feature{}),
};
- result[@enumToInt(Feature.thumb2)] = .{
- .llvm_name = "thumb2",
- .description = "Enable Thumb2 instructions",
- .dependencies = featureSet(&[_]Feature{}),
- };
result[@enumToInt(Feature.thumb_mode)] = .{
.llvm_name = "thumb-mode",
.description = "Thumb mode",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.thumb2)] = .{
+ .llvm_name = "thumb2",
+ .description = "Enable Thumb2 instructions",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
result[@enumToInt(Feature.trustzone)] = .{
.llvm_name = "trustzone",
.description = "Enable support for TrustZone security extensions",
@@ -905,399 +1292,142 @@ pub const all_features = blk: {
.description = "Use the MachineScheduler",
.dependencies = featureSet(&[_]Feature{}),
};
- result[@enumToInt(Feature.v2)] = .{
- .llvm_name = "armv2",
- .description = "ARMv2 architecture",
- .dependencies = featureSet(&[_]Feature{
- .strict_align,
- }),
- };
- result[@enumToInt(Feature.v2a)] = .{
- .llvm_name = "armv2a",
- .description = "ARMv2a architecture",
- .dependencies = featureSet(&[_]Feature{
- .strict_align,
- }),
- };
- result[@enumToInt(Feature.v3)] = .{
- .llvm_name = "armv3",
- .description = "ARMv3 architecture",
- .dependencies = featureSet(&[_]Feature{
- .strict_align,
- }),
- };
- result[@enumToInt(Feature.v3m)] = .{
- .llvm_name = "armv3m",
- .description = "ARMv3m architecture",
- .dependencies = featureSet(&[_]Feature{
- .strict_align,
- }),
- };
- result[@enumToInt(Feature.v4)] = .{
- .llvm_name = "armv4",
- .description = "ARMv4 architecture",
- .dependencies = featureSet(&[_]Feature{
- .strict_align,
- }),
- };
result[@enumToInt(Feature.v4t)] = .{
- .llvm_name = "armv4t",
- .description = "ARMv4t architecture",
- .dependencies = featureSet(&[_]Feature{
- .strict_align,
- .has_v4t,
- }),
+ .llvm_name = "v4t",
+ .description = "Support ARM v4T instructions",
+ .dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.v5t)] = .{
- .llvm_name = "armv5t",
- .description = "ARMv5t architecture",
+ .llvm_name = "v5t",
+ .description = "Support ARM v5T instructions",
.dependencies = featureSet(&[_]Feature{
- .strict_align,
- .has_v5t,
+ .v4t,
}),
};
result[@enumToInt(Feature.v5te)] = .{
- .llvm_name = "armv5te",
- .description = "ARMv5te architecture",
- .dependencies = featureSet(&[_]Feature{
- .strict_align,
- .has_v5te,
- }),
- };
- result[@enumToInt(Feature.v5tej)] = .{
- .llvm_name = "armv5tej",
- .description = "ARMv5tej architecture",
+ .llvm_name = "v5te",
+ .description = "Support ARM v5TE, v5TEj, and v5TExp instructions",
.dependencies = featureSet(&[_]Feature{
- .strict_align,
- .has_v5te,
+ .v5t,
}),
};
result[@enumToInt(Feature.v6)] = .{
- .llvm_name = "armv6",
- .description = "ARMv6 architecture",
- .dependencies = featureSet(&[_]Feature{
- .dsp,
- .has_v6,
- }),
- };
- result[@enumToInt(Feature.v6m)] = .{
- .llvm_name = "armv6-m",
- .description = "ARMv6m architecture",
- .dependencies = featureSet(&[_]Feature{
- .db,
- .mclass,
- .noarm,
- .strict_align,
- .thumb_mode,
- .has_v6m,
- }),
- };
- result[@enumToInt(Feature.v6j)] = .{
- .llvm_name = "armv6j",
- .description = "ARMv7a architecture",
+ .llvm_name = "v6",
+ .description = "Support ARM v6 instructions",
.dependencies = featureSet(&[_]Feature{
- .v6,
+ .v5te,
}),
};
result[@enumToInt(Feature.v6k)] = .{
- .llvm_name = "armv6k",
- .description = "ARMv6k architecture",
- .dependencies = featureSet(&[_]Feature{
- .has_v6k,
- }),
- };
- result[@enumToInt(Feature.v6kz)] = .{
- .llvm_name = "armv6kz",
- .description = "ARMv6kz architecture",
- .dependencies = featureSet(&[_]Feature{
- .trustzone,
- .has_v6k,
- }),
- };
- result[@enumToInt(Feature.v6sm)] = .{
- .llvm_name = "armv6s-m",
- .description = "ARMv6sm architecture",
- .dependencies = featureSet(&[_]Feature{
- .db,
- .mclass,
- .noarm,
- .strict_align,
- .thumb_mode,
- .has_v6m,
- }),
- };
- result[@enumToInt(Feature.v6t2)] = .{
- .llvm_name = "armv6t2",
- .description = "ARMv6t2 architecture",
- .dependencies = featureSet(&[_]Feature{
- .dsp,
- .has_v6t2,
- }),
- };
- result[@enumToInt(Feature.v7a)] = .{
- .llvm_name = "armv7-a",
- .description = "ARMv7a architecture",
- .dependencies = featureSet(&[_]Feature{
- .aclass,
- .db,
- .dsp,
- .neon,
- .has_v7,
- }),
- };
- result[@enumToInt(Feature.v7m)] = .{
- .llvm_name = "armv7-m",
- .description = "ARMv7m architecture",
- .dependencies = featureSet(&[_]Feature{
- .db,
- .hwdiv,
- .mclass,
- .noarm,
- .thumb_mode,
- .thumb2,
- .has_v7,
- }),
- };
- result[@enumToInt(Feature.v7r)] = .{
- .llvm_name = "armv7-r",
- .description = "ARMv7r architecture",
- .dependencies = featureSet(&[_]Feature{
- .db,
- .dsp,
- .hwdiv,
- .rclass,
- .has_v7,
- }),
- };
- result[@enumToInt(Feature.v7em)] = .{
- .llvm_name = "armv7e-m",
- .description = "ARMv7em architecture",
- .dependencies = featureSet(&[_]Feature{
- .db,
- .dsp,
- .hwdiv,
- .mclass,
- .noarm,
- .thumb_mode,
- .thumb2,
- .has_v7,
- }),
- };
- result[@enumToInt(Feature.v7k)] = .{
- .llvm_name = "armv7k",
- .description = "ARMv7a architecture",
- .dependencies = featureSet(&[_]Feature{
- .v7a,
- }),
- };
- result[@enumToInt(Feature.v7s)] = .{
- .llvm_name = "armv7s",
- .description = "ARMv7a architecture",
- .dependencies = featureSet(&[_]Feature{
- .v7a,
- }),
- };
- result[@enumToInt(Feature.v7ve)] = .{
- .llvm_name = "armv7ve",
- .description = "ARMv7ve architecture",
+ .llvm_name = "v6k",
+ .description = "Support ARM v6k instructions",
.dependencies = featureSet(&[_]Feature{
- .aclass,
- .db,
- .dsp,
- .mp,
- .neon,
- .trustzone,
- .has_v7,
- .virtualization,
+ .v6,
}),
};
- result[@enumToInt(Feature.v8a)] = .{
- .llvm_name = "armv8-a",
- .description = "ARMv8a architecture",
+ result[@enumToInt(Feature.v6m)] = .{
+ .llvm_name = "v6m",
+ .description = "Support ARM v6M instructions",
.dependencies = featureSet(&[_]Feature{
- .aclass,
- .crc,
- .crypto,
- .db,
- .dsp,
- .fp_armv8,
- .mp,
- .neon,
- .trustzone,
- .has_v8,
- .virtualization,
+ .v6,
}),
};
- result[@enumToInt(Feature.v8m)] = .{
- .llvm_name = "armv8-m.base",
- .description = "ARMv8mBaseline architecture",
+ result[@enumToInt(Feature.v6t2)] = .{
+ .llvm_name = "v6t2",
+ .description = "Support ARM v6t2 instructions",
.dependencies = featureSet(&[_]Feature{
- .@"8msecext",
- .acquire_release,
- .db,
- .hwdiv,
- .mclass,
- .noarm,
- .strict_align,
- .thumb_mode,
- .has_v7clrex,
- .has_v8m,
+ .thumb2,
+ .v6k,
+ .v8m,
}),
};
- result[@enumToInt(Feature.v8m_main)] = .{
- .llvm_name = "armv8-m.main",
- .description = "ARMv8mMainline architecture",
+ result[@enumToInt(Feature.v7)] = .{
+ .llvm_name = "v7",
+ .description = "Support ARM v7 instructions",
.dependencies = featureSet(&[_]Feature{
- .@"8msecext",
- .acquire_release,
- .db,
- .hwdiv,
- .mclass,
- .noarm,
- .thumb_mode,
- .has_v8m_main,
+ .perfmon,
+ .v6t2,
+ .v7clrex,
}),
};
- result[@enumToInt(Feature.v8r)] = .{
- .llvm_name = "armv8-r",
- .description = "ARMv8r architecture",
+ result[@enumToInt(Feature.v7clrex)] = .{
+ .llvm_name = "v7clrex",
+ .description = "Has v7 clrex instruction",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.v8)] = .{
+ .llvm_name = "v8",
+ .description = "Support ARM v8 instructions",
.dependencies = featureSet(&[_]Feature{
- .crc,
- .db,
- .dfb,
- .dsp,
- .fp_armv8,
- .mp,
- .neon,
- .rclass,
- .has_v8,
- .virtualization,
+ .acquire_release,
+ .v7,
}),
};
result[@enumToInt(Feature.v8_1a)] = .{
- .llvm_name = "armv8.1-a",
- .description = "ARMv81a architecture",
+ .llvm_name = "v8.1a",
+ .description = "Support ARM v8.1a instructions",
.dependencies = featureSet(&[_]Feature{
- .aclass,
- .crc,
- .crypto,
- .db,
- .dsp,
- .fp_armv8,
- .mp,
- .neon,
- .trustzone,
- .has_v8_1a,
- .virtualization,
+ .v8,
}),
};
result[@enumToInt(Feature.v8_1m_main)] = .{
- .llvm_name = "armv8.1-m.main",
- .description = "ARMv81mMainline architecture",
+ .llvm_name = "v8.1m.main",
+ .description = "Support ARM v8-1M Mainline instructions",
.dependencies = featureSet(&[_]Feature{
- .@"8msecext",
- .acquire_release,
- .db,
- .hwdiv,
- .lob,
- .mclass,
- .noarm,
- .ras,
- .thumb_mode,
- .has_v8_1m_main,
+ .v8m_main,
}),
};
result[@enumToInt(Feature.v8_2a)] = .{
- .llvm_name = "armv8.2-a",
- .description = "ARMv82a architecture",
+ .llvm_name = "v8.2a",
+ .description = "Support ARM v8.2a instructions",
.dependencies = featureSet(&[_]Feature{
- .aclass,
- .crc,
- .crypto,
- .db,
- .dsp,
- .fp_armv8,
- .mp,
- .neon,
- .ras,
- .trustzone,
- .has_v8_2a,
- .virtualization,
+ .v8_1a,
}),
};
result[@enumToInt(Feature.v8_3a)] = .{
- .llvm_name = "armv8.3-a",
- .description = "ARMv83a architecture",
+ .llvm_name = "v8.3a",
+ .description = "Support ARM v8.3a instructions",
.dependencies = featureSet(&[_]Feature{
- .aclass,
- .crc,
- .crypto,
- .db,
- .dsp,
- .fp_armv8,
- .mp,
- .neon,
- .ras,
- .trustzone,
- .has_v8_3a,
- .virtualization,
+ .v8_2a,
}),
};
result[@enumToInt(Feature.v8_4a)] = .{
- .llvm_name = "armv8.4-a",
- .description = "ARMv84a architecture",
+ .llvm_name = "v8.4a",
+ .description = "Support ARM v8.4a instructions",
.dependencies = featureSet(&[_]Feature{
- .aclass,
- .crc,
- .crypto,
- .db,
.dotprod,
- .dsp,
- .fp_armv8,
- .mp,
- .neon,
- .ras,
- .trustzone,
- .has_v8_4a,
- .virtualization,
+ .v8_3a,
}),
};
result[@enumToInt(Feature.v8_5a)] = .{
- .llvm_name = "armv8.5-a",
- .description = "ARMv85a architecture",
+ .llvm_name = "v8.5a",
+ .description = "Support ARM v8.5a instructions",
.dependencies = featureSet(&[_]Feature{
- .aclass,
- .crc,
- .crypto,
- .db,
- .dotprod,
- .dsp,
- .fp_armv8,
- .mp,
- .neon,
- .ras,
- .trustzone,
- .has_v8_5a,
- .virtualization,
+ .sb,
+ .v8_4a,
}),
};
result[@enumToInt(Feature.v8_6a)] = .{
- .llvm_name = "armv8.6-a",
- .description = "ARMv86a architecture",
+ .llvm_name = "v8.6a",
+ .description = "Support ARM v8.6a instructions",
.dependencies = featureSet(&[_]Feature{
- .aclass,
- .crc,
- .crypto,
- .db,
- .dotprod,
- .dsp,
- .fp_armv8,
- .mp,
- .neon,
- .ras,
- .trustzone,
- .has_v8_6a,
- .virtualization,
+ .bf16,
+ ._i8mm,
+ .v8_5a,
+ }),
+ };
+ result[@enumToInt(Feature.v8m)] = .{
+ .llvm_name = "v8m",
+ .description = "Support ARM v8M Baseline instructions",
+ .dependencies = featureSet(&[_]Feature{
+ .v6m,
+ }),
+ };
+ result[@enumToInt(Feature.v8m_main)] = .{
+ .llvm_name = "v8m.main",
+ .description = "Support ARM v8M Mainline instructions",
+ .dependencies = featureSet(&[_]Feature{
+ .v7,
}),
};
result[@enumToInt(Feature.vfp2)] = .{
@@ -1417,7 +1547,7 @@ pub const all_features = blk: {
.llvm_name = "xscale",
.description = "ARMv5te architecture",
.dependencies = featureSet(&[_]Feature{
- .has_v5te,
+ .armv5te,
}),
};
result[@enumToInt(Feature.zcz)] = .{
@@ -1438,49 +1568,49 @@ pub const cpu = struct {
.name = "arm1020e",
.llvm_name = "arm1020e",
.features = featureSet(&[_]Feature{
- .v5te,
+ .armv5te,
}),
};
pub const arm1020t = CpuModel{
.name = "arm1020t",
.llvm_name = "arm1020t",
.features = featureSet(&[_]Feature{
- .v5t,
+ .armv5t,
}),
};
pub const arm1022e = CpuModel{
.name = "arm1022e",
.llvm_name = "arm1022e",
.features = featureSet(&[_]Feature{
- .v5te,
+ .armv5te,
}),
};
pub const arm10e = CpuModel{
.name = "arm10e",
.llvm_name = "arm10e",
.features = featureSet(&[_]Feature{
- .v5te,
+ .armv5te,
}),
};
pub const arm10tdmi = CpuModel{
.name = "arm10tdmi",
.llvm_name = "arm10tdmi",
.features = featureSet(&[_]Feature{
- .v5t,
+ .armv5t,
}),
};
pub const arm1136j_s = CpuModel{
.name = "arm1136j_s",
.llvm_name = "arm1136j-s",
.features = featureSet(&[_]Feature{
- .v6,
+ .armv6,
}),
};
pub const arm1136jf_s = CpuModel{
.name = "arm1136jf_s",
.llvm_name = "arm1136jf-s",
.features = featureSet(&[_]Feature{
- .v6,
+ .armv6,
.slowfpvmlx,
.vfp2,
}),
@@ -1489,14 +1619,14 @@ pub const cpu = struct {
.name = "arm1156t2_s",
.llvm_name = "arm1156t2-s",
.features = featureSet(&[_]Feature{
- .v6t2,
+ .armv6t2,
}),
};
pub const arm1156t2f_s = CpuModel{
.name = "arm1156t2f_s",
.llvm_name = "arm1156t2f-s",
.features = featureSet(&[_]Feature{
- .v6t2,
+ .armv6t2,
.slowfpvmlx,
.vfp2,
}),
@@ -1505,21 +1635,21 @@ pub const cpu = struct {
.name = "arm1176j_s",
.llvm_name = "arm1176j-s",
.features = featureSet(&[_]Feature{
- .v6kz,
+ .armv6kz,
}),
};
pub const arm1176jz_s = CpuModel{
.name = "arm1176jz_s",
.llvm_name = "arm1176jz-s",
.features = featureSet(&[_]Feature{
- .v6kz,
+ .armv6kz,
}),
};
pub const arm1176jzf_s = CpuModel{
.name = "arm1176jzf_s",
.llvm_name = "arm1176jzf-s",
.features = featureSet(&[_]Feature{
- .v6kz,
+ .armv6kz,
.slowfpvmlx,
.vfp2,
}),
@@ -1528,133 +1658,127 @@ pub const cpu = struct {
.name = "arm710t",
.llvm_name = "arm710t",
.features = featureSet(&[_]Feature{
- .v4t,
+ .armv4t,
}),
};
pub const arm720t = CpuModel{
.name = "arm720t",
.llvm_name = "arm720t",
.features = featureSet(&[_]Feature{
- .v4t,
+ .armv4t,
}),
};
pub const arm7tdmi = CpuModel{
.name = "arm7tdmi",
.llvm_name = "arm7tdmi",
.features = featureSet(&[_]Feature{
- .v4t,
+ .armv4t,
}),
};
pub const arm7tdmi_s = CpuModel{
.name = "arm7tdmi_s",
.llvm_name = "arm7tdmi-s",
.features = featureSet(&[_]Feature{
- .v4t,
+ .armv4t,
}),
};
pub const arm8 = CpuModel{
.name = "arm8",
.llvm_name = "arm8",
.features = featureSet(&[_]Feature{
- .v4,
+ .armv4,
}),
};
pub const arm810 = CpuModel{
.name = "arm810",
.llvm_name = "arm810",
.features = featureSet(&[_]Feature{
- .v4,
+ .armv4,
}),
};
pub const arm9 = CpuModel{
.name = "arm9",
.llvm_name = "arm9",
.features = featureSet(&[_]Feature{
- .v4t,
+ .armv4t,
}),
};
pub const arm920 = CpuModel{
.name = "arm920",
.llvm_name = "arm920",
.features = featureSet(&[_]Feature{
- .v4t,
+ .armv4t,
}),
};
pub const arm920t = CpuModel{
.name = "arm920t",
.llvm_name = "arm920t",
.features = featureSet(&[_]Feature{
- .v4t,
+ .armv4t,
}),
};
pub const arm922t = CpuModel{
.name = "arm922t",
.llvm_name = "arm922t",
.features = featureSet(&[_]Feature{
- .v4t,
+ .armv4t,
}),
};
pub const arm926ej_s = CpuModel{
.name = "arm926ej_s",
.llvm_name = "arm926ej-s",
.features = featureSet(&[_]Feature{
- .v5te,
+ .armv5te,
}),
};
pub const arm940t = CpuModel{
.name = "arm940t",
.llvm_name = "arm940t",
.features = featureSet(&[_]Feature{
- .v4t,
+ .armv4t,
}),
};
pub const arm946e_s = CpuModel{
.name = "arm946e_s",
.llvm_name = "arm946e-s",
.features = featureSet(&[_]Feature{
- .v5te,
+ .armv5te,
}),
};
pub const arm966e_s = CpuModel{
.name = "arm966e_s",
.llvm_name = "arm966e-s",
.features = featureSet(&[_]Feature{
- .v5te,
+ .armv5te,
}),
};
pub const arm968e_s = CpuModel{
.name = "arm968e_s",
.llvm_name = "arm968e-s",
.features = featureSet(&[_]Feature{
- .v5te,
+ .armv5te,
}),
};
pub const arm9e = CpuModel{
.name = "arm9e",
.llvm_name = "arm9e",
.features = featureSet(&[_]Feature{
- .v5te,
+ .armv5te,
}),
};
pub const arm9tdmi = CpuModel{
.name = "arm9tdmi",
.llvm_name = "arm9tdmi",
.features = featureSet(&[_]Feature{
- .v4t,
- }),
- };
- pub const baseline = CpuModel{
- .name = "baseline",
- .llvm_name = "generic",
- .features = featureSet(&[_]Feature{
- .v7a,
+ .armv4t,
}),
};
pub const cortex_a12 = CpuModel{
.name = "cortex_a12",
.llvm_name = "cortex-a12",
.features = featureSet(&[_]Feature{
- .v7a,
+ .a12,
+ .armv7_a,
.avoid_partial_cpsr,
.mp,
.ret_addr_stack,
@@ -1668,7 +1792,8 @@ pub const cpu = struct {
.name = "cortex_a15",
.llvm_name = "cortex-a15",
.features = featureSet(&[_]Feature{
- .v7a,
+ .a15,
+ .armv7_a,
.avoid_partial_cpsr,
.dont_widen_vmovs,
.mp,
@@ -1685,7 +1810,8 @@ pub const cpu = struct {
.name = "cortex_a17",
.llvm_name = "cortex-a17",
.features = featureSet(&[_]Feature{
- .v7a,
+ .a17,
+ .armv7_a,
.avoid_partial_cpsr,
.mp,
.ret_addr_stack,
@@ -1699,29 +1825,31 @@ pub const cpu = struct {
.name = "cortex_a32",
.llvm_name = "cortex-a32",
.features = featureSet(&[_]Feature{
+ .armv8_a,
.crc,
.crypto,
.hwdiv,
.hwdiv_arm,
- .v8a,
}),
};
pub const cortex_a35 = CpuModel{
.name = "cortex_a35",
.llvm_name = "cortex-a35",
.features = featureSet(&[_]Feature{
+ .a35,
+ .armv8_a,
.crc,
.crypto,
.hwdiv,
.hwdiv_arm,
- .v8a,
}),
};
pub const cortex_a5 = CpuModel{
.name = "cortex_a5",
.llvm_name = "cortex-a5",
.features = featureSet(&[_]Feature{
- .v7a,
+ .a5,
+ .armv7_a,
.mp,
.ret_addr_stack,
.slow_fp_brcc,
@@ -1736,7 +1864,8 @@ pub const cpu = struct {
.name = "cortex_a53",
.llvm_name = "cortex-a53",
.features = featureSet(&[_]Feature{
- .v8a,
+ .a53,
+ .armv8_a,
.crc,
.crypto,
.fpao,
@@ -1748,7 +1877,8 @@ pub const cpu = struct {
.name = "cortex_a55",
.llvm_name = "cortex-a55",
.features = featureSet(&[_]Feature{
- .v8_2a,
+ .a55,
+ .armv8_2_a,
.dotprod,
.hwdiv,
.hwdiv_arm,
@@ -1758,7 +1888,8 @@ pub const cpu = struct {
.name = "cortex_a57",
.llvm_name = "cortex-a57",
.features = featureSet(&[_]Feature{
- .v8a,
+ .a57,
+ .armv8_a,
.avoid_partial_cpsr,
.cheap_predicable_cpsr,
.crc,
@@ -1772,7 +1903,8 @@ pub const cpu = struct {
.name = "cortex_a7",
.llvm_name = "cortex-a7",
.features = featureSet(&[_]Feature{
- .v7a,
+ .a7,
+ .armv7_a,
.mp,
.ret_addr_stack,
.slow_fp_brcc,
@@ -1789,7 +1921,8 @@ pub const cpu = struct {
.name = "cortex_a72",
.llvm_name = "cortex-a72",
.features = featureSet(&[_]Feature{
- .v8a,
+ .a72,
+ .armv8_a,
.crc,
.crypto,
.hwdiv,
@@ -1800,7 +1933,8 @@ pub const cpu = struct {
.name = "cortex_a73",
.llvm_name = "cortex-a73",
.features = featureSet(&[_]Feature{
- .v8a,
+ .a73,
+ .armv8_a,
.crc,
.crypto,
.hwdiv,
@@ -1811,7 +1945,8 @@ pub const cpu = struct {
.name = "cortex_a75",
.llvm_name = "cortex-a75",
.features = featureSet(&[_]Feature{
- .v8_2a,
+ .a75,
+ .armv8_2_a,
.dotprod,
.hwdiv,
.hwdiv_arm,
@@ -1822,7 +1957,7 @@ pub const cpu = struct {
.llvm_name = "cortex-a76",
.features = featureSet(&[_]Feature{
.a76,
- .v8_2a,
+ .armv8_2_a,
.crc,
.crypto,
.dotprod,
@@ -1836,7 +1971,7 @@ pub const cpu = struct {
.llvm_name = "cortex-a76ae",
.features = featureSet(&[_]Feature{
.a76,
- .v8_2a,
+ .armv8_2_a,
.crc,
.crypto,
.dotprod,
@@ -1849,7 +1984,8 @@ pub const cpu = struct {
.name = "cortex_a77",
.llvm_name = "cortex-a77",
.features = featureSet(&[_]Feature{
- .v8_2a,
+ .a77,
+ .armv8_2_a,
.crc,
.crypto,
.dotprod,
@@ -1862,7 +1998,8 @@ pub const cpu = struct {
.name = "cortex_a78",
.llvm_name = "cortex-a78",
.features = featureSet(&[_]Feature{
- .v8_2a,
+ .armv8_2_a,
+ .cortex_a78,
.crc,
.crypto,
.dotprod,
@@ -1875,7 +2012,8 @@ pub const cpu = struct {
.name = "cortex_a8",
.llvm_name = "cortex-a8",
.features = featureSet(&[_]Feature{
- .v7a,
+ .a8,
+ .armv7_a,
.nonpipelined_vfp,
.ret_addr_stack,
.slow_fp_brcc,
@@ -1890,7 +2028,8 @@ pub const cpu = struct {
.name = "cortex_a9",
.llvm_name = "cortex-a9",
.features = featureSet(&[_]Feature{
- .v7a,
+ .a9,
+ .armv7_a,
.avoid_partial_cpsr,
.expand_fp_mlx,
.fp16,
@@ -1909,28 +2048,28 @@ pub const cpu = struct {
.name = "cortex_m0",
.llvm_name = "cortex-m0",
.features = featureSet(&[_]Feature{
- .v6m,
+ .armv6_m,
}),
};
pub const cortex_m0plus = CpuModel{
.name = "cortex_m0plus",
.llvm_name = "cortex-m0plus",
.features = featureSet(&[_]Feature{
- .v6m,
+ .armv6_m,
}),
};
pub const cortex_m1 = CpuModel{
.name = "cortex_m1",
.llvm_name = "cortex-m1",
.features = featureSet(&[_]Feature{
- .v6m,
+ .armv6_m,
}),
};
pub const cortex_m23 = CpuModel{
.name = "cortex_m23",
.llvm_name = "cortex-m23",
.features = featureSet(&[_]Feature{
- .v8m,
+ .armv8_m_base,
.no_movt,
}),
};
@@ -1938,7 +2077,7 @@ pub const cpu = struct {
.name = "cortex_m3",
.llvm_name = "cortex-m3",
.features = featureSet(&[_]Feature{
- .v7m,
+ .armv7_m,
.loop_align,
.m3,
.no_branch_predictor,
@@ -1949,7 +2088,7 @@ pub const cpu = struct {
.name = "cortex_m33",
.llvm_name = "cortex-m33",
.features = featureSet(&[_]Feature{
- .v8m_main,
+ .armv8_m_main,
.dsp,
.fp_armv8d16sp,
.loop_align,
@@ -1963,7 +2102,7 @@ pub const cpu = struct {
.name = "cortex_m35p",
.llvm_name = "cortex-m35p",
.features = featureSet(&[_]Feature{
- .v8m_main,
+ .armv8_m_main,
.dsp,
.fp_armv8d16sp,
.loop_align,
@@ -1977,7 +2116,7 @@ pub const cpu = struct {
.name = "cortex_m4",
.llvm_name = "cortex-m4",
.features = featureSet(&[_]Feature{
- .v7em,
+ .armv7e_m,
.loop_align,
.no_branch_predictor,
.slowfpvfmx,
@@ -1990,7 +2129,7 @@ pub const cpu = struct {
.name = "cortex_m55",
.llvm_name = "cortex-m55",
.features = featureSet(&[_]Feature{
- .v8_1m_main,
+ .armv8_1_m_main,
.dsp,
.fp_armv8d16,
.loop_align,
@@ -2004,15 +2143,16 @@ pub const cpu = struct {
.name = "cortex_m7",
.llvm_name = "cortex-m7",
.features = featureSet(&[_]Feature{
- .v7em,
+ .armv7e_m,
.fp_armv8d16,
+ .use_misched,
}),
};
pub const cortex_r4 = CpuModel{
.name = "cortex_r4",
.llvm_name = "cortex-r4",
.features = featureSet(&[_]Feature{
- .v7r,
+ .armv7_r,
.avoid_partial_cpsr,
.r4,
.ret_addr_stack,
@@ -2022,7 +2162,7 @@ pub const cpu = struct {
.name = "cortex_r4f",
.llvm_name = "cortex-r4f",
.features = featureSet(&[_]Feature{
- .v7r,
+ .armv7_r,
.avoid_partial_cpsr,
.r4,
.ret_addr_stack,
@@ -2036,9 +2176,10 @@ pub const cpu = struct {
.name = "cortex_r5",
.llvm_name = "cortex-r5",
.features = featureSet(&[_]Feature{
- .v7r,
+ .armv7_r,
.avoid_partial_cpsr,
.hwdiv_arm,
+ .r5,
.ret_addr_stack,
.slow_fp_brcc,
.slowfpvfmx,
@@ -2050,8 +2191,9 @@ pub const cpu = struct {
.name = "cortex_r52",
.llvm_name = "cortex-r52",
.features = featureSet(&[_]Feature{
- .v8r,
+ .armv8_r,
.fpao,
+ .r52,
.use_misched,
}),
};
@@ -2059,11 +2201,12 @@ pub const cpu = struct {
.name = "cortex_r7",
.llvm_name = "cortex-r7",
.features = featureSet(&[_]Feature{
- .v7r,
+ .armv7_r,
.avoid_partial_cpsr,
.fp16,
.hwdiv_arm,
.mp,
+ .r7,
.ret_addr_stack,
.slow_fp_brcc,
.slowfpvfmx,
@@ -2075,7 +2218,7 @@ pub const cpu = struct {
.name = "cortex_r8",
.llvm_name = "cortex-r8",
.features = featureSet(&[_]Feature{
- .v7r,
+ .armv7_r,
.avoid_partial_cpsr,
.fp16,
.hwdiv_arm,
@@ -2091,7 +2234,8 @@ pub const cpu = struct {
.name = "cortex_x1",
.llvm_name = "cortex-x1",
.features = featureSet(&[_]Feature{
- .v8_2a,
+ .armv8_2_a,
+ .cortex_x1,
.crc,
.crypto,
.dotprod,
@@ -2104,7 +2248,7 @@ pub const cpu = struct {
.name = "cyclone",
.llvm_name = "cyclone",
.features = featureSet(&[_]Feature{
- .v8a,
+ .armv8_a,
.avoid_movs_shop,
.avoid_partial_cpsr,
.crypto,
@@ -2126,30 +2270,14 @@ pub const cpu = struct {
.name = "ep9312",
.llvm_name = "ep9312",
.features = featureSet(&[_]Feature{
- .v4t,
- }),
- };
- pub const exynos_m1 = CpuModel{
- .name = "exynos_m1",
- .llvm_name = null,
- .features = featureSet(&[_]Feature{
- .v8a,
- .exynos,
- }),
- };
- pub const exynos_m2 = CpuModel{
- .name = "exynos_m2",
- .llvm_name = null,
- .features = featureSet(&[_]Feature{
- .v8a,
- .exynos,
+ .armv4t,
}),
};
pub const exynos_m3 = CpuModel{
.name = "exynos_m3",
.llvm_name = "exynos-m3",
.features = featureSet(&[_]Feature{
- .v8_2a,
+ .armv8_a,
.exynos,
}),
};
@@ -2157,7 +2285,7 @@ pub const cpu = struct {
.name = "exynos_m4",
.llvm_name = "exynos-m4",
.features = featureSet(&[_]Feature{
- .v8_2a,
+ .armv8_2_a,
.dotprod,
.exynos,
.fullfp16,
@@ -2167,10 +2295,10 @@ pub const cpu = struct {
.name = "exynos_m5",
.llvm_name = "exynos-m5",
.features = featureSet(&[_]Feature{
+ .armv8_2_a,
.dotprod,
.exynos,
.fullfp16,
- .v8_2a,
}),
};
pub const generic = CpuModel{
@@ -2182,20 +2310,21 @@ pub const cpu = struct {
.name = "iwmmxt",
.llvm_name = "iwmmxt",
.features = featureSet(&[_]Feature{
- .v5te,
+ .armv5te,
}),
};
pub const krait = CpuModel{
.name = "krait",
.llvm_name = "krait",
.features = featureSet(&[_]Feature{
+ .armv7_a,
.avoid_partial_cpsr,
.fp16,
.hwdiv,
.hwdiv_arm,
+ .krait,
.muxed_units,
.ret_addr_stack,
- .v7a,
.vfp4,
.vldn_align,
.vmlx_forwarding,
@@ -2205,18 +2334,19 @@ pub const cpu = struct {
.name = "kryo",
.llvm_name = "kryo",
.features = featureSet(&[_]Feature{
+ .armv8_a,
.crc,
.crypto,
.hwdiv,
.hwdiv_arm,
- .v8a,
+ .kryo,
}),
};
pub const mpcore = CpuModel{
.name = "mpcore",
.llvm_name = "mpcore",
.features = featureSet(&[_]Feature{
- .v6k,
+ .armv6k,
.slowfpvmlx,
.vfp2,
}),
@@ -2225,14 +2355,14 @@ pub const cpu = struct {
.name = "mpcorenovfp",
.llvm_name = "mpcorenovfp",
.features = featureSet(&[_]Feature{
- .v6k,
+ .armv6k,
}),
};
pub const neoverse_n1 = CpuModel{
.name = "neoverse_n1",
.llvm_name = "neoverse-n1",
.features = featureSet(&[_]Feature{
- .v8_2a,
+ .armv8_2_a,
.crc,
.crypto,
.dotprod,
@@ -2240,18 +2370,42 @@ pub const cpu = struct {
.hwdiv_arm,
}),
};
+ pub const neoverse_n2 = CpuModel{
+ .name = "neoverse_n2",
+ .llvm_name = "neoverse-n2",
+ .features = featureSet(&[_]Feature{
+ .armv8_5_a,
+ .bf16,
+ ._i8mm,
+ .perfmon,
+ }),
+ };
+ pub const neoverse_v1 = CpuModel{
+ .name = "neoverse_v1",
+ .llvm_name = "neoverse-v1",
+ .features = featureSet(&[_]Feature{
+ .armv8_4_a,
+ .bf16,
+ .crc,
+ .crypto,
+ .fullfp16,
+ .hwdiv,
+ .hwdiv_arm,
+ ._i8mm,
+ }),
+ };
pub const sc000 = CpuModel{
.name = "sc000",
.llvm_name = "sc000",
.features = featureSet(&[_]Feature{
- .v6m,
+ .armv6_m,
}),
};
pub const sc300 = CpuModel{
.name = "sc300",
.llvm_name = "sc300",
.features = featureSet(&[_]Feature{
- .v7m,
+ .armv7_m,
.m3,
.no_branch_predictor,
.use_misched,
@@ -2261,35 +2415,35 @@ pub const cpu = struct {
.name = "strongarm",
.llvm_name = "strongarm",
.features = featureSet(&[_]Feature{
- .v4,
+ .armv4,
}),
};
pub const strongarm110 = CpuModel{
.name = "strongarm110",
.llvm_name = "strongarm110",
.features = featureSet(&[_]Feature{
- .v4,
+ .armv4,
}),
};
pub const strongarm1100 = CpuModel{
.name = "strongarm1100",
.llvm_name = "strongarm1100",
.features = featureSet(&[_]Feature{
- .v4,
+ .armv4,
}),
};
pub const strongarm1110 = CpuModel{
.name = "strongarm1110",
.llvm_name = "strongarm1110",
.features = featureSet(&[_]Feature{
- .v4,
+ .armv4,
}),
};
pub const swift = CpuModel{
.name = "swift",
.llvm_name = "swift",
.features = featureSet(&[_]Feature{
- .v7a,
+ .armv7_a,
.avoid_movs_shop,
.avoid_partial_cpsr,
.disable_postra_scheduler,
@@ -2317,7 +2471,7 @@ pub const cpu = struct {
.name = "xscale",
.llvm_name = "xscale",
.features = featureSet(&[_]Feature{
- .v5te,
+ .armv5te,
}),
};
};
lib/std/target/avr.zig
@@ -47,6 +47,7 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
+ @setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
@@ -163,7 +164,6 @@ pub const all_features = blk: {
.dependencies = featureSet(&[_]Feature{
.avr0,
.@"break",
- .memmappedregs,
.sram,
.tinyencoding,
}),
@@ -802,6 +802,13 @@ pub const cpu = struct {
.avr5,
}),
};
+ pub const atmega168pb = CpuModel{
+ .name = "atmega168pb",
+ .llvm_name = "atmega168pb",
+ .features = featureSet(&[_]Feature{
+ .avr5,
+ }),
+ };
pub const atmega169 = CpuModel{
.name = "atmega169",
.llvm_name = "atmega169",
@@ -949,6 +956,13 @@ pub const cpu = struct {
.avr5,
}),
};
+ pub const atmega324pb = CpuModel{
+ .name = "atmega324pb",
+ .llvm_name = "atmega324pb",
+ .features = featureSet(&[_]Feature{
+ .avr5,
+ }),
+ };
pub const atmega325 = CpuModel{
.name = "atmega325",
.llvm_name = "atmega325",
@@ -1019,6 +1033,13 @@ pub const cpu = struct {
.avr5,
}),
};
+ pub const atmega328pb = CpuModel{
+ .name = "atmega328pb",
+ .llvm_name = "atmega328pb",
+ .features = featureSet(&[_]Feature{
+ .avr5,
+ }),
+ };
pub const atmega329 = CpuModel{
.name = "atmega329",
.llvm_name = "atmega329",
@@ -1166,6 +1187,13 @@ pub const cpu = struct {
.avr4,
}),
};
+ pub const atmega48pb = CpuModel{
+ .name = "atmega48pb",
+ .llvm_name = "atmega48pb",
+ .features = featureSet(&[_]Feature{
+ .avr4,
+ }),
+ };
pub const atmega64 = CpuModel{
.name = "atmega64",
.llvm_name = "atmega64",
@@ -1338,7 +1366,11 @@ pub const cpu = struct {
.name = "atmega8",
.llvm_name = "atmega8",
.features = featureSet(&[_]Feature{
- .avr4,
+ .avr2,
+ .lpmx,
+ .movw,
+ .mul,
+ .spm,
}),
};
pub const atmega8515 = CpuModel{
@@ -1391,11 +1423,22 @@ pub const cpu = struct {
.avr4,
}),
};
+ pub const atmega88pb = CpuModel{
+ .name = "atmega88pb",
+ .llvm_name = "atmega88pb",
+ .features = featureSet(&[_]Feature{
+ .avr4,
+ }),
+ };
pub const atmega8a = CpuModel{
.name = "atmega8a",
.llvm_name = "atmega8a",
.features = featureSet(&[_]Feature{
- .avr4,
+ .avr2,
+ .lpmx,
+ .movw,
+ .mul,
+ .spm,
}),
};
pub const atmega8hva = CpuModel{
@@ -1595,6 +1638,13 @@ pub const cpu = struct {
.avr25,
}),
};
+ pub const attiny441 = CpuModel{
+ .name = "attiny441",
+ .llvm_name = "attiny441",
+ .features = featureSet(&[_]Feature{
+ .avr25,
+ }),
+ };
pub const attiny44a = CpuModel{
.name = "attiny44a",
.llvm_name = "attiny44a",
@@ -1651,6 +1701,13 @@ pub const cpu = struct {
.avr25,
}),
};
+ pub const attiny841 = CpuModel{
+ .name = "attiny841",
+ .llvm_name = "attiny841",
+ .features = featureSet(&[_]Feature{
+ .avr25,
+ }),
+ };
pub const attiny84a = CpuModel{
.name = "attiny84a",
.llvm_name = "attiny84a",
@@ -1802,7 +1859,7 @@ pub const cpu = struct {
.name = "atxmega16e5",
.llvm_name = "atxmega16e5",
.features = featureSet(&[_]Feature{
- .xmega,
+ .xmegau,
}),
};
pub const atxmega192a3 = CpuModel{
@@ -1907,7 +1964,7 @@ pub const cpu = struct {
.name = "atxmega32e5",
.llvm_name = "atxmega32e5",
.features = featureSet(&[_]Feature{
- .xmega,
+ .xmegau,
}),
};
pub const atxmega32x1 = CpuModel{
@@ -2005,7 +2062,7 @@ pub const cpu = struct {
.name = "atxmega8e5",
.llvm_name = "atxmega8e5",
.features = featureSet(&[_]Feature{
- .xmega,
+ .xmegau,
}),
};
pub const avr1 = CpuModel{
lib/std/target/bpf.zig
@@ -16,6 +16,7 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
+ @setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
lib/std/target/hexagon.zig
@@ -44,6 +44,7 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
+ @setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
lib/std/target/mips.zig
@@ -65,6 +65,7 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
+ @setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
lib/std/target/msp430.zig
@@ -17,6 +17,7 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
+ @setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
lib/std/target/nvptx.zig
@@ -41,6 +41,7 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
+ @setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
lib/std/target/powerpc.zig
@@ -32,6 +32,7 @@ pub const Feature = enum {
fsqrt,
fuse_addi_load,
fuse_addis_load,
+ fuse_store,
fusion,
hard_float,
htm,
@@ -44,7 +45,9 @@ pub const Feature = enum {
lfiwax,
longcall,
mfocrf,
+ mma,
msync,
+ paired_vector_memops,
partword_atomics,
pcrelative_memops,
popcntd,
@@ -59,7 +62,6 @@ pub const Feature = enum {
ppc6xx,
predictable_select_expensive,
prefix_instrs,
- qpx,
recipprec,
secure_plt,
slow_popcntd,
@@ -73,6 +75,7 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
+ @setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
@@ -228,6 +231,13 @@ pub const all_features = blk: {
.fusion,
}),
};
+ result[@enumToInt(Feature.fuse_store)] = .{
+ .llvm_name = "fuse-store",
+ .description = "Target supports store clustering",
+ .dependencies = featureSet(&[_]Feature{
+ .fusion,
+ }),
+ };
result[@enumToInt(Feature.fusion)] = .{
.llvm_name = "fusion",
.description = "Target supports instruction fusion",
@@ -292,6 +302,15 @@ pub const all_features = blk: {
.description = "Enable the MFOCRF instruction",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.mma)] = .{
+ .llvm_name = "mma",
+ .description = "Enable MMA instructions",
+ .dependencies = featureSet(&[_]Feature{
+ .paired_vector_memops,
+ .power8_vector,
+ .power9_altivec,
+ }),
+ };
result[@enumToInt(Feature.msync)] = .{
.llvm_name = "msync",
.description = "Has only the msync instruction instead of sync",
@@ -299,6 +318,13 @@ pub const all_features = blk: {
.booke,
}),
};
+ result[@enumToInt(Feature.paired_vector_memops)] = .{
+ .llvm_name = "paired-vector-memops",
+ .description = "32Byte load and store instructions",
+ .dependencies = featureSet(&[_]Feature{
+ .isa_v30_instructions,
+ }),
+ };
result[@enumToInt(Feature.partword_atomics)] = .{
.llvm_name = "partword-atomics",
.description = "Enable l[bh]arx and st[bh]cx.",
@@ -309,6 +335,7 @@ pub const all_features = blk: {
.description = "Enable PC relative Memory Ops",
.dependencies = featureSet(&[_]Feature{
.isa_v30_instructions,
+ .prefix_instrs,
}),
};
result[@enumToInt(Feature.popcntd)] = .{
@@ -390,13 +417,6 @@ pub const all_features = blk: {
.power9_altivec,
}),
};
- result[@enumToInt(Feature.qpx)] = .{
- .llvm_name = "qpx",
- .description = "Enable QPX instructions",
- .dependencies = featureSet(&[_]Feature{
- .fpu,
- }),
- };
result[@enumToInt(Feature.recipprec)] = .{
.llvm_name = "recipprec",
.description = "Assume higher precision reciprocal estimates",
@@ -452,8 +472,8 @@ pub const all_features = blk: {
};
pub const cpu = struct {
- pub const @"ppc440" = CpuModel{
- .name = "ppc440",
+ pub const @"440" = CpuModel{
+ .name = "440",
.llvm_name = "440",
.features = featureSet(&[_]Feature{
.booke,
@@ -464,8 +484,8 @@ pub const cpu = struct {
.msync,
}),
};
- pub const @"ppc450" = CpuModel{
- .name = "ppc450",
+ pub const @"450" = CpuModel{
+ .name = "450",
.llvm_name = "450",
.features = featureSet(&[_]Feature{
.booke,
@@ -476,70 +496,70 @@ pub const cpu = struct {
.msync,
}),
};
- pub const @"ppc601" = CpuModel{
- .name = "ppc601",
+ pub const @"601" = CpuModel{
+ .name = "601",
.llvm_name = "601",
.features = featureSet(&[_]Feature{
.fpu,
}),
};
- pub const @"ppc602" = CpuModel{
- .name = "ppc602",
+ pub const @"602" = CpuModel{
+ .name = "602",
.llvm_name = "602",
.features = featureSet(&[_]Feature{
.fpu,
}),
};
- pub const @"ppc603" = CpuModel{
- .name = "ppc603",
+ pub const @"603" = CpuModel{
+ .name = "603",
.llvm_name = "603",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
- pub const @"ppc603e" = CpuModel{
- .name = "ppc603e",
+ pub const @"603e" = CpuModel{
+ .name = "603e",
.llvm_name = "603e",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
- pub const @"ppc603ev" = CpuModel{
- .name = "ppc603ev",
+ pub const @"603ev" = CpuModel{
+ .name = "603ev",
.llvm_name = "603ev",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
- pub const @"ppc604" = CpuModel{
- .name = "ppc604",
+ pub const @"604" = CpuModel{
+ .name = "604",
.llvm_name = "604",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
- pub const @"ppc604e" = CpuModel{
- .name = "ppc604e",
+ pub const @"604e" = CpuModel{
+ .name = "604e",
.llvm_name = "604e",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
- pub const @"ppc620" = CpuModel{
- .name = "ppc620",
+ pub const @"620" = CpuModel{
+ .name = "620",
.llvm_name = "620",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
- pub const @"ppc7400" = CpuModel{
- .name = "ppc7400",
+ pub const @"7400" = CpuModel{
+ .name = "7400",
.llvm_name = "7400",
.features = featureSet(&[_]Feature{
.altivec,
@@ -547,8 +567,8 @@ pub const cpu = struct {
.frsqrte,
}),
};
- pub const @"ppc7450" = CpuModel{
- .name = "ppc7450",
+ pub const @"7450" = CpuModel{
+ .name = "7450",
.llvm_name = "7450",
.features = featureSet(&[_]Feature{
.altivec,
@@ -556,16 +576,16 @@ pub const cpu = struct {
.frsqrte,
}),
};
- pub const @"ppc750" = CpuModel{
- .name = "ppc750",
+ pub const @"750" = CpuModel{
+ .name = "750",
.llvm_name = "750",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
- pub const @"ppc970" = CpuModel{
- .name = "ppc970",
+ pub const @"970" = CpuModel{
+ .name = "970",
.llvm_name = "970",
.features = featureSet(&[_]Feature{
.@"64bit",
@@ -602,32 +622,6 @@ pub const cpu = struct {
.stfiwx,
}),
};
- pub const a2q = CpuModel{
- .name = "a2q",
- .llvm_name = "a2q",
- .features = featureSet(&[_]Feature{
- .@"64bit",
- .booke,
- .cmpb,
- .fcpsgn,
- .fpcvt,
- .fprnd,
- .fre,
- .fres,
- .frsqrte,
- .frsqrtes,
- .fsqrt,
- .icbt,
- .isel,
- .ldbrx,
- .lfiwax,
- .mfocrf,
- .qpx,
- .recipprec,
- .slow_popcntd,
- .stfiwx,
- }),
- };
pub const e500 = CpuModel{
.name = "e500",
.llvm_name = "e500",
@@ -681,6 +675,7 @@ pub const cpu = struct {
.frsqrte,
.frsqrtes,
.fsqrt,
+ .fuse_store,
.htm,
.icbt,
.isa_v30_instructions,
@@ -689,6 +684,8 @@ pub const cpu = struct {
.ldbrx,
.lfiwax,
.mfocrf,
+ .mma,
+ .paired_vector_memops,
.partword_atomics,
.pcrelative_memops,
.popcntd,
@@ -697,6 +694,8 @@ pub const cpu = struct {
.power8_vector,
.power9_altivec,
.power9_vector,
+ .ppc_postra_sched,
+ .ppc_prera_sched,
.predictable_select_expensive,
.prefix_instrs,
.recipprec,
@@ -837,6 +836,7 @@ pub const cpu = struct {
.frsqrte,
.frsqrtes,
.fsqrt,
+ .fuse_store,
.htm,
.icbt,
.isa_v30_instructions,
@@ -845,6 +845,8 @@ pub const cpu = struct {
.ldbrx,
.lfiwax,
.mfocrf,
+ .mma,
+ .paired_vector_memops,
.partword_atomics,
.pcrelative_memops,
.popcntd,
@@ -853,6 +855,8 @@ pub const cpu = struct {
.power8_vector,
.power9_altivec,
.power9_vector,
+ .ppc_postra_sched,
+ .ppc_prera_sched,
.predictable_select_expensive,
.prefix_instrs,
.recipprec,
lib/std/target/riscv.zig
@@ -25,6 +25,9 @@ pub const Feature = enum {
experimental_zbr,
experimental_zbs,
experimental_zbt,
+ experimental_zfh,
+ experimental_zvamo,
+ experimental_zvlsseg,
f,
m,
no_rvc_hints,
@@ -66,6 +69,7 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
+ @setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
@@ -168,6 +172,27 @@ pub const all_features = blk: {
.description = "'Zbt' (Ternary 'B' Instructions)",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.experimental_zfh)] = .{
+ .llvm_name = "experimental-zfh",
+ .description = "'Zfh' (Half-Precision Floating-Point)",
+ .dependencies = featureSet(&[_]Feature{
+ .f,
+ }),
+ };
+ result[@enumToInt(Feature.experimental_zvamo)] = .{
+ .llvm_name = "experimental-zvamo",
+ .description = "'Zvamo'(Vector AMO Operations)",
+ .dependencies = featureSet(&[_]Feature{
+ .experimental_v,
+ }),
+ };
+ result[@enumToInt(Feature.experimental_zvlsseg)] = .{
+ .llvm_name = "experimental-zvlsseg",
+ .description = "'Zvlsseg' (Vector segment load/store instructions)",
+ .dependencies = featureSet(&[_]Feature{
+ .experimental_v,
+ }),
+ };
result[@enumToInt(Feature.f)] = .{
.llvm_name = "f",
.description = "'F' (Single-Precision Floating-Point)",
@@ -357,29 +382,6 @@ pub const all_features = blk: {
};
pub const cpu = struct {
- pub const baseline_rv32 = CpuModel{
- .name = "baseline_rv32",
- .llvm_name = null,
- .features = featureSet(&[_]Feature{
- .a,
- .c,
- .d,
- .f,
- .m,
- }),
- };
- pub const baseline_rv64 = CpuModel{
- .name = "baseline_rv64",
- .llvm_name = null,
- .features = featureSet(&[_]Feature{
- .@"64bit",
- .a,
- .c,
- .d,
- .f,
- .m,
- }),
- };
pub const generic_rv32 = CpuModel{
.name = "generic_rv32",
.llvm_name = "generic-rv32",
@@ -404,6 +406,18 @@ pub const cpu = struct {
.@"64bit",
}),
};
+ pub const sifive_7_rv32 = CpuModel{
+ .name = "sifive_7_rv32",
+ .llvm_name = "sifive-7-rv32",
+ .features = featureSet(&[_]Feature{}),
+ };
+ pub const sifive_7_rv64 = CpuModel{
+ .name = "sifive_7_rv64",
+ .llvm_name = "sifive-7-rv64",
+ .features = featureSet(&[_]Feature{
+ .@"64bit",
+ }),
+ };
pub const sifive_e31 = CpuModel{
.name = "sifive_e31",
.llvm_name = "sifive-e31",
@@ -413,6 +427,16 @@ pub const cpu = struct {
.m,
}),
};
+ pub const sifive_e76 = CpuModel{
+ .name = "sifive_e76",
+ .llvm_name = "sifive-e76",
+ .features = featureSet(&[_]Feature{
+ .a,
+ .c,
+ .f,
+ .m,
+ }),
+ };
pub const sifive_u54 = CpuModel{
.name = "sifive_u54",
.llvm_name = "sifive-u54",
@@ -425,4 +449,16 @@ pub const cpu = struct {
.m,
}),
};
+ pub const sifive_u74 = CpuModel{
+ .name = "sifive_u74",
+ .llvm_name = "sifive-u74",
+ .features = featureSet(&[_]Feature{
+ .@"64bit",
+ .a,
+ .c,
+ .d,
+ .f,
+ .m,
+ }),
+ };
};
lib/std/target/sparc.zig
@@ -32,6 +32,7 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
+ @setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
@@ -160,6 +161,11 @@ pub const cpu = struct {
.llvm_name = "f934",
.features = featureSet(&[_]Feature{}),
};
+ pub const generic = CpuModel{
+ .name = "generic",
+ .llvm_name = "generic",
+ .features = featureSet(&[_]Feature{}),
+ };
pub const gr712rc = CpuModel{
.name = "gr712rc",
.llvm_name = "gr712rc",
lib/std/target/systemz.zig
@@ -49,6 +49,7 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
+ @setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
lib/std/target/wasm.zig
@@ -24,6 +24,7 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
+ @setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
lib/std/target/x86.zig
@@ -8,9 +8,12 @@ const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;
pub const Feature = enum {
+ @"16bit_mode",
+ @"32bit_mode",
@"3dnow",
@"3dnowa",
@"64bit",
+ @"64bit_mode",
adx,
aes,
amx_bf16,
@@ -33,6 +36,7 @@ pub const Feature = enum {
avx512vnni,
avx512vp2intersect,
avx512vpopcntdq,
+ avxvnni,
bmi,
bmi2,
branchfusion,
@@ -64,11 +68,14 @@ pub const Feature = enum {
fma,
fma4,
fsgsbase,
+ fsrm,
fxsr,
gfni,
+ hreset,
idivl_to_divb,
idivq_to_divl,
invpcid,
+ kl,
lea_sp,
lea_uses_ag,
lvi_cfi,
@@ -76,12 +83,10 @@ pub const Feature = enum {
lwp,
lzcnt,
macrofusion,
- merge_to_threeway_branch,
mmx,
movbe,
movdir64b,
movdiri,
- mpx,
mwaitx,
nopl,
pad_short_functions,
@@ -129,6 +134,7 @@ pub const Feature = enum {
ssse3,
tbm,
tsxldtrk,
+ uintr,
use_aa,
use_glm_div_sqrt_costs,
vaes,
@@ -136,6 +142,7 @@ pub const Feature = enum {
vzeroupper,
waitpkg,
wbnoinvd,
+ widekl,
x87,
xop,
xsave,
@@ -147,9 +154,20 @@ pub const Feature = enum {
pub usingnamespace CpuFeature.feature_set_fns(Feature);
pub const all_features = blk: {
+ @setEvalBranchQuota(10000);
const len = @typeInfo(Feature).Enum.fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
+ result[@enumToInt(Feature.@"16bit_mode")] = .{
+ .llvm_name = "16bit-mode",
+ .description = "16-bit mode (i8086)",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ result[@enumToInt(Feature.@"32bit_mode")] = .{
+ .llvm_name = "32bit-mode",
+ .description = "32-bit mode (80386)",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
result[@enumToInt(Feature.@"3dnow")] = .{
.llvm_name = "3dnow",
.description = "Enable 3DNow! instructions",
@@ -169,6 +187,11 @@ pub const all_features = blk: {
.description = "Support 64-bit instructions",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.@"64bit_mode")] = .{
+ .llvm_name = "64bit-mode",
+ .description = "64-bit mode (x86_64)",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
result[@enumToInt(Feature.adx)] = .{
.llvm_name = "adx",
.description = "Support ADX instructions",
@@ -321,6 +344,13 @@ pub const all_features = blk: {
.avx512f,
}),
};
+ result[@enumToInt(Feature.avxvnni)] = .{
+ .llvm_name = "avxvnni",
+ .description = "Support AVX_VNNI encoding",
+ .dependencies = featureSet(&[_]Feature{
+ .avx2,
+ }),
+ };
result[@enumToInt(Feature.bmi)] = .{
.llvm_name = "bmi",
.description = "Support BMI instructions",
@@ -485,6 +515,11 @@ pub const all_features = blk: {
.description = "Support FS/GS Base instructions",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.fsrm)] = .{
+ .llvm_name = "fsrm",
+ .description = "REP MOVSB of short lengths is faster",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
result[@enumToInt(Feature.fxsr)] = .{
.llvm_name = "fxsr",
.description = "Support fxsave/fxrestore instructions",
@@ -497,6 +532,11 @@ pub const all_features = blk: {
.sse2,
}),
};
+ result[@enumToInt(Feature.hreset)] = .{
+ .llvm_name = "hreset",
+ .description = "Has hreset instruction",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
result[@enumToInt(Feature.idivl_to_divb)] = .{
.llvm_name = "idivl-to-divb",
.description = "Use 8-bit divide for positive values less than 256",
@@ -512,6 +552,13 @@ pub const all_features = blk: {
.description = "Invalidate Process-Context Identifier",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.kl)] = .{
+ .llvm_name = "kl",
+ .description = "Support Key Locker kl Instructions",
+ .dependencies = featureSet(&[_]Feature{
+ .sse2,
+ }),
+ };
result[@enumToInt(Feature.lea_sp)] = .{
.llvm_name = "lea-sp",
.description = "Use LEA for adjusting the stack pointer",
@@ -547,11 +594,6 @@ pub const all_features = blk: {
.description = "Various instructions can be fused with conditional branches",
.dependencies = featureSet(&[_]Feature{}),
};
- result[@enumToInt(Feature.merge_to_threeway_branch)] = .{
- .llvm_name = "merge-to-threeway-branch",
- .description = "Merge branches to a three-way conditional branch",
- .dependencies = featureSet(&[_]Feature{}),
- };
result[@enumToInt(Feature.mmx)] = .{
.llvm_name = "mmx",
.description = "Enable MMX instructions",
@@ -572,11 +614,6 @@ pub const all_features = blk: {
.description = "Support movdiri instruction",
.dependencies = featureSet(&[_]Feature{}),
};
- result[@enumToInt(Feature.mpx)] = .{
- .llvm_name = "mpx",
- .description = "Deprecated. Support MPX instructions",
- .dependencies = featureSet(&[_]Feature{}),
- };
result[@enumToInt(Feature.mwaitx)] = .{
.llvm_name = "mwaitx",
.description = "Enable MONITORX/MWAITX timer functionality",
@@ -691,7 +728,7 @@ pub const all_features = blk: {
};
result[@enumToInt(Feature.sahf)] = .{
.llvm_name = "sahf",
- .description = "Support LAHF and SAHF instructions",
+ .description = "Support LAHF and SAHF instructions in 64-bit mode",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.serialize)] = .{
@@ -835,6 +872,11 @@ pub const all_features = blk: {
.description = "Support TSXLDTRK instructions",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.uintr)] = .{
+ .llvm_name = "uintr",
+ .description = "Has UINTR Instructions",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
result[@enumToInt(Feature.use_aa)] = .{
.llvm_name = "use-aa",
.description = "Use alias analysis during codegen",
@@ -876,6 +918,13 @@ pub const all_features = blk: {
.description = "Write Back No Invalidate",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.widekl)] = .{
+ .llvm_name = "widekl",
+ .description = "Support Key Locker wide Instructions",
+ .dependencies = featureSet(&[_]Feature{
+ .kl,
+ }),
+ };
result[@enumToInt(Feature.x87)] = .{
.llvm_name = "x87",
.description = "Enable X87 float instructions",
@@ -923,6 +972,53 @@ pub const all_features = blk: {
};
pub const cpu = struct {
+ pub const alderlake = CpuModel{
+ .name = "alderlake",
+ .llvm_name = "alderlake",
+ .features = featureSet(&[_]Feature{
+ .@"64bit",
+ .adx,
+ .aes,
+ .avx,
+ .avx2,
+ .avxvnni,
+ .bmi,
+ .bmi2,
+ .cldemote,
+ .clflushopt,
+ .cmov,
+ .cx16,
+ .cx8,
+ .ermsb,
+ .f16c,
+ .fma,
+ .fsgsbase,
+ .fxsr,
+ .hreset,
+ .invpcid,
+ .lzcnt,
+ .mmx,
+ .movbe,
+ .nopl,
+ .pclmul,
+ .popcnt,
+ .prfchw,
+ .ptwrite,
+ .rdrnd,
+ .rdseed,
+ .sahf,
+ .serialize,
+ .sgx,
+ .sse2,
+ .sse4_2,
+ .waitpkg,
+ .x87,
+ .xsave,
+ .xsavec,
+ .xsaveopt,
+ .xsaves,
+ }),
+ };
pub const amdfam10 = CpuModel{
.name = "amdfam10",
.llvm_name = "amdfam10",
@@ -932,16 +1028,13 @@ pub const cpu = struct {
.cmov,
.cx16,
.cx8,
- .fast_scalar_shift_masks,
.fxsr,
.lzcnt,
.nopl,
.popcnt,
.prfchw,
.sahf,
- .slow_shld,
.sse4a,
- .vzeroupper,
.x87,
}),
};
@@ -953,9 +1046,6 @@ pub const cpu = struct {
.cmov,
.cx8,
.nopl,
- .slow_shld,
- .slow_unaligned_mem_16,
- .vzeroupper,
.x87,
}),
};
@@ -968,10 +1058,7 @@ pub const cpu = struct {
.cx8,
.fxsr,
.nopl,
- .slow_shld,
- .slow_unaligned_mem_16,
.sse,
- .vzeroupper,
.x87,
}),
};
@@ -983,13 +1070,9 @@ pub const cpu = struct {
.@"64bit",
.cmov,
.cx8,
- .fast_scalar_shift_masks,
.fxsr,
.nopl,
- .slow_shld,
- .slow_unaligned_mem_16,
.sse2,
- .vzeroupper,
.x87,
}),
};
@@ -1002,10 +1085,7 @@ pub const cpu = struct {
.cx8,
.fxsr,
.nopl,
- .slow_shld,
- .slow_unaligned_mem_16,
.sse,
- .vzeroupper,
.x87,
}),
};
@@ -1017,9 +1097,6 @@ pub const cpu = struct {
.cmov,
.cx8,
.nopl,
- .slow_shld,
- .slow_unaligned_mem_16,
- .vzeroupper,
.x87,
}),
};
@@ -1032,10 +1109,7 @@ pub const cpu = struct {
.cx8,
.fxsr,
.nopl,
- .slow_shld,
- .slow_unaligned_mem_16,
.sse,
- .vzeroupper,
.x87,
}),
};
@@ -1047,13 +1121,9 @@ pub const cpu = struct {
.@"64bit",
.cmov,
.cx8,
- .fast_scalar_shift_masks,
.fxsr,
.nopl,
- .slow_shld,
- .slow_unaligned_mem_16,
.sse2,
- .vzeroupper,
.x87,
}),
};
@@ -1066,13 +1136,9 @@ pub const cpu = struct {
.cmov,
.cx16,
.cx8,
- .fast_scalar_shift_masks,
.fxsr,
.nopl,
- .slow_shld,
- .slow_unaligned_mem_16,
.sse3,
- .vzeroupper,
.x87,
}),
};
@@ -1085,19 +1151,11 @@ pub const cpu = struct {
.cx16,
.cx8,
.fxsr,
- .idivl_to_divb,
- .idivq_to_divl,
- .lea_sp,
- .lea_uses_ag,
.mmx,
.movbe,
.nopl,
- .pad_short_functions,
.sahf,
- .slow_two_mem_ops,
- .slow_unaligned_mem_16,
.ssse3,
- .vzeroupper,
.x87,
}),
};
@@ -1110,16 +1168,13 @@ pub const cpu = struct {
.cmov,
.cx16,
.cx8,
- .fast_scalar_shift_masks,
.fxsr,
.lzcnt,
.nopl,
.popcnt,
.prfchw,
.sahf,
- .slow_shld,
.sse4a,
- .vzeroupper,
.x87,
}),
};
@@ -1129,12 +1184,9 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.@"64bit",
.aes,
- .branchfusion,
.cmov,
.cx16,
.cx8,
- .fast_11bytenop,
- .fast_scalar_shift_masks,
.fxsr,
.lwp,
.lzcnt,
@@ -1144,8 +1196,6 @@ pub const cpu = struct {
.popcnt,
.prfchw,
.sahf,
- .slow_shld,
- .vzeroupper,
.x87,
.xop,
.xsave,
@@ -1158,14 +1208,11 @@ pub const cpu = struct {
.@"64bit",
.aes,
.bmi,
- .branchfusion,
.cmov,
.cx16,
.cx8,
.f16c,
- .fast_11bytenop,
.fast_bextr,
- .fast_scalar_shift_masks,
.fma,
.fxsr,
.lwp,
@@ -1176,9 +1223,7 @@ pub const cpu = struct {
.popcnt,
.prfchw,
.sahf,
- .slow_shld,
.tbm,
- .vzeroupper,
.x87,
.xop,
.xsave,
@@ -1191,14 +1236,11 @@ pub const cpu = struct {
.@"64bit",
.aes,
.bmi,
- .branchfusion,
.cmov,
.cx16,
.cx8,
.f16c,
- .fast_11bytenop,
.fast_bextr,
- .fast_scalar_shift_masks,
.fma,
.fsgsbase,
.fxsr,
@@ -1210,9 +1252,7 @@ pub const cpu = struct {
.popcnt,
.prfchw,
.sahf,
- .slow_shld,
.tbm,
- .vzeroupper,
.x87,
.xop,
.xsave,
@@ -1228,14 +1268,11 @@ pub const cpu = struct {
.avx2,
.bmi,
.bmi2,
- .branchfusion,
.cmov,
.cx16,
.cx8,
.f16c,
- .fast_11bytenop,
.fast_bextr,
- .fast_scalar_shift_masks,
.fma,
.fsgsbase,
.fxsr,
@@ -1250,9 +1287,7 @@ pub const cpu = struct {
.prfchw,
.rdrnd,
.sahf,
- .slow_shld,
.tbm,
- .vzeroupper,
.x87,
.xop,
.xsave,
@@ -1268,19 +1303,11 @@ pub const cpu = struct {
.cx16,
.cx8,
.fxsr,
- .idivl_to_divb,
- .idivq_to_divl,
- .lea_sp,
- .lea_uses_ag,
.mmx,
.movbe,
.nopl,
- .pad_short_functions,
.sahf,
- .slow_two_mem_ops,
- .slow_unaligned_mem_16,
.ssse3,
- .vzeroupper,
.x87,
}),
};
@@ -1299,20 +1326,11 @@ pub const cpu = struct {
.cx8,
.ermsb,
.f16c,
- .false_deps_lzcnt_tzcnt,
- .false_deps_popcnt,
- .fast_15bytenop,
- .fast_scalar_fsqrt,
- .fast_shld_rotate,
- .fast_variable_shuffle,
.fma,
.fsgsbase,
.fxsr,
- .idivq_to_divl,
.invpcid,
.lzcnt,
- .macrofusion,
- .merge_to_threeway_branch,
.mmx,
.movbe,
.nopl,
@@ -1322,9 +1340,8 @@ pub const cpu = struct {
.rdrnd,
.rdseed,
.sahf,
- .slow_3ops_lea,
+ .sse2,
.sse4_2,
- .vzeroupper,
.x87,
.xsave,
.xsaveopt,
@@ -1338,9 +1355,6 @@ pub const cpu = struct {
.cmov,
.cx16,
.cx8,
- .fast_15bytenop,
- .fast_scalar_shift_masks,
- .fast_vector_shift_masks,
.fxsr,
.lzcnt,
.mmx,
@@ -1348,10 +1362,8 @@ pub const cpu = struct {
.popcnt,
.prfchw,
.sahf,
- .slow_shld,
.sse4a,
.ssse3,
- .vzeroupper,
.x87,
}),
};
@@ -1367,12 +1379,6 @@ pub const cpu = struct {
.cx16,
.cx8,
.f16c,
- .fast_15bytenop,
- .fast_bextr,
- .fast_hops,
- .fast_lzcnt,
- .fast_scalar_shift_masks,
- .fast_vector_shift_masks,
.fxsr,
.lzcnt,
.mmx,
@@ -1382,7 +1388,6 @@ pub const cpu = struct {
.popcnt,
.prfchw,
.sahf,
- .slow_shld,
.sse4a,
.ssse3,
.x87,
@@ -1395,8 +1400,6 @@ pub const cpu = struct {
.llvm_name = "c3",
.features = featureSet(&[_]Feature{
.@"3dnow",
- .slow_unaligned_mem_16,
- .vzeroupper,
.x87,
}),
};
@@ -1408,9 +1411,7 @@ pub const cpu = struct {
.cx8,
.fxsr,
.mmx,
- .slow_unaligned_mem_16,
.sse,
- .vzeroupper,
.x87,
}),
};
@@ -1438,36 +1439,25 @@ pub const cpu = struct {
.cx8,
.ermsb,
.f16c,
- .fast_15bytenop,
- .fast_gather,
- .fast_scalar_fsqrt,
- .fast_shld_rotate,
- .fast_variable_shuffle,
- .fast_vector_fsqrt,
.fma,
.fsgsbase,
.fxsr,
- .idivq_to_divl,
.invpcid,
.lzcnt,
- .macrofusion,
- .merge_to_threeway_branch,
.mmx,
.movbe,
.nopl,
.pclmul,
.pku,
.popcnt,
- .prefer_256_bit,
.prfchw,
.rdrnd,
.rdseed,
.sahf,
.sgx,
.sha,
- .slow_3ops_lea,
+ .sse2,
.sse4_2,
- .vzeroupper,
.x87,
.xsave,
.xsavec,
@@ -1499,35 +1489,23 @@ pub const cpu = struct {
.cx8,
.ermsb,
.f16c,
- .false_deps_popcnt,
- .fast_15bytenop,
- .fast_gather,
- .fast_scalar_fsqrt,
- .fast_shld_rotate,
- .fast_variable_shuffle,
- .fast_vector_fsqrt,
.fma,
.fsgsbase,
.fxsr,
- .idivq_to_divl,
.invpcid,
.lzcnt,
- .macrofusion,
- .merge_to_threeway_branch,
.mmx,
.movbe,
.nopl,
.pclmul,
.pku,
.popcnt,
- .prefer_256_bit,
.prfchw,
.rdrnd,
.rdseed,
.sahf,
- .slow_3ops_lea,
+ .sse2,
.sse4_2,
- .vzeroupper,
.x87,
.xsave,
.xsavec,
@@ -1560,35 +1538,23 @@ pub const cpu = struct {
.cx8,
.ermsb,
.f16c,
- .false_deps_popcnt,
- .fast_15bytenop,
- .fast_gather,
- .fast_scalar_fsqrt,
- .fast_shld_rotate,
- .fast_variable_shuffle,
- .fast_vector_fsqrt,
.fma,
.fsgsbase,
.fxsr,
- .idivq_to_divl,
.invpcid,
.lzcnt,
- .macrofusion,
- .merge_to_threeway_branch,
.mmx,
.movbe,
.nopl,
.pclmul,
.pku,
.popcnt,
- .prefer_256_bit,
.prfchw,
.rdrnd,
.rdseed,
.sahf,
- .slow_3ops_lea,
+ .sse2,
.sse4_2,
- .vzeroupper,
.x87,
.xsave,
.xsavec,
@@ -1606,25 +1572,16 @@ pub const cpu = struct {
.cx16,
.cx8,
.f16c,
- .false_deps_popcnt,
- .fast_15bytenop,
- .fast_scalar_fsqrt,
- .fast_shld_rotate,
.fsgsbase,
.fxsr,
- .idivq_to_divl,
- .macrofusion,
- .merge_to_threeway_branch,
.mmx,
.nopl,
.pclmul,
.popcnt,
.rdrnd,
.sahf,
- .slow_3ops_lea,
- .slow_unaligned_mem_32,
+ .sse2,
.sse4_2,
- .vzeroupper,
.x87,
.xsave,
.xsaveopt,
@@ -1644,20 +1601,11 @@ pub const cpu = struct {
.cx8,
.ermsb,
.f16c,
- .false_deps_lzcnt_tzcnt,
- .false_deps_popcnt,
- .fast_15bytenop,
- .fast_scalar_fsqrt,
- .fast_shld_rotate,
- .fast_variable_shuffle,
.fma,
.fsgsbase,
.fxsr,
- .idivq_to_divl,
.invpcid,
.lzcnt,
- .macrofusion,
- .merge_to_threeway_branch,
.mmx,
.movbe,
.nopl,
@@ -1665,9 +1613,8 @@ pub const cpu = struct {
.popcnt,
.rdrnd,
.sahf,
- .slow_3ops_lea,
+ .sse2,
.sse4_2,
- .vzeroupper,
.x87,
.xsave,
.xsaveopt,
@@ -1682,13 +1629,10 @@ pub const cpu = struct {
.cx16,
.cx8,
.fxsr,
- .macrofusion,
.mmx,
.nopl,
.sahf,
- .slow_unaligned_mem_16,
.ssse3,
- .vzeroupper,
.x87,
}),
};
@@ -1701,13 +1645,12 @@ pub const cpu = struct {
.cx16,
.cx8,
.fxsr,
- .macrofusion,
.mmx,
.nopl,
.popcnt,
.sahf,
+ .sse2,
.sse4_2,
- .vzeroupper,
.x87,
}),
};
@@ -1720,23 +1663,14 @@ pub const cpu = struct {
.cmov,
.cx16,
.cx8,
- .false_deps_popcnt,
- .fast_15bytenop,
- .fast_scalar_fsqrt,
- .fast_shld_rotate,
.fxsr,
- .idivq_to_divl,
- .macrofusion,
- .merge_to_threeway_branch,
.mmx,
.nopl,
.pclmul,
.popcnt,
.sahf,
- .slow_3ops_lea,
- .slow_unaligned_mem_32,
+ .sse2,
.sse4_2,
- .vzeroupper,
.x87,
.xsave,
.xsaveopt,
@@ -1746,9 +1680,8 @@ pub const cpu = struct {
.name = "generic",
.llvm_name = "generic",
.features = featureSet(&[_]Feature{
+ .@"64bit",
.cx8,
- .slow_unaligned_mem_16,
- .vzeroupper,
.x87,
}),
};
@@ -1758,8 +1691,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.@"3dnowa",
.cx8,
- .slow_unaligned_mem_16,
- .vzeroupper,
.x87,
}),
};
@@ -1773,7 +1704,6 @@ pub const cpu = struct {
.cmov,
.cx16,
.cx8,
- .false_deps_popcnt,
.fsgsbase,
.fxsr,
.mmx,
@@ -1786,13 +1716,8 @@ pub const cpu = struct {
.rdseed,
.sahf,
.sha,
- .slow_incdec,
- .slow_lea,
- .slow_two_mem_ops,
.sse4_2,
.ssse3,
- .use_glm_div_sqrt_costs,
- .vzeroupper,
.x87,
.xsave,
.xsavec,
@@ -1825,13 +1750,8 @@ pub const cpu = struct {
.sahf,
.sgx,
.sha,
- .slow_incdec,
- .slow_lea,
- .slow_two_mem_ops,
.sse4_2,
.ssse3,
- .use_glm_div_sqrt_costs,
- .vzeroupper,
.x87,
.xsave,
.xsavec,
@@ -1853,20 +1773,11 @@ pub const cpu = struct {
.cx8,
.ermsb,
.f16c,
- .false_deps_lzcnt_tzcnt,
- .false_deps_popcnt,
- .fast_15bytenop,
- .fast_scalar_fsqrt,
- .fast_shld_rotate,
- .fast_variable_shuffle,
.fma,
.fsgsbase,
.fxsr,
- .idivq_to_divl,
.invpcid,
.lzcnt,
- .macrofusion,
- .merge_to_threeway_branch,
.mmx,
.movbe,
.nopl,
@@ -1874,9 +1785,8 @@ pub const cpu = struct {
.popcnt,
.rdrnd,
.sahf,
- .slow_3ops_lea,
+ .sse2,
.sse4_2,
- .vzeroupper,
.x87,
.xsave,
.xsaveopt,
@@ -1886,8 +1796,6 @@ pub const cpu = struct {
.name = "_i386",
.llvm_name = "i386",
.features = featureSet(&[_]Feature{
- .slow_unaligned_mem_16,
- .vzeroupper,
.x87,
}),
};
@@ -1895,8 +1803,6 @@ pub const cpu = struct {
.name = "_i486",
.llvm_name = "i486",
.features = featureSet(&[_]Feature{
- .slow_unaligned_mem_16,
- .vzeroupper,
.x87,
}),
};
@@ -1905,8 +1811,6 @@ pub const cpu = struct {
.llvm_name = "i586",
.features = featureSet(&[_]Feature{
.cx8,
- .slow_unaligned_mem_16,
- .vzeroupper,
.x87,
}),
};
@@ -1916,8 +1820,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.cmov,
.cx8,
- .slow_unaligned_mem_16,
- .vzeroupper,
.x87,
}),
};
@@ -1950,28 +1852,19 @@ pub const cpu = struct {
.cx8,
.ermsb,
.f16c,
- .fast_15bytenop,
- .fast_gather,
- .fast_scalar_fsqrt,
- .fast_shld_rotate,
- .fast_variable_shuffle,
- .fast_vector_fsqrt,
.fma,
.fsgsbase,
+ .fsrm,
.fxsr,
.gfni,
- .idivq_to_divl,
.invpcid,
.lzcnt,
- .macrofusion,
- .merge_to_threeway_branch,
.mmx,
.movbe,
.nopl,
.pclmul,
.pku,
.popcnt,
- .prefer_256_bit,
.prfchw,
.rdpid,
.rdrnd,
@@ -1979,11 +1872,10 @@ pub const cpu = struct {
.sahf,
.sgx,
.sha,
- .slow_3ops_lea,
+ .sse2,
.sse4_2,
.vaes,
.vpclmulqdq,
- .vzeroupper,
.x87,
.xsave,
.xsavec,
@@ -2020,21 +1912,13 @@ pub const cpu = struct {
.cx8,
.ermsb,
.f16c,
- .fast_15bytenop,
- .fast_gather,
- .fast_scalar_fsqrt,
- .fast_shld_rotate,
- .fast_variable_shuffle,
- .fast_vector_fsqrt,
.fma,
.fsgsbase,
+ .fsrm,
.fxsr,
.gfni,
- .idivq_to_divl,
.invpcid,
.lzcnt,
- .macrofusion,
- .merge_to_threeway_branch,
.mmx,
.movbe,
.nopl,
@@ -2042,7 +1926,6 @@ pub const cpu = struct {
.pconfig,
.pku,
.popcnt,
- .prefer_256_bit,
.prfchw,
.rdpid,
.rdrnd,
@@ -2050,11 +1933,10 @@ pub const cpu = struct {
.sahf,
.sgx,
.sha,
- .slow_3ops_lea,
+ .sse2,
.sse4_2,
.vaes,
.vpclmulqdq,
- .vzeroupper,
.wbnoinvd,
.x87,
.xsave,
@@ -2073,25 +1955,16 @@ pub const cpu = struct {
.cx16,
.cx8,
.f16c,
- .false_deps_popcnt,
- .fast_15bytenop,
- .fast_scalar_fsqrt,
- .fast_shld_rotate,
.fsgsbase,
.fxsr,
- .idivq_to_divl,
- .macrofusion,
- .merge_to_threeway_branch,
.mmx,
.nopl,
.pclmul,
.popcnt,
.rdrnd,
.sahf,
- .slow_3ops_lea,
- .slow_unaligned_mem_32,
+ .sse2,
.sse4_2,
- .vzeroupper,
.x87,
.xsave,
.xsaveopt,
@@ -2103,8 +1976,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.cx8,
.mmx,
- .slow_unaligned_mem_16,
- .vzeroupper,
.x87,
}),
};
@@ -2114,8 +1985,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.@"3dnow",
.cx8,
- .slow_unaligned_mem_16,
- .vzeroupper,
.x87,
}),
};
@@ -2125,8 +1994,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.@"3dnow",
.cx8,
- .slow_unaligned_mem_16,
- .vzeroupper,
.x87,
}),
};
@@ -2138,13 +2005,9 @@ pub const cpu = struct {
.@"64bit",
.cmov,
.cx8,
- .fast_scalar_shift_masks,
.fxsr,
.nopl,
- .slow_shld,
- .slow_unaligned_mem_16,
.sse2,
- .vzeroupper,
.x87,
}),
};
@@ -2157,13 +2020,9 @@ pub const cpu = struct {
.cmov,
.cx16,
.cx8,
- .fast_scalar_shift_masks,
.fxsr,
.nopl,
- .slow_shld,
- .slow_unaligned_mem_16,
.sse3,
- .vzeroupper,
.x87,
}),
};
@@ -2184,27 +2043,20 @@ pub const cpu = struct {
.cx16,
.cx8,
.f16c,
- .fast_gather,
.fma,
.fsgsbase,
.fxsr,
- .idivq_to_divl,
.lzcnt,
.mmx,
.movbe,
.nopl,
.pclmul,
.popcnt,
- .prefer_mask_registers,
.prefetchwt1,
.prfchw,
.rdrnd,
.rdseed,
.sahf,
- .slow_3ops_lea,
- .slow_incdec,
- .slow_pmaddwd,
- .slow_two_mem_ops,
.x87,
.xsave,
.xsaveopt,
@@ -2228,27 +2080,20 @@ pub const cpu = struct {
.cx16,
.cx8,
.f16c,
- .fast_gather,
.fma,
.fsgsbase,
.fxsr,
- .idivq_to_divl,
.lzcnt,
.mmx,
.movbe,
.nopl,
.pclmul,
.popcnt,
- .prefer_mask_registers,
.prefetchwt1,
.prfchw,
.rdrnd,
.rdseed,
.sahf,
- .slow_3ops_lea,
- .slow_incdec,
- .slow_pmaddwd,
- .slow_two_mem_ops,
.x87,
.xsave,
.xsaveopt,
@@ -2258,7 +2103,7 @@ pub const cpu = struct {
.name = "lakemont",
.llvm_name = "lakemont",
.features = featureSet(&[_]Feature{
- .vzeroupper,
+ .cx8,
}),
};
pub const nehalem = CpuModel{
@@ -2270,13 +2115,12 @@ pub const cpu = struct {
.cx16,
.cx8,
.fxsr,
- .macrofusion,
.mmx,
.nopl,
.popcnt,
.sahf,
+ .sse2,
.sse4_2,
- .vzeroupper,
.x87,
}),
};
@@ -2291,9 +2135,7 @@ pub const cpu = struct {
.fxsr,
.mmx,
.nopl,
- .slow_unaligned_mem_16,
.sse3,
- .vzeroupper,
.x87,
}),
};
@@ -2305,13 +2147,9 @@ pub const cpu = struct {
.@"64bit",
.cmov,
.cx8,
- .fast_scalar_shift_masks,
.fxsr,
.nopl,
- .slow_shld,
- .slow_unaligned_mem_16,
.sse2,
- .vzeroupper,
.x87,
}),
};
@@ -2324,13 +2162,9 @@ pub const cpu = struct {
.cmov,
.cx16,
.cx8,
- .fast_scalar_shift_masks,
.fxsr,
.nopl,
- .slow_shld,
- .slow_unaligned_mem_16,
.sse3,
- .vzeroupper,
.x87,
}),
};
@@ -2343,13 +2177,10 @@ pub const cpu = struct {
.cx16,
.cx8,
.fxsr,
- .macrofusion,
.mmx,
.nopl,
.sahf,
- .slow_unaligned_mem_16,
.sse4_1,
- .vzeroupper,
.x87,
}),
};
@@ -2358,8 +2189,6 @@ pub const cpu = struct {
.llvm_name = "pentium",
.features = featureSet(&[_]Feature{
.cx8,
- .slow_unaligned_mem_16,
- .vzeroupper,
.x87,
}),
};
@@ -2372,9 +2201,7 @@ pub const cpu = struct {
.fxsr,
.mmx,
.nopl,
- .slow_unaligned_mem_16,
.sse2,
- .vzeroupper,
.x87,
}),
};
@@ -2384,8 +2211,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.cx8,
.mmx,
- .slow_unaligned_mem_16,
- .vzeroupper,
.x87,
}),
};
@@ -2398,8 +2223,6 @@ pub const cpu = struct {
.fxsr,
.mmx,
.nopl,
- .slow_unaligned_mem_16,
- .vzeroupper,
.x87,
}),
};
@@ -2412,9 +2235,7 @@ pub const cpu = struct {
.fxsr,
.mmx,
.nopl,
- .slow_unaligned_mem_16,
.sse,
- .vzeroupper,
.x87,
}),
};
@@ -2427,9 +2248,7 @@ pub const cpu = struct {
.fxsr,
.mmx,
.nopl,
- .slow_unaligned_mem_16,
.sse,
- .vzeroupper,
.x87,
}),
};
@@ -2442,9 +2261,7 @@ pub const cpu = struct {
.fxsr,
.mmx,
.nopl,
- .slow_unaligned_mem_16,
.sse2,
- .vzeroupper,
.x87,
}),
};
@@ -2457,9 +2274,7 @@ pub const cpu = struct {
.fxsr,
.mmx,
.nopl,
- .slow_unaligned_mem_16,
.sse2,
- .vzeroupper,
.x87,
}),
};
@@ -2470,8 +2285,6 @@ pub const cpu = struct {
.cmov,
.cx8,
.nopl,
- .slow_unaligned_mem_16,
- .vzeroupper,
.x87,
}),
};
@@ -2484,9 +2297,7 @@ pub const cpu = struct {
.fxsr,
.mmx,
.nopl,
- .slow_unaligned_mem_16,
.sse3,
- .vzeroupper,
.x87,
}),
};
@@ -2499,26 +2310,95 @@ pub const cpu = struct {
.cmov,
.cx16,
.cx8,
- .false_deps_popcnt,
- .fast_15bytenop,
- .fast_scalar_fsqrt,
- .fast_shld_rotate,
.fxsr,
- .idivq_to_divl,
- .macrofusion,
- .merge_to_threeway_branch,
.mmx,
.nopl,
.pclmul,
.popcnt,
.sahf,
- .slow_3ops_lea,
- .slow_unaligned_mem_32,
+ .sse2,
+ .sse4_2,
+ .x87,
+ .xsave,
+ .xsaveopt,
+ }),
+ };
+ pub const sapphirerapids = CpuModel{
+ .name = "sapphirerapids",
+ .llvm_name = "sapphirerapids",
+ .features = featureSet(&[_]Feature{
+ .@"64bit",
+ .adx,
+ .aes,
+ .amx_bf16,
+ .amx_int8,
+ .amx_tile,
+ .avx,
+ .avx2,
+ .avx512bf16,
+ .avx512bitalg,
+ .avx512bw,
+ .avx512cd,
+ .avx512dq,
+ .avx512f,
+ .avx512ifma,
+ .avx512vbmi,
+ .avx512vbmi2,
+ .avx512vl,
+ .avx512vnni,
+ .avx512vp2intersect,
+ .avx512vpopcntdq,
+ .avxvnni,
+ .bmi,
+ .bmi2,
+ .cldemote,
+ .clflushopt,
+ .clwb,
+ .cmov,
+ .cx16,
+ .cx8,
+ .enqcmd,
+ .ermsb,
+ .f16c,
+ .fma,
+ .fsgsbase,
+ .fsrm,
+ .fxsr,
+ .gfni,
+ .invpcid,
+ .lzcnt,
+ .mmx,
+ .movbe,
+ .movdir64b,
+ .movdiri,
+ .nopl,
+ .pclmul,
+ .pconfig,
+ .pku,
+ .popcnt,
+ .prfchw,
+ .ptwrite,
+ .rdpid,
+ .rdrnd,
+ .rdseed,
+ .sahf,
+ .serialize,
+ .sgx,
+ .sha,
+ .shstk,
+ .sse2,
.sse4_2,
- .vzeroupper,
+ .tsxldtrk,
+ .uintr,
+ .vaes,
+ .vpclmulqdq,
+ .waitpkg,
+ .wbnoinvd,
.x87,
.xsave,
+ .xsavec,
.xsaveopt,
+ .xsaves,
}),
};
pub const silvermont = CpuModel{
@@ -2529,10 +2409,7 @@ pub const cpu = struct {
.cmov,
.cx16,
.cx8,
- .false_deps_popcnt,
- .fast_7bytenop,
.fxsr,
- .idivq_to_divl,
.mmx,
.movbe,
.nopl,
@@ -2541,13 +2418,8 @@ pub const cpu = struct {
.prfchw,
.rdrnd,
.sahf,
- .slow_incdec,
- .slow_lea,
- .slow_pmulld,
- .slow_two_mem_ops,
.sse4_2,
.ssse3,
- .vzeroupper,
.x87,
}),
};
@@ -2574,35 +2446,23 @@ pub const cpu = struct {
.cx8,
.ermsb,
.f16c,
- .false_deps_popcnt,
- .fast_15bytenop,
- .fast_gather,
- .fast_scalar_fsqrt,
- .fast_shld_rotate,
- .fast_variable_shuffle,
- .fast_vector_fsqrt,
.fma,
.fsgsbase,
.fxsr,
- .idivq_to_divl,
.invpcid,
.lzcnt,
- .macrofusion,
- .merge_to_threeway_branch,
.mmx,
.movbe,
.nopl,
.pclmul,
.pku,
.popcnt,
- .prefer_256_bit,
.prfchw,
.rdrnd,
.rdseed,
.sahf,
- .slow_3ops_lea,
+ .sse2,
.sse4_2,
- .vzeroupper,
.x87,
.xsave,
.xsavec,
@@ -2627,21 +2487,11 @@ pub const cpu = struct {
.cx8,
.ermsb,
.f16c,
- .false_deps_popcnt,
- .fast_15bytenop,
- .fast_gather,
- .fast_scalar_fsqrt,
- .fast_shld_rotate,
- .fast_variable_shuffle,
- .fast_vector_fsqrt,
.fma,
.fsgsbase,
.fxsr,
- .idivq_to_divl,
.invpcid,
.lzcnt,
- .macrofusion,
- .merge_to_threeway_branch,
.mmx,
.movbe,
.nopl,
@@ -2652,9 +2502,8 @@ pub const cpu = struct {
.rdseed,
.sahf,
.sgx,
- .slow_3ops_lea,
+ .sse2,
.sse4_2,
- .vzeroupper,
.x87,
.xsave,
.xsavec,
@@ -2685,35 +2534,23 @@ pub const cpu = struct {
.cx8,
.ermsb,
.f16c,
- .false_deps_popcnt,
- .fast_15bytenop,
- .fast_gather,
- .fast_scalar_fsqrt,
- .fast_shld_rotate,
- .fast_variable_shuffle,
- .fast_vector_fsqrt,
.fma,
.fsgsbase,
.fxsr,
- .idivq_to_divl,
.invpcid,
.lzcnt,
- .macrofusion,
- .merge_to_threeway_branch,
.mmx,
.movbe,
.nopl,
.pclmul,
.pku,
.popcnt,
- .prefer_256_bit,
.prfchw,
.rdrnd,
.rdseed,
.sahf,
- .slow_3ops_lea,
+ .sse2,
.sse4_2,
- .vzeroupper,
.x87,
.xsave,
.xsavec,
@@ -2729,10 +2566,7 @@ pub const cpu = struct {
.cmov,
.cx16,
.cx8,
- .false_deps_popcnt,
- .fast_7bytenop,
.fxsr,
- .idivq_to_divl,
.mmx,
.movbe,
.nopl,
@@ -2741,13 +2575,8 @@ pub const cpu = struct {
.prfchw,
.rdrnd,
.sahf,
- .slow_incdec,
- .slow_lea,
- .slow_pmulld,
- .slow_two_mem_ops,
.sse4_2,
.ssse3,
- .vzeroupper,
.x87,
}),
};
@@ -2781,21 +2610,13 @@ pub const cpu = struct {
.cx8,
.ermsb,
.f16c,
- .fast_15bytenop,
- .fast_gather,
- .fast_scalar_fsqrt,
- .fast_shld_rotate,
- .fast_variable_shuffle,
- .fast_vector_fsqrt,
.fma,
.fsgsbase,
+ .fsrm,
.fxsr,
.gfni,
- .idivq_to_divl,
.invpcid,
.lzcnt,
- .macrofusion,
- .merge_to_threeway_branch,
.mmx,
.movbe,
.movdir64b,
@@ -2804,7 +2625,6 @@ pub const cpu = struct {
.pclmul,
.pku,
.popcnt,
- .prefer_256_bit,
.prfchw,
.rdpid,
.rdrnd,
@@ -2813,11 +2633,10 @@ pub const cpu = struct {
.sgx,
.sha,
.shstk,
- .slow_3ops_lea,
+ .sse2,
.sse4_2,
.vaes,
.vpclmulqdq,
- .vzeroupper,
.x87,
.xsave,
.xsavec,
@@ -2852,13 +2671,8 @@ pub const cpu = struct {
.sahf,
.sgx,
.sha,
- .slow_incdec,
- .slow_lea,
- .slow_two_mem_ops,
.sse4_2,
.ssse3,
- .use_glm_div_sqrt_costs,
- .vzeroupper,
.x87,
.xsave,
.xsavec,
@@ -2875,14 +2689,13 @@ pub const cpu = struct {
.cx16,
.cx8,
.fxsr,
- .macrofusion,
.mmx,
.nopl,
.pclmul,
.popcnt,
.sahf,
+ .sse2,
.sse4_2,
- .vzeroupper,
.x87,
}),
};
@@ -2891,8 +2704,6 @@ pub const cpu = struct {
.llvm_name = "winchip-c6",
.features = featureSet(&[_]Feature{
.mmx,
- .slow_unaligned_mem_16,
- .vzeroupper,
.x87,
}),
};
@@ -2901,8 +2712,6 @@ pub const cpu = struct {
.llvm_name = "winchip2",
.features = featureSet(&[_]Feature{
.@"3dnow",
- .slow_unaligned_mem_16,
- .vzeroupper,
.x87,
}),
};
@@ -2914,17 +2723,86 @@ pub const cpu = struct {
.cmov,
.cx8,
.fxsr,
- .idivq_to_divl,
- .macrofusion,
.mmx,
.nopl,
- .slow_3ops_lea,
- .slow_incdec,
.sse2,
- .vzeroupper,
.x87,
}),
};
+ pub const x86_64_v2 = CpuModel{
+ .name = "x86_64_v2",
+ .llvm_name = "x86-64-v2",
+ .features = featureSet(&[_]Feature{
+ .@"64bit",
+ .cmov,
+ .cx16,
+ .cx8,
+ .fxsr,
+ .mmx,
+ .nopl,
+ .popcnt,
+ .sahf,
+ .sse2,
+ .sse4_2,
+ .x87,
+ }),
+ };
+ pub const x86_64_v3 = CpuModel{
+ .name = "x86_64_v3",
+ .llvm_name = "x86-64-v3",
+ .features = featureSet(&[_]Feature{
+ .@"64bit",
+ .avx2,
+ .bmi,
+ .bmi2,
+ .cmov,
+ .cx16,
+ .cx8,
+ .f16c,
+ .fma,
+ .fxsr,
+ .lzcnt,
+ .mmx,
+ .movbe,
+ .nopl,
+ .popcnt,
+ .sahf,
+ .sse2,
+ .sse4_2,
+ .x87,
+ .xsave,
+ }),
+ };
+ pub const x86_64_v4 = CpuModel{
+ .name = "x86_64_v4",
+ .llvm_name = "x86-64-v4",
+ .features = featureSet(&[_]Feature{
+ .@"64bit",
+ .avx2,
+ .avx512bw,
+ .avx512cd,
+ .avx512dq,
+ .avx512vl,
+ .bmi,
+ .bmi2,
+ .cmov,
+ .cx16,
+ .cx8,
+ .f16c,
+ .fma,
+ .fxsr,
+ .lzcnt,
+ .mmx,
+ .movbe,
+ .nopl,
+ .popcnt,
+ .sahf,
+ .sse2,
+ .sse4_2,
+ .x87,
+ .xsave,
+ }),
+ };
pub const yonah = CpuModel{
.name = "yonah",
.llvm_name = "yonah",
@@ -2934,9 +2812,7 @@ pub const cpu = struct {
.fxsr,
.mmx,
.nopl,
- .slow_unaligned_mem_16,
.sse3,
- .vzeroupper,
.x87,
}),
};
@@ -2950,16 +2826,11 @@ pub const cpu = struct {
.avx2,
.bmi,
.bmi2,
- .branchfusion,
.clflushopt,
.clzero,
.cmov,
.cx16,
.f16c,
- .fast_15bytenop,
- .fast_bextr,
- .fast_lzcnt,
- .fast_scalar_shift_masks,
.fma,
.fsgsbase,
.fxsr,
@@ -2975,9 +2846,7 @@ pub const cpu = struct {
.rdseed,
.sahf,
.sha,
- .slow_shld,
.sse4a,
- .vzeroupper,
.x87,
.xsave,
.xsavec,
@@ -2995,17 +2864,12 @@ pub const cpu = struct {
.avx2,
.bmi,
.bmi2,
- .branchfusion,
.clflushopt,
.clwb,
.clzero,
.cmov,
.cx16,
.f16c,
- .fast_15bytenop,
- .fast_bextr,
- .fast_lzcnt,
- .fast_scalar_shift_masks,
.fma,
.fsgsbase,
.fxsr,
@@ -3022,9 +2886,52 @@ pub const cpu = struct {
.rdseed,
.sahf,
.sha,
- .slow_shld,
.sse4a,
- .vzeroupper,
+ .wbnoinvd,
+ .x87,
+ .xsave,
+ .xsavec,
+ .xsaveopt,
+ .xsaves,
+ }),
+ };
+ pub const znver3 = CpuModel{
+ .name = "znver3",
+ .llvm_name = "znver3",
+ .features = featureSet(&[_]Feature{
+ .@"64bit",
+ .adx,
+ .aes,
+ .avx2,
+ .bmi,
+ .bmi2,
+ .clflushopt,
+ .clwb,
+ .clzero,
+ .cmov,
+ .cx16,
+ .f16c,
+ .fma,
+ .fsgsbase,
+ .fxsr,
+ .invpcid,
+ .lzcnt,
+ .mmx,
+ .movbe,
+ .mwaitx,
+ .nopl,
+ .pclmul,
+ .pku,
+ .popcnt,
+ .prfchw,
+ .rdpid,
+ .rdrnd,
+ .rdseed,
+ .sahf,
+ .sha,
+ .sse4a,
+ .vaes,
+ .vpclmulqdq,
.wbnoinvd,
.x87,
.xsave,