Commit 6dc1fafe98

Robin Voetter <robin@voetter.nl>
2022-11-25 01:51:55
std: add generic target for spirv
This adds a general target for SPIR-V compilation. Previously there was not any target machine defined for SPIR-V. TODO is to reword the features for this target. We don't really need the full list of capabilities in the features, we should only put a few features here which we can actually use during code generation.
master
1 parent 17de4a8
Changed files (2)
lib
std
target
spirv.zig
target.zig
lib/std/target/spirv.zig
@@ -2081,3 +2081,11 @@ pub const all_features = blk: {
     }
     break :blk result;
 };
+
+pub const cpu = struct {
+    pub const generic = CpuModel{
+        .name = "generic",
+        .llvm_name = "generic",
+        .features = featureSet(&[_]Feature{}),
+    };
+};
lib/std/target.zig
@@ -1329,6 +1329,7 @@ pub const Target = struct {
                     .amdgcn => comptime allCpusFromDecls(amdgpu.cpu),
                     .riscv32, .riscv64 => comptime allCpusFromDecls(riscv.cpu),
                     .sparc, .sparc64, .sparcel => comptime allCpusFromDecls(sparc.cpu),
+                    .spirv32, .spirv64 => comptime allCpusFromDecls(spirv.cpu),
                     .s390x => comptime allCpusFromDecls(s390x.cpu),
                     .x86, .x86_64 => comptime allCpusFromDecls(x86.cpu),
                     .xtensa => comptime allCpusFromDecls(xtensa.cpu),
@@ -1392,6 +1393,7 @@ pub const Target = struct {
                     .amdgcn => &amdgpu.cpu.generic,
                     .riscv32 => &riscv.cpu.generic_rv32,
                     .riscv64 => &riscv.cpu.generic_rv64,
+                    .spirv32, .spirv64 => &spirv.cpu.generic,
                     .sparc, .sparcel => &sparc.cpu.generic,
                     .sparc64 => &sparc.cpu.v9, // 64-bit SPARC needs v9 as the baseline
                     .s390x => &s390x.cpu.generic,