Commit 6bed45b873

Jacob Young <jacobly0@users.noreply.github.com>
2023-02-27 22:12:02
codegen: fix test failures
Various backend were mismatching arg instructions and function args.
master
1 parent 5723696
Changed files (3)
src
arch
aarch64
CodeGen.zig
arm
CodeGen.zig
x86_64
CodeGen.zig
src/arch/aarch64/CodeGen.zig
@@ -4177,8 +4177,10 @@ fn airFieldParentPtr(self: *Self, inst: Air.Inst.Index) !void {
 }
 
 fn airArg(self: *Self, inst: Air.Inst.Index) !void {
-    const arg_index = self.arg_index;
-    self.arg_index += 1;
+    // skip zero-bit arguments as they don't have a corresponding arg instruction
+    var arg_index = self.arg_index;
+    while (self.args[arg_index] == .none) arg_index += 1;
+    self.arg_index = arg_index + 1;
 
     const ty = self.air.typeOfIndex(inst);
     const tag = self.air.instructions.items(.tag)[inst];
src/arch/arm/CodeGen.zig
@@ -4125,8 +4125,10 @@ fn genInlineMemsetCode(
 }
 
 fn airArg(self: *Self, inst: Air.Inst.Index) !void {
-    const arg_index = self.arg_index;
-    self.arg_index += 1;
+    // skip zero-bit arguments as they don't have a corresponding arg instruction
+    var arg_index = self.arg_index;
+    while (self.args[arg_index] == .none) arg_index += 1;
+    self.arg_index = arg_index + 1;
 
     const ty = self.air.typeOfIndex(inst);
     const tag = self.air.instructions.items(.tag)[inst];
src/arch/x86_64/CodeGen.zig
@@ -3827,8 +3827,10 @@ fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: M
 }
 
 fn airArg(self: *Self, inst: Air.Inst.Index) !void {
-    const arg_index = self.arg_index;
-    self.arg_index += 1;
+    // skip zero-bit arguments as they don't have a corresponding arg instruction
+    var arg_index = self.arg_index;
+    while (self.args[arg_index] == .none) arg_index += 1;
+    self.arg_index = arg_index + 1;
 
     const ty = self.air.typeOfIndex(inst);
     const mcv = self.args[arg_index];