Commit 64365bc5d7

Andrew Kelley <andrew@ziglang.org>
2020-02-17 06:06:19
enable behavior and std lib tests for RISC-V 64-bit
closes #3338
master
1 parent 816b69a
Changed files (3)
lib
std
target
riscv.zig
fmt.zig
test
tests.zig
lib/std/target/riscv.zig
@@ -263,7 +263,7 @@ pub const all_features = blk: {
 pub const cpu = struct {
     pub const baseline_rv32 = Cpu{
         .name = "baseline_rv32",
-        .llvm_name = "generic-rv32",
+        .llvm_name = null,
         .features = featureSet(&[_]Feature{
             .a,
             .c,
@@ -275,7 +275,7 @@ pub const cpu = struct {
 
     pub const baseline_rv64 = Cpu{
         .name = "baseline_rv64",
-        .llvm_name = "generic-rv64",
+        .llvm_name = null,
         .features = featureSet(&[_]Feature{
             .@"64bit",
             .a,
@@ -288,14 +288,14 @@ pub const cpu = struct {
 
     pub const generic_rv32 = Cpu{
         .name = "generic_rv32",
-        .llvm_name = "generic-rv32",
+        .llvm_name = null,
         .features = featureSet(&[_]Feature{
             .rvc_hints,
         }),
     };
     pub const generic_rv64 = Cpu{
         .name = "generic_rv64",
-        .llvm_name = "generic-rv64",
+        .llvm_name = null,
         .features = featureSet(&[_]Feature{
             .@"64bit",
             .rvc_hints,
lib/std/fmt.zig
@@ -1728,8 +1728,14 @@ test "positional/alignment/width/precision" {
 }
 
 test "vector" {
-    // https://github.com/ziglang/zig/issues/3317
-    if (builtin.arch == .mipsel) return error.SkipZigTest;
+    if (builtin.arch == .mipsel) {
+        // https://github.com/ziglang/zig/issues/3317
+        return error.SkipZigTest;
+    }
+    if (builtin.arch == .riscv64) {
+        // https://github.com/ziglang/zig/issues/4486
+        return error.SkipZigTest;
+    }
 
     const vbool: @Vector(4, bool) = [_]bool{ true, false, true, false };
     const vi64: @Vector(4, i64) = [_]i64{ -2, -1, 0, 1 };
test/tests.zig
@@ -196,6 +196,43 @@ const test_targets = blk: {
             .link_libc = true,
         },
 
+        TestTarget{
+            .target = Target{
+                .Cross = CrossTarget{
+                    .os = .linux,
+                    .arch = .riscv64,
+                    .cpu_features = Target.Arch.riscv64.getBaselineCpuFeatures(),
+                    .abi = .none,
+                },
+            },
+        },
+
+        // https://github.com/ziglang/zig/issues/4485
+        //TestTarget{
+        //    .target = Target{
+        //        .Cross = CrossTarget{
+        //            .os = .linux,
+        //            .arch = .riscv64,
+        //            .cpu_features = Target.Arch.riscv64.getBaselineCpuFeatures(),
+        //            .abi = .musl,
+        //        },
+        //    },
+        //    .link_libc = true,
+        //},
+
+        // https://github.com/ziglang/zig/issues/3340
+        //TestTarget{
+        //    .target = Target{
+        //        .Cross = CrossTarget{
+        //            .os = .linux,
+        //            .arch = .riscv64,
+        //            .cpu_features = Target.Arch.riscv64.getBaselineCpuFeatures(),
+        //            .abi = .gnu,
+        //        },
+        //    },
+        //    .link_libc = true,
+        //},
+
         TestTarget{
             .target = Target{
                 .Cross = CrossTarget{