Commit `5e9e1fb0c8`

Alex Rønne Petersen <alex@alexrp.com>

2025-09-17 17:24:07

std.Target: adjustments to LoongArch CPU models

* Remove the generic model; we already have generic_la32 and generic_la64 and pick appropriately based on bitness. * Remove the loongarch64 model. We used this as our baseline for 64-bit, but it's actually pretty misleading and useless; it doesn't represent any real CPU and has less features than generic_la64. * Add la64v1_0 and la64v1_1 models. * Change our baseline CPU model for 64-bit to be la64v1_0, thus adding LSX to the baseline feature set.

master

1 parent 6208e74

Changed files (3)

lib

std

Target

loongarch.zig

Target.zig

tools

update_cpu_features.zig

@@ -159,11 +159,6 @@ pub const all_features = blk: {
 };
 
 pub const cpu = struct {
-    pub const generic: CpuModel = .{
-        .name = "generic",
-        .llvm_name = "generic",
-        .features = featureSet(&[_]Feature{}),
-    };
     pub const generic_la32: CpuModel = .{
         .name = "generic_la32",
         .llvm_name = "generic-la32",
@@ -191,6 +186,30 @@ pub const cpu = struct {
             .ual,
         }),
     };
+    pub const la64v1_0: CpuModel = .{
+        .name = "la64v1_0",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+            .lsx,
+            .ual,
+        }),
+    };
+    pub const la64v1_1: CpuModel = .{
+        .name = "la64v1_1",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+            .div32,
+            .frecipe,
+            .lam_bh,
+            .lamcas,
+            .ld_seq_sa,
+            .lsx,
+            .scq,
+            .ual,
+        }),
+    };
     pub const la664: CpuModel = .{
         .name = "la664",
         .llvm_name = "la664",
@@ -208,13 +227,4 @@ pub const cpu = struct {
             .ual,
         }),
     };
-    pub const loongarch64: CpuModel = .{
-        .name = "loongarch64",
-        .llvm_name = "loongarch64",
-        .features = featureSet(&[_]Feature{
-            .@"64bit",
-            .d,
-            .ual,
-        }),
-    };
 };

@@ -1903,7 +1903,7 @@ pub const Cpu = struct {
                 .csky => &csky.cpu.ck810, // gcc/clang do not have a generic csky model.
                 .hexagon => &hexagon.cpu.hexagonv68, // gcc/clang do not have a generic hexagon model.
                 .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model.
-                .loongarch64 => &loongarch.cpu.loongarch64,
+                .loongarch64 => &loongarch.cpu.la64v1_0,
                 .m68k => &m68k.cpu.M68000,
                 .mips, .mipsel => &mips.cpu.mips32r2,
                 .mips64, .mips64el => &mips.cpu.mips64r2,

@@ -986,6 +986,36 @@ const targets = [_]ArchTarget{
             .name = "LoongArch",
             .td_name = "LoongArch",
         },
+        .extra_cpus = &.{
+            .{
+                .llvm_name = null,
+                .zig_name = "la64v1_0",
+                .features = &.{
+                    "64bit",
+                    "lsx",
+                    "ual",
+                },
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "la64v1_1",
+                .features = &.{
+                    "64bit",
+                    "div32",
+                    "frecipe",
+                    "lam_bh",
+                    "lamcas",
+                    "ld_seq_sa",
+                    "lsx",
+                    "scq",
+                    "ual",
+                },
+            },
+        },
+        .omit_cpus = &.{
+            "generic",
+            "loongarch64",
+        },
     },
     .{
         .zig_name = "m68k",

Commit 5e9e1fb0c8

Commit `5e9e1fb0c8`