Commit 5bc35fa75b

serg <sergpolkin@gmail.com>
2023-04-16 09:59:11
std.target.riscv: fix baseline_rv32 missing feature "32bit"
master
1 parent 2b7334c
Changed files (2)
lib
std
target
riscv.zig
tools
update_cpu_features.zig
lib/std/target/riscv.zig
@@ -748,6 +748,7 @@ pub const cpu = struct {
         .name = "baseline_rv32",
         .llvm_name = null,
         .features = featureSet(&[_]Feature{
+            .@"32bit",
             .a,
             .c,
             .d,
tools/update_cpu_features.zig
@@ -866,7 +866,7 @@ const llvm_targets = [_]LlvmTarget{
             .{
                 .llvm_name = null,
                 .zig_name = "baseline_rv32",
-                .features = &.{ "a", "c", "d", "f", "m" },
+                .features = &.{ "32bit", "a", "c", "d", "f", "m" },
             },
             .{
                 .llvm_name = null,