Commit 50a5fc98dc
Changed files (12)
lib/std/target/avr.zig
@@ -1,8 +1,5 @@
-// SPDX-License-Identifier: MIT
-// Copyright (c) 2015-2021 Zig Contributors
-// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
-// The MIT license requires this copyright notice to be included in all copies
-// and substantial portions of the software.
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
const std = @import("../std.zig");
const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;
@@ -163,7 +160,6 @@ pub const all_features = blk: {
.dependencies = featureSet(&[_]Feature{
.avr0,
.@"break",
- .memmappedregs,
.sram,
.tinyencoding,
}),
@@ -1859,7 +1855,7 @@ pub const cpu = struct {
.name = "atxmega16e5",
.llvm_name = "atxmega16e5",
.features = featureSet(&[_]Feature{
- .xmega,
+ .xmegau,
}),
};
pub const atxmega192a3 = CpuModel{
lib/std/target/bpf.zig
@@ -1,8 +1,5 @@
-// SPDX-License-Identifier: MIT
-// Copyright (c) 2015-2021 Zig Contributors
-// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
-// The MIT license requires this copyright notice to be included in all copies
-// and substantial portions of the software.
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
const std = @import("../std.zig");
const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;
lib/std/target/hexagon.zig
@@ -1,8 +1,5 @@
-// SPDX-License-Identifier: MIT
-// Copyright (c) 2015-2021 Zig Contributors
-// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
-// The MIT license requires this copyright notice to be included in all copies
-// and substantial portions of the software.
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
const std = @import("../std.zig");
const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;
@@ -92,7 +89,6 @@ pub const all_features = blk: {
.llvm_name = "hvxv62",
.description = "Hexagon HVX instructions",
.dependencies = featureSet(&[_]Feature{
- .hvx,
.hvxv60,
}),
};
@@ -100,8 +96,6 @@ pub const all_features = blk: {
.llvm_name = "hvxv65",
.description = "Hexagon HVX instructions",
.dependencies = featureSet(&[_]Feature{
- .hvx,
- .hvxv60,
.hvxv62,
}),
};
@@ -109,9 +103,6 @@ pub const all_features = blk: {
.llvm_name = "hvxv66",
.description = "Hexagon HVX instructions",
.dependencies = featureSet(&[_]Feature{
- .hvx,
- .hvxv60,
- .hvxv62,
.hvxv65,
.zreg,
}),
@@ -120,9 +111,6 @@ pub const all_features = blk: {
.llvm_name = "hvxv67",
.description = "Hexagon HVX instructions",
.dependencies = featureSet(&[_]Feature{
- .hvxv60,
- .hvxv62,
- .hvxv65,
.hvxv66,
}),
};
@@ -248,7 +236,6 @@ pub const cpu = struct {
.memops,
.nvj,
.nvs,
- .packets,
.prev65,
.small_data,
.v5,
@@ -265,7 +252,6 @@ pub const cpu = struct {
.memops,
.nvj,
.nvs,
- .packets,
.prev65,
.small_data,
.v5,
@@ -280,7 +266,6 @@ pub const cpu = struct {
.memops,
.nvj,
.nvs,
- .packets,
.prev65,
.small_data,
.v5,
@@ -296,7 +281,6 @@ pub const cpu = struct {
.memops,
.nvj,
.nvs,
- .packets,
.prev65,
.small_data,
.v5,
@@ -313,7 +297,6 @@ pub const cpu = struct {
.memops,
.nvj,
.nvs,
- .packets,
.prev65,
.small_data,
.v5,
@@ -332,7 +315,6 @@ pub const cpu = struct {
.memops,
.nvj,
.nvs,
- .packets,
.small_data,
.v5,
.v55,
@@ -351,7 +333,6 @@ pub const cpu = struct {
.memops,
.nvj,
.nvs,
- .packets,
.small_data,
.v5,
.v55,
@@ -371,7 +352,6 @@ pub const cpu = struct {
.memops,
.nvj,
.nvs,
- .packets,
.small_data,
.v5,
.v55,
@@ -391,7 +371,6 @@ pub const cpu = struct {
.mem_noshuf,
.memops,
.nvs,
- .packets,
.small_data,
.tinycore,
.v5,
lib/std/target/mips.zig
@@ -1,8 +1,5 @@
-// SPDX-License-Identifier: MIT
-// Copyright (c) 2015-2021 Zig Contributors
-// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
-// The MIT license requires this copyright notice to be included in all copies
-// and substantial portions of the software.
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
const std = @import("../std.zig");
const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;
@@ -108,7 +105,6 @@ pub const all_features = blk: {
.llvm_name = "dspr3",
.description = "Mips DSP-R3 ASE",
.dependencies = featureSet(&[_]Feature{
- .dsp,
.dspr2,
}),
};
@@ -301,10 +297,8 @@ pub const all_features = blk: {
.llvm_name = "mips64r6",
.description = "Mips64r6 ISA Support [experimental]",
.dependencies = featureSet(&[_]Feature{
- .abs2008,
.mips32r6,
.mips64r5,
- .nan2008,
}),
};
result[@enumToInt(Feature.msa)] = .{
@@ -515,16 +509,13 @@ pub const cpu = struct {
.llvm_name = "octeon",
.features = featureSet(&[_]Feature{
.cnmips,
- .mips64r2,
}),
};
pub const @"octeon+" = CpuModel{
.name = "octeon+",
.llvm_name = "octeon+",
.features = featureSet(&[_]Feature{
- .cnmips,
.cnmipsp,
- .mips64r2,
}),
};
pub const p5600 = CpuModel{
lib/std/target/msp430.zig
@@ -1,8 +1,5 @@
-// SPDX-License-Identifier: MIT
-// Copyright (c) 2015-2021 Zig Contributors
-// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
-// The MIT license requires this copyright notice to be included in all copies
-// and substantial portions of the software.
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
const std = @import("../std.zig");
const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;
lib/std/target/nvptx.zig
@@ -1,8 +1,5 @@
-// SPDX-License-Identifier: MIT
-// Copyright (c) 2015-2021 Zig Contributors
-// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
-// The MIT license requires this copyright notice to be included in all copies
-// and substantial portions of the software.
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
const std = @import("../std.zig");
const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;
lib/std/target/powerpc.zig
@@ -1,8 +1,5 @@
-// SPDX-License-Identifier: MIT
-// Copyright (c) 2015-2021 Zig Contributors
-// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
-// The MIT license requires this copyright notice to be included in all copies
-// and substantial portions of the software.
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
const std = @import("../std.zig");
const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;
@@ -10,6 +7,7 @@ const CpuModel = std.Target.Cpu.Model;
pub const Feature = enum {
@"64bit",
@"64bitregs",
+ aix,
allow_unaligned_fp_access,
altivec,
booke,
@@ -19,6 +17,7 @@ pub const Feature = enum {
crypto,
direct_move,
e500,
+ efpu2,
extdiv,
fcpsgn,
float128,
@@ -46,6 +45,7 @@ pub const Feature = enum {
longcall,
mfocrf,
mma,
+ modern_aix_as,
msync,
paired_vector_memops,
partword_atomics,
@@ -62,7 +62,6 @@ pub const Feature = enum {
ppc6xx,
predictable_select_expensive,
prefix_instrs,
- qpx,
recipprec,
secure_plt,
slow_popcntd,
@@ -89,6 +88,11 @@ pub const all_features = blk: {
.description = "Enable 64-bit registers usage for ppc32 [beta]",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.aix)] = .{
+ .llvm_name = "aix",
+ .description = "AIX OS",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
result[@enumToInt(Feature.allow_unaligned_fp_access)] = .{
.llvm_name = "allow-unaligned-fp-access",
.description = "CPU does not trap on unaligned FP access",
@@ -142,6 +146,13 @@ pub const all_features = blk: {
.description = "Enable E500/E500mc instructions",
.dependencies = featureSet(&[_]Feature{}),
};
+ result[@enumToInt(Feature.efpu2)] = .{
+ .llvm_name = "efpu2",
+ .description = "Enable Embedded Floating-Point APU 2 instructions",
+ .dependencies = featureSet(&[_]Feature{
+ .spe,
+ }),
+ };
result[@enumToInt(Feature.extdiv)] = .{
.llvm_name = "extdiv",
.description = "Enable extended divide instructions",
@@ -311,6 +322,11 @@ pub const all_features = blk: {
.power9_altivec,
}),
};
+ result[@enumToInt(Feature.modern_aix_as)] = .{
+ .llvm_name = "modern-aix-as",
+ .description = "AIX system assembler is modern enough to support new mnes",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
result[@enumToInt(Feature.msync)] = .{
.llvm_name = "msync",
.description = "Has only the msync instruction instead of sync",
@@ -334,7 +350,6 @@ pub const all_features = blk: {
.llvm_name = "pcrelative-memops",
.description = "Enable PC relative Memory Ops",
.dependencies = featureSet(&[_]Feature{
- .isa_v30_instructions,
.prefix_instrs,
}),
};
@@ -378,7 +393,6 @@ pub const all_features = blk: {
.llvm_name = "power9-vector",
.description = "Enable POWER9 vector instructions",
.dependencies = featureSet(&[_]Feature{
- .isa_v30_instructions,
.power8_vector,
.power9_altivec,
}),
@@ -412,18 +426,10 @@ pub const all_features = blk: {
.llvm_name = "prefix-instrs",
.description = "Enable prefixed instructions",
.dependencies = featureSet(&[_]Feature{
- .isa_v30_instructions,
.power8_vector,
.power9_altivec,
}),
};
- result[@enumToInt(Feature.qpx)] = .{
- .llvm_name = null,
- .description = "Enable QPX instructions",
- .dependencies = featureSet(&[_]Feature{
- .fpu,
- }),
- };
result[@enumToInt(Feature.recipprec)] = .{
.llvm_name = "recipprec",
.description = "Assume higher precision reciprocal estimates",
@@ -479,94 +485,90 @@ pub const all_features = blk: {
};
pub const cpu = struct {
- pub const @"ppc440" = CpuModel{
- .name = "ppc440",
+ pub const @"440" = CpuModel{
+ .name = "440",
.llvm_name = "440",
.features = featureSet(&[_]Feature{
- .booke,
.fres,
.frsqrte,
- .icbt,
.isel,
.msync,
}),
};
- pub const @"ppc450" = CpuModel{
- .name = "ppc450",
+ pub const @"450" = CpuModel{
+ .name = "450",
.llvm_name = "450",
.features = featureSet(&[_]Feature{
- .booke,
.fres,
.frsqrte,
- .icbt,
.isel,
.msync,
}),
};
- pub const @"ppc601" = CpuModel{
- .name = "ppc601",
+ pub const @"601" = CpuModel{
+ .name = "601",
.llvm_name = "601",
.features = featureSet(&[_]Feature{
.fpu,
}),
};
- pub const @"ppc602" = CpuModel{
- .name = "ppc602",
+ pub const @"602" = CpuModel{
+ .name = "602",
.llvm_name = "602",
.features = featureSet(&[_]Feature{
.fpu,
}),
};
- pub const @"ppc603" = CpuModel{
- .name = "ppc603",
+ pub const @"603" = CpuModel{
+ .name = "603",
.llvm_name = "603",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
- pub const @"ppc603e" = CpuModel{
- .name = "ppc603e",
+ pub const @"603e" = CpuModel{
+ .name = "603e",
.llvm_name = "603e",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
- pub const @"ppc603ev" = CpuModel{
- .name = "ppc603ev",
+ pub const @"603ev" = CpuModel{
+ .name = "603ev",
.llvm_name = "603ev",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
- pub const @"ppc604" = CpuModel{
- .name = "ppc604",
+ pub const @"604" = CpuModel{
+ .name = "604",
.llvm_name = "604",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
- pub const @"ppc604e" = CpuModel{
- .name = "ppc604e",
+ pub const @"604e" = CpuModel{
+ .name = "604e",
.llvm_name = "604e",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
- pub const @"ppc620" = CpuModel{
- .name = "ppc620",
+ pub const @"620" = CpuModel{
+ .name = "620",
.llvm_name = "620",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
- pub const @"ppc7400" = CpuModel{
- .name = "ppc7400",
+ pub const @"7400" = CpuModel{
+ .name = "7400",
.llvm_name = "7400",
.features = featureSet(&[_]Feature{
.altivec,
@@ -574,8 +576,8 @@ pub const cpu = struct {
.frsqrte,
}),
};
- pub const @"ppc7450" = CpuModel{
- .name = "ppc7450",
+ pub const @"7450" = CpuModel{
+ .name = "7450",
.llvm_name = "7450",
.features = featureSet(&[_]Feature{
.altivec,
@@ -583,16 +585,16 @@ pub const cpu = struct {
.frsqrte,
}),
};
- pub const @"ppc750" = CpuModel{
- .name = "ppc750",
+ pub const @"750" = CpuModel{
+ .name = "750",
.llvm_name = "750",
.features = featureSet(&[_]Feature{
.fres,
.frsqrte,
}),
};
- pub const @"ppc970" = CpuModel{
- .name = "ppc970",
+ pub const @"970" = CpuModel{
+ .name = "970",
.llvm_name = "970",
.features = featureSet(&[_]Feature{
.@"64bit",
@@ -619,7 +621,6 @@ pub const cpu = struct {
.frsqrte,
.frsqrtes,
.fsqrt,
- .icbt,
.isel,
.ldbrx,
.lfiwax,
@@ -629,38 +630,10 @@ pub const cpu = struct {
.stfiwx,
}),
};
- pub const a2q = CpuModel{
- .name = "a2q",
- .llvm_name = "a2q",
- .features = featureSet(&[_]Feature{
- .@"64bit",
- .booke,
- .cmpb,
- .fcpsgn,
- .fpcvt,
- .fprnd,
- .fre,
- .fres,
- .frsqrte,
- .frsqrtes,
- .fsqrt,
- .icbt,
- .isel,
- .ldbrx,
- .lfiwax,
- .mfocrf,
- .qpx,
- .recipprec,
- .slow_popcntd,
- .stfiwx,
- }),
- };
pub const e500 = CpuModel{
.name = "e500",
.llvm_name = "e500",
.features = featureSet(&[_]Feature{
- .booke,
- .icbt,
.isel,
.msync,
.spe,
@@ -671,7 +644,6 @@ pub const cpu = struct {
.llvm_name = "e500mc",
.features = featureSet(&[_]Feature{
.booke,
- .icbt,
.isel,
.stfiwx,
}),
@@ -682,7 +654,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.@"64bit",
.booke,
- .icbt,
.isel,
.mfocrf,
.stfiwx,
@@ -694,7 +665,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.@"64bit",
.allow_unaligned_fp_access,
- .altivec,
.bpermd,
.cmpb,
.crypto,
@@ -711,30 +681,21 @@ pub const cpu = struct {
.fuse_store,
.htm,
.icbt,
- .isa_v30_instructions,
- .isa_v31_instructions,
.isel,
.ldbrx,
.lfiwax,
.mfocrf,
.mma,
- .paired_vector_memops,
.partword_atomics,
.pcrelative_memops,
.popcntd,
.power10_vector,
- .power8_altivec,
- .power8_vector,
- .power9_altivec,
- .power9_vector,
.ppc_postra_sched,
.ppc_prera_sched,
.predictable_select_expensive,
- .prefix_instrs,
.recipprec,
.stfiwx,
.two_const_nr,
- .vsx,
}),
};
pub const g3 = CpuModel{
@@ -792,7 +753,7 @@ pub const cpu = struct {
};
pub const ppc32 = CpuModel{
.name = "ppc32",
- .llvm_name = "ppc",
+ .llvm_name = "ppc32",
.features = featureSet(&[_]Feature{
.hard_float,
}),
@@ -816,7 +777,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.@"64bit",
.allow_unaligned_fp_access,
- .altivec,
.bpermd,
.cmpb,
.crypto,
@@ -840,13 +800,11 @@ pub const cpu = struct {
.mfocrf,
.partword_atomics,
.popcntd,
- .power8_altivec,
.power8_vector,
.predictable_select_expensive,
.recipprec,
.stfiwx,
.two_const_nr,
- .vsx,
}),
};
pub const pwr10 = CpuModel{
@@ -855,7 +813,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.@"64bit",
.allow_unaligned_fp_access,
- .altivec,
.bpermd,
.cmpb,
.crypto,
@@ -872,30 +829,21 @@ pub const cpu = struct {
.fuse_store,
.htm,
.icbt,
- .isa_v30_instructions,
- .isa_v31_instructions,
.isel,
.ldbrx,
.lfiwax,
.mfocrf,
.mma,
- .paired_vector_memops,
.partword_atomics,
.pcrelative_memops,
.popcntd,
.power10_vector,
- .power8_altivec,
- .power8_vector,
- .power9_altivec,
- .power9_vector,
.ppc_postra_sched,
.ppc_prera_sched,
.predictable_select_expensive,
- .prefix_instrs,
.recipprec,
.stfiwx,
.two_const_nr,
- .vsx,
}),
};
pub const pwr3 = CpuModel{
@@ -1000,7 +948,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.@"64bit",
.allow_unaligned_fp_access,
- .altivec,
.bpermd,
.cmpb,
.extdiv,
@@ -1029,7 +976,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.@"64bit",
.allow_unaligned_fp_access,
- .altivec,
.bpermd,
.cmpb,
.crypto,
@@ -1053,13 +999,11 @@ pub const cpu = struct {
.mfocrf,
.partword_atomics,
.popcntd,
- .power8_altivec,
.power8_vector,
.predictable_select_expensive,
.recipprec,
.stfiwx,
.two_const_nr,
- .vsx,
}),
};
pub const pwr9 = CpuModel{
@@ -1068,7 +1012,6 @@ pub const cpu = struct {
.features = featureSet(&[_]Feature{
.@"64bit",
.allow_unaligned_fp_access,
- .altivec,
.bpermd,
.cmpb,
.crypto,
@@ -1084,16 +1027,12 @@ pub const cpu = struct {
.fsqrt,
.htm,
.icbt,
- .isa_v30_instructions,
.isel,
.ldbrx,
.lfiwax,
.mfocrf,
.partword_atomics,
.popcntd,
- .power8_altivec,
- .power8_vector,
- .power9_altivec,
.power9_vector,
.ppc_postra_sched,
.ppc_prera_sched,
@@ -1102,7 +1041,6 @@ pub const cpu = struct {
.stfiwx,
.two_const_nr,
.vectors_use_two_units,
- .vsx,
}),
};
};
lib/std/target/sparc.zig
@@ -1,8 +1,5 @@
-// SPDX-License-Identifier: MIT
-// Copyright (c) 2015-2021 Zig Contributors
-// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
-// The MIT license requires this copyright notice to be included in all copies
-// and substantial portions of the software.
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
const std = @import("../std.zig");
const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;
@@ -160,6 +157,11 @@ pub const cpu = struct {
.llvm_name = "f934",
.features = featureSet(&[_]Feature{}),
};
+ pub const generic = CpuModel{
+ .name = "generic",
+ .llvm_name = "generic",
+ .features = featureSet(&[_]Feature{}),
+ };
pub const gr712rc = CpuModel{
.name = "gr712rc",
.llvm_name = "gr712rc",
lib/std/target/systemz.zig
@@ -1,8 +1,5 @@
-// SPDX-License-Identifier: MIT
-// Copyright (c) 2015-2021 Zig Contributors
-// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
-// The MIT license requires this copyright notice to be included in all copies
-// and substantial portions of the software.
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
const std = @import("../std.zig");
const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;
lib/std/target/ve.zig
@@ -0,0 +1,36 @@
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
+const std = @import("../std.zig");
+const CpuFeature = std.Target.Cpu.Feature;
+const CpuModel = std.Target.Cpu.Model;
+
+pub const Feature = enum {
+ vpu,
+};
+
+pub usingnamespace CpuFeature.feature_set_fns(Feature);
+
+pub const all_features = blk: {
+ const len = @typeInfo(Feature).Enum.fields.len;
+ std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
+ var result: [len]CpuFeature = undefined;
+ result[@enumToInt(Feature.vpu)] = .{
+ .llvm_name = "vpu",
+ .description = "Enable the VPU",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ const ti = @typeInfo(Feature);
+ for (result) |*elem, i| {
+ elem.index = i;
+ elem.name = ti.Enum.fields[i].name;
+ }
+ break :blk result;
+};
+
+pub const cpu = struct {
+ pub const generic = CpuModel{
+ .name = "generic",
+ .llvm_name = "generic",
+ .features = featureSet(&[_]Feature{}),
+ };
+};
lib/std/target/wasm.zig
@@ -1,8 +1,5 @@
-// SPDX-License-Identifier: MIT
-// Copyright (c) 2015-2021 Zig Contributors
-// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
-// The MIT license requires this copyright notice to be included in all copies
-// and substantial portions of the software.
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
const std = @import("../std.zig");
const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;
lib/std/target.zig
@@ -1070,17 +1070,13 @@ pub const Target = struct {
}
}
- /// Returns a name that matches the lib/std/target/* directory name.
+ /// Returns a name that matches the lib/std/target/* source file name.
pub fn genericName(arch: Arch) []const u8 {
return switch (arch) {
.arm, .armeb, .thumb, .thumbeb => "arm",
.aarch64, .aarch64_be, .aarch64_32 => "aarch64",
- .avr => "avr",
.bpfel, .bpfeb => "bpf",
- .csky => "csky",
- .hexagon => "hexagon",
.mips, .mipsel, .mips64, .mips64el => "mips",
- .msp430 => "msp430",
.powerpc, .powerpc64, .powerpc64le => "powerpc",
.amdgcn => "amdgpu",
.riscv32, .riscv64 => "riscv",
@@ -1111,6 +1107,7 @@ pub const Target = struct {
.s390x => &systemz.all_features,
.i386, .x86_64 => &x86.all_features,
.nvptx, .nvptx64 => &nvptx.all_features,
+ .ve => &ve.all_features,
.wasm32, .wasm64 => &wasm.all_features,
else => &[0]Cpu.Feature{},
@@ -1134,6 +1131,7 @@ pub const Target = struct {
.s390x => comptime allCpusFromDecls(systemz.cpu),
.i386, .x86_64 => comptime allCpusFromDecls(x86.cpu),
.nvptx, .nvptx64 => comptime allCpusFromDecls(nvptx.cpu),
+ .ve => comptime allCpusFromDecls(ve.cpu),
.wasm32, .wasm64 => comptime allCpusFromDecls(wasm.cpu),
else => &[0]*const Model{},
@@ -1188,12 +1186,13 @@ pub const Target = struct {
.amdgcn => &amdgpu.cpu.generic,
.riscv32 => &riscv.cpu.generic_rv32,
.riscv64 => &riscv.cpu.generic_rv64,
- .sparc, .sparcel => &sparc.cpu.v8,
+ .sparc, .sparcel => &sparc.cpu.generic,
.sparcv9 => &sparc.cpu.v9,
.s390x => &systemz.cpu.generic,
.i386 => &x86.cpu._i386,
.x86_64 => &x86.cpu.x86_64,
.nvptx, .nvptx64 => &nvptx.cpu.sm_20,
+ .ve => &ve.cpu.generic,
.wasm32, .wasm64 => &wasm.cpu.generic,
else => &S.generic_model,
@@ -1207,6 +1206,7 @@ pub const Target = struct {
.riscv64 => &riscv.cpu.baseline_rv64,
.i386 => &x86.cpu.pentium4,
.nvptx, .nvptx64 => &nvptx.cpu.sm_20,
+ .sparc, .sparcel => &sparc.cpu.v8,
else => generic(arch),
};