Commit 4bd4c5e06d

data-man <datamanrb@gmail.com>
2019-08-09 09:43:29
Fixed tiny typo in the math module (shr's description)
1 parent e6ebc41
Changed files (1)
std/math.zig
@@ -366,7 +366,7 @@ test "math.shl" {
 }
 
 /// Shifts right. Overflowed bits are truncated.
-/// A negative shift amount results in a lefft shift.
+/// A negative shift amount results in a left shift.
 pub fn shr(comptime T: type, a: T, shift_amt: var) T {
     const abs_shift_amt = absCast(shift_amt);
     const casted_shift_amt = if (abs_shift_amt >= T.bit_count) return 0 else @intCast(Log2Int(T), abs_shift_amt);