Commit 3d7fb4f204

Alex Rønne Petersen <alex@alexrp.com>
2025-06-30 06:59:06
std.zig.system.linux: Add detection for some extra RISC-V CPUs
master
1 parent fd2d450
Changed files (1)
lib
std
zig
system
linux.zig
lib/std/zig/system/linux.zig
@@ -76,9 +76,11 @@ const RiscvCpuinfoImpl = struct {
 
     const cpu_names = .{
         .{ "sifive,u54", &Target.riscv.cpu.sifive_u54 },
+        .{ "sifive,u54-mc", &Target.riscv.cpu.sifive_u54 },
         .{ "sifive,u7", &Target.riscv.cpu.sifive_7_series },
         .{ "sifive,u74", &Target.riscv.cpu.sifive_u74 },
         .{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 },
+        .{ "spacemit,x60", &Target.riscv.cpu.spacemit_x60 },
     };
 
     fn line_hook(self: *RiscvCpuinfoImpl, key: []const u8, value: []const u8) !bool {