Commit 2fe32ef847
Changed files (9)
lib
std
src
lib/std/Target/propeller.zig
@@ -1,20 +1,46 @@
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
const std = @import("../std.zig");
const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;
-pub const Feature = enum {};
+pub const Feature = enum {
+ p2,
+};
pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
-pub const all_features: [0]CpuFeature = .{};
+pub const all_features = blk: {
+ const len = @typeInfo(Feature).@"enum".fields.len;
+ std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
+ var result: [len]CpuFeature = undefined;
+ result[@intFromEnum(Feature.p2)] = .{
+ .llvm_name = null,
+ .description = "Enable Propeller 2",
+ .dependencies = featureSet(&[_]Feature{}),
+ };
+ const ti = @typeInfo(Feature);
+ for (&result, 0..) |*elem, i| {
+ elem.index = i;
+ elem.name = ti.@"enum".fields[i].name;
+ }
+ break :blk result;
+};
pub const cpu = struct {
- pub const generic = CpuModel{
- .name = "generic",
+ pub const p1: CpuModel = .{
+ .name = "p1",
.llvm_name = null,
.features = featureSet(&[_]Feature{}),
};
+ pub const p2: CpuModel = .{
+ .name = "p2",
+ .llvm_name = null,
+ .features = featureSet(&[_]Feature{
+ .p2,
+ }),
+ };
};
lib/std/builtin.zig
@@ -371,12 +371,9 @@ pub const CallingConvention = union(enum(u8)) {
/// The standard `msp430` calling convention.
msp430_eabi: CommonOptions,
- /// The standard `propeller1` calling convention.
+ /// The standard `propeller` calling convention.
propeller1_sysv: CommonOptions,
- /// The standard `propeller2` calling convention.
- propeller2_sysv: CommonOptions,
-
// Calling conventions for the `s390x` architecture.
s390x_sysv: CommonOptions,
s390x_sysv_vx: CommonOptions,
lib/std/Target.zig
@@ -763,6 +763,7 @@ pub const mips = @import("Target/mips.zig");
pub const msp430 = @import("Target/msp430.zig");
pub const nvptx = @import("Target/nvptx.zig");
pub const powerpc = @import("Target/powerpc.zig");
+pub const propeller = @import("Target/propeller.zig");
pub const riscv = @import("Target/riscv.zig");
pub const sparc = @import("Target/sparc.zig");
pub const spirv = @import("Target/spirv.zig");
@@ -772,7 +773,6 @@ pub const wasm = @import("Target/wasm.zig");
pub const x86 = @import("Target/x86.zig");
pub const xcore = @import("Target/xcore.zig");
pub const xtensa = @import("Target/xtensa.zig");
-pub const propeller = @import("Target/propeller.zig");
pub const Abi = enum {
none,
@@ -1081,6 +1081,7 @@ pub fn toElfMachine(target: Target) std.elf.EM {
.msp430 => .MSP430,
.powerpc, .powerpcle => .PPC,
.powerpc64, .powerpc64le => .PPC64,
+ .propeller => .PROPELLER,
.riscv32, .riscv64 => .RISCV,
.s390x => .S390,
.sparc => if (Target.sparc.featureSetHas(target.cpu.features, .v9)) .SPARC32PLUS else .SPARC,
@@ -1091,9 +1092,6 @@ pub fn toElfMachine(target: Target) std.elf.EM {
.xcore => .XCORE,
.xtensa => .XTENSA,
- .propeller1 => .PROPELLER,
- .propeller2 => .PROPELLER2,
-
.nvptx,
.nvptx64,
.spirv,
@@ -1152,8 +1150,7 @@ pub fn toCoffMachine(target: Target) std.coff.MachineType {
.wasm64,
.xcore,
.xtensa,
- .propeller1,
- .propeller2,
+ .propeller,
=> .UNKNOWN,
};
}
@@ -1366,8 +1363,7 @@ pub const Cpu = struct {
powerpcle,
powerpc64,
powerpc64le,
- propeller1,
- propeller2,
+ propeller,
riscv32,
riscv64,
s390x,
@@ -1517,14 +1513,6 @@ pub const Cpu = struct {
};
}
- /// Returns if the architecture is a Parallax propeller architecture.
- pub inline fn isPropeller(arch: Arch) bool {
- return switch (arch) {
- .propeller1, .propeller2 => true,
- else => false,
- };
- }
-
pub fn parseCpuModel(arch: Arch, cpu_name: []const u8) !*const Cpu.Model {
for (arch.allCpuModels()) |cpu| {
if (std.mem.eql(u8, cpu_name, cpu.name)) {
@@ -1568,8 +1556,7 @@ pub const Cpu = struct {
.loongarch32,
.loongarch64,
.arc,
- .propeller1,
- .propeller2,
+ .propeller,
=> .little,
.armeb,
@@ -1604,8 +1591,8 @@ pub const Cpu = struct {
.flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr,
// Propeller address spaces:
- .cog, .hub => arch.isPropeller(),
- .lut => (arch == .propeller2),
+ .cog, .hub => arch == .propeller,
+ .lut => arch == .propeller, // TODO: This should check for the `p2` CPU feature.
};
}
@@ -1618,6 +1605,7 @@ pub const Cpu = struct {
.loongarch32, .loongarch64 => "loongarch",
.mips, .mipsel, .mips64, .mips64el => "mips",
.powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
+ .propeller => "propeller",
.riscv32, .riscv64 => "riscv",
.sparc, .sparc64 => "sparc",
.s390x => "s390x",
@@ -1625,7 +1613,6 @@ pub const Cpu = struct {
.nvptx, .nvptx64 => "nvptx",
.wasm32, .wasm64 => "wasm",
.spirv, .spirv32, .spirv64 => "spirv",
- .propeller1, .propeller2 => "propeller",
else => @tagName(arch),
};
}
@@ -1851,10 +1838,7 @@ pub const Cpu = struct {
=> &.{.msp430},
.propeller1_sysv,
- => &.{.propeller1},
-
- .propeller2_sysv,
- => &.{.propeller2},
+ => &.{.propeller},
.s390x_sysv,
.s390x_sysv_vx,
@@ -1933,8 +1917,7 @@ pub const Cpu = struct {
.msp430 => &msp430.cpu.generic,
.powerpc, .powerpcle => &powerpc.cpu.ppc,
.powerpc64, .powerpc64le => &powerpc.cpu.ppc64,
- .propeller1 => &propeller.cpu.generic,
- .propeller2 => &propeller.cpu.generic,
+ .propeller => &propeller.cpu.p1,
.riscv32 => &riscv.cpu.generic_rv32,
.riscv64 => &riscv.cpu.generic_rv64,
.spirv, .spirv32, .spirv64 => &spirv.cpu.generic,
@@ -2647,8 +2630,7 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
.spirv32,
.loongarch32,
.xtensa,
- .propeller1,
- .propeller2,
+ .propeller,
=> 32,
.aarch64,
@@ -3159,8 +3141,7 @@ pub fn cTypeAlignment(target: Target, c_type: CType) u16 {
.xcore,
.kalimba,
.xtensa,
- .propeller1,
- .propeller2,
+ .propeller,
=> 4,
.arm,
@@ -3254,8 +3235,7 @@ pub fn cTypePreferredAlignment(target: Target, c_type: CType) u16 {
.xcore,
.kalimba,
.xtensa,
- .propeller1,
- .propeller2,
+ .propeller,
=> 4,
.arc,
@@ -3360,8 +3340,7 @@ pub fn cCallingConvention(target: Target) ?std.builtin.CallingConvention {
else
.{ .m68k_sysv = .{} },
.msp430 => .{ .msp430_eabi = .{} },
- .propeller1 => .{ .propeller1_sysv = .{} },
- .propeller2 => .{ .propeller2_sysv = .{} },
+ .propeller => .{ .propeller1_sysv = .{} },
.s390x => .{ .s390x_sysv = .{} },
.ve => .{ .ve_sysv = .{} },
.xcore => .{ .xcore_xs1 = .{} },
src/codegen/llvm.zig
@@ -98,8 +98,7 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
.ve => "ve",
.kalimba,
- .propeller1,
- .propeller2,
+ .propeller,
=> unreachable, // Gated by hasLlvmSupport().
};
@@ -11834,7 +11833,6 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: std.Targ
.m68k_gnu,
.msp430_eabi,
.propeller1_sysv,
- .propeller2_sysv,
.s390x_sysv,
.s390x_sysv_vx,
.ve_sysv,
@@ -13023,8 +13021,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
// LLVM does does not have a backend for these.
.kalimba,
- .propeller1,
- .propeller2,
+ .propeller,
=> unreachable,
}
}
src/Sema.zig
@@ -37271,6 +37271,7 @@ pub fn analyzeAsAddressSpace(
const is_spirv = arch.isSpirV();
const is_gpu = is_nv or is_amd or is_spirv;
+ // TODO: Deduplicate with `std.Target.Cpu.Arch.supportsAddressSpace`.
const supported = switch (address_space) {
// TODO: on spir-v only when os is opencl.
.generic => true,
@@ -37283,8 +37284,8 @@ pub fn analyzeAsAddressSpace(
// TODO this should also check how many flash banks the cpu has
.flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr,
- .cog, .hub => arch.isPropeller(),
- .lut => (arch == .propeller2),
+ .cog, .hub => arch == .propeller,
+ .lut => arch == .propeller and std.Target.propeller.featureSetHas(target.cpu.features, .p2),
};
if (!supported) {
src/target.zig
@@ -195,8 +195,7 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
// No LLVM backend exists.
.kalimba,
- .propeller1,
- .propeller2,
+ .propeller,
=> false,
};
}
src/Type.zig
@@ -1647,7 +1647,7 @@ pub fn maxIntAlignment(target: std.Target) u16 {
.avr => 1,
.msp430 => 2,
.xcore => 4,
- .propeller1, .propeller2 => 4,
+ .propeller => 4,
.arm,
.armeb,
src/Zcu.zig
@@ -3619,8 +3619,7 @@ pub fn atomicPtrAlignment(
.spirv32,
.loongarch32,
.xtensa,
- .propeller1,
- .propeller2,
+ .propeller,
=> 32,
.amdgcn,
tools/update_cpu_features.zig
@@ -1016,6 +1016,29 @@ const targets = [_]ArchTarget{
"ppc32",
},
},
+ .{
+ .zig_name = "propeller",
+ .llvm = null,
+ .extra_features = &.{
+ .{
+ .zig_name = "p2",
+ .desc = "Enable Propeller 2",
+ .deps = &.{},
+ },
+ },
+ .extra_cpus = &.{
+ .{
+ .llvm_name = null,
+ .zig_name = "p1",
+ .features = &.{},
+ },
+ .{
+ .llvm_name = null,
+ .zig_name = "p2",
+ .features = &.{"p2"},
+ },
+ },
+ },
.{
.zig_name = "riscv",
.llvm = .{