Commit 0f46c12f78
Changed files (36)
lib
std
target
cpu
feature
lib/std/target/cpu/AArch64Cpu.zig
@@ -0,0 +1,480 @@
+const feature = @import("std").target.feature;
+const CpuInfo = @import("std").target.cpu.CpuInfo;
+
+pub const AArch64Cpu = enum {
+ AppleLatest,
+ CortexA35,
+ CortexA53,
+ CortexA55,
+ CortexA57,
+ CortexA65,
+ CortexA65ae,
+ CortexA72,
+ CortexA73,
+ CortexA75,
+ CortexA76,
+ CortexA76ae,
+ Cyclone,
+ ExynosM1,
+ ExynosM2,
+ ExynosM3,
+ ExynosM4,
+ ExynosM5,
+ Falkor,
+ Generic,
+ Kryo,
+ NeoverseE1,
+ NeoverseN1,
+ Saphira,
+ Thunderx,
+ Thunderx2t99,
+ Thunderxt81,
+ Thunderxt83,
+ Thunderxt88,
+ Tsv110,
+
+ pub fn getInfo(self: @This()) CpuInfo {
+ return cpu_infos[@enumToInt(self)];
+ }
+
+ pub const FeatureType = feature.AArch64Feature;
+
+ const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
+ CpuInfo(@This()).create(.AppleLatest, "apple-latest", &[_]FeatureType {
+ .ZczFp,
+ .ArithCbzFusion,
+ .FuseAes,
+ .AlternateSextloadCvtF32Pattern,
+ .ZczFpWorkaround,
+ .FpArmv8,
+ .Perfmon,
+ .DisableLatencySchedHeuristic,
+ .Zcm,
+ .ZczGp,
+ .ArithBccFusion,
+ .FuseCryptoEor,
+ .Cyclone,
+ },
+ CpuInfo(@This()).create(.CortexA35, "cortex-a35", &[_]FeatureType {
+ .Perfmon,
+ .FpArmv8,
+ .Crc,
+ .A35,
+ },
+ CpuInfo(@This()).create(.CortexA53, "cortex-a53", &[_]FeatureType {
+ .UseAa,
+ .FuseAes,
+ .FpArmv8,
+ .Perfmon,
+ .Crc,
+ .BalanceFpOps,
+ .UsePostraScheduler,
+ .CustomCheapAsMove,
+ .A53,
+ },
+ CpuInfo(@This()).create(.CortexA55, "cortex-a55", &[_]FeatureType {
+ .Rcpc,
+ .Ccpp,
+ .Pan,
+ .Rdm,
+ .FuseAes,
+ .Perfmon,
+ .FpArmv8,
+ .Lse,
+ .Crc,
+ .Dotprod,
+ .Lor,
+ .Uaops,
+ .Vh,
+ .Ras,
+ .A55,
+ },
+ CpuInfo(@This()).create(.CortexA57, "cortex-a57", &[_]FeatureType {
+ .FuseLiterals,
+ .FuseAes,
+ .FpArmv8,
+ .Perfmon,
+ .Crc,
+ .BalanceFpOps,
+ .UsePostraScheduler,
+ .CustomCheapAsMove,
+ .PredictableSelectExpensive,
+ .A57,
+ },
+ CpuInfo(@This()).create(.CortexA65, "cortex-a65", &[_]FeatureType {
+ .Rcpc,
+ .Ccpp,
+ .Pan,
+ .Rdm,
+ .FpArmv8,
+ .Lse,
+ .Crc,
+ .Dotprod,
+ .Lor,
+ .Ssbs,
+ .Uaops,
+ .Vh,
+ .Ras,
+ .A65,
+ },
+ CpuInfo(@This()).create(.CortexA65ae, "cortex-a65ae", &[_]FeatureType {
+ .Rcpc,
+ .Ccpp,
+ .Pan,
+ .Rdm,
+ .FpArmv8,
+ .Lse,
+ .Crc,
+ .Dotprod,
+ .Lor,
+ .Ssbs,
+ .Uaops,
+ .Vh,
+ .Ras,
+ .A65,
+ },
+ CpuInfo(@This()).create(.CortexA72, "cortex-a72", &[_]FeatureType {
+ .Perfmon,
+ .FuseAes,
+ .FpArmv8,
+ .Crc,
+ .A72,
+ },
+ CpuInfo(@This()).create(.CortexA73, "cortex-a73", &[_]FeatureType {
+ .Perfmon,
+ .FuseAes,
+ .FpArmv8,
+ .Crc,
+ .A73,
+ },
+ CpuInfo(@This()).create(.CortexA75, "cortex-a75", &[_]FeatureType {
+ .Rcpc,
+ .Ccpp,
+ .Pan,
+ .Rdm,
+ .FuseAes,
+ .Perfmon,
+ .FpArmv8,
+ .Lse,
+ .Crc,
+ .Dotprod,
+ .Lor,
+ .Uaops,
+ .Vh,
+ .Ras,
+ .A75,
+ },
+ CpuInfo(@This()).create(.CortexA76, "cortex-a76", &[_]FeatureType {
+ .Rcpc,
+ .Ccpp,
+ .Pan,
+ .Rdm,
+ .FpArmv8,
+ .Lse,
+ .Crc,
+ .Dotprod,
+ .Lor,
+ .Ssbs,
+ .Uaops,
+ .Vh,
+ .Ras,
+ .A76,
+ },
+ CpuInfo(@This()).create(.CortexA76ae, "cortex-a76ae", &[_]FeatureType {
+ .Rcpc,
+ .Ccpp,
+ .Pan,
+ .Rdm,
+ .FpArmv8,
+ .Lse,
+ .Crc,
+ .Dotprod,
+ .Lor,
+ .Ssbs,
+ .Uaops,
+ .Vh,
+ .Ras,
+ .A76,
+ },
+ CpuInfo(@This()).create(.Cyclone, "cyclone", &[_]FeatureType {
+ .ZczFp,
+ .ArithCbzFusion,
+ .FuseAes,
+ .AlternateSextloadCvtF32Pattern,
+ .ZczFpWorkaround,
+ .FpArmv8,
+ .Perfmon,
+ .DisableLatencySchedHeuristic,
+ .Zcm,
+ .ZczGp,
+ .ArithBccFusion,
+ .FuseCryptoEor,
+ .Cyclone,
+ },
+ CpuInfo(@This()).create(.ExynosM1, "exynos-m1", &[_]FeatureType {
+ .ZczFp,
+ .FuseAes,
+ .SlowPaired128,
+ .Force32bitJumpTables,
+ .UseReciprocalSquareRoot,
+ .FpArmv8,
+ .Perfmon,
+ .SlowMisaligned128store,
+ .Crc,
+ .UsePostraScheduler,
+ .CustomCheapAsMove,
+ .Exynosm1,
+ },
+ CpuInfo(@This()).create(.ExynosM2, "exynos-m2", &[_]FeatureType {
+ .ZczFp,
+ .FuseAes,
+ .SlowPaired128,
+ .Force32bitJumpTables,
+ .FpArmv8,
+ .Perfmon,
+ .SlowMisaligned128store,
+ .Crc,
+ .UsePostraScheduler,
+ .CustomCheapAsMove,
+ .Exynosm2,
+ },
+ CpuInfo(@This()).create(.ExynosM3, "exynos-m3", &[_]FeatureType {
+ .ZczFp,
+ .FuseLiterals,
+ .FuseAes,
+ .Force32bitJumpTables,
+ .FpArmv8,
+ .Perfmon,
+ .Crc,
+ .LslFast,
+ .FuseAddress,
+ .UsePostraScheduler,
+ .CustomCheapAsMove,
+ .PredictableSelectExpensive,
+ .FuseCsel,
+ .Exynosm3,
+ },
+ CpuInfo(@This()).create(.ExynosM4, "exynos-m4", &[_]FeatureType {
+ .ZczFp,
+ .Lse,
+ .FuseArithLogic,
+ .Lor,
+ .UsePostraScheduler,
+ .Uaops,
+ .CustomCheapAsMove,
+ .ArithBccFusion,
+ .Ccpp,
+ .Perfmon,
+ .Pan,
+ .Rdm,
+ .FuseLiterals,
+ .Force32bitJumpTables,
+ .LslFast,
+ .FuseAddress,
+ .ZczGp,
+ .Ras,
+ .FuseCsel,
+ .ArithCbzFusion,
+ .FuseAes,
+ .FpArmv8,
+ .Crc,
+ .Dotprod,
+ .Vh,
+ .Exynosm4,
+ },
+ CpuInfo(@This()).create(.ExynosM5, "exynos-m5", &[_]FeatureType {
+ .ZczFp,
+ .Lse,
+ .FuseArithLogic,
+ .Lor,
+ .UsePostraScheduler,
+ .Uaops,
+ .CustomCheapAsMove,
+ .ArithBccFusion,
+ .Ccpp,
+ .Perfmon,
+ .Pan,
+ .Rdm,
+ .FuseLiterals,
+ .Force32bitJumpTables,
+ .LslFast,
+ .FuseAddress,
+ .ZczGp,
+ .Ras,
+ .FuseCsel,
+ .ArithCbzFusion,
+ .FuseAes,
+ .FpArmv8,
+ .Crc,
+ .Dotprod,
+ .Vh,
+ .Exynosm4,
+ },
+ CpuInfo(@This()).create(.Falkor, "falkor", &[_]FeatureType {
+ .ZczFp,
+ .Rdm,
+ .SlowStrqroStore,
+ .Perfmon,
+ .FpArmv8,
+ .Crc,
+ .LslFast,
+ .UsePostraScheduler,
+ .ZczGp,
+ .CustomCheapAsMove,
+ .PredictableSelectExpensive,
+ .Falkor,
+ },
+ CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
+ .Trbe,
+ .Ete,
+ .FpArmv8,
+ .FuseAes,
+ .Neon,
+ .Perfmon,
+ .UsePostraScheduler,
+ },
+ CpuInfo(@This()).create(.Kryo, "kryo", &[_]FeatureType {
+ .ZczFp,
+ .Perfmon,
+ .FpArmv8,
+ .Crc,
+ .LslFast,
+ .UsePostraScheduler,
+ .ZczGp,
+ .CustomCheapAsMove,
+ .PredictableSelectExpensive,
+ .Kryo,
+ },
+ CpuInfo(@This()).create(.NeoverseE1, "neoverse-e1", &[_]FeatureType {
+ .Rcpc,
+ .Ccpp,
+ .Pan,
+ .Rdm,
+ .FpArmv8,
+ .Lse,
+ .Crc,
+ .Dotprod,
+ .Lor,
+ .Ssbs,
+ .Uaops,
+ .Vh,
+ .Ras,
+ .Neoversee1,
+ },
+ CpuInfo(@This()).create(.NeoverseN1, "neoverse-n1", &[_]FeatureType {
+ .Rcpc,
+ .Spe,
+ .Ccpp,
+ .Pan,
+ .Rdm,
+ .FpArmv8,
+ .Lse,
+ .Crc,
+ .Dotprod,
+ .Lor,
+ .Ssbs,
+ .Uaops,
+ .Vh,
+ .Ras,
+ .Neoversen1,
+ },
+ CpuInfo(@This()).create(.Saphira, "saphira", &[_]FeatureType {
+ .ZczFp,
+ .Nv,
+ .Am,
+ .Lse,
+ .Sel2,
+ .Lor,
+ .Tracev84,
+ .Uaops,
+ .UsePostraScheduler,
+ .CustomCheapAsMove,
+ .Ccpp,
+ .Perfmon,
+ .TlbRmi,
+ .PredictableSelectExpensive,
+ .Fmi,
+ .Rcpc,
+ .Pan,
+ .Rdm,
+ .LslFast,
+ .Pa,
+ .ZczGp,
+ .Dit,
+ .Ras,
+ .Spe,
+ .Mpam,
+ .FpArmv8,
+ .Ccidx,
+ .Dotprod,
+ .Crc,
+ .Vh,
+ .Saphira,
+ },
+ CpuInfo(@This()).create(.Thunderx, "thunderx", &[_]FeatureType {
+ .Perfmon,
+ .FpArmv8,
+ .Crc,
+ .UsePostraScheduler,
+ .PredictableSelectExpensive,
+ .Thunderx,
+ },
+ CpuInfo(@This()).create(.Thunderx2t99, "thunderx2t99", &[_]FeatureType {
+ .Pan,
+ .Rdm,
+ .Vh,
+ .AggressiveFma,
+ .FpArmv8,
+ .Lse,
+ .Crc,
+ .Lor,
+ .UsePostraScheduler,
+ .ArithBccFusion,
+ .PredictableSelectExpensive,
+ .Thunderx2t99,
+ },
+ CpuInfo(@This()).create(.Thunderxt81, "thunderxt81", &[_]FeatureType {
+ .Perfmon,
+ .FpArmv8,
+ .Crc,
+ .UsePostraScheduler,
+ .PredictableSelectExpensive,
+ .Thunderxt81,
+ },
+ CpuInfo(@This()).create(.Thunderxt83, "thunderxt83", &[_]FeatureType {
+ .Perfmon,
+ .FpArmv8,
+ .Crc,
+ .UsePostraScheduler,
+ .PredictableSelectExpensive,
+ .Thunderxt83,
+ },
+ CpuInfo(@This()).create(.Thunderxt88, "thunderxt88", &[_]FeatureType {
+ .Perfmon,
+ .FpArmv8,
+ .Crc,
+ .UsePostraScheduler,
+ .PredictableSelectExpensive,
+ .Thunderxt88,
+ },
+ CpuInfo(@This()).create(.Tsv110, "tsv110", &[_]FeatureType {
+ .Uaops,
+ .Spe,
+ .Ccpp,
+ .Pan,
+ .Rdm,
+ .FuseAes,
+ .Vh,
+ .Perfmon,
+ .FpArmv8,
+ .Lse,
+ .Crc,
+ .Dotprod,
+ .Lor,
+ .UsePostraScheduler,
+ .CustomCheapAsMove,
+ .Ras,
+ .Tsv110,
+ },
+ };
+};
lib/std/target/cpu/AmdGpuCpu.zig
@@ -0,0 +1,1060 @@
+const feature = @import("std").target.feature;
+const CpuInfo = @import("std").target.cpu.CpuInfo;
+
+pub const AmdGpuCpu = enum {
+ Bonaire,
+ Carrizo,
+ Fiji,
+ Generic,
+ GenericHsa,
+ Gfx1010,
+ Gfx1011,
+ Gfx1012,
+ Gfx600,
+ Gfx601,
+ Gfx700,
+ Gfx701,
+ Gfx702,
+ Gfx703,
+ Gfx704,
+ Gfx801,
+ Gfx802,
+ Gfx803,
+ Gfx810,
+ Gfx900,
+ Gfx902,
+ Gfx904,
+ Gfx906,
+ Gfx908,
+ Gfx909,
+ Hainan,
+ Hawaii,
+ Iceland,
+ Kabini,
+ Kaveri,
+ Mullins,
+ Oland,
+ Pitcairn,
+ Polaris10,
+ Polaris11,
+ Stoney,
+ Tahiti,
+ Tonga,
+ Verde,
+
+ pub fn getInfo(self: @This()) CpuInfo {
+ return cpu_infos[@enumToInt(self)];
+ }
+
+ pub const FeatureType = feature.AmdGpuFeature;
+
+ const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
+ CpuInfo(@This()).create(.Bonaire, "bonaire", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .Ldsbankcount32,
+ .Wavefrontsize64,
+ .MimgR128,
+ .Fp64,
+ .CiInsts,
+ .FlatAddressSpace,
+ .TrigReducedRange,
+ .NoSramEccSupport,
+ .Movrel,
+ .Localmemorysize65536,
+ .Gfx7Gfx8Gfx9Insts,
+ .SeaIslands,
+ },
+ CpuInfo(@This()).create(.Carrizo, "carrizo", &[_]FeatureType {
+ .CodeObjectV3,
+ .FastFmaf,
+ .Ldsbankcount32,
+ .UnpackedD16Vmem,
+ .Wavefrontsize64,
+ .Fp64,
+ .Gcn3Encoding,
+ .TrigReducedRange,
+ .Sdwa,
+ .VgprIndexMode,
+ .Dpp,
+ .FlatAddressSpace,
+ .Gfx8Insts,
+ .Gfx7Gfx8Gfx9Insts,
+ .MimgR128,
+ .NoSramEccSupport,
+ .IntClampInsts,
+ .ScalarStores,
+ .Movrel,
+ .SdwaMav,
+ .CiInsts,
+ .BitInsts16,
+ .SMemrealtime,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .SdwaOutModsVopc,
+ .VolcanicIslands,
+ .Xnack,
+ .HalfRate64Ops,
+ },
+ CpuInfo(@This()).create(.Fiji, "fiji", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .Ldsbankcount32,
+ .UnpackedD16Vmem,
+ .Wavefrontsize64,
+ .Fp64,
+ .Gcn3Encoding,
+ .TrigReducedRange,
+ .Sdwa,
+ .VgprIndexMode,
+ .Dpp,
+ .FlatAddressSpace,
+ .Gfx8Insts,
+ .Gfx7Gfx8Gfx9Insts,
+ .MimgR128,
+ .NoSramEccSupport,
+ .IntClampInsts,
+ .ScalarStores,
+ .Movrel,
+ .SdwaMav,
+ .CiInsts,
+ .BitInsts16,
+ .SMemrealtime,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .SdwaOutModsVopc,
+ .VolcanicIslands,
+ },
+ CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
+ .Wavefrontsize64,
+ },
+ CpuInfo(@This()).create(.GenericHsa, "generic-hsa", &[_]FeatureType {
+ .FlatAddressSpace,
+ .Wavefrontsize64,
+ },
+ CpuInfo(@This()).create(.Gfx1010, "gfx1010", &[_]FeatureType {
+ .CodeObjectV3,
+ .DlInsts,
+ .NoXnackSupport,
+ .FlatSegmentOffsetBug,
+ .Gfx9Insts,
+ .NoSdstCmpx,
+ .Fp64,
+ .FastFmaf,
+ .Sdwa,
+ .SdwaScalar,
+ .Dpp,
+ .RegisterBanking,
+ .Gfx10Insts,
+ .AddNoCarryInsts,
+ .SdwaOmod,
+ .SdwaSdst,
+ .FlatAddressSpace,
+ .Gfx8Insts,
+ .FmaMixInsts,
+ .PkFmacF16Inst,
+ .Vop3Literal,
+ .MimgR128,
+ .NoSramEccSupport,
+ .IntClampInsts,
+ .Movrel,
+ .Dpp8,
+ .ApertureRegs,
+ .NoDataDepHazard,
+ .CiInsts,
+ .FlatGlobalInsts,
+ .BitInsts16,
+ .FlatScratchInsts,
+ .SMemrealtime,
+ .Vop3p,
+ .FlatInstOffsets,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .Vscnt,
+ .Gfx10,
+ .InstFwdPrefetchBug,
+ .Ldsbankcount32,
+ .LdsBranchVmemWarHazard,
+ .LdsMisalignedBug,
+ .NsaEncoding,
+ .NsaToVmemBug,
+ .Offset3fBug,
+ .SmemToVectorWriteHazard,
+ .ScalarAtomics,
+ .ScalarFlatScratchInsts,
+ .ScalarStores,
+ .VmemToScalarWriteHazard,
+ .VcmpxExecWarHazard,
+ .VcmpxPermlaneHazard,
+ .Wavefrontsize32,
+ },
+ CpuInfo(@This()).create(.Gfx1011, "gfx1011", &[_]FeatureType {
+ .CodeObjectV3,
+ .DlInsts,
+ .NoXnackSupport,
+ .Dot1Insts,
+ .Dot2Insts,
+ .Dot5Insts,
+ .Dot6Insts,
+ .FlatSegmentOffsetBug,
+ .Gfx9Insts,
+ .NoSdstCmpx,
+ .Fp64,
+ .FastFmaf,
+ .Sdwa,
+ .SdwaScalar,
+ .Dpp,
+ .RegisterBanking,
+ .Gfx10Insts,
+ .AddNoCarryInsts,
+ .SdwaOmod,
+ .SdwaSdst,
+ .FlatAddressSpace,
+ .Gfx8Insts,
+ .FmaMixInsts,
+ .PkFmacF16Inst,
+ .Vop3Literal,
+ .MimgR128,
+ .NoSramEccSupport,
+ .IntClampInsts,
+ .Movrel,
+ .Dpp8,
+ .ApertureRegs,
+ .NoDataDepHazard,
+ .CiInsts,
+ .FlatGlobalInsts,
+ .BitInsts16,
+ .FlatScratchInsts,
+ .SMemrealtime,
+ .Vop3p,
+ .FlatInstOffsets,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .Vscnt,
+ .Gfx10,
+ .InstFwdPrefetchBug,
+ .Ldsbankcount32,
+ .LdsBranchVmemWarHazard,
+ .NsaEncoding,
+ .NsaToVmemBug,
+ .Offset3fBug,
+ .SmemToVectorWriteHazard,
+ .ScalarAtomics,
+ .ScalarFlatScratchInsts,
+ .ScalarStores,
+ .VmemToScalarWriteHazard,
+ .VcmpxExecWarHazard,
+ .VcmpxPermlaneHazard,
+ .Wavefrontsize32,
+ },
+ CpuInfo(@This()).create(.Gfx1012, "gfx1012", &[_]FeatureType {
+ .CodeObjectV3,
+ .DlInsts,
+ .NoXnackSupport,
+ .Dot1Insts,
+ .Dot2Insts,
+ .Dot5Insts,
+ .Dot6Insts,
+ .FlatSegmentOffsetBug,
+ .Gfx9Insts,
+ .NoSdstCmpx,
+ .Fp64,
+ .FastFmaf,
+ .Sdwa,
+ .SdwaScalar,
+ .Dpp,
+ .RegisterBanking,
+ .Gfx10Insts,
+ .AddNoCarryInsts,
+ .SdwaOmod,
+ .SdwaSdst,
+ .FlatAddressSpace,
+ .Gfx8Insts,
+ .FmaMixInsts,
+ .PkFmacF16Inst,
+ .Vop3Literal,
+ .MimgR128,
+ .NoSramEccSupport,
+ .IntClampInsts,
+ .Movrel,
+ .Dpp8,
+ .ApertureRegs,
+ .NoDataDepHazard,
+ .CiInsts,
+ .FlatGlobalInsts,
+ .BitInsts16,
+ .FlatScratchInsts,
+ .SMemrealtime,
+ .Vop3p,
+ .FlatInstOffsets,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .Vscnt,
+ .Gfx10,
+ .InstFwdPrefetchBug,
+ .Ldsbankcount32,
+ .LdsBranchVmemWarHazard,
+ .LdsMisalignedBug,
+ .NsaEncoding,
+ .NsaToVmemBug,
+ .Offset3fBug,
+ .SmemToVectorWriteHazard,
+ .ScalarAtomics,
+ .ScalarFlatScratchInsts,
+ .ScalarStores,
+ .VmemToScalarWriteHazard,
+ .VcmpxExecWarHazard,
+ .VcmpxPermlaneHazard,
+ .Wavefrontsize32,
+ },
+ CpuInfo(@This()).create(.Gfx600, "gfx600", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .FastFmaf,
+ .Ldsbankcount32,
+ .Wavefrontsize64,
+ .MimgR128,
+ .Fp64,
+ .TrigReducedRange,
+ .NoSramEccSupport,
+ .Movrel,
+ .Localmemorysize32768,
+ .SouthernIslands,
+ .HalfRate64Ops,
+ },
+ CpuInfo(@This()).create(.Gfx601, "gfx601", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .Ldsbankcount32,
+ .Wavefrontsize64,
+ .MimgR128,
+ .Fp64,
+ .TrigReducedRange,
+ .NoSramEccSupport,
+ .Movrel,
+ .Localmemorysize32768,
+ .SouthernIslands,
+ },
+ CpuInfo(@This()).create(.Gfx700, "gfx700", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .Ldsbankcount32,
+ .Wavefrontsize64,
+ .MimgR128,
+ .Fp64,
+ .CiInsts,
+ .FlatAddressSpace,
+ .TrigReducedRange,
+ .NoSramEccSupport,
+ .Movrel,
+ .Localmemorysize65536,
+ .Gfx7Gfx8Gfx9Insts,
+ .SeaIslands,
+ },
+ CpuInfo(@This()).create(.Gfx701, "gfx701", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .FastFmaf,
+ .Ldsbankcount32,
+ .Wavefrontsize64,
+ .MimgR128,
+ .Fp64,
+ .CiInsts,
+ .FlatAddressSpace,
+ .TrigReducedRange,
+ .NoSramEccSupport,
+ .Movrel,
+ .Localmemorysize65536,
+ .Gfx7Gfx8Gfx9Insts,
+ .SeaIslands,
+ .HalfRate64Ops,
+ },
+ CpuInfo(@This()).create(.Gfx702, "gfx702", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .FastFmaf,
+ .Ldsbankcount16,
+ .Wavefrontsize64,
+ .MimgR128,
+ .Fp64,
+ .CiInsts,
+ .FlatAddressSpace,
+ .TrigReducedRange,
+ .NoSramEccSupport,
+ .Movrel,
+ .Localmemorysize65536,
+ .Gfx7Gfx8Gfx9Insts,
+ .SeaIslands,
+ },
+ CpuInfo(@This()).create(.Gfx703, "gfx703", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .Ldsbankcount16,
+ .Wavefrontsize64,
+ .MimgR128,
+ .Fp64,
+ .CiInsts,
+ .FlatAddressSpace,
+ .TrigReducedRange,
+ .NoSramEccSupport,
+ .Movrel,
+ .Localmemorysize65536,
+ .Gfx7Gfx8Gfx9Insts,
+ .SeaIslands,
+ },
+ CpuInfo(@This()).create(.Gfx704, "gfx704", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .Ldsbankcount32,
+ .Wavefrontsize64,
+ .MimgR128,
+ .Fp64,
+ .CiInsts,
+ .FlatAddressSpace,
+ .TrigReducedRange,
+ .NoSramEccSupport,
+ .Movrel,
+ .Localmemorysize65536,
+ .Gfx7Gfx8Gfx9Insts,
+ .SeaIslands,
+ },
+ CpuInfo(@This()).create(.Gfx801, "gfx801", &[_]FeatureType {
+ .CodeObjectV3,
+ .FastFmaf,
+ .Ldsbankcount32,
+ .UnpackedD16Vmem,
+ .Wavefrontsize64,
+ .Fp64,
+ .Gcn3Encoding,
+ .TrigReducedRange,
+ .Sdwa,
+ .VgprIndexMode,
+ .Dpp,
+ .FlatAddressSpace,
+ .Gfx8Insts,
+ .Gfx7Gfx8Gfx9Insts,
+ .MimgR128,
+ .NoSramEccSupport,
+ .IntClampInsts,
+ .ScalarStores,
+ .Movrel,
+ .SdwaMav,
+ .CiInsts,
+ .BitInsts16,
+ .SMemrealtime,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .SdwaOutModsVopc,
+ .VolcanicIslands,
+ .Xnack,
+ .HalfRate64Ops,
+ },
+ CpuInfo(@This()).create(.Gfx802, "gfx802", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .Ldsbankcount32,
+ .SgprInitBug,
+ .UnpackedD16Vmem,
+ .Wavefrontsize64,
+ .Fp64,
+ .Gcn3Encoding,
+ .TrigReducedRange,
+ .Sdwa,
+ .VgprIndexMode,
+ .Dpp,
+ .FlatAddressSpace,
+ .Gfx8Insts,
+ .Gfx7Gfx8Gfx9Insts,
+ .MimgR128,
+ .NoSramEccSupport,
+ .IntClampInsts,
+ .ScalarStores,
+ .Movrel,
+ .SdwaMav,
+ .CiInsts,
+ .BitInsts16,
+ .SMemrealtime,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .SdwaOutModsVopc,
+ .VolcanicIslands,
+ },
+ CpuInfo(@This()).create(.Gfx803, "gfx803", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .Ldsbankcount32,
+ .UnpackedD16Vmem,
+ .Wavefrontsize64,
+ .Fp64,
+ .Gcn3Encoding,
+ .TrigReducedRange,
+ .Sdwa,
+ .VgprIndexMode,
+ .Dpp,
+ .FlatAddressSpace,
+ .Gfx8Insts,
+ .Gfx7Gfx8Gfx9Insts,
+ .MimgR128,
+ .NoSramEccSupport,
+ .IntClampInsts,
+ .ScalarStores,
+ .Movrel,
+ .SdwaMav,
+ .CiInsts,
+ .BitInsts16,
+ .SMemrealtime,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .SdwaOutModsVopc,
+ .VolcanicIslands,
+ },
+ CpuInfo(@This()).create(.Gfx810, "gfx810", &[_]FeatureType {
+ .CodeObjectV3,
+ .Ldsbankcount16,
+ .Wavefrontsize64,
+ .Fp64,
+ .Gcn3Encoding,
+ .TrigReducedRange,
+ .Sdwa,
+ .VgprIndexMode,
+ .Dpp,
+ .FlatAddressSpace,
+ .Gfx8Insts,
+ .Gfx7Gfx8Gfx9Insts,
+ .MimgR128,
+ .NoSramEccSupport,
+ .IntClampInsts,
+ .ScalarStores,
+ .Movrel,
+ .SdwaMav,
+ .CiInsts,
+ .BitInsts16,
+ .SMemrealtime,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .SdwaOutModsVopc,
+ .VolcanicIslands,
+ .Xnack,
+ },
+ CpuInfo(@This()).create(.Gfx900, "gfx900", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoSramEccSupport,
+ .NoXnackSupport,
+ .Gfx9Insts,
+ .Wavefrontsize64,
+ .Fp64,
+ .Gcn3Encoding,
+ .FastFmaf,
+ .Sdwa,
+ .SdwaScalar,
+ .VgprIndexMode,
+ .Dpp,
+ .AddNoCarryInsts,
+ .SdwaOmod,
+ .SdwaSdst,
+ .ScalarAtomics,
+ .FlatAddressSpace,
+ .ScalarFlatScratchInsts,
+ .Gfx8Insts,
+ .Gfx7Gfx8Gfx9Insts,
+ .R128A16,
+ .IntClampInsts,
+ .ScalarStores,
+ .ApertureRegs,
+ .CiInsts,
+ .FlatGlobalInsts,
+ .BitInsts16,
+ .FlatScratchInsts,
+ .SMemrealtime,
+ .Vop3p,
+ .FlatInstOffsets,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .Gfx9,
+ .Ldsbankcount32,
+ .MadMixInsts,
+ },
+ CpuInfo(@This()).create(.Gfx902, "gfx902", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoSramEccSupport,
+ .Gfx9Insts,
+ .Wavefrontsize64,
+ .Fp64,
+ .Gcn3Encoding,
+ .FastFmaf,
+ .Sdwa,
+ .SdwaScalar,
+ .VgprIndexMode,
+ .Dpp,
+ .AddNoCarryInsts,
+ .SdwaOmod,
+ .SdwaSdst,
+ .ScalarAtomics,
+ .FlatAddressSpace,
+ .ScalarFlatScratchInsts,
+ .Gfx8Insts,
+ .Gfx7Gfx8Gfx9Insts,
+ .R128A16,
+ .IntClampInsts,
+ .ScalarStores,
+ .ApertureRegs,
+ .CiInsts,
+ .FlatGlobalInsts,
+ .BitInsts16,
+ .FlatScratchInsts,
+ .SMemrealtime,
+ .Vop3p,
+ .FlatInstOffsets,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .Gfx9,
+ .Ldsbankcount32,
+ .MadMixInsts,
+ .Xnack,
+ },
+ CpuInfo(@This()).create(.Gfx904, "gfx904", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoSramEccSupport,
+ .NoXnackSupport,
+ .FmaMixInsts,
+ .Gfx9Insts,
+ .Wavefrontsize64,
+ .Fp64,
+ .Gcn3Encoding,
+ .FastFmaf,
+ .Sdwa,
+ .SdwaScalar,
+ .VgprIndexMode,
+ .Dpp,
+ .AddNoCarryInsts,
+ .SdwaOmod,
+ .SdwaSdst,
+ .ScalarAtomics,
+ .FlatAddressSpace,
+ .ScalarFlatScratchInsts,
+ .Gfx8Insts,
+ .Gfx7Gfx8Gfx9Insts,
+ .R128A16,
+ .IntClampInsts,
+ .ScalarStores,
+ .ApertureRegs,
+ .CiInsts,
+ .FlatGlobalInsts,
+ .BitInsts16,
+ .FlatScratchInsts,
+ .SMemrealtime,
+ .Vop3p,
+ .FlatInstOffsets,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .Gfx9,
+ .Ldsbankcount32,
+ },
+ CpuInfo(@This()).create(.Gfx906, "gfx906", &[_]FeatureType {
+ .CodeObjectV3,
+ .DlInsts,
+ .NoXnackSupport,
+ .Dot1Insts,
+ .Dot2Insts,
+ .FmaMixInsts,
+ .Gfx9Insts,
+ .Wavefrontsize64,
+ .Fp64,
+ .Gcn3Encoding,
+ .FastFmaf,
+ .Sdwa,
+ .SdwaScalar,
+ .VgprIndexMode,
+ .Dpp,
+ .AddNoCarryInsts,
+ .SdwaOmod,
+ .SdwaSdst,
+ .ScalarAtomics,
+ .FlatAddressSpace,
+ .ScalarFlatScratchInsts,
+ .Gfx8Insts,
+ .Gfx7Gfx8Gfx9Insts,
+ .R128A16,
+ .IntClampInsts,
+ .ScalarStores,
+ .ApertureRegs,
+ .CiInsts,
+ .FlatGlobalInsts,
+ .BitInsts16,
+ .FlatScratchInsts,
+ .SMemrealtime,
+ .Vop3p,
+ .FlatInstOffsets,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .Gfx9,
+ .Ldsbankcount32,
+ .HalfRate64Ops,
+ },
+ CpuInfo(@This()).create(.Gfx908, "gfx908", &[_]FeatureType {
+ .AtomicFaddInsts,
+ .CodeObjectV3,
+ .DlInsts,
+ .Dot1Insts,
+ .Dot2Insts,
+ .Dot3Insts,
+ .Dot4Insts,
+ .Dot5Insts,
+ .Dot6Insts,
+ .FmaMixInsts,
+ .Gfx9Insts,
+ .Wavefrontsize64,
+ .Fp64,
+ .Gcn3Encoding,
+ .FastFmaf,
+ .Sdwa,
+ .SdwaScalar,
+ .VgprIndexMode,
+ .Dpp,
+ .AddNoCarryInsts,
+ .SdwaOmod,
+ .SdwaSdst,
+ .ScalarAtomics,
+ .FlatAddressSpace,
+ .ScalarFlatScratchInsts,
+ .Gfx8Insts,
+ .Gfx7Gfx8Gfx9Insts,
+ .R128A16,
+ .IntClampInsts,
+ .ScalarStores,
+ .ApertureRegs,
+ .CiInsts,
+ .FlatGlobalInsts,
+ .BitInsts16,
+ .FlatScratchInsts,
+ .SMemrealtime,
+ .Vop3p,
+ .FlatInstOffsets,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .Gfx9,
+ .Ldsbankcount32,
+ .MaiInsts,
+ .MfmaInlineLiteralBug,
+ .PkFmacF16Inst,
+ .SramEcc,
+ .HalfRate64Ops,
+ },
+ CpuInfo(@This()).create(.Gfx909, "gfx909", &[_]FeatureType {
+ .CodeObjectV3,
+ .Gfx9Insts,
+ .Wavefrontsize64,
+ .Fp64,
+ .Gcn3Encoding,
+ .FastFmaf,
+ .Sdwa,
+ .SdwaScalar,
+ .VgprIndexMode,
+ .Dpp,
+ .AddNoCarryInsts,
+ .SdwaOmod,
+ .SdwaSdst,
+ .ScalarAtomics,
+ .FlatAddressSpace,
+ .ScalarFlatScratchInsts,
+ .Gfx8Insts,
+ .Gfx7Gfx8Gfx9Insts,
+ .R128A16,
+ .IntClampInsts,
+ .ScalarStores,
+ .ApertureRegs,
+ .CiInsts,
+ .FlatGlobalInsts,
+ .BitInsts16,
+ .FlatScratchInsts,
+ .SMemrealtime,
+ .Vop3p,
+ .FlatInstOffsets,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .Gfx9,
+ .Ldsbankcount32,
+ .MadMixInsts,
+ .Xnack,
+ },
+ CpuInfo(@This()).create(.Hainan, "hainan", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .Ldsbankcount32,
+ .Wavefrontsize64,
+ .MimgR128,
+ .Fp64,
+ .TrigReducedRange,
+ .NoSramEccSupport,
+ .Movrel,
+ .Localmemorysize32768,
+ .SouthernIslands,
+ },
+ CpuInfo(@This()).create(.Hawaii, "hawaii", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .FastFmaf,
+ .Ldsbankcount32,
+ .Wavefrontsize64,
+ .MimgR128,
+ .Fp64,
+ .CiInsts,
+ .FlatAddressSpace,
+ .TrigReducedRange,
+ .NoSramEccSupport,
+ .Movrel,
+ .Localmemorysize65536,
+ .Gfx7Gfx8Gfx9Insts,
+ .SeaIslands,
+ .HalfRate64Ops,
+ },
+ CpuInfo(@This()).create(.Iceland, "iceland", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .Ldsbankcount32,
+ .SgprInitBug,
+ .UnpackedD16Vmem,
+ .Wavefrontsize64,
+ .Fp64,
+ .Gcn3Encoding,
+ .TrigReducedRange,
+ .Sdwa,
+ .VgprIndexMode,
+ .Dpp,
+ .FlatAddressSpace,
+ .Gfx8Insts,
+ .Gfx7Gfx8Gfx9Insts,
+ .MimgR128,
+ .NoSramEccSupport,
+ .IntClampInsts,
+ .ScalarStores,
+ .Movrel,
+ .SdwaMav,
+ .CiInsts,
+ .BitInsts16,
+ .SMemrealtime,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .SdwaOutModsVopc,
+ .VolcanicIslands,
+ },
+ CpuInfo(@This()).create(.Kabini, "kabini", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .Ldsbankcount16,
+ .Wavefrontsize64,
+ .MimgR128,
+ .Fp64,
+ .CiInsts,
+ .FlatAddressSpace,
+ .TrigReducedRange,
+ .NoSramEccSupport,
+ .Movrel,
+ .Localmemorysize65536,
+ .Gfx7Gfx8Gfx9Insts,
+ .SeaIslands,
+ },
+ CpuInfo(@This()).create(.Kaveri, "kaveri", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .Ldsbankcount32,
+ .Wavefrontsize64,
+ .MimgR128,
+ .Fp64,
+ .CiInsts,
+ .FlatAddressSpace,
+ .TrigReducedRange,
+ .NoSramEccSupport,
+ .Movrel,
+ .Localmemorysize65536,
+ .Gfx7Gfx8Gfx9Insts,
+ .SeaIslands,
+ },
+ CpuInfo(@This()).create(.Mullins, "mullins", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .Ldsbankcount16,
+ .Wavefrontsize64,
+ .MimgR128,
+ .Fp64,
+ .CiInsts,
+ .FlatAddressSpace,
+ .TrigReducedRange,
+ .NoSramEccSupport,
+ .Movrel,
+ .Localmemorysize65536,
+ .Gfx7Gfx8Gfx9Insts,
+ .SeaIslands,
+ },
+ CpuInfo(@This()).create(.Oland, "oland", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .Ldsbankcount32,
+ .Wavefrontsize64,
+ .MimgR128,
+ .Fp64,
+ .TrigReducedRange,
+ .NoSramEccSupport,
+ .Movrel,
+ .Localmemorysize32768,
+ .SouthernIslands,
+ },
+ CpuInfo(@This()).create(.Pitcairn, "pitcairn", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .Ldsbankcount32,
+ .Wavefrontsize64,
+ .MimgR128,
+ .Fp64,
+ .TrigReducedRange,
+ .NoSramEccSupport,
+ .Movrel,
+ .Localmemorysize32768,
+ .SouthernIslands,
+ },
+ CpuInfo(@This()).create(.Polaris10, "polaris10", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .Ldsbankcount32,
+ .UnpackedD16Vmem,
+ .Wavefrontsize64,
+ .Fp64,
+ .Gcn3Encoding,
+ .TrigReducedRange,
+ .Sdwa,
+ .VgprIndexMode,
+ .Dpp,
+ .FlatAddressSpace,
+ .Gfx8Insts,
+ .Gfx7Gfx8Gfx9Insts,
+ .MimgR128,
+ .NoSramEccSupport,
+ .IntClampInsts,
+ .ScalarStores,
+ .Movrel,
+ .SdwaMav,
+ .CiInsts,
+ .BitInsts16,
+ .SMemrealtime,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .SdwaOutModsVopc,
+ .VolcanicIslands,
+ },
+ CpuInfo(@This()).create(.Polaris11, "polaris11", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .Ldsbankcount32,
+ .UnpackedD16Vmem,
+ .Wavefrontsize64,
+ .Fp64,
+ .Gcn3Encoding,
+ .TrigReducedRange,
+ .Sdwa,
+ .VgprIndexMode,
+ .Dpp,
+ .FlatAddressSpace,
+ .Gfx8Insts,
+ .Gfx7Gfx8Gfx9Insts,
+ .MimgR128,
+ .NoSramEccSupport,
+ .IntClampInsts,
+ .ScalarStores,
+ .Movrel,
+ .SdwaMav,
+ .CiInsts,
+ .BitInsts16,
+ .SMemrealtime,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .SdwaOutModsVopc,
+ .VolcanicIslands,
+ },
+ CpuInfo(@This()).create(.Stoney, "stoney", &[_]FeatureType {
+ .CodeObjectV3,
+ .Ldsbankcount16,
+ .Wavefrontsize64,
+ .Fp64,
+ .Gcn3Encoding,
+ .TrigReducedRange,
+ .Sdwa,
+ .VgprIndexMode,
+ .Dpp,
+ .FlatAddressSpace,
+ .Gfx8Insts,
+ .Gfx7Gfx8Gfx9Insts,
+ .MimgR128,
+ .NoSramEccSupport,
+ .IntClampInsts,
+ .ScalarStores,
+ .Movrel,
+ .SdwaMav,
+ .CiInsts,
+ .BitInsts16,
+ .SMemrealtime,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .SdwaOutModsVopc,
+ .VolcanicIslands,
+ .Xnack,
+ },
+ CpuInfo(@This()).create(.Tahiti, "tahiti", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .FastFmaf,
+ .Ldsbankcount32,
+ .Wavefrontsize64,
+ .MimgR128,
+ .Fp64,
+ .TrigReducedRange,
+ .NoSramEccSupport,
+ .Movrel,
+ .Localmemorysize32768,
+ .SouthernIslands,
+ .HalfRate64Ops,
+ },
+ CpuInfo(@This()).create(.Tonga, "tonga", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .Ldsbankcount32,
+ .SgprInitBug,
+ .UnpackedD16Vmem,
+ .Wavefrontsize64,
+ .Fp64,
+ .Gcn3Encoding,
+ .TrigReducedRange,
+ .Sdwa,
+ .VgprIndexMode,
+ .Dpp,
+ .FlatAddressSpace,
+ .Gfx8Insts,
+ .Gfx7Gfx8Gfx9Insts,
+ .MimgR128,
+ .NoSramEccSupport,
+ .IntClampInsts,
+ .ScalarStores,
+ .Movrel,
+ .SdwaMav,
+ .CiInsts,
+ .BitInsts16,
+ .SMemrealtime,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .SdwaOutModsVopc,
+ .VolcanicIslands,
+ },
+ CpuInfo(@This()).create(.Verde, "verde", &[_]FeatureType {
+ .CodeObjectV3,
+ .NoXnackSupport,
+ .Ldsbankcount32,
+ .Wavefrontsize64,
+ .MimgR128,
+ .Fp64,
+ .TrigReducedRange,
+ .NoSramEccSupport,
+ .Movrel,
+ .Localmemorysize32768,
+ .SouthernIslands,
+ },
+ };
+};
lib/std/target/cpu/ArmCpu.zig
@@ -0,0 +1,1230 @@
+const feature = @import("std").target.feature;
+const CpuInfo = @import("std").target.cpu.CpuInfo;
+
+pub const ArmCpu = enum {
+ Arm1020e,
+ Arm1020t,
+ Arm1022e,
+ Arm10e,
+ Arm10tdmi,
+ Arm1136jS,
+ Arm1136jfS,
+ Arm1156t2S,
+ Arm1156t2fS,
+ Arm1176jS,
+ Arm1176jzS,
+ Arm1176jzfS,
+ Arm710t,
+ Arm720t,
+ Arm7tdmi,
+ Arm7tdmiS,
+ Arm8,
+ Arm810,
+ Arm9,
+ Arm920,
+ Arm920t,
+ Arm922t,
+ Arm926ejS,
+ Arm940t,
+ Arm946eS,
+ Arm966eS,
+ Arm968eS,
+ Arm9e,
+ Arm9tdmi,
+ CortexA12,
+ CortexA15,
+ CortexA17,
+ CortexA32,
+ CortexA35,
+ CortexA5,
+ CortexA53,
+ CortexA55,
+ CortexA57,
+ CortexA7,
+ CortexA72,
+ CortexA73,
+ CortexA75,
+ CortexA76,
+ CortexA76ae,
+ CortexA8,
+ CortexA9,
+ CortexM0,
+ CortexM0plus,
+ CortexM1,
+ CortexM23,
+ CortexM3,
+ CortexM33,
+ CortexM35p,
+ CortexM4,
+ CortexM7,
+ CortexR4,
+ CortexR4f,
+ CortexR5,
+ CortexR52,
+ CortexR7,
+ CortexR8,
+ Cyclone,
+ Ep9312,
+ ExynosM1,
+ ExynosM2,
+ ExynosM3,
+ ExynosM4,
+ ExynosM5,
+ Generic,
+ Iwmmxt,
+ Krait,
+ Kryo,
+ Mpcore,
+ Mpcorenovfp,
+ NeoverseN1,
+ Sc000,
+ Sc300,
+ Strongarm,
+ Strongarm110,
+ Strongarm1100,
+ Strongarm1110,
+ Swift,
+ Xscale,
+
+ pub fn getInfo(self: @This()) CpuInfo {
+ return cpu_infos[@enumToInt(self)];
+ }
+
+ pub const FeatureType = feature.ArmFeature;
+
+ const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
+ CpuInfo(@This()).create(.Arm1020e, "arm1020e", &[_]FeatureType {
+ .V4t,
+ .Armv5te,
+ },
+ CpuInfo(@This()).create(.Arm1020t, "arm1020t", &[_]FeatureType {
+ .V4t,
+ .Armv5t,
+ },
+ CpuInfo(@This()).create(.Arm1022e, "arm1022e", &[_]FeatureType {
+ .V4t,
+ .Armv5te,
+ },
+ CpuInfo(@This()).create(.Arm10e, "arm10e", &[_]FeatureType {
+ .V4t,
+ .Armv5te,
+ },
+ CpuInfo(@This()).create(.Arm10tdmi, "arm10tdmi", &[_]FeatureType {
+ .V4t,
+ .Armv5t,
+ },
+ CpuInfo(@This()).create(.Arm1136jS, "arm1136j-s", &[_]FeatureType {
+ .V4t,
+ .Dsp,
+ .Armv6,
+ },
+ CpuInfo(@This()).create(.Arm1136jfS, "arm1136jf-s", &[_]FeatureType {
+ .V4t,
+ .Dsp,
+ .Armv6,
+ .Slowfpvmlx,
+ .Fpregs,
+ .Vfp2,
+ },
+ CpuInfo(@This()).create(.Arm1156t2S, "arm1156t2-s", &[_]FeatureType {
+ .Thumb2,
+ .V4t,
+ .Dsp,
+ .Armv6t2,
+ },
+ CpuInfo(@This()).create(.Arm1156t2fS, "arm1156t2f-s", &[_]FeatureType {
+ .Thumb2,
+ .V4t,
+ .Dsp,
+ .Armv6t2,
+ .Slowfpvmlx,
+ .Fpregs,
+ .Vfp2,
+ },
+ CpuInfo(@This()).create(.Arm1176jS, "arm1176j-s", &[_]FeatureType {
+ .V4t,
+ .Trustzone,
+ .Armv6kz,
+ },
+ CpuInfo(@This()).create(.Arm1176jzS, "arm1176jz-s", &[_]FeatureType {
+ .V4t,
+ .Trustzone,
+ .Armv6kz,
+ },
+ CpuInfo(@This()).create(.Arm1176jzfS, "arm1176jzf-s", &[_]FeatureType {
+ .V4t,
+ .Trustzone,
+ .Armv6kz,
+ .Slowfpvmlx,
+ .Fpregs,
+ .Vfp2,
+ },
+ CpuInfo(@This()).create(.Arm710t, "arm710t", &[_]FeatureType {
+ .V4t,
+ .Armv4t,
+ },
+ CpuInfo(@This()).create(.Arm720t, "arm720t", &[_]FeatureType {
+ .V4t,
+ .Armv4t,
+ },
+ CpuInfo(@This()).create(.Arm7tdmi, "arm7tdmi", &[_]FeatureType {
+ .V4t,
+ .Armv4t,
+ },
+ CpuInfo(@This()).create(.Arm7tdmiS, "arm7tdmi-s", &[_]FeatureType {
+ .V4t,
+ .Armv4t,
+ },
+ CpuInfo(@This()).create(.Arm8, "arm8", &[_]FeatureType {
+ .Armv4,
+ },
+ CpuInfo(@This()).create(.Arm810, "arm810", &[_]FeatureType {
+ .Armv4,
+ },
+ CpuInfo(@This()).create(.Arm9, "arm9", &[_]FeatureType {
+ .V4t,
+ .Armv4t,
+ },
+ CpuInfo(@This()).create(.Arm920, "arm920", &[_]FeatureType {
+ .V4t,
+ .Armv4t,
+ },
+ CpuInfo(@This()).create(.Arm920t, "arm920t", &[_]FeatureType {
+ .V4t,
+ .Armv4t,
+ },
+ CpuInfo(@This()).create(.Arm922t, "arm922t", &[_]FeatureType {
+ .V4t,
+ .Armv4t,
+ },
+ CpuInfo(@This()).create(.Arm926ejS, "arm926ej-s", &[_]FeatureType {
+ .V4t,
+ .Armv5te,
+ },
+ CpuInfo(@This()).create(.Arm940t, "arm940t", &[_]FeatureType {
+ .V4t,
+ .Armv4t,
+ },
+ CpuInfo(@This()).create(.Arm946eS, "arm946e-s", &[_]FeatureType {
+ .V4t,
+ .Armv5te,
+ },
+ CpuInfo(@This()).create(.Arm966eS, "arm966e-s", &[_]FeatureType {
+ .V4t,
+ .Armv5te,
+ },
+ CpuInfo(@This()).create(.Arm968eS, "arm968e-s", &[_]FeatureType {
+ .V4t,
+ .Armv5te,
+ },
+ CpuInfo(@This()).create(.Arm9e, "arm9e", &[_]FeatureType {
+ .V4t,
+ .Armv5te,
+ },
+ CpuInfo(@This()).create(.Arm9tdmi, "arm9tdmi", &[_]FeatureType {
+ .V4t,
+ .Armv4t,
+ },
+ CpuInfo(@This()).create(.CortexA12, "cortex-a12", &[_]FeatureType {
+ .Thumb2,
+ .Perfmon,
+ .Db,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Aclass,
+ .Armv7A,
+ .AvoidPartialCpsr,
+ .RetAddrStack,
+ .Mp,
+ .Trustzone,
+ .Fp16,
+ .Vfp4,
+ .VmlxForwarding,
+ .HwdivArm,
+ .Hwdiv,
+ .Virtualization,
+ .A12,
+ },
+ CpuInfo(@This()).create(.CortexA15, "cortex-a15", &[_]FeatureType {
+ .Thumb2,
+ .Perfmon,
+ .Db,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Aclass,
+ .Armv7A,
+ .AvoidPartialCpsr,
+ .VldnAlign,
+ .DontWidenVmovs,
+ .RetAddrStack,
+ .Mp,
+ .MuxedUnits,
+ .SplatVfpNeon,
+ .Trustzone,
+ .Fp16,
+ .Vfp4,
+ .HwdivArm,
+ .Hwdiv,
+ .Virtualization,
+ .A15,
+ },
+ CpuInfo(@This()).create(.CortexA17, "cortex-a17", &[_]FeatureType {
+ .Thumb2,
+ .Perfmon,
+ .Db,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Aclass,
+ .Armv7A,
+ .AvoidPartialCpsr,
+ .RetAddrStack,
+ .Mp,
+ .Trustzone,
+ .Fp16,
+ .Vfp4,
+ .VmlxForwarding,
+ .HwdivArm,
+ .Hwdiv,
+ .Virtualization,
+ .A17,
+ },
+ CpuInfo(@This()).create(.CortexA32, "cortex-a32", &[_]FeatureType {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ .Armv8A,
+ .Crypto,
+ },
+ CpuInfo(@This()).create(.CortexA35, "cortex-a35", &[_]FeatureType {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ .Armv8A,
+ .Crypto,
+ .A35,
+ },
+ CpuInfo(@This()).create(.CortexA5, "cortex-a5", &[_]FeatureType {
+ .Thumb2,
+ .Perfmon,
+ .Db,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Aclass,
+ .Armv7A,
+ .RetAddrStack,
+ .Slowfpvmlx,
+ .Mp,
+ .SlowFpBrcc,
+ .Trustzone,
+ .Fp16,
+ .Vfp4,
+ .VmlxForwarding,
+ .A5,
+ },
+ CpuInfo(@This()).create(.CortexA53, "cortex-a53", &[_]FeatureType {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ .Armv8A,
+ .Crypto,
+ .Fpao,
+ .A53,
+ },
+ CpuInfo(@This()).create(.CortexA55, "cortex-a55", &[_]FeatureType {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Ras,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ .Armv82A,
+ .Dotprod,
+ .A55,
+ },
+ CpuInfo(@This()).create(.CortexA57, "cortex-a57", &[_]FeatureType {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ .Armv8A,
+ .AvoidPartialCpsr,
+ .CheapPredicableCpsr,
+ .Crypto,
+ .Fpao,
+ .A57,
+ },
+ CpuInfo(@This()).create(.CortexA7, "cortex-a7", &[_]FeatureType {
+ .Thumb2,
+ .Perfmon,
+ .Db,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Aclass,
+ .Armv7A,
+ .RetAddrStack,
+ .Slowfpvmlx,
+ .VmlxHazards,
+ .Mp,
+ .SlowFpBrcc,
+ .Trustzone,
+ .Fp16,
+ .Vfp4,
+ .VmlxForwarding,
+ .HwdivArm,
+ .Hwdiv,
+ .Virtualization,
+ .A7,
+ },
+ CpuInfo(@This()).create(.CortexA72, "cortex-a72", &[_]FeatureType {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ .Armv8A,
+ .Crypto,
+ .A72,
+ },
+ CpuInfo(@This()).create(.CortexA73, "cortex-a73", &[_]FeatureType {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ .Armv8A,
+ .Crypto,
+ .A73,
+ },
+ CpuInfo(@This()).create(.CortexA75, "cortex-a75", &[_]FeatureType {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Ras,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ .Armv82A,
+ .Dotprod,
+ .A75,
+ },
+ CpuInfo(@This()).create(.CortexA76, "cortex-a76", &[_]FeatureType {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Ras,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ .Armv82A,
+ .Crypto,
+ .Dotprod,
+ .Fullfp16,
+ .A76,
+ },
+ CpuInfo(@This()).create(.CortexA76ae, "cortex-a76ae", &[_]FeatureType {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Ras,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ .Armv82A,
+ .Crypto,
+ .Dotprod,
+ .Fullfp16,
+ .A76,
+ },
+ CpuInfo(@This()).create(.CortexA8, "cortex-a8", &[_]FeatureType {
+ .Thumb2,
+ .Perfmon,
+ .Db,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Aclass,
+ .Armv7A,
+ .RetAddrStack,
+ .Slowfpvmlx,
+ .VmlxHazards,
+ .NonpipelinedVfp,
+ .SlowFpBrcc,
+ .Trustzone,
+ .VmlxForwarding,
+ .A8,
+ },
+ CpuInfo(@This()).create(.CortexA9, "cortex-a9", &[_]FeatureType {
+ .Thumb2,
+ .Perfmon,
+ .Db,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Aclass,
+ .Armv7A,
+ .AvoidPartialCpsr,
+ .VldnAlign,
+ .ExpandFpMlx,
+ .Fp16,
+ .RetAddrStack,
+ .VmlxHazards,
+ .Mp,
+ .MuxedUnits,
+ .NeonFpmovs,
+ .PreferVmovsr,
+ .Trustzone,
+ .VmlxForwarding,
+ .A9,
+ },
+ CpuInfo(@This()).create(.CortexM0, "cortex-m0", &[_]FeatureType {
+ .Mclass,
+ .StrictAlign,
+ .ThumbMode,
+ .Db,
+ .V4t,
+ .Noarm,
+ .Armv6M,
+ },
+ CpuInfo(@This()).create(.CortexM0plus, "cortex-m0plus", &[_]FeatureType {
+ .Mclass,
+ .StrictAlign,
+ .ThumbMode,
+ .Db,
+ .V4t,
+ .Noarm,
+ .Armv6M,
+ },
+ CpuInfo(@This()).create(.CortexM1, "cortex-m1", &[_]FeatureType {
+ .Mclass,
+ .StrictAlign,
+ .ThumbMode,
+ .Db,
+ .V4t,
+ .Noarm,
+ .Armv6M,
+ },
+ CpuInfo(@This()).create(.CortexM23, "cortex-m23", &[_]FeatureType {
+ .Mclass,
+ .StrictAlign,
+ .ThumbMode,
+ .Db,
+ .Msecext8,
+ .V7clrex,
+ .V4t,
+ .Hwdiv,
+ .Noarm,
+ .AcquireRelease,
+ .Armv8Mbase,
+ .NoMovt,
+ },
+ CpuInfo(@This()).create(.CortexM3, "cortex-m3", &[_]FeatureType {
+ .Thumb2,
+ .Mclass,
+ .Perfmon,
+ .ThumbMode,
+ .Db,
+ .V7clrex,
+ .V4t,
+ .Hwdiv,
+ .Noarm,
+ .Armv7M,
+ .NoBranchPredictor,
+ .LoopAlign,
+ .UseAa,
+ .UseMisched,
+ .M3,
+ },
+ CpuInfo(@This()).create(.CortexM33, "cortex-m33", &[_]FeatureType {
+ .Thumb2,
+ .Mclass,
+ .Perfmon,
+ .ThumbMode,
+ .Db,
+ .Msecext8,
+ .V7clrex,
+ .V4t,
+ .Hwdiv,
+ .Noarm,
+ .AcquireRelease,
+ .Armv8Mmain,
+ .Dsp,
+ .Fp16,
+ .Fpregs,
+ .FpArmv8d16sp,
+ .NoBranchPredictor,
+ .Slowfpvmlx,
+ .LoopAlign,
+ .UseAa,
+ .UseMisched,
+ },
+ CpuInfo(@This()).create(.CortexM35p, "cortex-m35p", &[_]FeatureType {
+ .Thumb2,
+ .Mclass,
+ .Perfmon,
+ .ThumbMode,
+ .Db,
+ .Msecext8,
+ .V7clrex,
+ .V4t,
+ .Hwdiv,
+ .Noarm,
+ .AcquireRelease,
+ .Armv8Mmain,
+ .Dsp,
+ .Fp16,
+ .Fpregs,
+ .FpArmv8d16sp,
+ .NoBranchPredictor,
+ .Slowfpvmlx,
+ .LoopAlign,
+ .UseAa,
+ .UseMisched,
+ },
+ CpuInfo(@This()).create(.CortexM4, "cortex-m4", &[_]FeatureType {
+ .Thumb2,
+ .Mclass,
+ .Perfmon,
+ .ThumbMode,
+ .Db,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Hwdiv,
+ .Noarm,
+ .Armv7eM,
+ .NoBranchPredictor,
+ .Slowfpvmlx,
+ .LoopAlign,
+ .UseAa,
+ .UseMisched,
+ .Fp16,
+ .Fpregs,
+ .Vfp4d16sp,
+ },
+ CpuInfo(@This()).create(.CortexM7, "cortex-m7", &[_]FeatureType {
+ .Thumb2,
+ .Mclass,
+ .Perfmon,
+ .ThumbMode,
+ .Db,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Hwdiv,
+ .Noarm,
+ .Armv7eM,
+ .Fp16,
+ .Fpregs,
+ .FpArmv8d16,
+ },
+ CpuInfo(@This()).create(.CortexR4, "cortex-r4", &[_]FeatureType {
+ .Thumb2,
+ .Perfmon,
+ .Db,
+ .Dsp,
+ .Rclass,
+ .V7clrex,
+ .V4t,
+ .Hwdiv,
+ .Armv7R,
+ .AvoidPartialCpsr,
+ .RetAddrStack,
+ .R4,
+ },
+ CpuInfo(@This()).create(.CortexR4f, "cortex-r4f", &[_]FeatureType {
+ .Thumb2,
+ .Perfmon,
+ .Db,
+ .Dsp,
+ .Rclass,
+ .V7clrex,
+ .V4t,
+ .Hwdiv,
+ .Armv7R,
+ .AvoidPartialCpsr,
+ .RetAddrStack,
+ .Slowfpvmlx,
+ .SlowFpBrcc,
+ .Fpregs,
+ .Vfp3d16,
+ .R4,
+ },
+ CpuInfo(@This()).create(.CortexR5, "cortex-r5", &[_]FeatureType {
+ .Thumb2,
+ .Perfmon,
+ .Db,
+ .Dsp,
+ .Rclass,
+ .V7clrex,
+ .V4t,
+ .Hwdiv,
+ .Armv7R,
+ .AvoidPartialCpsr,
+ .HwdivArm,
+ .RetAddrStack,
+ .Slowfpvmlx,
+ .SlowFpBrcc,
+ .Fpregs,
+ .Vfp3d16,
+ .R5,
+ },
+ CpuInfo(@This()).create(.CortexR52, "cortex-r52", &[_]FeatureType {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Dfb,
+ .Dsp,
+ .Rclass,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .AcquireRelease,
+ .Armv8R,
+ .Fpao,
+ .UseAa,
+ .UseMisched,
+ .R52,
+ },
+ CpuInfo(@This()).create(.CortexR7, "cortex-r7", &[_]FeatureType {
+ .Thumb2,
+ .Perfmon,
+ .Db,
+ .Dsp,
+ .Rclass,
+ .V7clrex,
+ .V4t,
+ .Hwdiv,
+ .Armv7R,
+ .AvoidPartialCpsr,
+ .Fp16,
+ .HwdivArm,
+ .RetAddrStack,
+ .Slowfpvmlx,
+ .Mp,
+ .SlowFpBrcc,
+ .Fpregs,
+ .Vfp3d16,
+ .R7,
+ },
+ CpuInfo(@This()).create(.CortexR8, "cortex-r8", &[_]FeatureType {
+ .Thumb2,
+ .Perfmon,
+ .Db,
+ .Dsp,
+ .Rclass,
+ .V7clrex,
+ .V4t,
+ .Hwdiv,
+ .Armv7R,
+ .AvoidPartialCpsr,
+ .Fp16,
+ .HwdivArm,
+ .RetAddrStack,
+ .Slowfpvmlx,
+ .Mp,
+ .SlowFpBrcc,
+ .Fpregs,
+ .Vfp3d16,
+ },
+ CpuInfo(@This()).create(.Cyclone, "cyclone", &[_]FeatureType {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ .Armv8A,
+ .AvoidMovsShop,
+ .AvoidPartialCpsr,
+ .Crypto,
+ .RetAddrStack,
+ .Slowfpvmlx,
+ .Neonfp,
+ .DisablePostraScheduler,
+ .UseMisched,
+ .Vfp4,
+ .Zcz,
+ .Swift,
+ },
+ CpuInfo(@This()).create(.Ep9312, "ep9312", &[_]FeatureType {
+ .V4t,
+ .Armv4t,
+ },
+ CpuInfo(@This()).create(.ExynosM1, "exynos-m1", &[_]FeatureType {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ .Armv8A,
+ .Zcz,
+ .SlowVdup32,
+ .SlowVgetlni32,
+ .DontWidenVmovs,
+ .FuseAes,
+ .WideStrideVfp,
+ .ProfUnpr,
+ .Slowfpvmlx,
+ .SlowFpBrcc,
+ .FuseLiterals,
+ .ExpandFpMlx,
+ .RetAddrStack,
+ .UseAa,
+ .Exynos,
+ },
+ CpuInfo(@This()).create(.ExynosM2, "exynos-m2", &[_]FeatureType {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ .Armv8A,
+ .Zcz,
+ .SlowVdup32,
+ .SlowVgetlni32,
+ .DontWidenVmovs,
+ .FuseAes,
+ .WideStrideVfp,
+ .ProfUnpr,
+ .Slowfpvmlx,
+ .SlowFpBrcc,
+ .FuseLiterals,
+ .ExpandFpMlx,
+ .RetAddrStack,
+ .UseAa,
+ .Exynos,
+ },
+ CpuInfo(@This()).create(.ExynosM3, "exynos-m3", &[_]FeatureType {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ .Armv8A,
+ .Zcz,
+ .SlowVdup32,
+ .SlowVgetlni32,
+ .DontWidenVmovs,
+ .FuseAes,
+ .WideStrideVfp,
+ .ProfUnpr,
+ .Slowfpvmlx,
+ .SlowFpBrcc,
+ .FuseLiterals,
+ .ExpandFpMlx,
+ .RetAddrStack,
+ .UseAa,
+ .Exynos,
+ },
+ CpuInfo(@This()).create(.ExynosM4, "exynos-m4", &[_]FeatureType {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Ras,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ .Armv82A,
+ .Dotprod,
+ .Fullfp16,
+ .Zcz,
+ .SlowVdup32,
+ .SlowVgetlni32,
+ .DontWidenVmovs,
+ .FuseAes,
+ .WideStrideVfp,
+ .ProfUnpr,
+ .Slowfpvmlx,
+ .SlowFpBrcc,
+ .FuseLiterals,
+ .ExpandFpMlx,
+ .RetAddrStack,
+ .UseAa,
+ .Exynos,
+ },
+ CpuInfo(@This()).create(.ExynosM5, "exynos-m5", &[_]FeatureType {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Ras,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ .Armv82A,
+ .Dotprod,
+ .Fullfp16,
+ .Zcz,
+ .SlowVdup32,
+ .SlowVgetlni32,
+ .DontWidenVmovs,
+ .FuseAes,
+ .WideStrideVfp,
+ .ProfUnpr,
+ .Slowfpvmlx,
+ .SlowFpBrcc,
+ .FuseLiterals,
+ .ExpandFpMlx,
+ .RetAddrStack,
+ .UseAa,
+ .Exynos,
+ },
+ CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.Iwmmxt, "iwmmxt", &[_]FeatureType {
+ .V4t,
+ .Armv5te,
+ },
+ CpuInfo(@This()).create(.Krait, "krait", &[_]FeatureType {
+ .Thumb2,
+ .Perfmon,
+ .Db,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Aclass,
+ .Armv7A,
+ .AvoidPartialCpsr,
+ .VldnAlign,
+ .Fp16,
+ .HwdivArm,
+ .Hwdiv,
+ .RetAddrStack,
+ .MuxedUnits,
+ .Vfp4,
+ .VmlxForwarding,
+ .Krait,
+ },
+ CpuInfo(@This()).create(.Kryo, "kryo", &[_]FeatureType {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ .Armv8A,
+ .Crypto,
+ .Kryo,
+ },
+ CpuInfo(@This()).create(.Mpcore, "mpcore", &[_]FeatureType {
+ .V4t,
+ .Armv6k,
+ .Slowfpvmlx,
+ .Fpregs,
+ .Vfp2,
+ },
+ CpuInfo(@This()).create(.Mpcorenovfp, "mpcorenovfp", &[_]FeatureType {
+ .V4t,
+ .Armv6k,
+ },
+ CpuInfo(@This()).create(.NeoverseN1, "neoverse-n1", &[_]FeatureType {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Ras,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ .Armv82A,
+ .Crypto,
+ .Dotprod,
+ },
+ CpuInfo(@This()).create(.Sc000, "sc000", &[_]FeatureType {
+ .Mclass,
+ .StrictAlign,
+ .ThumbMode,
+ .Db,
+ .V4t,
+ .Noarm,
+ .Armv6M,
+ },
+ CpuInfo(@This()).create(.Sc300, "sc300", &[_]FeatureType {
+ .Thumb2,
+ .Mclass,
+ .Perfmon,
+ .ThumbMode,
+ .Db,
+ .V7clrex,
+ .V4t,
+ .Hwdiv,
+ .Noarm,
+ .Armv7M,
+ .NoBranchPredictor,
+ .UseAa,
+ .UseMisched,
+ .M3,
+ },
+ CpuInfo(@This()).create(.Strongarm, "strongarm", &[_]FeatureType {
+ .Armv4,
+ },
+ CpuInfo(@This()).create(.Strongarm110, "strongarm110", &[_]FeatureType {
+ .Armv4,
+ },
+ CpuInfo(@This()).create(.Strongarm1100, "strongarm1100", &[_]FeatureType {
+ .Armv4,
+ },
+ CpuInfo(@This()).create(.Strongarm1110, "strongarm1110", &[_]FeatureType {
+ .Armv4,
+ },
+ CpuInfo(@This()).create(.Swift, "swift", &[_]FeatureType {
+ .Thumb2,
+ .Perfmon,
+ .Db,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Aclass,
+ .Armv7A,
+ .AvoidMovsShop,
+ .AvoidPartialCpsr,
+ .HwdivArm,
+ .Hwdiv,
+ .RetAddrStack,
+ .Slowfpvmlx,
+ .VmlxHazards,
+ .Mp,
+ .Neonfp,
+ .DisablePostraScheduler,
+ .PreferIshst,
+ .ProfUnpr,
+ .SlowLoadDSubreg,
+ .SlowOddReg,
+ .SlowVdup32,
+ .SlowVgetlni32,
+ .UseMisched,
+ .WideStrideVfp,
+ .Fp16,
+ .Vfp4,
+ .Swift,
+ },
+ CpuInfo(@This()).create(.Xscale, "xscale", &[_]FeatureType {
+ .V4t,
+ .Armv5te,
+ },
+ };
+};
lib/std/target/cpu/AvrCpu.zig
@@ -0,0 +1,3863 @@
+const feature = @import("std").target.feature;
+const CpuInfo = @import("std").target.cpu.CpuInfo;
+
+pub const AvrCpu = enum {
+ At43usb320,
+ At43usb355,
+ At76c711,
+ At86rf401,
+ At90c8534,
+ At90can128,
+ At90can32,
+ At90can64,
+ At90pwm1,
+ At90pwm161,
+ At90pwm2,
+ At90pwm216,
+ At90pwm2b,
+ At90pwm3,
+ At90pwm316,
+ At90pwm3b,
+ At90pwm81,
+ At90s1200,
+ At90s2313,
+ At90s2323,
+ At90s2333,
+ At90s2343,
+ At90s4414,
+ At90s4433,
+ At90s4434,
+ At90s8515,
+ At90s8535,
+ At90scr100,
+ At90usb1286,
+ At90usb1287,
+ At90usb162,
+ At90usb646,
+ At90usb647,
+ At90usb82,
+ At94k,
+ Ata5272,
+ Ata5505,
+ Ata5790,
+ Ata5795,
+ Ata6285,
+ Ata6286,
+ Ata6289,
+ Atmega103,
+ Atmega128,
+ Atmega1280,
+ Atmega1281,
+ Atmega1284,
+ Atmega1284p,
+ Atmega1284rfr2,
+ Atmega128a,
+ Atmega128rfa1,
+ Atmega128rfr2,
+ Atmega16,
+ Atmega161,
+ Atmega162,
+ Atmega163,
+ Atmega164a,
+ Atmega164p,
+ Atmega164pa,
+ Atmega165,
+ Atmega165a,
+ Atmega165p,
+ Atmega165pa,
+ Atmega168,
+ Atmega168a,
+ Atmega168p,
+ Atmega168pa,
+ Atmega169,
+ Atmega169a,
+ Atmega169p,
+ Atmega169pa,
+ Atmega16a,
+ Atmega16hva,
+ Atmega16hva2,
+ Atmega16hvb,
+ Atmega16hvbrevb,
+ Atmega16m1,
+ Atmega16u2,
+ Atmega16u4,
+ Atmega2560,
+ Atmega2561,
+ Atmega2564rfr2,
+ Atmega256rfr2,
+ Atmega32,
+ Atmega323,
+ Atmega324a,
+ Atmega324p,
+ Atmega324pa,
+ Atmega325,
+ Atmega3250,
+ Atmega3250a,
+ Atmega3250p,
+ Atmega3250pa,
+ Atmega325a,
+ Atmega325p,
+ Atmega325pa,
+ Atmega328,
+ Atmega328p,
+ Atmega329,
+ Atmega3290,
+ Atmega3290a,
+ Atmega3290p,
+ Atmega3290pa,
+ Atmega329a,
+ Atmega329p,
+ Atmega329pa,
+ Atmega32a,
+ Atmega32c1,
+ Atmega32hvb,
+ Atmega32hvbrevb,
+ Atmega32m1,
+ Atmega32u2,
+ Atmega32u4,
+ Atmega32u6,
+ Atmega406,
+ Atmega48,
+ Atmega48a,
+ Atmega48p,
+ Atmega48pa,
+ Atmega64,
+ Atmega640,
+ Atmega644,
+ Atmega644a,
+ Atmega644p,
+ Atmega644pa,
+ Atmega644rfr2,
+ Atmega645,
+ Atmega6450,
+ Atmega6450a,
+ Atmega6450p,
+ Atmega645a,
+ Atmega645p,
+ Atmega649,
+ Atmega6490,
+ Atmega6490a,
+ Atmega6490p,
+ Atmega649a,
+ Atmega649p,
+ Atmega64a,
+ Atmega64c1,
+ Atmega64hve,
+ Atmega64m1,
+ Atmega64rfr2,
+ Atmega8,
+ Atmega8515,
+ Atmega8535,
+ Atmega88,
+ Atmega88a,
+ Atmega88p,
+ Atmega88pa,
+ Atmega8a,
+ Atmega8hva,
+ Atmega8u2,
+ Attiny10,
+ Attiny102,
+ Attiny104,
+ Attiny11,
+ Attiny12,
+ Attiny13,
+ Attiny13a,
+ Attiny15,
+ Attiny1634,
+ Attiny167,
+ Attiny20,
+ Attiny22,
+ Attiny2313,
+ Attiny2313a,
+ Attiny24,
+ Attiny24a,
+ Attiny25,
+ Attiny26,
+ Attiny261,
+ Attiny261a,
+ Attiny28,
+ Attiny4,
+ Attiny40,
+ Attiny4313,
+ Attiny43u,
+ Attiny44,
+ Attiny44a,
+ Attiny45,
+ Attiny461,
+ Attiny461a,
+ Attiny48,
+ Attiny5,
+ Attiny828,
+ Attiny84,
+ Attiny84a,
+ Attiny85,
+ Attiny861,
+ Attiny861a,
+ Attiny87,
+ Attiny88,
+ Attiny9,
+ Atxmega128a1,
+ Atxmega128a1u,
+ Atxmega128a3,
+ Atxmega128a3u,
+ Atxmega128a4u,
+ Atxmega128b1,
+ Atxmega128b3,
+ Atxmega128c3,
+ Atxmega128d3,
+ Atxmega128d4,
+ Atxmega16a4,
+ Atxmega16a4u,
+ Atxmega16c4,
+ Atxmega16d4,
+ Atxmega16e5,
+ Atxmega192a3,
+ Atxmega192a3u,
+ Atxmega192c3,
+ Atxmega192d3,
+ Atxmega256a3,
+ Atxmega256a3b,
+ Atxmega256a3bu,
+ Atxmega256a3u,
+ Atxmega256c3,
+ Atxmega256d3,
+ Atxmega32a4,
+ Atxmega32a4u,
+ Atxmega32c4,
+ Atxmega32d4,
+ Atxmega32e5,
+ Atxmega32x1,
+ Atxmega384c3,
+ Atxmega384d3,
+ Atxmega64a1,
+ Atxmega64a1u,
+ Atxmega64a3,
+ Atxmega64a3u,
+ Atxmega64a4u,
+ Atxmega64b1,
+ Atxmega64b3,
+ Atxmega64c3,
+ Atxmega64d3,
+ Atxmega64d4,
+ Atxmega8e5,
+ Avr1,
+ Avr2,
+ Avr25,
+ Avr3,
+ Avr31,
+ Avr35,
+ Avr4,
+ Avr5,
+ Avr51,
+ Avr6,
+ Avrtiny,
+ Avrxmega1,
+ Avrxmega2,
+ Avrxmega3,
+ Avrxmega4,
+ Avrxmega5,
+ Avrxmega6,
+ Avrxmega7,
+ M3000,
+
+ pub fn getInfo(self: @This()) CpuInfo {
+ return cpu_infos[@enumToInt(self)];
+ }
+
+ pub const FeatureType = feature.AvrFeature;
+
+ const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
+ CpuInfo(@This()).create(.At43usb320, "at43usb320", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Elpm,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr31,
+ },
+ CpuInfo(@This()).create(.At43usb355, "at43usb355", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr3,
+ },
+ CpuInfo(@This()).create(.At76c711, "at76c711", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr3,
+ },
+ CpuInfo(@This()).create(.At86rf401, "at86rf401", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr2,
+ .Lpmx,
+ .Movw,
+ },
+ CpuInfo(@This()).create(.At90c8534, "at90c8534", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr2,
+ },
+ CpuInfo(@This()).create(.At90can128, "at90can128", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr51,
+ },
+ CpuInfo(@This()).create(.At90can32, "at90can32", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.At90can64, "at90can64", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.At90pwm1, "at90pwm1", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.At90pwm161, "at90pwm161", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.At90pwm2, "at90pwm2", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.At90pwm216, "at90pwm216", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.At90pwm2b, "at90pwm2b", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.At90pwm3, "at90pwm3", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.At90pwm316, "at90pwm316", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.At90pwm3b, "at90pwm3b", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.At90pwm81, "at90pwm81", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.At90s1200, "at90s1200", &[_]FeatureType {
+ .Avr0,
+ },
+ CpuInfo(@This()).create(.At90s2313, "at90s2313", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr2,
+ },
+ CpuInfo(@This()).create(.At90s2323, "at90s2323", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr2,
+ },
+ CpuInfo(@This()).create(.At90s2333, "at90s2333", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr2,
+ },
+ CpuInfo(@This()).create(.At90s2343, "at90s2343", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr2,
+ },
+ CpuInfo(@This()).create(.At90s4414, "at90s4414", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr2,
+ },
+ CpuInfo(@This()).create(.At90s4433, "at90s4433", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr2,
+ },
+ CpuInfo(@This()).create(.At90s4434, "at90s4434", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr2,
+ },
+ CpuInfo(@This()).create(.At90s8515, "at90s8515", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr2,
+ },
+ CpuInfo(@This()).create(.At90s8535, "at90s8535", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr2,
+ },
+ CpuInfo(@This()).create(.At90scr100, "at90scr100", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.At90usb1286, "at90usb1286", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr51,
+ },
+ CpuInfo(@This()).create(.At90usb1287, "at90usb1287", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr51,
+ },
+ CpuInfo(@This()).create(.At90usb162, "at90usb162", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr35,
+ },
+ CpuInfo(@This()).create(.At90usb646, "at90usb646", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.At90usb647, "at90usb647", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.At90usb82, "at90usb82", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr35,
+ },
+ CpuInfo(@This()).create(.At94k, "at94k", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr3,
+ .Lpmx,
+ .Movw,
+ .Mul,
+ },
+ CpuInfo(@This()).create(.Ata5272, "ata5272", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Ata5505, "ata5505", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr35,
+ },
+ CpuInfo(@This()).create(.Ata5790, "ata5790", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Ata5795, "ata5795", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Ata6285, "ata6285", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.Ata6286, "ata6286", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.Ata6289, "ata6289", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.Atmega103, "atmega103", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Elpm,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr31,
+ },
+ CpuInfo(@This()).create(.Atmega128, "atmega128", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr51,
+ },
+ CpuInfo(@This()).create(.Atmega1280, "atmega1280", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr51,
+ },
+ CpuInfo(@This()).create(.Atmega1281, "atmega1281", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr51,
+ },
+ CpuInfo(@This()).create(.Atmega1284, "atmega1284", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr51,
+ },
+ CpuInfo(@This()).create(.Atmega1284p, "atmega1284p", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr51,
+ },
+ CpuInfo(@This()).create(.Atmega1284rfr2, "atmega1284rfr2", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr51,
+ },
+ CpuInfo(@This()).create(.Atmega128a, "atmega128a", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr51,
+ },
+ CpuInfo(@This()).create(.Atmega128rfa1, "atmega128rfa1", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr51,
+ },
+ CpuInfo(@This()).create(.Atmega128rfr2, "atmega128rfr2", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr51,
+ },
+ CpuInfo(@This()).create(.Atmega16, "atmega16", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega161, "atmega161", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr3,
+ .Lpmx,
+ .Movw,
+ .Mul,
+ .Spm,
+ },
+ CpuInfo(@This()).create(.Atmega162, "atmega162", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega163, "atmega163", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr3,
+ .Lpmx,
+ .Movw,
+ .Mul,
+ .Spm,
+ },
+ CpuInfo(@This()).create(.Atmega164a, "atmega164a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega164p, "atmega164p", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega164pa, "atmega164pa", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega165, "atmega165", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega165a, "atmega165a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega165p, "atmega165p", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega165pa, "atmega165pa", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega168, "atmega168", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega168a, "atmega168a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega168p, "atmega168p", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega168pa, "atmega168pa", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega169, "atmega169", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega169a, "atmega169a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega169p, "atmega169p", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega169pa, "atmega169pa", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega16a, "atmega16a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega16hva, "atmega16hva", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega16hva2, "atmega16hva2", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega16hvb, "atmega16hvb", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega16hvbrevb, "atmega16hvbrevb", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega16m1, "atmega16m1", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega16u2, "atmega16u2", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr35,
+ },
+ CpuInfo(@This()).create(.Atmega16u4, "atmega16u4", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega2560, "atmega2560", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr6,
+ },
+ CpuInfo(@This()).create(.Atmega2561, "atmega2561", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr6,
+ },
+ CpuInfo(@This()).create(.Atmega2564rfr2, "atmega2564rfr2", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr6,
+ },
+ CpuInfo(@This()).create(.Atmega256rfr2, "atmega256rfr2", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr6,
+ },
+ CpuInfo(@This()).create(.Atmega32, "atmega32", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega323, "atmega323", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega324a, "atmega324a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega324p, "atmega324p", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega324pa, "atmega324pa", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega325, "atmega325", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega3250, "atmega3250", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega3250a, "atmega3250a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega3250p, "atmega3250p", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega3250pa, "atmega3250pa", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega325a, "atmega325a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega325p, "atmega325p", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega325pa, "atmega325pa", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega328, "atmega328", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega328p, "atmega328p", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega329, "atmega329", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega3290, "atmega3290", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega3290a, "atmega3290a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega3290p, "atmega3290p", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega3290pa, "atmega3290pa", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega329a, "atmega329a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega329p, "atmega329p", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega329pa, "atmega329pa", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega32a, "atmega32a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega32c1, "atmega32c1", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega32hvb, "atmega32hvb", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega32hvbrevb, "atmega32hvbrevb", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega32m1, "atmega32m1", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega32u2, "atmega32u2", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr35,
+ },
+ CpuInfo(@This()).create(.Atmega32u4, "atmega32u4", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega32u6, "atmega32u6", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega406, "atmega406", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega48, "atmega48", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.Atmega48a, "atmega48a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.Atmega48p, "atmega48p", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.Atmega48pa, "atmega48pa", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.Atmega64, "atmega64", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega640, "atmega640", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega644, "atmega644", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega644a, "atmega644a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega644p, "atmega644p", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega644pa, "atmega644pa", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega644rfr2, "atmega644rfr2", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega645, "atmega645", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega6450, "atmega6450", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega6450a, "atmega6450a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega6450p, "atmega6450p", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega645a, "atmega645a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega645p, "atmega645p", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega649, "atmega649", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega6490, "atmega6490", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega6490a, "atmega6490a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega6490p, "atmega6490p", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega649a, "atmega649a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega649p, "atmega649p", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega64a, "atmega64a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega64c1, "atmega64c1", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega64hve, "atmega64hve", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega64m1, "atmega64m1", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega64rfr2, "atmega64rfr2", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Atmega8, "atmega8", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.Atmega8515, "atmega8515", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr2,
+ .Lpmx,
+ .Movw,
+ .Mul,
+ .Spm,
+ },
+ CpuInfo(@This()).create(.Atmega8535, "atmega8535", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr2,
+ .Lpmx,
+ .Movw,
+ .Mul,
+ .Spm,
+ },
+ CpuInfo(@This()).create(.Atmega88, "atmega88", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.Atmega88a, "atmega88a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.Atmega88p, "atmega88p", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.Atmega88pa, "atmega88pa", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.Atmega8a, "atmega8a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.Atmega8hva, "atmega8hva", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.Atmega8u2, "atmega8u2", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr35,
+ },
+ CpuInfo(@This()).create(.Attiny10, "attiny10", &[_]FeatureType {
+ .Break,
+ .Tinyencoding,
+ .Avr0,
+ .Sram,
+ .Avrtiny,
+ },
+ CpuInfo(@This()).create(.Attiny102, "attiny102", &[_]FeatureType {
+ .Break,
+ .Tinyencoding,
+ .Avr0,
+ .Sram,
+ .Avrtiny,
+ },
+ CpuInfo(@This()).create(.Attiny104, "attiny104", &[_]FeatureType {
+ .Break,
+ .Tinyencoding,
+ .Avr0,
+ .Sram,
+ .Avrtiny,
+ },
+ CpuInfo(@This()).create(.Attiny11, "attiny11", &[_]FeatureType {
+ .Lpm,
+ .Avr0,
+ .Avr1,
+ },
+ CpuInfo(@This()).create(.Attiny12, "attiny12", &[_]FeatureType {
+ .Lpm,
+ .Avr0,
+ .Avr1,
+ },
+ CpuInfo(@This()).create(.Attiny13, "attiny13", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny13a, "attiny13a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny15, "attiny15", &[_]FeatureType {
+ .Lpm,
+ .Avr0,
+ .Avr1,
+ },
+ CpuInfo(@This()).create(.Attiny1634, "attiny1634", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr35,
+ },
+ CpuInfo(@This()).create(.Attiny167, "attiny167", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr35,
+ },
+ CpuInfo(@This()).create(.Attiny20, "attiny20", &[_]FeatureType {
+ .Break,
+ .Tinyencoding,
+ .Avr0,
+ .Sram,
+ .Avrtiny,
+ },
+ CpuInfo(@This()).create(.Attiny22, "attiny22", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr2,
+ },
+ CpuInfo(@This()).create(.Attiny2313, "attiny2313", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny2313a, "attiny2313a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny24, "attiny24", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny24a, "attiny24a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny25, "attiny25", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny26, "attiny26", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr2,
+ .Lpmx,
+ },
+ CpuInfo(@This()).create(.Attiny261, "attiny261", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny261a, "attiny261a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny28, "attiny28", &[_]FeatureType {
+ .Lpm,
+ .Avr0,
+ .Avr1,
+ },
+ CpuInfo(@This()).create(.Attiny4, "attiny4", &[_]FeatureType {
+ .Break,
+ .Tinyencoding,
+ .Avr0,
+ .Sram,
+ .Avrtiny,
+ },
+ CpuInfo(@This()).create(.Attiny40, "attiny40", &[_]FeatureType {
+ .Break,
+ .Tinyencoding,
+ .Avr0,
+ .Sram,
+ .Avrtiny,
+ },
+ CpuInfo(@This()).create(.Attiny4313, "attiny4313", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny43u, "attiny43u", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny44, "attiny44", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny44a, "attiny44a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny45, "attiny45", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny461, "attiny461", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny461a, "attiny461a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny48, "attiny48", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny5, "attiny5", &[_]FeatureType {
+ .Break,
+ .Tinyencoding,
+ .Avr0,
+ .Sram,
+ .Avrtiny,
+ },
+ CpuInfo(@This()).create(.Attiny828, "attiny828", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny84, "attiny84", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny84a, "attiny84a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny85, "attiny85", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny861, "attiny861", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny861a, "attiny861a", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny87, "attiny87", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny88, "attiny88", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Attiny9, "attiny9", &[_]FeatureType {
+ .Break,
+ .Tinyencoding,
+ .Avr0,
+ .Sram,
+ .Avrtiny,
+ },
+ CpuInfo(@This()).create(.Atxmega128a1, "atxmega128a1", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega128a1u, "atxmega128a1u", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega128a3, "atxmega128a3", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega128a3u, "atxmega128a3u", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega128a4u, "atxmega128a4u", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega128b1, "atxmega128b1", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega128b3, "atxmega128b3", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega128c3, "atxmega128c3", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega128d3, "atxmega128d3", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega128d4, "atxmega128d4", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega16a4, "atxmega16a4", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega16a4u, "atxmega16a4u", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega16c4, "atxmega16c4", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega16d4, "atxmega16d4", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega16e5, "atxmega16e5", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega192a3, "atxmega192a3", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega192a3u, "atxmega192a3u", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega192c3, "atxmega192c3", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega192d3, "atxmega192d3", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega256a3, "atxmega256a3", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega256a3b, "atxmega256a3b", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega256a3bu, "atxmega256a3bu", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega256a3u, "atxmega256a3u", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega256c3, "atxmega256c3", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega256d3, "atxmega256d3", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega32a4, "atxmega32a4", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega32a4u, "atxmega32a4u", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega32c4, "atxmega32c4", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega32d4, "atxmega32d4", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega32e5, "atxmega32e5", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega32x1, "atxmega32x1", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega384c3, "atxmega384c3", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega384d3, "atxmega384d3", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega64a1, "atxmega64a1", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega64a1u, "atxmega64a1u", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega64a3, "atxmega64a3", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega64a3u, "atxmega64a3u", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega64a4u, "atxmega64a4u", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega64b1, "atxmega64b1", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega64b3, "atxmega64b3", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega64c3, "atxmega64c3", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmegau,
+ },
+ CpuInfo(@This()).create(.Atxmega64d3, "atxmega64d3", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega64d4, "atxmega64d4", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Atxmega8e5, "atxmega8e5", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Avr1, "avr1", &[_]FeatureType {
+ .Lpm,
+ .Avr0,
+ .Avr1,
+ },
+ CpuInfo(@This()).create(.Avr2, "avr2", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr2,
+ },
+ CpuInfo(@This()).create(.Avr25, "avr25", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr25,
+ },
+ CpuInfo(@This()).create(.Avr3, "avr3", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr3,
+ },
+ CpuInfo(@This()).create(.Avr31, "avr31", &[_]FeatureType {
+ .Ijmpcall,
+ .Sram,
+ .Elpm,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr31,
+ },
+ CpuInfo(@This()).create(.Avr35, "avr35", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr35,
+ },
+ CpuInfo(@This()).create(.Avr4, "avr4", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ .Avr4,
+ },
+ CpuInfo(@This()).create(.Avr5, "avr5", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ CpuInfo(@This()).create(.Avr51, "avr51", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr51,
+ },
+ CpuInfo(@This()).create(.Avr6, "avr6", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr6,
+ },
+ CpuInfo(@This()).create(.Avrtiny, "avrtiny", &[_]FeatureType {
+ .Break,
+ .Tinyencoding,
+ .Avr0,
+ .Sram,
+ .Avrtiny,
+ },
+ CpuInfo(@This()).create(.Avrxmega1, "avrxmega1", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Avrxmega2, "avrxmega2", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Avrxmega3, "avrxmega3", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Avrxmega4, "avrxmega4", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Avrxmega5, "avrxmega5", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Avrxmega6, "avrxmega6", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.Avrxmega7, "avrxmega7", &[_]FeatureType {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ .Xmega,
+ },
+ CpuInfo(@This()).create(.M3000, "m3000", &[_]FeatureType {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Avr5,
+ },
+ };
+};
lib/std/target/cpu/BpfCpu.zig
@@ -0,0 +1,29 @@
+const feature = @import("std").target.feature;
+const CpuInfo = @import("std").target.cpu.CpuInfo;
+
+pub const BpfCpu = enum {
+ Generic,
+ Probe,
+ V1,
+ V2,
+ V3,
+
+ pub fn getInfo(self: @This()) CpuInfo {
+ return cpu_infos[@enumToInt(self)];
+ }
+
+ pub const FeatureType = feature.BpfFeature;
+
+ const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
+ CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.Probe, "probe", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.V1, "v1", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.V2, "v2", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.V3, "v3", &[_]FeatureType {
+ },
+ };
+};
lib/std/target/cpu/empty.zig
@@ -0,0 +1,6 @@
+const feature = @import("std").target.feature;
+const CpuInfo = @import("std").target.cpu.CpuInfo;
+
+pub const EmptyCpu = enum {
+ pub const cpu_infos = [0]CpuInfo(@This()) {};
+};
lib/std/target/cpu/HexagonCpu.zig
@@ -0,0 +1,103 @@
+const feature = @import("std").target.feature;
+const CpuInfo = @import("std").target.cpu.CpuInfo;
+
+pub const HexagonCpu = enum {
+ Generic,
+ Hexagonv5,
+ Hexagonv55,
+ Hexagonv60,
+ Hexagonv62,
+ Hexagonv65,
+ Hexagonv66,
+
+ pub fn getInfo(self: @This()) CpuInfo {
+ return cpu_infos[@enumToInt(self)];
+ }
+
+ pub const FeatureType = feature.HexagonFeature;
+
+ const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
+ CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
+ .V5,
+ .V55,
+ .V60,
+ .Duplex,
+ .Memops,
+ .Packets,
+ .Nvj,
+ .Nvs,
+ .SmallData,
+ },
+ CpuInfo(@This()).create(.Hexagonv5, "hexagonv5", &[_]FeatureType {
+ .V5,
+ .Duplex,
+ .Memops,
+ .Packets,
+ .Nvj,
+ .Nvs,
+ .SmallData,
+ },
+ CpuInfo(@This()).create(.Hexagonv55, "hexagonv55", &[_]FeatureType {
+ .V5,
+ .V55,
+ .Duplex,
+ .Memops,
+ .Packets,
+ .Nvj,
+ .Nvs,
+ .SmallData,
+ },
+ CpuInfo(@This()).create(.Hexagonv60, "hexagonv60", &[_]FeatureType {
+ .V5,
+ .V55,
+ .V60,
+ .Duplex,
+ .Memops,
+ .Packets,
+ .Nvj,
+ .Nvs,
+ .SmallData,
+ },
+ CpuInfo(@This()).create(.Hexagonv62, "hexagonv62", &[_]FeatureType {
+ .V5,
+ .V55,
+ .V60,
+ .V62,
+ .Duplex,
+ .Memops,
+ .Packets,
+ .Nvj,
+ .Nvs,
+ .SmallData,
+ },
+ CpuInfo(@This()).create(.Hexagonv65, "hexagonv65", &[_]FeatureType {
+ .V5,
+ .V55,
+ .V60,
+ .V62,
+ .V65,
+ .Duplex,
+ .Mem_noshuf,
+ .Memops,
+ .Packets,
+ .Nvj,
+ .Nvs,
+ .SmallData,
+ },
+ CpuInfo(@This()).create(.Hexagonv66, "hexagonv66", &[_]FeatureType {
+ .V5,
+ .V55,
+ .V60,
+ .V62,
+ .V65,
+ .V66,
+ .Duplex,
+ .Mem_noshuf,
+ .Memops,
+ .Packets,
+ .Nvj,
+ .Nvs,
+ .SmallData,
+ },
+ };
+};
lib/std/target/cpu/MipsCpu.zig
@@ -0,0 +1,190 @@
+const feature = @import("std").target.feature;
+const CpuInfo = @import("std").target.cpu.CpuInfo;
+
+pub const MipsCpu = enum {
+ Mips1,
+ Mips2,
+ Mips3,
+ Mips32,
+ Mips32r2,
+ Mips32r3,
+ Mips32r5,
+ Mips32r6,
+ Mips4,
+ Mips5,
+ Mips64,
+ Mips64r2,
+ Mips64r3,
+ Mips64r5,
+ Mips64r6,
+ Octeon,
+ P5600,
+
+ pub fn getInfo(self: @This()) CpuInfo {
+ return cpu_infos[@enumToInt(self)];
+ }
+
+ pub const FeatureType = feature.MipsFeature;
+
+ const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
+ CpuInfo(@This()).create(.Mips1, "mips1", &[_]FeatureType {
+ .Mips1,
+ },
+ CpuInfo(@This()).create(.Mips2, "mips2", &[_]FeatureType {
+ .Mips1,
+ .Mips2,
+ },
+ CpuInfo(@This()).create(.Mips3, "mips3", &[_]FeatureType {
+ .Mips3_32,
+ .Fp64,
+ .Mips3_32r2,
+ .Mips1,
+ .Gp64,
+ .Mips3,
+ },
+ CpuInfo(@This()).create(.Mips32, "mips32", &[_]FeatureType {
+ .Mips3_32,
+ .Mips4_32,
+ .Mips1,
+ .Mips32,
+ },
+ CpuInfo(@This()).create(.Mips32r2, "mips32r2", &[_]FeatureType {
+ .Mips3_32,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Mips5_32r2,
+ .Mips32r2,
+ },
+ CpuInfo(@This()).create(.Mips32r3, "mips32r3", &[_]FeatureType {
+ .Mips3_32,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Mips5_32r2,
+ .Mips32r3,
+ },
+ CpuInfo(@This()).create(.Mips32r5, "mips32r5", &[_]FeatureType {
+ .Mips3_32,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Mips5_32r2,
+ .Mips32r5,
+ },
+ CpuInfo(@This()).create(.Mips32r6, "mips32r6", &[_]FeatureType {
+ .Mips3_32,
+ .Fp64,
+ .Mips4_32r2,
+ .Abs2008,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Nan2008,
+ .Mips5_32r2,
+ .Mips32r6,
+ },
+ CpuInfo(@This()).create(.Mips4, "mips4", &[_]FeatureType {
+ .Mips3_32,
+ .Fp64,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Gp64,
+ .Mips4,
+ },
+ CpuInfo(@This()).create(.Mips5, "mips5", &[_]FeatureType {
+ .Mips3_32,
+ .Fp64,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Gp64,
+ .Mips5_32r2,
+ .Mips5,
+ },
+ CpuInfo(@This()).create(.Mips64, "mips64", &[_]FeatureType {
+ .Mips3_32,
+ .Fp64,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Gp64,
+ .Mips5_32r2,
+ .Mips64,
+ },
+ CpuInfo(@This()).create(.Mips64r2, "mips64r2", &[_]FeatureType {
+ .Mips3_32,
+ .Fp64,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Gp64,
+ .Mips5_32r2,
+ .Mips64r2,
+ },
+ CpuInfo(@This()).create(.Mips64r3, "mips64r3", &[_]FeatureType {
+ .Mips3_32,
+ .Fp64,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Gp64,
+ .Mips5_32r2,
+ .Mips64r3,
+ },
+ CpuInfo(@This()).create(.Mips64r5, "mips64r5", &[_]FeatureType {
+ .Mips3_32,
+ .Fp64,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Gp64,
+ .Mips5_32r2,
+ .Mips64r5,
+ },
+ CpuInfo(@This()).create(.Mips64r6, "mips64r6", &[_]FeatureType {
+ .Mips3_32,
+ .Fp64,
+ .Mips4_32r2,
+ .Abs2008,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Nan2008,
+ .Gp64,
+ .Mips5_32r2,
+ .Mips64r6,
+ },
+ CpuInfo(@This()).create(.Octeon, "octeon", &[_]FeatureType {
+ .Mips3_32,
+ .Fp64,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Gp64,
+ .Mips5_32r2,
+ .Cnmips,
+ .Mips64r2,
+ },
+ CpuInfo(@This()).create(.P5600, "p5600", &[_]FeatureType {
+ .Mips3_32,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Mips5_32r2,
+ .P5600,
+ },
+ };
+};
lib/std/target/cpu/Msp430Cpu.zig
@@ -0,0 +1,24 @@
+const feature = @import("std").target.feature;
+const CpuInfo = @import("std").target.cpu.CpuInfo;
+
+pub const Msp430Cpu = enum {
+ Generic,
+ Msp430,
+ Msp430x,
+
+ pub fn getInfo(self: @This()) CpuInfo {
+ return cpu_infos[@enumToInt(self)];
+ }
+
+ pub const FeatureType = feature.Msp430Feature;
+
+ const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
+ CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.Msp430, "msp430", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.Msp430x, "msp430x", &[_]FeatureType {
+ .Ext,
+ },
+ };
+};
lib/std/target/cpu/NvptxCpu.zig
@@ -0,0 +1,85 @@
+const feature = @import("std").target.feature;
+const CpuInfo = @import("std").target.cpu.CpuInfo;
+
+pub const NvptxCpu = enum {
+ Sm_20,
+ Sm_21,
+ Sm_30,
+ Sm_32,
+ Sm_35,
+ Sm_37,
+ Sm_50,
+ Sm_52,
+ Sm_53,
+ Sm_60,
+ Sm_61,
+ Sm_62,
+ Sm_70,
+ Sm_72,
+ Sm_75,
+
+ pub fn getInfo(self: @This()) CpuInfo {
+ return cpu_infos[@enumToInt(self)];
+ }
+
+ pub const FeatureType = feature.NvptxFeature;
+
+ const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
+ CpuInfo(@This()).create(.Sm_20, "sm_20", &[_]FeatureType {
+ .Sm_20,
+ },
+ CpuInfo(@This()).create(.Sm_21, "sm_21", &[_]FeatureType {
+ .Sm_21,
+ },
+ CpuInfo(@This()).create(.Sm_30, "sm_30", &[_]FeatureType {
+ .Sm_30,
+ },
+ CpuInfo(@This()).create(.Sm_32, "sm_32", &[_]FeatureType {
+ .Ptx40,
+ .Sm_32,
+ },
+ CpuInfo(@This()).create(.Sm_35, "sm_35", &[_]FeatureType {
+ .Sm_35,
+ },
+ CpuInfo(@This()).create(.Sm_37, "sm_37", &[_]FeatureType {
+ .Ptx41,
+ .Sm_37,
+ },
+ CpuInfo(@This()).create(.Sm_50, "sm_50", &[_]FeatureType {
+ .Ptx40,
+ .Sm_50,
+ },
+ CpuInfo(@This()).create(.Sm_52, "sm_52", &[_]FeatureType {
+ .Ptx41,
+ .Sm_52,
+ },
+ CpuInfo(@This()).create(.Sm_53, "sm_53", &[_]FeatureType {
+ .Ptx42,
+ .Sm_53,
+ },
+ CpuInfo(@This()).create(.Sm_60, "sm_60", &[_]FeatureType {
+ .Ptx50,
+ .Sm_60,
+ },
+ CpuInfo(@This()).create(.Sm_61, "sm_61", &[_]FeatureType {
+ .Ptx50,
+ .Sm_61,
+ },
+ CpuInfo(@This()).create(.Sm_62, "sm_62", &[_]FeatureType {
+ .Ptx50,
+ .Sm_62,
+ },
+ CpuInfo(@This()).create(.Sm_70, "sm_70", &[_]FeatureType {
+ .Ptx60,
+ .Sm_70,
+ },
+ CpuInfo(@This()).create(.Sm_72, "sm_72", &[_]FeatureType {
+ .Ptx61,
+ .Sm_72,
+ },
+ CpuInfo(@This()).create(.Sm_75, "sm_75", &[_]FeatureType {
+ .Ptx63,
+ .Sm_75,
+ },
+ };
+};
lib/std/target/cpu/PowerPcCpu.zig
@@ -0,0 +1,451 @@
+const feature = @import("std").target.feature;
+const CpuInfo = @import("std").target.cpu.CpuInfo;
+
+pub const PowerPcCpu = enum {
+ 440,
+ 450,
+ 601,
+ 602,
+ 603,
+ E603,
+ Ev603,
+ 604,
+ E604,
+ 620,
+ 7400,
+ 7450,
+ 750,
+ 970,
+ A2,
+ A2q,
+ E500,
+ E500mc,
+ E5500,
+ G3,
+ G4,
+ G4+,
+ G5,
+ Generic,
+ Ppc,
+ Ppc32,
+ Ppc64,
+ Ppc64le,
+ Pwr3,
+ Pwr4,
+ Pwr5,
+ Pwr5x,
+ Pwr6,
+ Pwr6x,
+ Pwr7,
+ Pwr8,
+ Pwr9,
+
+ pub fn getInfo(self: @This()) CpuInfo {
+ return cpu_infos[@enumToInt(self)];
+ }
+
+ pub const FeatureType = feature.PowerPcFeature;
+
+ const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
+ CpuInfo(@This()).create(.440, "440", &[_]FeatureType {
+ .Icbt,
+ .Booke,
+ .HardFloat,
+ .Fres,
+ .Frsqrte,
+ .Isel,
+ .Msync,
+ },
+ CpuInfo(@This()).create(.450, "450", &[_]FeatureType {
+ .Icbt,
+ .Booke,
+ .HardFloat,
+ .Fres,
+ .Frsqrte,
+ .Isel,
+ .Msync,
+ },
+ CpuInfo(@This()).create(.601, "601", &[_]FeatureType {
+ .HardFloat,
+ .Fpu,
+ },
+ CpuInfo(@This()).create(.602, "602", &[_]FeatureType {
+ .HardFloat,
+ .Fpu,
+ },
+ CpuInfo(@This()).create(.603, "603", &[_]FeatureType {
+ .HardFloat,
+ .Fres,
+ .Frsqrte,
+ },
+ CpuInfo(@This()).create(.E603, "603e", &[_]FeatureType {
+ .HardFloat,
+ .Fres,
+ .Frsqrte,
+ },
+ CpuInfo(@This()).create(.Ev603, "603ev", &[_]FeatureType {
+ .HardFloat,
+ .Fres,
+ .Frsqrte,
+ },
+ CpuInfo(@This()).create(.604, "604", &[_]FeatureType {
+ .HardFloat,
+ .Fres,
+ .Frsqrte,
+ },
+ CpuInfo(@This()).create(.E604, "604e", &[_]FeatureType {
+ .HardFloat,
+ .Fres,
+ .Frsqrte,
+ },
+ CpuInfo(@This()).create(.620, "620", &[_]FeatureType {
+ .HardFloat,
+ .Fres,
+ .Frsqrte,
+ },
+ CpuInfo(@This()).create(.7400, "7400", &[_]FeatureType {
+ .HardFloat,
+ .Altivec,
+ .Fres,
+ .Frsqrte,
+ },
+ CpuInfo(@This()).create(.7450, "7450", &[_]FeatureType {
+ .HardFloat,
+ .Altivec,
+ .Fres,
+ .Frsqrte,
+ },
+ CpuInfo(@This()).create(.750, "750", &[_]FeatureType {
+ .HardFloat,
+ .Fres,
+ .Frsqrte,
+ },
+ CpuInfo(@This()).create(.970, "970", &[_]FeatureType {
+ .Bit64,
+ .HardFloat,
+ .Altivec,
+ .Fres,
+ .Frsqrte,
+ .Fsqrt,
+ .Mfocrf,
+ .Stfiwx,
+ },
+ CpuInfo(@This()).create(.A2, "a2", &[_]FeatureType {
+ .Bit64,
+ .Icbt,
+ .Booke,
+ .Cmpb,
+ .HardFloat,
+ .Fcpsgn,
+ .Fpcvt,
+ .Fprnd,
+ .Fre,
+ .Fres,
+ .Frsqrte,
+ .Frsqrtes,
+ .Fsqrt,
+ .Isel,
+ .Ldbrx,
+ .Lfiwax,
+ .Mfocrf,
+ .Recipprec,
+ .Stfiwx,
+ .SlowPopcntd,
+ },
+ CpuInfo(@This()).create(.A2q, "a2q", &[_]FeatureType {
+ .Bit64,
+ .Icbt,
+ .Booke,
+ .Cmpb,
+ .HardFloat,
+ .Fcpsgn,
+ .Fpcvt,
+ .Fprnd,
+ .Fre,
+ .Fres,
+ .Frsqrte,
+ .Frsqrtes,
+ .Fsqrt,
+ .Isel,
+ .Ldbrx,
+ .Lfiwax,
+ .Mfocrf,
+ .Qpx,
+ .Recipprec,
+ .Stfiwx,
+ .SlowPopcntd,
+ },
+ CpuInfo(@This()).create(.E500, "e500", &[_]FeatureType {
+ .Icbt,
+ .Booke,
+ .Isel,
+ },
+ CpuInfo(@This()).create(.E500mc, "e500mc", &[_]FeatureType {
+ .Icbt,
+ .Booke,
+ .Isel,
+ .HardFloat,
+ .Stfiwx,
+ },
+ CpuInfo(@This()).create(.E5500, "e5500", &[_]FeatureType {
+ .Bit64,
+ .Icbt,
+ .Booke,
+ .Isel,
+ .Mfocrf,
+ .HardFloat,
+ .Stfiwx,
+ },
+ CpuInfo(@This()).create(.G3, "g3", &[_]FeatureType {
+ .HardFloat,
+ .Fres,
+ .Frsqrte,
+ },
+ CpuInfo(@This()).create(.G4, "g4", &[_]FeatureType {
+ .HardFloat,
+ .Altivec,
+ .Fres,
+ .Frsqrte,
+ },
+ CpuInfo(@This()).create(.G4+, "g4+", &[_]FeatureType {
+ .HardFloat,
+ .Altivec,
+ .Fres,
+ .Frsqrte,
+ },
+ CpuInfo(@This()).create(.G5, "g5", &[_]FeatureType {
+ .Bit64,
+ .HardFloat,
+ .Altivec,
+ .Fres,
+ .Frsqrte,
+ .Fsqrt,
+ .Mfocrf,
+ .Stfiwx,
+ },
+ CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
+ .HardFloat,
+ },
+ CpuInfo(@This()).create(.Ppc, "ppc", &[_]FeatureType {
+ .HardFloat,
+ },
+ CpuInfo(@This()).create(.Ppc32, "ppc32", &[_]FeatureType {
+ .HardFloat,
+ },
+ CpuInfo(@This()).create(.Ppc64, "ppc64", &[_]FeatureType {
+ .Bit64,
+ .HardFloat,
+ .Altivec,
+ .Fres,
+ .Frsqrte,
+ .Fsqrt,
+ .Mfocrf,
+ .Stfiwx,
+ },
+ CpuInfo(@This()).create(.Ppc64le, "ppc64le", &[_]FeatureType {
+ .Bit64,
+ .HardFloat,
+ .Altivec,
+ .Bpermd,
+ .Cmpb,
+ .DirectMove,
+ .Extdiv,
+ .Fcpsgn,
+ .Fpcvt,
+ .Fprnd,
+ .Fre,
+ .Fres,
+ .Frsqrte,
+ .Frsqrtes,
+ .Fsqrt,
+ .Htm,
+ .Icbt,
+ .Isel,
+ .Ldbrx,
+ .Lfiwax,
+ .Mfocrf,
+ .Power8Altivec,
+ .Crypto,
+ .Power8Vector,
+ .Popcntd,
+ .PartwordAtomics,
+ .Recipprec,
+ .Stfiwx,
+ .TwoConstNr,
+ .Vsx,
+ },
+ CpuInfo(@This()).create(.Pwr3, "pwr3", &[_]FeatureType {
+ .Bit64,
+ .HardFloat,
+ .Altivec,
+ .Fres,
+ .Frsqrte,
+ .Mfocrf,
+ .Stfiwx,
+ },
+ CpuInfo(@This()).create(.Pwr4, "pwr4", &[_]FeatureType {
+ .Bit64,
+ .HardFloat,
+ .Altivec,
+ .Fres,
+ .Frsqrte,
+ .Fsqrt,
+ .Mfocrf,
+ .Stfiwx,
+ },
+ CpuInfo(@This()).create(.Pwr5, "pwr5", &[_]FeatureType {
+ .Bit64,
+ .HardFloat,
+ .Altivec,
+ .Fre,
+ .Fres,
+ .Frsqrte,
+ .Frsqrtes,
+ .Fsqrt,
+ .Mfocrf,
+ .Stfiwx,
+ },
+ CpuInfo(@This()).create(.Pwr5x, "pwr5x", &[_]FeatureType {
+ .Bit64,
+ .HardFloat,
+ .Altivec,
+ .Fprnd,
+ .Fre,
+ .Fres,
+ .Frsqrte,
+ .Frsqrtes,
+ .Fsqrt,
+ .Mfocrf,
+ .Stfiwx,
+ },
+ CpuInfo(@This()).create(.Pwr6, "pwr6", &[_]FeatureType {
+ .Bit64,
+ .HardFloat,
+ .Altivec,
+ .Cmpb,
+ .Fcpsgn,
+ .Fprnd,
+ .Fre,
+ .Fres,
+ .Frsqrte,
+ .Frsqrtes,
+ .Fsqrt,
+ .Lfiwax,
+ .Mfocrf,
+ .Recipprec,
+ .Stfiwx,
+ },
+ CpuInfo(@This()).create(.Pwr6x, "pwr6x", &[_]FeatureType {
+ .Bit64,
+ .HardFloat,
+ .Altivec,
+ .Cmpb,
+ .Fcpsgn,
+ .Fprnd,
+ .Fre,
+ .Fres,
+ .Frsqrte,
+ .Frsqrtes,
+ .Fsqrt,
+ .Lfiwax,
+ .Mfocrf,
+ .Recipprec,
+ .Stfiwx,
+ },
+ CpuInfo(@This()).create(.Pwr7, "pwr7", &[_]FeatureType {
+ .Bit64,
+ .HardFloat,
+ .Altivec,
+ .Bpermd,
+ .Cmpb,
+ .Extdiv,
+ .Fcpsgn,
+ .Fpcvt,
+ .Fprnd,
+ .Fre,
+ .Fres,
+ .Frsqrte,
+ .Frsqrtes,
+ .Fsqrt,
+ .Isel,
+ .Ldbrx,
+ .Lfiwax,
+ .Mfocrf,
+ .Popcntd,
+ .Recipprec,
+ .Stfiwx,
+ .TwoConstNr,
+ .Vsx,
+ },
+ CpuInfo(@This()).create(.Pwr8, "pwr8", &[_]FeatureType {
+ .Bit64,
+ .HardFloat,
+ .Altivec,
+ .Bpermd,
+ .Cmpb,
+ .DirectMove,
+ .Extdiv,
+ .Fcpsgn,
+ .Fpcvt,
+ .Fprnd,
+ .Fre,
+ .Fres,
+ .Frsqrte,
+ .Frsqrtes,
+ .Fsqrt,
+ .Htm,
+ .Icbt,
+ .Isel,
+ .Ldbrx,
+ .Lfiwax,
+ .Mfocrf,
+ .Power8Altivec,
+ .Crypto,
+ .Power8Vector,
+ .Popcntd,
+ .PartwordAtomics,
+ .Recipprec,
+ .Stfiwx,
+ .TwoConstNr,
+ .Vsx,
+ },
+ CpuInfo(@This()).create(.Pwr9, "pwr9", &[_]FeatureType {
+ .Bit64,
+ .HardFloat,
+ .Altivec,
+ .Bpermd,
+ .Cmpb,
+ .DirectMove,
+ .Extdiv,
+ .Fcpsgn,
+ .Fpcvt,
+ .Fprnd,
+ .Fre,
+ .Fres,
+ .Frsqrte,
+ .Frsqrtes,
+ .Fsqrt,
+ .Htm,
+ .Icbt,
+ .IsaV30Instructions,
+ .Isel,
+ .Ldbrx,
+ .Lfiwax,
+ .Mfocrf,
+ .Power8Altivec,
+ .Crypto,
+ .Power8Vector,
+ .Power9Altivec,
+ .Power9Vector,
+ .Popcntd,
+ .PpcPostraSched,
+ .PpcPreraSched,
+ .PartwordAtomics,
+ .Recipprec,
+ .Stfiwx,
+ .TwoConstNr,
+ .Vsx,
+ .VectorsUseTwoUnits,
+ },
+ };
+};
lib/std/target/cpu/RiscVCpu.zig
@@ -0,0 +1,23 @@
+const feature = @import("std").target.feature;
+const CpuInfo = @import("std").target.cpu.CpuInfo;
+
+pub const RiscVCpu = enum {
+ GenericRv32,
+ GenericRv64,
+
+ pub fn getInfo(self: @This()) CpuInfo {
+ return cpu_infos[@enumToInt(self)];
+ }
+
+ pub const FeatureType = feature.RiscVFeature;
+
+ const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
+ CpuInfo(@This()).create(.GenericRv32, "generic-rv32", &[_]FeatureType {
+ .RvcHints,
+ },
+ CpuInfo(@This()).create(.GenericRv64, "generic-rv64", &[_]FeatureType {
+ .Bit64,
+ .RvcHints,
+ },
+ };
+};
lib/std/target/cpu/SparcCpu.zig
@@ -0,0 +1,216 @@
+const feature = @import("std").target.feature;
+const CpuInfo = @import("std").target.cpu.CpuInfo;
+
+pub const SparcCpu = enum {
+ At697e,
+ At697f,
+ F934,
+ Generic,
+ Gr712rc,
+ Gr740,
+ Hypersparc,
+ Leon2,
+ Leon3,
+ Leon4,
+ Ma2080,
+ Ma2085,
+ Ma2100,
+ Ma2150,
+ Ma2155,
+ Ma2450,
+ Ma2455,
+ Ma2480,
+ Ma2485,
+ Ma2x5x,
+ Ma2x8x,
+ Myriad2,
+ Myriad21,
+ Myriad22,
+ Myriad23,
+ Niagara,
+ Niagara2,
+ Niagara3,
+ Niagara4,
+ Sparclet,
+ Sparclite,
+ Sparclite86x,
+ Supersparc,
+ Tsc701,
+ Ultrasparc,
+ Ultrasparc3,
+ Ut699,
+ V7,
+ V8,
+ V9,
+
+ pub fn getInfo(self: @This()) CpuInfo {
+ return cpu_infos[@enumToInt(self)];
+ }
+
+ pub const FeatureType = feature.SparcFeature;
+
+ const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
+ CpuInfo(@This()).create(.At697e, "at697e", &[_]FeatureType {
+ .Leon,
+ .Insertnopload,
+ },
+ CpuInfo(@This()).create(.At697f, "at697f", &[_]FeatureType {
+ .Leon,
+ .Insertnopload,
+ },
+ CpuInfo(@This()).create(.F934, "f934", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.Gr712rc, "gr712rc", &[_]FeatureType {
+ .Leon,
+ .Hasleoncasa,
+ },
+ CpuInfo(@This()).create(.Gr740, "gr740", &[_]FeatureType {
+ .Leon,
+ .Leonpwrpsr,
+ .Hasleoncasa,
+ .Leoncyclecounter,
+ .Hasumacsmac,
+ },
+ CpuInfo(@This()).create(.Hypersparc, "hypersparc", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.Leon2, "leon2", &[_]FeatureType {
+ .Leon,
+ },
+ CpuInfo(@This()).create(.Leon3, "leon3", &[_]FeatureType {
+ .Leon,
+ .Hasumacsmac,
+ },
+ CpuInfo(@This()).create(.Leon4, "leon4", &[_]FeatureType {
+ .Leon,
+ .Hasleoncasa,
+ .Hasumacsmac,
+ },
+ CpuInfo(@This()).create(.Ma2080, "ma2080", &[_]FeatureType {
+ .Leon,
+ .Hasleoncasa,
+ },
+ CpuInfo(@This()).create(.Ma2085, "ma2085", &[_]FeatureType {
+ .Leon,
+ .Hasleoncasa,
+ },
+ CpuInfo(@This()).create(.Ma2100, "ma2100", &[_]FeatureType {
+ .Leon,
+ .Hasleoncasa,
+ },
+ CpuInfo(@This()).create(.Ma2150, "ma2150", &[_]FeatureType {
+ .Leon,
+ .Hasleoncasa,
+ },
+ CpuInfo(@This()).create(.Ma2155, "ma2155", &[_]FeatureType {
+ .Leon,
+ .Hasleoncasa,
+ },
+ CpuInfo(@This()).create(.Ma2450, "ma2450", &[_]FeatureType {
+ .Leon,
+ .Hasleoncasa,
+ },
+ CpuInfo(@This()).create(.Ma2455, "ma2455", &[_]FeatureType {
+ .Leon,
+ .Hasleoncasa,
+ },
+ CpuInfo(@This()).create(.Ma2480, "ma2480", &[_]FeatureType {
+ .Leon,
+ .Hasleoncasa,
+ },
+ CpuInfo(@This()).create(.Ma2485, "ma2485", &[_]FeatureType {
+ .Leon,
+ .Hasleoncasa,
+ },
+ CpuInfo(@This()).create(.Ma2x5x, "ma2x5x", &[_]FeatureType {
+ .Leon,
+ .Hasleoncasa,
+ },
+ CpuInfo(@This()).create(.Ma2x8x, "ma2x8x", &[_]FeatureType {
+ .Leon,
+ .Hasleoncasa,
+ },
+ CpuInfo(@This()).create(.Myriad2, "myriad2", &[_]FeatureType {
+ .Leon,
+ .Hasleoncasa,
+ },
+ CpuInfo(@This()).create(.Myriad21, "myriad2.1", &[_]FeatureType {
+ .Leon,
+ .Hasleoncasa,
+ },
+ CpuInfo(@This()).create(.Myriad22, "myriad2.2", &[_]FeatureType {
+ .Leon,
+ .Hasleoncasa,
+ },
+ CpuInfo(@This()).create(.Myriad23, "myriad2.3", &[_]FeatureType {
+ .Leon,
+ .Hasleoncasa,
+ },
+ CpuInfo(@This()).create(.Niagara, "niagara", &[_]FeatureType {
+ .DeprecatedV8,
+ .V9,
+ .Vis,
+ .Vis2,
+ },
+ CpuInfo(@This()).create(.Niagara2, "niagara2", &[_]FeatureType {
+ .DeprecatedV8,
+ .V9,
+ .Vis,
+ .Vis2,
+ .Popc,
+ },
+ CpuInfo(@This()).create(.Niagara3, "niagara3", &[_]FeatureType {
+ .DeprecatedV8,
+ .V9,
+ .Vis,
+ .Vis2,
+ .Popc,
+ },
+ CpuInfo(@This()).create(.Niagara4, "niagara4", &[_]FeatureType {
+ .DeprecatedV8,
+ .V9,
+ .Vis,
+ .Vis2,
+ .Vis3,
+ .Popc,
+ },
+ CpuInfo(@This()).create(.Sparclet, "sparclet", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.Sparclite, "sparclite", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.Sparclite86x, "sparclite86x", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.Supersparc, "supersparc", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.Tsc701, "tsc701", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.Ultrasparc, "ultrasparc", &[_]FeatureType {
+ .DeprecatedV8,
+ .V9,
+ .Vis,
+ },
+ CpuInfo(@This()).create(.Ultrasparc3, "ultrasparc3", &[_]FeatureType {
+ .DeprecatedV8,
+ .V9,
+ .Vis,
+ .Vis2,
+ },
+ CpuInfo(@This()).create(.Ut699, "ut699", &[_]FeatureType {
+ .Leon,
+ .NoFmuls,
+ .NoFsmuld,
+ .Fixallfdivsqrt,
+ .Insertnopload,
+ },
+ CpuInfo(@This()).create(.V7, "v7", &[_]FeatureType {
+ .NoFsmuld,
+ .SoftMulDiv,
+ },
+ CpuInfo(@This()).create(.V8, "v8", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.V9, "v9", &[_]FeatureType {
+ .V9,
+ },
+ };
+};
lib/std/target/cpu/SystemZCpu.zig
@@ -0,0 +1,279 @@
+const feature = @import("std").target.feature;
+const CpuInfo = @import("std").target.cpu.CpuInfo;
+
+pub const SystemZCpu = enum {
+ Arch10,
+ Arch11,
+ Arch12,
+ Arch13,
+ Arch8,
+ Arch9,
+ Generic,
+ Z10,
+ Z13,
+ Z14,
+ Z15,
+ Z196,
+ ZEC12,
+
+ pub fn getInfo(self: @This()) CpuInfo {
+ return cpu_infos[@enumToInt(self)];
+ }
+
+ pub const FeatureType = feature.SystemZFeature;
+
+ const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
+ CpuInfo(@This()).create(.Arch10, "arch10", &[_]FeatureType {
+ .DfpZonedConversion,
+ .DistinctOps,
+ .EnhancedDat2,
+ .ExecutionHint,
+ .FpExtension,
+ .FastSerialization,
+ .HighWord,
+ .InterlockedAccess1,
+ .LoadAndTrap,
+ .LoadStoreOnCond,
+ .MessageSecurityAssistExtension3,
+ .MessageSecurityAssistExtension4,
+ .MiscellaneousExtensions,
+ .PopulationCount,
+ .ProcessorAssist,
+ .ResetReferenceBitsMultiple,
+ .TransactionalExecution,
+ },
+ CpuInfo(@This()).create(.Arch11, "arch11", &[_]FeatureType {
+ .DfpPackedConversion,
+ .DfpZonedConversion,
+ .DistinctOps,
+ .EnhancedDat2,
+ .ExecutionHint,
+ .FpExtension,
+ .FastSerialization,
+ .HighWord,
+ .InterlockedAccess1,
+ .LoadAndTrap,
+ .LoadAndZeroRightmostByte,
+ .LoadStoreOnCond,
+ .LoadStoreOnCond2,
+ .MessageSecurityAssistExtension3,
+ .MessageSecurityAssistExtension4,
+ .MessageSecurityAssistExtension5,
+ .MiscellaneousExtensions,
+ .PopulationCount,
+ .ProcessorAssist,
+ .ResetReferenceBitsMultiple,
+ .TransactionalExecution,
+ .Vector,
+ },
+ CpuInfo(@This()).create(.Arch12, "arch12", &[_]FeatureType {
+ .DfpPackedConversion,
+ .DfpZonedConversion,
+ .DistinctOps,
+ .EnhancedDat2,
+ .ExecutionHint,
+ .FpExtension,
+ .FastSerialization,
+ .GuardedStorage,
+ .HighWord,
+ .InsertReferenceBitsMultiple,
+ .InterlockedAccess1,
+ .LoadAndTrap,
+ .LoadAndZeroRightmostByte,
+ .LoadStoreOnCond,
+ .LoadStoreOnCond2,
+ .MessageSecurityAssistExtension3,
+ .MessageSecurityAssistExtension4,
+ .MessageSecurityAssistExtension5,
+ .MessageSecurityAssistExtension7,
+ .MessageSecurityAssistExtension8,
+ .MiscellaneousExtensions,
+ .MiscellaneousExtensions2,
+ .PopulationCount,
+ .ProcessorAssist,
+ .ResetReferenceBitsMultiple,
+ .TransactionalExecution,
+ .Vector,
+ .VectorEnhancements1,
+ .VectorPackedDecimal,
+ },
+ CpuInfo(@This()).create(.Arch13, "arch13", &[_]FeatureType {
+ .DfpPackedConversion,
+ .DfpZonedConversion,
+ .DeflateConversion,
+ .DistinctOps,
+ .EnhancedDat2,
+ .EnhancedSort,
+ .ExecutionHint,
+ .FpExtension,
+ .FastSerialization,
+ .GuardedStorage,
+ .HighWord,
+ .InsertReferenceBitsMultiple,
+ .InterlockedAccess1,
+ .LoadAndTrap,
+ .LoadAndZeroRightmostByte,
+ .LoadStoreOnCond,
+ .LoadStoreOnCond2,
+ .MessageSecurityAssistExtension3,
+ .MessageSecurityAssistExtension4,
+ .MessageSecurityAssistExtension5,
+ .MessageSecurityAssistExtension7,
+ .MessageSecurityAssistExtension8,
+ .MessageSecurityAssistExtension9,
+ .MiscellaneousExtensions,
+ .MiscellaneousExtensions2,
+ .MiscellaneousExtensions3,
+ .PopulationCount,
+ .ProcessorAssist,
+ .ResetReferenceBitsMultiple,
+ .TransactionalExecution,
+ .Vector,
+ .VectorEnhancements1,
+ .VectorEnhancements2,
+ .VectorPackedDecimal,
+ .VectorPackedDecimalEnhancement,
+ },
+ CpuInfo(@This()).create(.Arch8, "arch8", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.Arch9, "arch9", &[_]FeatureType {
+ .DistinctOps,
+ .FpExtension,
+ .FastSerialization,
+ .HighWord,
+ .InterlockedAccess1,
+ .LoadStoreOnCond,
+ .MessageSecurityAssistExtension3,
+ .MessageSecurityAssistExtension4,
+ .PopulationCount,
+ .ResetReferenceBitsMultiple,
+ },
+ CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.Z10, "z10", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.Z13, "z13", &[_]FeatureType {
+ .DfpPackedConversion,
+ .DfpZonedConversion,
+ .DistinctOps,
+ .EnhancedDat2,
+ .ExecutionHint,
+ .FpExtension,
+ .FastSerialization,
+ .HighWord,
+ .InterlockedAccess1,
+ .LoadAndTrap,
+ .LoadAndZeroRightmostByte,
+ .LoadStoreOnCond,
+ .LoadStoreOnCond2,
+ .MessageSecurityAssistExtension3,
+ .MessageSecurityAssistExtension4,
+ .MessageSecurityAssistExtension5,
+ .MiscellaneousExtensions,
+ .PopulationCount,
+ .ProcessorAssist,
+ .ResetReferenceBitsMultiple,
+ .TransactionalExecution,
+ .Vector,
+ },
+ CpuInfo(@This()).create(.Z14, "z14", &[_]FeatureType {
+ .DfpPackedConversion,
+ .DfpZonedConversion,
+ .DistinctOps,
+ .EnhancedDat2,
+ .ExecutionHint,
+ .FpExtension,
+ .FastSerialization,
+ .GuardedStorage,
+ .HighWord,
+ .InsertReferenceBitsMultiple,
+ .InterlockedAccess1,
+ .LoadAndTrap,
+ .LoadAndZeroRightmostByte,
+ .LoadStoreOnCond,
+ .LoadStoreOnCond2,
+ .MessageSecurityAssistExtension3,
+ .MessageSecurityAssistExtension4,
+ .MessageSecurityAssistExtension5,
+ .MessageSecurityAssistExtension7,
+ .MessageSecurityAssistExtension8,
+ .MiscellaneousExtensions,
+ .MiscellaneousExtensions2,
+ .PopulationCount,
+ .ProcessorAssist,
+ .ResetReferenceBitsMultiple,
+ .TransactionalExecution,
+ .Vector,
+ .VectorEnhancements1,
+ .VectorPackedDecimal,
+ },
+ CpuInfo(@This()).create(.Z15, "z15", &[_]FeatureType {
+ .DfpPackedConversion,
+ .DfpZonedConversion,
+ .DeflateConversion,
+ .DistinctOps,
+ .EnhancedDat2,
+ .EnhancedSort,
+ .ExecutionHint,
+ .FpExtension,
+ .FastSerialization,
+ .GuardedStorage,
+ .HighWord,
+ .InsertReferenceBitsMultiple,
+ .InterlockedAccess1,
+ .LoadAndTrap,
+ .LoadAndZeroRightmostByte,
+ .LoadStoreOnCond,
+ .LoadStoreOnCond2,
+ .MessageSecurityAssistExtension3,
+ .MessageSecurityAssistExtension4,
+ .MessageSecurityAssistExtension5,
+ .MessageSecurityAssistExtension7,
+ .MessageSecurityAssistExtension8,
+ .MessageSecurityAssistExtension9,
+ .MiscellaneousExtensions,
+ .MiscellaneousExtensions2,
+ .MiscellaneousExtensions3,
+ .PopulationCount,
+ .ProcessorAssist,
+ .ResetReferenceBitsMultiple,
+ .TransactionalExecution,
+ .Vector,
+ .VectorEnhancements1,
+ .VectorEnhancements2,
+ .VectorPackedDecimal,
+ .VectorPackedDecimalEnhancement,
+ },
+ CpuInfo(@This()).create(.Z196, "z196", &[_]FeatureType {
+ .DistinctOps,
+ .FpExtension,
+ .FastSerialization,
+ .HighWord,
+ .InterlockedAccess1,
+ .LoadStoreOnCond,
+ .MessageSecurityAssistExtension3,
+ .MessageSecurityAssistExtension4,
+ .PopulationCount,
+ .ResetReferenceBitsMultiple,
+ },
+ CpuInfo(@This()).create(.ZEC12, "zEC12", &[_]FeatureType {
+ .DfpZonedConversion,
+ .DistinctOps,
+ .EnhancedDat2,
+ .ExecutionHint,
+ .FpExtension,
+ .FastSerialization,
+ .HighWord,
+ .InterlockedAccess1,
+ .LoadAndTrap,
+ .LoadStoreOnCond,
+ .MessageSecurityAssistExtension3,
+ .MessageSecurityAssistExtension4,
+ .MiscellaneousExtensions,
+ .PopulationCount,
+ .ProcessorAssist,
+ .ResetReferenceBitsMultiple,
+ .TransactionalExecution,
+ },
+ };
+};
lib/std/target/cpu/WebAssemblyCpu.zig
@@ -0,0 +1,28 @@
+const feature = @import("std").target.feature;
+const CpuInfo = @import("std").target.cpu.CpuInfo;
+
+pub const WebAssemblyCpu = enum {
+ BleedingEdge,
+ Generic,
+ Mvp,
+
+ pub fn getInfo(self: @This()) CpuInfo {
+ return cpu_infos[@enumToInt(self)];
+ }
+
+ pub const FeatureType = feature.WebAssemblyFeature;
+
+ const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
+ CpuInfo(@This()).create(.BleedingEdge, "bleeding-edge", &[_]FeatureType {
+ .Atomics,
+ .MutableGlobals,
+ .NontrappingFptoint,
+ .Simd128,
+ .SignExt,
+ },
+ CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.Mvp, "mvp", &[_]FeatureType {
+ },
+ };
+};
lib/std/target/cpu/X86Cpu.zig
@@ -0,0 +1,1864 @@
+const feature = @import("std").target.feature;
+const CpuInfo = @import("std").target.cpu.CpuInfo;
+
+pub const X86Cpu = enum {
+ Amdfam10,
+ Athlon,
+ Athlon4,
+ AthlonFx,
+ AthlonMp,
+ AthlonTbird,
+ AthlonXp,
+ Athlon64,
+ Athlon64Sse3,
+ Atom,
+ Barcelona,
+ Bdver1,
+ Bdver2,
+ Bdver3,
+ Bdver4,
+ Bonnell,
+ Broadwell,
+ Btver1,
+ Btver2,
+ C3,
+ C32,
+ Cannonlake,
+ Cascadelake,
+ Cooperlake,
+ CoreAvxI,
+ CoreAvx2,
+ Core2,
+ Corei7,
+ Corei7Avx,
+ Generic,
+ Geode,
+ Goldmont,
+ GoldmontPlus,
+ Haswell,
+ I386,
+ I486,
+ I586,
+ I686,
+ IcelakeClient,
+ IcelakeServer,
+ Ivybridge,
+ K6,
+ K62,
+ K63,
+ K8,
+ K8Sse3,
+ Knl,
+ Knm,
+ Lakemont,
+ Nehalem,
+ Nocona,
+ Opteron,
+ OpteronSse3,
+ Penryn,
+ Pentium,
+ PentiumM,
+ PentiumMmx,
+ Pentium2,
+ Pentium3,
+ Pentium3m,
+ Pentium4,
+ Pentium4m,
+ Pentiumpro,
+ Prescott,
+ Sandybridge,
+ Silvermont,
+ Skx,
+ Skylake,
+ SkylakeAvx512,
+ Slm,
+ Tigerlake,
+ Tremont,
+ Westmere,
+ WinchipC6,
+ Winchip2,
+ X8664,
+ Yonah,
+ Znver1,
+ Znver2,
+
+ pub fn getInfo(self: @This()) CpuInfo {
+ return cpu_infos[@enumToInt(self)];
+ }
+
+ pub const FeatureType = feature.X86Feature;
+
+ const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
+ CpuInfo(@This()).create(.Amdfam10, "amdfam10", &[_]FeatureType {
+ .Mmx,
+ .Dnowa3,
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fxsr,
+ .FastScalarShiftMasks,
+ .Sahf,
+ .Lzcnt,
+ .Nopl,
+ .Popcnt,
+ .Sse,
+ .Sse4a,
+ .SlowShld,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Athlon, "athlon", &[_]FeatureType {
+ .Mmx,
+ .Dnowa3,
+ .Cmov,
+ .Cx8,
+ .Nopl,
+ .SlowShld,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Athlon4, "athlon-4", &[_]FeatureType {
+ .Mmx,
+ .Dnowa3,
+ .Cmov,
+ .Cx8,
+ .Fxsr,
+ .Nopl,
+ .Sse,
+ .SlowShld,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.AthlonFx, "athlon-fx", &[_]FeatureType {
+ .Mmx,
+ .Dnowa3,
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Fxsr,
+ .FastScalarShiftMasks,
+ .Nopl,
+ .Sse,
+ .Sse2,
+ .SlowShld,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.AthlonMp, "athlon-mp", &[_]FeatureType {
+ .Mmx,
+ .Dnowa3,
+ .Cmov,
+ .Cx8,
+ .Fxsr,
+ .Nopl,
+ .Sse,
+ .SlowShld,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.AthlonTbird, "athlon-tbird", &[_]FeatureType {
+ .Mmx,
+ .Dnowa3,
+ .Cmov,
+ .Cx8,
+ .Nopl,
+ .SlowShld,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.AthlonXp, "athlon-xp", &[_]FeatureType {
+ .Mmx,
+ .Dnowa3,
+ .Cmov,
+ .Cx8,
+ .Fxsr,
+ .Nopl,
+ .Sse,
+ .SlowShld,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Athlon64, "athlon64", &[_]FeatureType {
+ .Mmx,
+ .Dnowa3,
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Fxsr,
+ .FastScalarShiftMasks,
+ .Nopl,
+ .Sse,
+ .Sse2,
+ .SlowShld,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Athlon64Sse3, "athlon64-sse3", &[_]FeatureType {
+ .Mmx,
+ .Dnowa3,
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fxsr,
+ .FastScalarShiftMasks,
+ .Nopl,
+ .Sse,
+ .Sse3,
+ .SlowShld,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Atom, "atom", &[_]FeatureType {
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fxsr,
+ .Sahf,
+ .LeaSp,
+ .LeaUsesAg,
+ .Mmx,
+ .Movbe,
+ .Nopl,
+ .PadShortFunctions,
+ .Sse,
+ .Ssse3,
+ .IdivlToDivb,
+ .IdivqToDivl,
+ .SlowTwoMemOps,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Barcelona, "barcelona", &[_]FeatureType {
+ .Mmx,
+ .Dnowa3,
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fxsr,
+ .FastScalarShiftMasks,
+ .Sahf,
+ .Lzcnt,
+ .Nopl,
+ .Popcnt,
+ .Sse,
+ .Sse4a,
+ .SlowShld,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Bdver1, "bdver1", &[_]FeatureType {
+ .Bit64,
+ .Sse,
+ .Aes,
+ .Branchfusion,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fxsr,
+ .Fast11bytenop,
+ .FastScalarShiftMasks,
+ .Sahf,
+ .Lwp,
+ .Lzcnt,
+ .Mmx,
+ .Nopl,
+ .Pclmul,
+ .Popcnt,
+ .Prfchw,
+ .SlowShld,
+ .X87,
+ .Xop,
+ .Xsave,
+ },
+ CpuInfo(@This()).create(.Bdver2, "bdver2", &[_]FeatureType {
+ .Bit64,
+ .Sse,
+ .Aes,
+ .Bmi,
+ .Branchfusion,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .F16c,
+ .Fma,
+ .Fxsr,
+ .Fast11bytenop,
+ .FastBextr,
+ .FastScalarShiftMasks,
+ .Sahf,
+ .Lwp,
+ .Lzcnt,
+ .Mmx,
+ .Nopl,
+ .Pclmul,
+ .Popcnt,
+ .Prfchw,
+ .SlowShld,
+ .Tbm,
+ .X87,
+ .Xop,
+ .Xsave,
+ },
+ CpuInfo(@This()).create(.Bdver3, "bdver3", &[_]FeatureType {
+ .Bit64,
+ .Sse,
+ .Aes,
+ .Bmi,
+ .Branchfusion,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .F16c,
+ .Fma,
+ .Fsgsbase,
+ .Fxsr,
+ .Fast11bytenop,
+ .FastBextr,
+ .FastScalarShiftMasks,
+ .Sahf,
+ .Lwp,
+ .Lzcnt,
+ .Mmx,
+ .Nopl,
+ .Pclmul,
+ .Popcnt,
+ .Prfchw,
+ .SlowShld,
+ .Tbm,
+ .X87,
+ .Xop,
+ .Xsave,
+ .Xsaveopt,
+ },
+ CpuInfo(@This()).create(.Bdver4, "bdver4", &[_]FeatureType {
+ .Bit64,
+ .Sse,
+ .Aes,
+ .Avx2,
+ .Bmi,
+ .Bmi2,
+ .Branchfusion,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .F16c,
+ .Fma,
+ .Fsgsbase,
+ .Fxsr,
+ .Fast11bytenop,
+ .FastBextr,
+ .FastScalarShiftMasks,
+ .Sahf,
+ .Lwp,
+ .Lzcnt,
+ .Mmx,
+ .Mwaitx,
+ .Nopl,
+ .Pclmul,
+ .Popcnt,
+ .Prfchw,
+ .SlowShld,
+ .Tbm,
+ .X87,
+ .Xop,
+ .Xsave,
+ .Xsaveopt,
+ },
+ CpuInfo(@This()).create(.Bonnell, "bonnell", &[_]FeatureType {
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fxsr,
+ .Sahf,
+ .LeaSp,
+ .LeaUsesAg,
+ .Mmx,
+ .Movbe,
+ .Nopl,
+ .PadShortFunctions,
+ .Sse,
+ .Ssse3,
+ .IdivlToDivb,
+ .IdivqToDivl,
+ .SlowTwoMemOps,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Broadwell, "broadwell", &[_]FeatureType {
+ .Bit64,
+ .Adx,
+ .Sse,
+ .Avx,
+ .Avx2,
+ .Bmi,
+ .Bmi2,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Ermsb,
+ .F16c,
+ .Fma,
+ .Fsgsbase,
+ .Fxsr,
+ .FastShldRotate,
+ .FastScalarFsqrt,
+ .FastVariableShuffle,
+ .Invpcid,
+ .Sahf,
+ .Lzcnt,
+ .FalseDepsLzcntTzcnt,
+ .Mmx,
+ .Movbe,
+ .Macrofusion,
+ .MergeToThreewayBranch,
+ .Nopl,
+ .Pclmul,
+ .Popcnt,
+ .FalseDepsPopcnt,
+ .Prfchw,
+ .Rdrnd,
+ .Rdseed,
+ .Sse42,
+ .Slow3opsLea,
+ .IdivqToDivl,
+ .X87,
+ .Xsave,
+ .Xsaveopt,
+ },
+ CpuInfo(@This()).create(.Btver1, "btver1", &[_]FeatureType {
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fxsr,
+ .Fast15bytenop,
+ .FastScalarShiftMasks,
+ .FastVectorShiftMasks,
+ .Sahf,
+ .Lzcnt,
+ .Mmx,
+ .Nopl,
+ .Popcnt,
+ .Prfchw,
+ .Sse,
+ .Sse4a,
+ .Ssse3,
+ .SlowShld,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Btver2, "btver2", &[_]FeatureType {
+ .Bit64,
+ .Sse,
+ .Aes,
+ .Avx,
+ .Bmi,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .F16c,
+ .Fxsr,
+ .Fast15bytenop,
+ .FastBextr,
+ .FastHops,
+ .FastLzcnt,
+ .FastPartialYmmOrZmmWrite,
+ .FastScalarShiftMasks,
+ .FastVectorShiftMasks,
+ .Sahf,
+ .Lzcnt,
+ .Mmx,
+ .Movbe,
+ .Nopl,
+ .Pclmul,
+ .Popcnt,
+ .Prfchw,
+ .Sse4a,
+ .Ssse3,
+ .SlowShld,
+ .X87,
+ .Xsave,
+ .Xsaveopt,
+ },
+ CpuInfo(@This()).create(.C3, "c3", &[_]FeatureType {
+ .Mmx,
+ .Dnow3,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.C32, "c3-2", &[_]FeatureType {
+ .Cmov,
+ .Cx8,
+ .Fxsr,
+ .Mmx,
+ .Sse,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Cannonlake, "cannonlake", &[_]FeatureType {
+ .Bit64,
+ .Adx,
+ .Sse,
+ .Aes,
+ .Avx,
+ .Avx2,
+ .Avx512f,
+ .Bmi,
+ .Bmi2,
+ .Avx512bw,
+ .Avx512cd,
+ .Clflushopt,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Avx512dq,
+ .Ermsb,
+ .F16c,
+ .Fma,
+ .Fsgsbase,
+ .Fxsr,
+ .FastShldRotate,
+ .FastScalarFsqrt,
+ .FastVariableShuffle,
+ .FastVectorFsqrt,
+ .FastGather,
+ .Avx512ifma,
+ .Invpcid,
+ .Sahf,
+ .Lzcnt,
+ .Mmx,
+ .Movbe,
+ .Macrofusion,
+ .MergeToThreewayBranch,
+ .Nopl,
+ .Pclmul,
+ .Pku,
+ .Popcnt,
+ .Prfchw,
+ .Prefer256Bit,
+ .Rdrnd,
+ .Rdseed,
+ .Sgx,
+ .Sha,
+ .Sse42,
+ .Slow3opsLea,
+ .IdivqToDivl,
+ .Avx512vbmi,
+ .Avx512vl,
+ .X87,
+ .Xsave,
+ .Xsavec,
+ .Xsaveopt,
+ .Xsaves,
+ },
+ CpuInfo(@This()).create(.Cascadelake, "cascadelake", &[_]FeatureType {
+ .Bit64,
+ .Adx,
+ .Sse,
+ .Aes,
+ .Avx,
+ .Avx2,
+ .Avx512f,
+ .Bmi,
+ .Bmi2,
+ .Avx512bw,
+ .Avx512cd,
+ .Clflushopt,
+ .Clwb,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Avx512dq,
+ .Ermsb,
+ .F16c,
+ .Fma,
+ .Fsgsbase,
+ .Fxsr,
+ .FastShldRotate,
+ .FastScalarFsqrt,
+ .FastVariableShuffle,
+ .FastVectorFsqrt,
+ .FastGather,
+ .Invpcid,
+ .Sahf,
+ .Lzcnt,
+ .Mmx,
+ .Movbe,
+ .Macrofusion,
+ .MergeToThreewayBranch,
+ .Nopl,
+ .Pclmul,
+ .Pku,
+ .Popcnt,
+ .FalseDepsPopcnt,
+ .Prfchw,
+ .Prefer256Bit,
+ .Rdrnd,
+ .Rdseed,
+ .Sse42,
+ .Slow3opsLea,
+ .IdivqToDivl,
+ .Avx512vl,
+ .Avx512vnni,
+ .X87,
+ .Xsave,
+ .Xsavec,
+ .Xsaveopt,
+ .Xsaves,
+ },
+ CpuInfo(@This()).create(.Cooperlake, "cooperlake", &[_]FeatureType {
+ .Bit64,
+ .Adx,
+ .Sse,
+ .Aes,
+ .Avx,
+ .Avx2,
+ .Avx512f,
+ .Avx512bf16,
+ .Bmi,
+ .Bmi2,
+ .Avx512bw,
+ .Avx512cd,
+ .Clflushopt,
+ .Clwb,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Avx512dq,
+ .Ermsb,
+ .F16c,
+ .Fma,
+ .Fsgsbase,
+ .Fxsr,
+ .FastShldRotate,
+ .FastScalarFsqrt,
+ .FastVariableShuffle,
+ .FastVectorFsqrt,
+ .FastGather,
+ .Invpcid,
+ .Sahf,
+ .Lzcnt,
+ .Mmx,
+ .Movbe,
+ .Macrofusion,
+ .MergeToThreewayBranch,
+ .Nopl,
+ .Pclmul,
+ .Pku,
+ .Popcnt,
+ .FalseDepsPopcnt,
+ .Prfchw,
+ .Prefer256Bit,
+ .Rdrnd,
+ .Rdseed,
+ .Sse42,
+ .Slow3opsLea,
+ .IdivqToDivl,
+ .Avx512vl,
+ .Avx512vnni,
+ .X87,
+ .Xsave,
+ .Xsavec,
+ .Xsaveopt,
+ .Xsaves,
+ },
+ CpuInfo(@This()).create(.CoreAvxI, "core-avx-i", &[_]FeatureType {
+ .Bit64,
+ .Sse,
+ .Avx,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .F16c,
+ .Fsgsbase,
+ .Fxsr,
+ .FastShldRotate,
+ .FastScalarFsqrt,
+ .Sahf,
+ .Mmx,
+ .Macrofusion,
+ .MergeToThreewayBranch,
+ .Nopl,
+ .Pclmul,
+ .Popcnt,
+ .FalseDepsPopcnt,
+ .Rdrnd,
+ .Sse42,
+ .Slow3opsLea,
+ .IdivqToDivl,
+ .SlowUnalignedMem32,
+ .X87,
+ .Xsave,
+ .Xsaveopt,
+ },
+ CpuInfo(@This()).create(.CoreAvx2, "core-avx2", &[_]FeatureType {
+ .Bit64,
+ .Sse,
+ .Avx,
+ .Avx2,
+ .Bmi,
+ .Bmi2,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Ermsb,
+ .F16c,
+ .Fma,
+ .Fsgsbase,
+ .Fxsr,
+ .FastShldRotate,
+ .FastScalarFsqrt,
+ .FastVariableShuffle,
+ .Invpcid,
+ .Sahf,
+ .Lzcnt,
+ .FalseDepsLzcntTzcnt,
+ .Mmx,
+ .Movbe,
+ .Macrofusion,
+ .MergeToThreewayBranch,
+ .Nopl,
+ .Pclmul,
+ .Popcnt,
+ .FalseDepsPopcnt,
+ .Rdrnd,
+ .Sse42,
+ .Slow3opsLea,
+ .IdivqToDivl,
+ .X87,
+ .Xsave,
+ .Xsaveopt,
+ },
+ CpuInfo(@This()).create(.Core2, "core2", &[_]FeatureType {
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fxsr,
+ .Sahf,
+ .Mmx,
+ .Macrofusion,
+ .Nopl,
+ .Sse,
+ .Ssse3,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Corei7, "corei7", &[_]FeatureType {
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fxsr,
+ .Sahf,
+ .Mmx,
+ .Macrofusion,
+ .Nopl,
+ .Popcnt,
+ .Sse,
+ .Sse42,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Corei7Avx, "corei7-avx", &[_]FeatureType {
+ .Bit64,
+ .Sse,
+ .Avx,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fxsr,
+ .FastShldRotate,
+ .FastScalarFsqrt,
+ .Sahf,
+ .Mmx,
+ .Macrofusion,
+ .MergeToThreewayBranch,
+ .Nopl,
+ .Pclmul,
+ .Popcnt,
+ .FalseDepsPopcnt,
+ .Sse42,
+ .Slow3opsLea,
+ .IdivqToDivl,
+ .SlowUnalignedMem32,
+ .X87,
+ .Xsave,
+ .Xsaveopt,
+ },
+ CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
+ .Cx8,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Geode, "geode", &[_]FeatureType {
+ .Mmx,
+ .Dnowa3,
+ .Cx8,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Goldmont, "goldmont", &[_]FeatureType {
+ .Bit64,
+ .Sse,
+ .Aes,
+ .Clflushopt,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fsgsbase,
+ .Fxsr,
+ .Sahf,
+ .Mmx,
+ .Movbe,
+ .Nopl,
+ .Pclmul,
+ .Popcnt,
+ .FalseDepsPopcnt,
+ .Prfchw,
+ .Rdrnd,
+ .Rdseed,
+ .Sha,
+ .Sse42,
+ .Ssse3,
+ .SlowIncdec,
+ .SlowLea,
+ .SlowTwoMemOps,
+ .X87,
+ .Xsave,
+ .Xsavec,
+ .Xsaveopt,
+ .Xsaves,
+ },
+ CpuInfo(@This()).create(.GoldmontPlus, "goldmont-plus", &[_]FeatureType {
+ .Bit64,
+ .Sse,
+ .Aes,
+ .Clflushopt,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fsgsbase,
+ .Fxsr,
+ .Sahf,
+ .Mmx,
+ .Movbe,
+ .Nopl,
+ .Pclmul,
+ .Popcnt,
+ .Prfchw,
+ .Ptwrite,
+ .Rdpid,
+ .Rdrnd,
+ .Rdseed,
+ .Sgx,
+ .Sha,
+ .Sse42,
+ .Ssse3,
+ .SlowIncdec,
+ .SlowLea,
+ .SlowTwoMemOps,
+ .X87,
+ .Xsave,
+ .Xsavec,
+ .Xsaveopt,
+ .Xsaves,
+ },
+ CpuInfo(@This()).create(.Haswell, "haswell", &[_]FeatureType {
+ .Bit64,
+ .Sse,
+ .Avx,
+ .Avx2,
+ .Bmi,
+ .Bmi2,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Ermsb,
+ .F16c,
+ .Fma,
+ .Fsgsbase,
+ .Fxsr,
+ .FastShldRotate,
+ .FastScalarFsqrt,
+ .FastVariableShuffle,
+ .Invpcid,
+ .Sahf,
+ .Lzcnt,
+ .FalseDepsLzcntTzcnt,
+ .Mmx,
+ .Movbe,
+ .Macrofusion,
+ .MergeToThreewayBranch,
+ .Nopl,
+ .Pclmul,
+ .Popcnt,
+ .FalseDepsPopcnt,
+ .Rdrnd,
+ .Sse42,
+ .Slow3opsLea,
+ .IdivqToDivl,
+ .X87,
+ .Xsave,
+ .Xsaveopt,
+ },
+ CpuInfo(@This()).create(.I386, "i386", &[_]FeatureType {
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.I486, "i486", &[_]FeatureType {
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.I586, "i586", &[_]FeatureType {
+ .Cx8,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.I686, "i686", &[_]FeatureType {
+ .Cmov,
+ .Cx8,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.IcelakeClient, "icelake-client", &[_]FeatureType {
+ .Bit64,
+ .Adx,
+ .Sse,
+ .Aes,
+ .Avx,
+ .Avx2,
+ .Avx512f,
+ .Avx512bitalg,
+ .Bmi,
+ .Bmi2,
+ .Avx512bw,
+ .Avx512cd,
+ .Clflushopt,
+ .Clwb,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Avx512dq,
+ .Ermsb,
+ .F16c,
+ .Fma,
+ .Fsgsbase,
+ .Fxsr,
+ .FastShldRotate,
+ .FastScalarFsqrt,
+ .FastVariableShuffle,
+ .FastVectorFsqrt,
+ .Gfni,
+ .FastGather,
+ .Avx512ifma,
+ .Invpcid,
+ .Sahf,
+ .Lzcnt,
+ .Mmx,
+ .Movbe,
+ .Macrofusion,
+ .MergeToThreewayBranch,
+ .Nopl,
+ .Pclmul,
+ .Pku,
+ .Popcnt,
+ .Prfchw,
+ .Prefer256Bit,
+ .Rdpid,
+ .Rdrnd,
+ .Rdseed,
+ .Sgx,
+ .Sha,
+ .Sse42,
+ .Slow3opsLea,
+ .IdivqToDivl,
+ .Vaes,
+ .Avx512vbmi,
+ .Avx512vbmi2,
+ .Avx512vl,
+ .Avx512vnni,
+ .Vpclmulqdq,
+ .Avx512vpopcntdq,
+ .X87,
+ .Xsave,
+ .Xsavec,
+ .Xsaveopt,
+ .Xsaves,
+ },
+ CpuInfo(@This()).create(.IcelakeServer, "icelake-server", &[_]FeatureType {
+ .Bit64,
+ .Adx,
+ .Sse,
+ .Aes,
+ .Avx,
+ .Avx2,
+ .Avx512f,
+ .Avx512bitalg,
+ .Bmi,
+ .Bmi2,
+ .Avx512bw,
+ .Avx512cd,
+ .Clflushopt,
+ .Clwb,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Avx512dq,
+ .Ermsb,
+ .F16c,
+ .Fma,
+ .Fsgsbase,
+ .Fxsr,
+ .FastShldRotate,
+ .FastScalarFsqrt,
+ .FastVariableShuffle,
+ .FastVectorFsqrt,
+ .Gfni,
+ .FastGather,
+ .Avx512ifma,
+ .Invpcid,
+ .Sahf,
+ .Lzcnt,
+ .Mmx,
+ .Movbe,
+ .Macrofusion,
+ .MergeToThreewayBranch,
+ .Nopl,
+ .Pclmul,
+ .Pconfig,
+ .Pku,
+ .Popcnt,
+ .Prfchw,
+ .Prefer256Bit,
+ .Rdpid,
+ .Rdrnd,
+ .Rdseed,
+ .Sgx,
+ .Sha,
+ .Sse42,
+ .Slow3opsLea,
+ .IdivqToDivl,
+ .Vaes,
+ .Avx512vbmi,
+ .Avx512vbmi2,
+ .Avx512vl,
+ .Avx512vnni,
+ .Vpclmulqdq,
+ .Avx512vpopcntdq,
+ .Wbnoinvd,
+ .X87,
+ .Xsave,
+ .Xsavec,
+ .Xsaveopt,
+ .Xsaves,
+ },
+ CpuInfo(@This()).create(.Ivybridge, "ivybridge", &[_]FeatureType {
+ .Bit64,
+ .Sse,
+ .Avx,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .F16c,
+ .Fsgsbase,
+ .Fxsr,
+ .FastShldRotate,
+ .FastScalarFsqrt,
+ .Sahf,
+ .Mmx,
+ .Macrofusion,
+ .MergeToThreewayBranch,
+ .Nopl,
+ .Pclmul,
+ .Popcnt,
+ .FalseDepsPopcnt,
+ .Rdrnd,
+ .Sse42,
+ .Slow3opsLea,
+ .IdivqToDivl,
+ .SlowUnalignedMem32,
+ .X87,
+ .Xsave,
+ .Xsaveopt,
+ },
+ CpuInfo(@This()).create(.K6, "k6", &[_]FeatureType {
+ .Cx8,
+ .Mmx,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.K62, "k6-2", &[_]FeatureType {
+ .Mmx,
+ .Dnow3,
+ .Cx8,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.K63, "k6-3", &[_]FeatureType {
+ .Mmx,
+ .Dnow3,
+ .Cx8,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.K8, "k8", &[_]FeatureType {
+ .Mmx,
+ .Dnowa3,
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Fxsr,
+ .FastScalarShiftMasks,
+ .Nopl,
+ .Sse,
+ .Sse2,
+ .SlowShld,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.K8Sse3, "k8-sse3", &[_]FeatureType {
+ .Mmx,
+ .Dnowa3,
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fxsr,
+ .FastScalarShiftMasks,
+ .Nopl,
+ .Sse,
+ .Sse3,
+ .SlowShld,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Knl, "knl", &[_]FeatureType {
+ .Bit64,
+ .Adx,
+ .Sse,
+ .Aes,
+ .Avx512f,
+ .Bmi,
+ .Bmi2,
+ .Avx512cd,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Avx512er,
+ .F16c,
+ .Fma,
+ .Fsgsbase,
+ .Fxsr,
+ .FastPartialYmmOrZmmWrite,
+ .FastGather,
+ .Sahf,
+ .Lzcnt,
+ .Mmx,
+ .Movbe,
+ .Nopl,
+ .Pclmul,
+ .Avx512pf,
+ .Popcnt,
+ .Prefetchwt1,
+ .Prfchw,
+ .Rdrnd,
+ .Rdseed,
+ .Slow3opsLea,
+ .IdivqToDivl,
+ .SlowIncdec,
+ .SlowPmaddwd,
+ .SlowTwoMemOps,
+ .X87,
+ .Xsave,
+ .Xsaveopt,
+ },
+ CpuInfo(@This()).create(.Knm, "knm", &[_]FeatureType {
+ .Bit64,
+ .Adx,
+ .Sse,
+ .Aes,
+ .Avx512f,
+ .Bmi,
+ .Bmi2,
+ .Avx512cd,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Avx512er,
+ .F16c,
+ .Fma,
+ .Fsgsbase,
+ .Fxsr,
+ .FastPartialYmmOrZmmWrite,
+ .FastGather,
+ .Sahf,
+ .Lzcnt,
+ .Mmx,
+ .Movbe,
+ .Nopl,
+ .Pclmul,
+ .Avx512pf,
+ .Popcnt,
+ .Prefetchwt1,
+ .Prfchw,
+ .Rdrnd,
+ .Rdseed,
+ .Slow3opsLea,
+ .IdivqToDivl,
+ .SlowIncdec,
+ .SlowPmaddwd,
+ .SlowTwoMemOps,
+ .Avx512vpopcntdq,
+ .X87,
+ .Xsave,
+ .Xsaveopt,
+ },
+ CpuInfo(@This()).create(.Lakemont, "lakemont", &[_]FeatureType {
+ },
+ CpuInfo(@This()).create(.Nehalem, "nehalem", &[_]FeatureType {
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fxsr,
+ .Sahf,
+ .Mmx,
+ .Macrofusion,
+ .Nopl,
+ .Popcnt,
+ .Sse,
+ .Sse42,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Nocona, "nocona", &[_]FeatureType {
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fxsr,
+ .Mmx,
+ .Nopl,
+ .Sse,
+ .Sse3,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Opteron, "opteron", &[_]FeatureType {
+ .Mmx,
+ .Dnowa3,
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Fxsr,
+ .FastScalarShiftMasks,
+ .Nopl,
+ .Sse,
+ .Sse2,
+ .SlowShld,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.OpteronSse3, "opteron-sse3", &[_]FeatureType {
+ .Mmx,
+ .Dnowa3,
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fxsr,
+ .FastScalarShiftMasks,
+ .Nopl,
+ .Sse,
+ .Sse3,
+ .SlowShld,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Penryn, "penryn", &[_]FeatureType {
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fxsr,
+ .Sahf,
+ .Mmx,
+ .Macrofusion,
+ .Nopl,
+ .Sse,
+ .Sse41,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Pentium, "pentium", &[_]FeatureType {
+ .Cx8,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.PentiumM, "pentium-m", &[_]FeatureType {
+ .Cmov,
+ .Cx8,
+ .Fxsr,
+ .Mmx,
+ .Nopl,
+ .Sse,
+ .Sse2,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.PentiumMmx, "pentium-mmx", &[_]FeatureType {
+ .Cx8,
+ .Mmx,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Pentium2, "pentium2", &[_]FeatureType {
+ .Cmov,
+ .Cx8,
+ .Fxsr,
+ .Mmx,
+ .Nopl,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Pentium3, "pentium3", &[_]FeatureType {
+ .Cmov,
+ .Cx8,
+ .Fxsr,
+ .Mmx,
+ .Nopl,
+ .Sse,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Pentium3m, "pentium3m", &[_]FeatureType {
+ .Cmov,
+ .Cx8,
+ .Fxsr,
+ .Mmx,
+ .Nopl,
+ .Sse,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Pentium4, "pentium4", &[_]FeatureType {
+ .Cmov,
+ .Cx8,
+ .Fxsr,
+ .Mmx,
+ .Nopl,
+ .Sse,
+ .Sse2,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Pentium4m, "pentium4m", &[_]FeatureType {
+ .Cmov,
+ .Cx8,
+ .Fxsr,
+ .Mmx,
+ .Nopl,
+ .Sse,
+ .Sse2,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Pentiumpro, "pentiumpro", &[_]FeatureType {
+ .Cmov,
+ .Cx8,
+ .Nopl,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Prescott, "prescott", &[_]FeatureType {
+ .Cmov,
+ .Cx8,
+ .Fxsr,
+ .Mmx,
+ .Nopl,
+ .Sse,
+ .Sse3,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Sandybridge, "sandybridge", &[_]FeatureType {
+ .Bit64,
+ .Sse,
+ .Avx,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fxsr,
+ .FastShldRotate,
+ .FastScalarFsqrt,
+ .Sahf,
+ .Mmx,
+ .Macrofusion,
+ .MergeToThreewayBranch,
+ .Nopl,
+ .Pclmul,
+ .Popcnt,
+ .FalseDepsPopcnt,
+ .Sse42,
+ .Slow3opsLea,
+ .IdivqToDivl,
+ .SlowUnalignedMem32,
+ .X87,
+ .Xsave,
+ .Xsaveopt,
+ },
+ CpuInfo(@This()).create(.Silvermont, "silvermont", &[_]FeatureType {
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fxsr,
+ .Sahf,
+ .Mmx,
+ .Movbe,
+ .Nopl,
+ .Sse,
+ .Pclmul,
+ .Popcnt,
+ .FalseDepsPopcnt,
+ .Prfchw,
+ .Rdrnd,
+ .Sse42,
+ .Ssse3,
+ .IdivqToDivl,
+ .SlowIncdec,
+ .SlowLea,
+ .SlowPmulld,
+ .SlowTwoMemOps,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Skx, "skx", &[_]FeatureType {
+ .Bit64,
+ .Adx,
+ .Sse,
+ .Aes,
+ .Avx,
+ .Avx2,
+ .Avx512f,
+ .Bmi,
+ .Bmi2,
+ .Avx512bw,
+ .Avx512cd,
+ .Clflushopt,
+ .Clwb,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Avx512dq,
+ .Ermsb,
+ .F16c,
+ .Fma,
+ .Fsgsbase,
+ .Fxsr,
+ .FastShldRotate,
+ .FastScalarFsqrt,
+ .FastVariableShuffle,
+ .FastVectorFsqrt,
+ .FastGather,
+ .Invpcid,
+ .Sahf,
+ .Lzcnt,
+ .Mmx,
+ .Movbe,
+ .Macrofusion,
+ .MergeToThreewayBranch,
+ .Nopl,
+ .Pclmul,
+ .Pku,
+ .Popcnt,
+ .FalseDepsPopcnt,
+ .Prfchw,
+ .Prefer256Bit,
+ .Rdrnd,
+ .Rdseed,
+ .Sse42,
+ .Slow3opsLea,
+ .IdivqToDivl,
+ .Avx512vl,
+ .X87,
+ .Xsave,
+ .Xsavec,
+ .Xsaveopt,
+ .Xsaves,
+ },
+ CpuInfo(@This()).create(.Skylake, "skylake", &[_]FeatureType {
+ .Bit64,
+ .Adx,
+ .Sse,
+ .Aes,
+ .Avx,
+ .Avx2,
+ .Bmi,
+ .Bmi2,
+ .Clflushopt,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Ermsb,
+ .F16c,
+ .Fma,
+ .Fsgsbase,
+ .Fxsr,
+ .FastShldRotate,
+ .FastScalarFsqrt,
+ .FastVariableShuffle,
+ .FastVectorFsqrt,
+ .FastGather,
+ .Invpcid,
+ .Sahf,
+ .Lzcnt,
+ .Mmx,
+ .Movbe,
+ .Macrofusion,
+ .MergeToThreewayBranch,
+ .Nopl,
+ .Pclmul,
+ .Popcnt,
+ .FalseDepsPopcnt,
+ .Prfchw,
+ .Rdrnd,
+ .Rdseed,
+ .Sgx,
+ .Sse42,
+ .Slow3opsLea,
+ .IdivqToDivl,
+ .X87,
+ .Xsave,
+ .Xsavec,
+ .Xsaveopt,
+ .Xsaves,
+ },
+ CpuInfo(@This()).create(.SkylakeAvx512, "skylake-avx512", &[_]FeatureType {
+ .Bit64,
+ .Adx,
+ .Sse,
+ .Aes,
+ .Avx,
+ .Avx2,
+ .Avx512f,
+ .Bmi,
+ .Bmi2,
+ .Avx512bw,
+ .Avx512cd,
+ .Clflushopt,
+ .Clwb,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Avx512dq,
+ .Ermsb,
+ .F16c,
+ .Fma,
+ .Fsgsbase,
+ .Fxsr,
+ .FastShldRotate,
+ .FastScalarFsqrt,
+ .FastVariableShuffle,
+ .FastVectorFsqrt,
+ .FastGather,
+ .Invpcid,
+ .Sahf,
+ .Lzcnt,
+ .Mmx,
+ .Movbe,
+ .Macrofusion,
+ .MergeToThreewayBranch,
+ .Nopl,
+ .Pclmul,
+ .Pku,
+ .Popcnt,
+ .FalseDepsPopcnt,
+ .Prfchw,
+ .Prefer256Bit,
+ .Rdrnd,
+ .Rdseed,
+ .Sse42,
+ .Slow3opsLea,
+ .IdivqToDivl,
+ .Avx512vl,
+ .X87,
+ .Xsave,
+ .Xsavec,
+ .Xsaveopt,
+ .Xsaves,
+ },
+ CpuInfo(@This()).create(.Slm, "slm", &[_]FeatureType {
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fxsr,
+ .Sahf,
+ .Mmx,
+ .Movbe,
+ .Nopl,
+ .Sse,
+ .Pclmul,
+ .Popcnt,
+ .FalseDepsPopcnt,
+ .Prfchw,
+ .Rdrnd,
+ .Sse42,
+ .Ssse3,
+ .IdivqToDivl,
+ .SlowIncdec,
+ .SlowLea,
+ .SlowPmulld,
+ .SlowTwoMemOps,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Tigerlake, "tigerlake", &[_]FeatureType {
+ .Bit64,
+ .Adx,
+ .Sse,
+ .Aes,
+ .Avx,
+ .Avx2,
+ .Avx512f,
+ .Avx512bitalg,
+ .Bmi,
+ .Bmi2,
+ .Avx512bw,
+ .Avx512cd,
+ .Clflushopt,
+ .Clwb,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Avx512dq,
+ .Ermsb,
+ .F16c,
+ .Fma,
+ .Fsgsbase,
+ .Fxsr,
+ .FastShldRotate,
+ .FastScalarFsqrt,
+ .FastVariableShuffle,
+ .FastVectorFsqrt,
+ .Gfni,
+ .FastGather,
+ .Avx512ifma,
+ .Invpcid,
+ .Sahf,
+ .Lzcnt,
+ .Mmx,
+ .Movbe,
+ .Movdir64b,
+ .Movdiri,
+ .Macrofusion,
+ .MergeToThreewayBranch,
+ .Nopl,
+ .Pclmul,
+ .Pku,
+ .Popcnt,
+ .Prfchw,
+ .Prefer256Bit,
+ .Rdpid,
+ .Rdrnd,
+ .Rdseed,
+ .Sgx,
+ .Sha,
+ .Shstk,
+ .Sse42,
+ .Slow3opsLea,
+ .IdivqToDivl,
+ .Vaes,
+ .Avx512vbmi,
+ .Avx512vbmi2,
+ .Avx512vl,
+ .Avx512vnni,
+ .Avx512vp2intersect,
+ .Vpclmulqdq,
+ .Avx512vpopcntdq,
+ .X87,
+ .Xsave,
+ .Xsavec,
+ .Xsaveopt,
+ .Xsaves,
+ },
+ CpuInfo(@This()).create(.Tremont, "tremont", &[_]FeatureType {
+ .Bit64,
+ .Sse,
+ .Aes,
+ .Cldemote,
+ .Clflushopt,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fsgsbase,
+ .Fxsr,
+ .Gfni,
+ .Sahf,
+ .Mmx,
+ .Movbe,
+ .Movdir64b,
+ .Movdiri,
+ .Nopl,
+ .Pclmul,
+ .Popcnt,
+ .Prfchw,
+ .Ptwrite,
+ .Rdpid,
+ .Rdrnd,
+ .Rdseed,
+ .Sgx,
+ .Sha,
+ .Sse42,
+ .Ssse3,
+ .SlowIncdec,
+ .SlowLea,
+ .SlowTwoMemOps,
+ .Waitpkg,
+ .X87,
+ .Xsave,
+ .Xsavec,
+ .Xsaveopt,
+ .Xsaves,
+ },
+ CpuInfo(@This()).create(.Westmere, "westmere", &[_]FeatureType {
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .Fxsr,
+ .Sahf,
+ .Mmx,
+ .Macrofusion,
+ .Nopl,
+ .Sse,
+ .Pclmul,
+ .Popcnt,
+ .Sse42,
+ .X87,
+ },
+ CpuInfo(@This()).create(.WinchipC6, "winchip-c6", &[_]FeatureType {
+ .Mmx,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Winchip2, "winchip2", &[_]FeatureType {
+ .Mmx,
+ .Dnow3,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.X8664, "x86-64", &[_]FeatureType {
+ .Bit64,
+ .Cmov,
+ .Cx8,
+ .Fxsr,
+ .Mmx,
+ .Macrofusion,
+ .Nopl,
+ .Sse,
+ .Sse2,
+ .Slow3opsLea,
+ .SlowIncdec,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Yonah, "yonah", &[_]FeatureType {
+ .Cmov,
+ .Cx8,
+ .Fxsr,
+ .Mmx,
+ .Nopl,
+ .Sse,
+ .Sse3,
+ .SlowUnalignedMem16,
+ .X87,
+ },
+ CpuInfo(@This()).create(.Znver1, "znver1", &[_]FeatureType {
+ .Bit64,
+ .Adx,
+ .Sse,
+ .Aes,
+ .Avx2,
+ .Bmi,
+ .Bmi2,
+ .Branchfusion,
+ .Clflushopt,
+ .Clzero,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .F16c,
+ .Fma,
+ .Fsgsbase,
+ .Fxsr,
+ .Fast15bytenop,
+ .FastBextr,
+ .FastLzcnt,
+ .FastScalarShiftMasks,
+ .Sahf,
+ .Lzcnt,
+ .Mmx,
+ .Movbe,
+ .Mwaitx,
+ .Nopl,
+ .Pclmul,
+ .Popcnt,
+ .Prfchw,
+ .Rdrnd,
+ .Rdseed,
+ .Sha,
+ .Sse4a,
+ .SlowShld,
+ .X87,
+ .Xsave,
+ .Xsavec,
+ .Xsaveopt,
+ .Xsaves,
+ },
+ CpuInfo(@This()).create(.Znver2, "znver2", &[_]FeatureType {
+ .Bit64,
+ .Adx,
+ .Sse,
+ .Aes,
+ .Avx2,
+ .Bmi,
+ .Bmi2,
+ .Branchfusion,
+ .Clflushopt,
+ .Clwb,
+ .Clzero,
+ .Cmov,
+ .Cx8,
+ .Cx16,
+ .F16c,
+ .Fma,
+ .Fsgsbase,
+ .Fxsr,
+ .Fast15bytenop,
+ .FastBextr,
+ .FastLzcnt,
+ .FastScalarShiftMasks,
+ .Sahf,
+ .Lzcnt,
+ .Mmx,
+ .Movbe,
+ .Mwaitx,
+ .Nopl,
+ .Pclmul,
+ .Popcnt,
+ .Prfchw,
+ .Rdpid,
+ .Rdrnd,
+ .Rdseed,
+ .Sha,
+ .Sse4a,
+ .SlowShld,
+ .Wbnoinvd,
+ .X87,
+ .Xsave,
+ .Xsavec,
+ .Xsaveopt,
+ .Xsaves,
+ },
+ };
+};
lib/std/target/feature/AArch64Feature.zig
@@ -0,0 +1,750 @@
+const FeatureInfo = @import("std").target.feature.FeatureInfo;
+
+pub const AArch64Feature = enum {
+ Aes,
+ Am,
+ AggressiveFma,
+ Altnzcv,
+ AlternateSextloadCvtF32Pattern,
+ ArithBccFusion,
+ ArithCbzFusion,
+ BalanceFpOps,
+ Bti,
+ Ccidx,
+ Ccpp,
+ Crc,
+ Ccdp,
+ CallSavedX8,
+ CallSavedX9,
+ CallSavedX10,
+ CallSavedX11,
+ CallSavedX12,
+ CallSavedX13,
+ CallSavedX14,
+ CallSavedX15,
+ CallSavedX18,
+ Complxnum,
+ Crypto,
+ CustomCheapAsMove,
+ Dit,
+ DisableLatencySchedHeuristic,
+ Dotprod,
+ Ete,
+ ExynosCheapAsMove,
+ Fmi,
+ Fp16fml,
+ FpArmv8,
+ Fptoint,
+ Force32bitJumpTables,
+ Fullfp16,
+ FuseAes,
+ FuseAddress,
+ FuseArithLogic,
+ FuseCsel,
+ FuseCryptoEor,
+ FuseLiterals,
+ Jsconv,
+ Lor,
+ Lse,
+ LslFast,
+ Mpam,
+ Mte,
+ Neon,
+ Nv,
+ NoNegImmediates,
+ Pa,
+ Pan,
+ PanRwv,
+ Perfmon,
+ UsePostraScheduler,
+ Predres,
+ PredictableSelectExpensive,
+ Uaops,
+ Ras,
+ Rasv8_4,
+ Rcpc,
+ RcpcImmo,
+ Rdm,
+ Rand,
+ ReserveX1,
+ ReserveX2,
+ ReserveX3,
+ ReserveX4,
+ ReserveX5,
+ ReserveX6,
+ ReserveX7,
+ ReserveX9,
+ ReserveX10,
+ ReserveX11,
+ ReserveX12,
+ ReserveX13,
+ ReserveX14,
+ ReserveX15,
+ ReserveX18,
+ ReserveX20,
+ ReserveX21,
+ ReserveX22,
+ ReserveX23,
+ ReserveX24,
+ ReserveX25,
+ ReserveX26,
+ ReserveX27,
+ ReserveX28,
+ Sb,
+ Sel2,
+ Sha2,
+ Sha3,
+ Sm4,
+ Spe,
+ Ssbs,
+ Sve,
+ Sve2,
+ Sve2Aes,
+ Sve2Bitperm,
+ Sve2Sha3,
+ Sve2Sm4,
+ SlowMisaligned128store,
+ SlowPaired128,
+ SlowStrqroStore,
+ Specrestrict,
+ StrictAlign,
+ TlbRmi,
+ Tme,
+ Tracev84,
+ Trbe,
+ TaggedGlobals,
+ UseAa,
+ TpidrEl1,
+ TpidrEl2,
+ TpidrEl3,
+ UseReciprocalSquareRoot,
+ Vh,
+ Zcm,
+ Zcz,
+ ZczFp,
+ ZczFpWorkaround,
+ ZczGp,
+ V81a,
+ V82a,
+ V83a,
+ V84a,
+ V85a,
+ A35,
+ A53,
+ A55,
+ A57,
+ A65,
+ A72,
+ A73,
+ A75,
+ A76,
+ Cyclone,
+ Exynosm1,
+ Exynosm2,
+ Exynosm3,
+ Exynosm4,
+ Falkor,
+ Kryo,
+ Neoversee1,
+ Neoversen1,
+ Saphira,
+ Tsv110,
+ Thunderx,
+ Thunderx2t99,
+ Thunderxt81,
+ Thunderxt83,
+ Thunderxt88,
+
+ pub fn getInfo(self: @This()) FeatureInfo {
+ return feature_infos[@enumToInt(self)];
+ }
+
+ pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
+ FeatureInfo(@This()).createWithSubfeatures(.Aes, "aes", "Enable AES support", "aes", &[_]@This() {
+ .FpArmv8,
+ }),
+ FeatureInfo(@This()).create(.Am, "am", "Enable v8.4-A Activity Monitors extension", "am"),
+ FeatureInfo(@This()).create(.AggressiveFma, "aggressive-fma", "Enable Aggressive FMA for floating-point.", "aggressive-fma"),
+ FeatureInfo(@This()).create(.Altnzcv, "altnzcv", "Enable alternative NZCV format for floating point comparisons", "altnzcv"),
+ FeatureInfo(@This()).create(.AlternateSextloadCvtF32Pattern, "alternate-sextload-cvt-f32-pattern", "Use alternative pattern for sextload convert to f32", "alternate-sextload-cvt-f32-pattern"),
+ FeatureInfo(@This()).create(.ArithBccFusion, "arith-bcc-fusion", "CPU fuses arithmetic+bcc operations", "arith-bcc-fusion"),
+ FeatureInfo(@This()).create(.ArithCbzFusion, "arith-cbz-fusion", "CPU fuses arithmetic + cbz/cbnz operations", "arith-cbz-fusion"),
+ FeatureInfo(@This()).create(.BalanceFpOps, "balance-fp-ops", "balance mix of odd and even D-registers for fp multiply(-accumulate) ops", "balance-fp-ops"),
+ FeatureInfo(@This()).create(.Bti, "bti", "Enable Branch Target Identification", "bti"),
+ FeatureInfo(@This()).create(.Ccidx, "ccidx", "Enable v8.3-A Extend of the CCSIDR number of sets", "ccidx"),
+ FeatureInfo(@This()).create(.Ccpp, "ccpp", "Enable v8.2 data Cache Clean to Point of Persistence", "ccpp"),
+ FeatureInfo(@This()).create(.Crc, "crc", "Enable ARMv8 CRC-32 checksum instructions", "crc"),
+ FeatureInfo(@This()).create(.Ccdp, "ccdp", "Enable v8.5 Cache Clean to Point of Deep Persistence", "ccdp"),
+ FeatureInfo(@This()).create(.CallSavedX8, "call-saved-x8", "Make X8 callee saved.", "call-saved-x8"),
+ FeatureInfo(@This()).create(.CallSavedX9, "call-saved-x9", "Make X9 callee saved.", "call-saved-x9"),
+ FeatureInfo(@This()).create(.CallSavedX10, "call-saved-x10", "Make X10 callee saved.", "call-saved-x10"),
+ FeatureInfo(@This()).create(.CallSavedX11, "call-saved-x11", "Make X11 callee saved.", "call-saved-x11"),
+ FeatureInfo(@This()).create(.CallSavedX12, "call-saved-x12", "Make X12 callee saved.", "call-saved-x12"),
+ FeatureInfo(@This()).create(.CallSavedX13, "call-saved-x13", "Make X13 callee saved.", "call-saved-x13"),
+ FeatureInfo(@This()).create(.CallSavedX14, "call-saved-x14", "Make X14 callee saved.", "call-saved-x14"),
+ FeatureInfo(@This()).create(.CallSavedX15, "call-saved-x15", "Make X15 callee saved.", "call-saved-x15"),
+ FeatureInfo(@This()).create(.CallSavedX18, "call-saved-x18", "Make X18 callee saved.", "call-saved-x18"),
+ FeatureInfo(@This()).createWithSubfeatures(.Complxnum, "complxnum", "Enable v8.3-A Floating-point complex number support", "complxnum", &[_]@This() {
+ .FpArmv8,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Crypto, "crypto", "Enable cryptographic instructions", "crypto", &[_]@This() {
+ .FpArmv8,
+ }),
+ FeatureInfo(@This()).create(.CustomCheapAsMove, "custom-cheap-as-move", "Use custom handling of cheap instructions", "custom-cheap-as-move"),
+ FeatureInfo(@This()).create(.Dit, "dit", "Enable v8.4-A Data Independent Timing instructions", "dit"),
+ FeatureInfo(@This()).create(.DisableLatencySchedHeuristic, "disable-latency-sched-heuristic", "Disable latency scheduling heuristic", "disable-latency-sched-heuristic"),
+ FeatureInfo(@This()).create(.Dotprod, "dotprod", "Enable dot product support", "dotprod"),
+ FeatureInfo(@This()).createWithSubfeatures(.Ete, "ete", "Enable Embedded Trace Extension", "ete", &[_]@This() {
+ .Trbe,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.ExynosCheapAsMove, "exynos-cheap-as-move", "Use Exynos specific handling of cheap instructions", "exynos-cheap-as-move", &[_]@This() {
+ .CustomCheapAsMove,
+ }),
+ FeatureInfo(@This()).create(.Fmi, "fmi", "Enable v8.4-A Flag Manipulation Instructions", "fmi"),
+ FeatureInfo(@This()).createWithSubfeatures(.Fp16fml, "fp16fml", "Enable FP16 FML instructions", "fp16fml", &[_]@This() {
+ .FpArmv8,
+ }),
+ FeatureInfo(@This()).create(.FpArmv8, "fp-armv8", "Enable ARMv8 FP", "fp-armv8"),
+ FeatureInfo(@This()).create(.Fptoint, "fptoint", "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int", "fptoint"),
+ FeatureInfo(@This()).create(.Force32bitJumpTables, "force-32bit-jump-tables", "Force jump table entries to be 32-bits wide except at MinSize", "force-32bit-jump-tables"),
+ FeatureInfo(@This()).createWithSubfeatures(.Fullfp16, "fullfp16", "Full FP16", "fullfp16", &[_]@This() {
+ .FpArmv8,
+ }),
+ FeatureInfo(@This()).create(.FuseAes, "fuse-aes", "CPU fuses AES crypto operations", "fuse-aes"),
+ FeatureInfo(@This()).create(.FuseAddress, "fuse-address", "CPU fuses address generation and memory operations", "fuse-address"),
+ FeatureInfo(@This()).create(.FuseArithLogic, "fuse-arith-logic", "CPU fuses arithmetic and logic operations", "fuse-arith-logic"),
+ FeatureInfo(@This()).create(.FuseCsel, "fuse-csel", "CPU fuses conditional select operations", "fuse-csel"),
+ FeatureInfo(@This()).create(.FuseCryptoEor, "fuse-crypto-eor", "CPU fuses AES/PMULL and EOR operations", "fuse-crypto-eor"),
+ FeatureInfo(@This()).create(.FuseLiterals, "fuse-literals", "CPU fuses literal generation operations", "fuse-literals"),
+ FeatureInfo(@This()).createWithSubfeatures(.Jsconv, "jsconv", "Enable v8.3-A JavaScript FP conversion enchancement", "jsconv", &[_]@This() {
+ .FpArmv8,
+ }),
+ FeatureInfo(@This()).create(.Lor, "lor", "Enables ARM v8.1 Limited Ordering Regions extension", "lor"),
+ FeatureInfo(@This()).create(.Lse, "lse", "Enable ARMv8.1 Large System Extension (LSE) atomic instructions", "lse"),
+ FeatureInfo(@This()).create(.LslFast, "lsl-fast", "CPU has a fastpath logical shift of up to 3 places", "lsl-fast"),
+ FeatureInfo(@This()).create(.Mpam, "mpam", "Enable v8.4-A Memory system Partitioning and Monitoring extension", "mpam"),
+ FeatureInfo(@This()).create(.Mte, "mte", "Enable Memory Tagging Extension", "mte"),
+ FeatureInfo(@This()).createWithSubfeatures(.Neon, "neon", "Enable Advanced SIMD instructions", "neon", &[_]@This() {
+ .FpArmv8,
+ }),
+ FeatureInfo(@This()).create(.Nv, "nv", "Enable v8.4-A Nested Virtualization Enchancement", "nv"),
+ FeatureInfo(@This()).create(.NoNegImmediates, "no-neg-immediates", "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.", "no-neg-immediates"),
+ FeatureInfo(@This()).create(.Pa, "pa", "Enable v8.3-A Pointer Authentication enchancement", "pa"),
+ FeatureInfo(@This()).create(.Pan, "pan", "Enables ARM v8.1 Privileged Access-Never extension", "pan"),
+ FeatureInfo(@This()).createWithSubfeatures(.PanRwv, "pan-rwv", "Enable v8.2 PAN s1e1R and s1e1W Variants", "pan-rwv", &[_]@This() {
+ .Pan,
+ }),
+ FeatureInfo(@This()).create(.Perfmon, "perfmon", "Enable ARMv8 PMUv3 Performance Monitors extension", "perfmon"),
+ FeatureInfo(@This()).create(.UsePostraScheduler, "use-postra-scheduler", "Schedule again after register allocation", "use-postra-scheduler"),
+ FeatureInfo(@This()).create(.Predres, "predres", "Enable v8.5a execution and data prediction invalidation instructions", "predres"),
+ FeatureInfo(@This()).create(.PredictableSelectExpensive, "predictable-select-expensive", "Prefer likely predicted branches over selects", "predictable-select-expensive"),
+ FeatureInfo(@This()).create(.Uaops, "uaops", "Enable v8.2 UAO PState", "uaops"),
+ FeatureInfo(@This()).create(.Ras, "ras", "Enable ARMv8 Reliability, Availability and Serviceability Extensions", "ras"),
+ FeatureInfo(@This()).createWithSubfeatures(.Rasv8_4, "rasv8_4", "Enable v8.4-A Reliability, Availability and Serviceability extension", "rasv8_4", &[_]@This() {
+ .Ras,
+ }),
+ FeatureInfo(@This()).create(.Rcpc, "rcpc", "Enable support for RCPC extension", "rcpc"),
+ FeatureInfo(@This()).createWithSubfeatures(.RcpcImmo, "rcpc-immo", "Enable v8.4-A RCPC instructions with Immediate Offsets", "rcpc-immo", &[_]@This() {
+ .Rcpc,
+ }),
+ FeatureInfo(@This()).create(.Rdm, "rdm", "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions", "rdm"),
+ FeatureInfo(@This()).create(.Rand, "rand", "Enable Random Number generation instructions", "rand"),
+ FeatureInfo(@This()).create(.ReserveX1, "reserve-x1", "Reserve X1, making it unavailable as a GPR", "reserve-x1"),
+ FeatureInfo(@This()).create(.ReserveX2, "reserve-x2", "Reserve X2, making it unavailable as a GPR", "reserve-x2"),
+ FeatureInfo(@This()).create(.ReserveX3, "reserve-x3", "Reserve X3, making it unavailable as a GPR", "reserve-x3"),
+ FeatureInfo(@This()).create(.ReserveX4, "reserve-x4", "Reserve X4, making it unavailable as a GPR", "reserve-x4"),
+ FeatureInfo(@This()).create(.ReserveX5, "reserve-x5", "Reserve X5, making it unavailable as a GPR", "reserve-x5"),
+ FeatureInfo(@This()).create(.ReserveX6, "reserve-x6", "Reserve X6, making it unavailable as a GPR", "reserve-x6"),
+ FeatureInfo(@This()).create(.ReserveX7, "reserve-x7", "Reserve X7, making it unavailable as a GPR", "reserve-x7"),
+ FeatureInfo(@This()).create(.ReserveX9, "reserve-x9", "Reserve X9, making it unavailable as a GPR", "reserve-x9"),
+ FeatureInfo(@This()).create(.ReserveX10, "reserve-x10", "Reserve X10, making it unavailable as a GPR", "reserve-x10"),
+ FeatureInfo(@This()).create(.ReserveX11, "reserve-x11", "Reserve X11, making it unavailable as a GPR", "reserve-x11"),
+ FeatureInfo(@This()).create(.ReserveX12, "reserve-x12", "Reserve X12, making it unavailable as a GPR", "reserve-x12"),
+ FeatureInfo(@This()).create(.ReserveX13, "reserve-x13", "Reserve X13, making it unavailable as a GPR", "reserve-x13"),
+ FeatureInfo(@This()).create(.ReserveX14, "reserve-x14", "Reserve X14, making it unavailable as a GPR", "reserve-x14"),
+ FeatureInfo(@This()).create(.ReserveX15, "reserve-x15", "Reserve X15, making it unavailable as a GPR", "reserve-x15"),
+ FeatureInfo(@This()).create(.ReserveX18, "reserve-x18", "Reserve X18, making it unavailable as a GPR", "reserve-x18"),
+ FeatureInfo(@This()).create(.ReserveX20, "reserve-x20", "Reserve X20, making it unavailable as a GPR", "reserve-x20"),
+ FeatureInfo(@This()).create(.ReserveX21, "reserve-x21", "Reserve X21, making it unavailable as a GPR", "reserve-x21"),
+ FeatureInfo(@This()).create(.ReserveX22, "reserve-x22", "Reserve X22, making it unavailable as a GPR", "reserve-x22"),
+ FeatureInfo(@This()).create(.ReserveX23, "reserve-x23", "Reserve X23, making it unavailable as a GPR", "reserve-x23"),
+ FeatureInfo(@This()).create(.ReserveX24, "reserve-x24", "Reserve X24, making it unavailable as a GPR", "reserve-x24"),
+ FeatureInfo(@This()).create(.ReserveX25, "reserve-x25", "Reserve X25, making it unavailable as a GPR", "reserve-x25"),
+ FeatureInfo(@This()).create(.ReserveX26, "reserve-x26", "Reserve X26, making it unavailable as a GPR", "reserve-x26"),
+ FeatureInfo(@This()).create(.ReserveX27, "reserve-x27", "Reserve X27, making it unavailable as a GPR", "reserve-x27"),
+ FeatureInfo(@This()).create(.ReserveX28, "reserve-x28", "Reserve X28, making it unavailable as a GPR", "reserve-x28"),
+ FeatureInfo(@This()).create(.Sb, "sb", "Enable v8.5 Speculation Barrier", "sb"),
+ FeatureInfo(@This()).create(.Sel2, "sel2", "Enable v8.4-A Secure Exception Level 2 extension", "sel2"),
+ FeatureInfo(@This()).createWithSubfeatures(.Sha2, "sha2", "Enable SHA1 and SHA256 support", "sha2", &[_]@This() {
+ .FpArmv8,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Sha3, "sha3", "Enable SHA512 and SHA3 support", "sha3", &[_]@This() {
+ .FpArmv8,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Sm4, "sm4", "Enable SM3 and SM4 support", "sm4", &[_]@This() {
+ .FpArmv8,
+ }),
+ FeatureInfo(@This()).create(.Spe, "spe", "Enable Statistical Profiling extension", "spe"),
+ FeatureInfo(@This()).create(.Ssbs, "ssbs", "Enable Speculative Store Bypass Safe bit", "ssbs"),
+ FeatureInfo(@This()).create(.Sve, "sve", "Enable Scalable Vector Extension (SVE) instructions", "sve"),
+ FeatureInfo(@This()).createWithSubfeatures(.Sve2, "sve2", "Enable Scalable Vector Extension 2 (SVE2) instructions", "sve2", &[_]@This() {
+ .Sve,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Sve2Aes, "sve2-aes", "Enable AES SVE2 instructions", "sve2-aes", &[_]@This() {
+ .Sve,
+ .FpArmv8,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Sve2Bitperm, "sve2-bitperm", "Enable bit permutation SVE2 instructions", "sve2-bitperm", &[_]@This() {
+ .Sve,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Sve2Sha3, "sve2-sha3", "Enable SHA3 SVE2 instructions", "sve2-sha3", &[_]@This() {
+ .Sve,
+ .FpArmv8,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Sve2Sm4, "sve2-sm4", "Enable SM4 SVE2 instructions", "sve2-sm4", &[_]@This() {
+ .Sve,
+ .FpArmv8,
+ }),
+ FeatureInfo(@This()).create(.SlowMisaligned128store, "slow-misaligned-128store", "Misaligned 128 bit stores are slow", "slow-misaligned-128store"),
+ FeatureInfo(@This()).create(.SlowPaired128, "slow-paired-128", "Paired 128 bit loads and stores are slow", "slow-paired-128"),
+ FeatureInfo(@This()).create(.SlowStrqroStore, "slow-strqro-store", "STR of Q register with register offset is slow", "slow-strqro-store"),
+ FeatureInfo(@This()).create(.Specrestrict, "specrestrict", "Enable architectural speculation restriction", "specrestrict"),
+ FeatureInfo(@This()).create(.StrictAlign, "strict-align", "Disallow all unaligned memory access", "strict-align"),
+ FeatureInfo(@This()).create(.TlbRmi, "tlb-rmi", "Enable v8.4-A TLB Range and Maintenance Instructions", "tlb-rmi"),
+ FeatureInfo(@This()).create(.Tme, "tme", "Enable Transactional Memory Extension", "tme"),
+ FeatureInfo(@This()).create(.Tracev84, "tracev8.4", "Enable v8.4-A Trace extension", "tracev8.4"),
+ FeatureInfo(@This()).create(.Trbe, "trbe", "Enable Trace Buffer Extension", "trbe"),
+ FeatureInfo(@This()).create(.TaggedGlobals, "tagged-globals", "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits", "tagged-globals"),
+ FeatureInfo(@This()).create(.UseAa, "use-aa", "Use alias analysis during codegen", "use-aa"),
+ FeatureInfo(@This()).create(.TpidrEl1, "tpidr-el1", "Permit use of TPIDR_EL1 for the TLS base", "tpidr-el1"),
+ FeatureInfo(@This()).create(.TpidrEl2, "tpidr-el2", "Permit use of TPIDR_EL2 for the TLS base", "tpidr-el2"),
+ FeatureInfo(@This()).create(.TpidrEl3, "tpidr-el3", "Permit use of TPIDR_EL3 for the TLS base", "tpidr-el3"),
+ FeatureInfo(@This()).create(.UseReciprocalSquareRoot, "use-reciprocal-square-root", "Use the reciprocal square root approximation", "use-reciprocal-square-root"),
+ FeatureInfo(@This()).create(.Vh, "vh", "Enables ARM v8.1 Virtual Host extension", "vh"),
+ FeatureInfo(@This()).create(.Zcm, "zcm", "Has zero-cycle register moves", "zcm"),
+ FeatureInfo(@This()).createWithSubfeatures(.Zcz, "zcz", "Has zero-cycle zeroing instructions", "zcz", &[_]@This() {
+ .ZczFp,
+ .ZczGp,
+ }),
+ FeatureInfo(@This()).create(.ZczFp, "zcz-fp", "Has zero-cycle zeroing instructions for FP registers", "zcz-fp"),
+ FeatureInfo(@This()).create(.ZczFpWorkaround, "zcz-fp-workaround", "The zero-cycle floating-point zeroing instruction has a bug", "zcz-fp-workaround"),
+ FeatureInfo(@This()).create(.ZczGp, "zcz-gp", "Has zero-cycle zeroing instructions for generic registers", "zcz-gp"),
+ FeatureInfo(@This()).createWithSubfeatures(.V81a, "v8.1a", "Support ARM v8.1a instructions", "v8.1a", &[_]@This() {
+ .Pan,
+ .Rdm,
+ .Lse,
+ .Crc,
+ .Lor,
+ .Vh,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.V82a, "v8.2a", "Support ARM v8.2a instructions", "v8.2a", &[_]@This() {
+ .Ccpp,
+ .Pan,
+ .Rdm,
+ .Lse,
+ .Crc,
+ .Lor,
+ .Uaops,
+ .Vh,
+ .Ras,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.V83a, "v8.3a", "Support ARM v8.3a instructions", "v8.3a", &[_]@This() {
+ .Rcpc,
+ .Ccpp,
+ .Pan,
+ .Rdm,
+ .FpArmv8,
+ .Lse,
+ .Ccidx,
+ .Crc,
+ .Lor,
+ .Pa,
+ .Uaops,
+ .Vh,
+ .Ras,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.V84a, "v8.4a", "Support ARM v8.4a instructions", "v8.4a", &[_]@This() {
+ .Nv,
+ .Am,
+ .Lse,
+ .Sel2,
+ .Lor,
+ .Tracev84,
+ .Uaops,
+ .Ccpp,
+ .TlbRmi,
+ .Fmi,
+ .Rcpc,
+ .Pan,
+ .Rdm,
+ .Pa,
+ .Dit,
+ .Ras,
+ .Mpam,
+ .FpArmv8,
+ .Ccidx,
+ .Dotprod,
+ .Crc,
+ .Vh,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.V85a, "v8.5a", "Support ARM v8.5a instructions", "v8.5a", &[_]@This() {
+ .Nv,
+ .Am,
+ .Lse,
+ .Fptoint,
+ .Sel2,
+ .Lor,
+ .Tracev84,
+ .Uaops,
+ .Sb,
+ .Ccpp,
+ .Specrestrict,
+ .Bti,
+ .Ccdp,
+ .TlbRmi,
+ .Fmi,
+ .Rcpc,
+ .Pan,
+ .Rdm,
+ .Pa,
+ .Ssbs,
+ .Dit,
+ .Ras,
+ .Mpam,
+ .Altnzcv,
+ .FpArmv8,
+ .Ccidx,
+ .Dotprod,
+ .Crc,
+ .Predres,
+ .Vh,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.A35, "a35", "Cortex-A35 ARM processors", "a35", &[_]@This() {
+ .Perfmon,
+ .FpArmv8,
+ .Crc,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.A53, "a53", "Cortex-A53 ARM processors", "a53", &[_]@This() {
+ .UseAa,
+ .FuseAes,
+ .FpArmv8,
+ .Perfmon,
+ .Crc,
+ .BalanceFpOps,
+ .UsePostraScheduler,
+ .CustomCheapAsMove,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.A55, "a55", "Cortex-A55 ARM processors", "a55", &[_]@This() {
+ .Rcpc,
+ .Ccpp,
+ .Pan,
+ .Rdm,
+ .FuseAes,
+ .Perfmon,
+ .FpArmv8,
+ .Lse,
+ .Crc,
+ .Dotprod,
+ .Lor,
+ .Uaops,
+ .Vh,
+ .Ras,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.A57, "a57", "Cortex-A57 ARM processors", "a57", &[_]@This() {
+ .FuseLiterals,
+ .FuseAes,
+ .FpArmv8,
+ .Perfmon,
+ .Crc,
+ .BalanceFpOps,
+ .UsePostraScheduler,
+ .CustomCheapAsMove,
+ .PredictableSelectExpensive,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.A65, "a65", "Cortex-A65 ARM processors", "a65", &[_]@This() {
+ .Rcpc,
+ .Ccpp,
+ .Pan,
+ .Rdm,
+ .FpArmv8,
+ .Lse,
+ .Crc,
+ .Dotprod,
+ .Lor,
+ .Ssbs,
+ .Uaops,
+ .Vh,
+ .Ras,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.A72, "a72", "Cortex-A72 ARM processors", "a72", &[_]@This() {
+ .Perfmon,
+ .FuseAes,
+ .FpArmv8,
+ .Crc,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.A73, "a73", "Cortex-A73 ARM processors", "a73", &[_]@This() {
+ .Perfmon,
+ .FuseAes,
+ .FpArmv8,
+ .Crc,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.A75, "a75", "Cortex-A75 ARM processors", "a75", &[_]@This() {
+ .Rcpc,
+ .Ccpp,
+ .Pan,
+ .Rdm,
+ .FuseAes,
+ .Perfmon,
+ .FpArmv8,
+ .Lse,
+ .Crc,
+ .Dotprod,
+ .Lor,
+ .Uaops,
+ .Vh,
+ .Ras,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.A76, "a76", "Cortex-A76 ARM processors", "a76", &[_]@This() {
+ .Rcpc,
+ .Ccpp,
+ .Pan,
+ .Rdm,
+ .FpArmv8,
+ .Lse,
+ .Crc,
+ .Dotprod,
+ .Lor,
+ .Ssbs,
+ .Uaops,
+ .Vh,
+ .Ras,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Cyclone, "cyclone", "Cyclone", "cyclone", &[_]@This() {
+ .ZczFp,
+ .ArithCbzFusion,
+ .FuseAes,
+ .AlternateSextloadCvtF32Pattern,
+ .ZczFpWorkaround,
+ .FpArmv8,
+ .Perfmon,
+ .DisableLatencySchedHeuristic,
+ .Zcm,
+ .ZczGp,
+ .ArithBccFusion,
+ .FuseCryptoEor,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Exynosm1, "exynosm1", "Samsung Exynos-M1 processors", "exynosm1", &[_]@This() {
+ .ZczFp,
+ .FuseAes,
+ .SlowPaired128,
+ .Force32bitJumpTables,
+ .UseReciprocalSquareRoot,
+ .FpArmv8,
+ .Perfmon,
+ .SlowMisaligned128store,
+ .Crc,
+ .UsePostraScheduler,
+ .CustomCheapAsMove,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Exynosm2, "exynosm2", "Samsung Exynos-M2 processors", "exynosm2", &[_]@This() {
+ .ZczFp,
+ .FuseAes,
+ .SlowPaired128,
+ .Force32bitJumpTables,
+ .FpArmv8,
+ .Perfmon,
+ .SlowMisaligned128store,
+ .Crc,
+ .UsePostraScheduler,
+ .CustomCheapAsMove,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Exynosm3, "exynosm3", "Samsung Exynos-M3 processors", "exynosm3", &[_]@This() {
+ .ZczFp,
+ .FuseLiterals,
+ .FuseAes,
+ .Force32bitJumpTables,
+ .FpArmv8,
+ .Perfmon,
+ .Crc,
+ .LslFast,
+ .FuseAddress,
+ .UsePostraScheduler,
+ .CustomCheapAsMove,
+ .PredictableSelectExpensive,
+ .FuseCsel,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Exynosm4, "exynosm4", "Samsung Exynos-M4 processors", "exynosm4", &[_]@This() {
+ .ZczFp,
+ .Lse,
+ .FuseArithLogic,
+ .Lor,
+ .UsePostraScheduler,
+ .Uaops,
+ .CustomCheapAsMove,
+ .ArithBccFusion,
+ .Ccpp,
+ .Perfmon,
+ .Pan,
+ .Rdm,
+ .FuseLiterals,
+ .Force32bitJumpTables,
+ .LslFast,
+ .FuseAddress,
+ .ZczGp,
+ .Ras,
+ .FuseCsel,
+ .ArithCbzFusion,
+ .FuseAes,
+ .FpArmv8,
+ .Crc,
+ .Dotprod,
+ .Vh,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Falkor, "falkor", "Qualcomm Falkor processors", "falkor", &[_]@This() {
+ .ZczFp,
+ .Rdm,
+ .SlowStrqroStore,
+ .Perfmon,
+ .FpArmv8,
+ .Crc,
+ .LslFast,
+ .UsePostraScheduler,
+ .ZczGp,
+ .CustomCheapAsMove,
+ .PredictableSelectExpensive,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Kryo, "kryo", "Qualcomm Kryo processors", "kryo", &[_]@This() {
+ .ZczFp,
+ .Perfmon,
+ .FpArmv8,
+ .Crc,
+ .LslFast,
+ .UsePostraScheduler,
+ .ZczGp,
+ .CustomCheapAsMove,
+ .PredictableSelectExpensive,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Neoversee1, "neoversee1", "Neoverse E1 ARM processors", "neoversee1", &[_]@This() {
+ .Rcpc,
+ .Ccpp,
+ .Pan,
+ .Rdm,
+ .FpArmv8,
+ .Lse,
+ .Crc,
+ .Dotprod,
+ .Lor,
+ .Ssbs,
+ .Uaops,
+ .Vh,
+ .Ras,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Neoversen1, "neoversen1", "Neoverse N1 ARM processors", "neoversen1", &[_]@This() {
+ .Rcpc,
+ .Spe,
+ .Ccpp,
+ .Pan,
+ .Rdm,
+ .FpArmv8,
+ .Lse,
+ .Crc,
+ .Dotprod,
+ .Lor,
+ .Ssbs,
+ .Uaops,
+ .Vh,
+ .Ras,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Saphira, "saphira", "Qualcomm Saphira processors", "saphira", &[_]@This() {
+ .ZczFp,
+ .Nv,
+ .Am,
+ .Lse,
+ .Sel2,
+ .Lor,
+ .Tracev84,
+ .Uaops,
+ .UsePostraScheduler,
+ .CustomCheapAsMove,
+ .Ccpp,
+ .Perfmon,
+ .TlbRmi,
+ .PredictableSelectExpensive,
+ .Fmi,
+ .Rcpc,
+ .Pan,
+ .Rdm,
+ .LslFast,
+ .Pa,
+ .ZczGp,
+ .Dit,
+ .Ras,
+ .Spe,
+ .Mpam,
+ .FpArmv8,
+ .Ccidx,
+ .Dotprod,
+ .Crc,
+ .Vh,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Tsv110, "tsv110", "HiSilicon TS-V110 processors", "tsv110", &[_]@This() {
+ .Uaops,
+ .Spe,
+ .Ccpp,
+ .Pan,
+ .Rdm,
+ .FuseAes,
+ .Vh,
+ .Perfmon,
+ .FpArmv8,
+ .Lse,
+ .Crc,
+ .Dotprod,
+ .Lor,
+ .UsePostraScheduler,
+ .CustomCheapAsMove,
+ .Ras,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Thunderx, "thunderx", "Cavium ThunderX processors", "thunderx", &[_]@This() {
+ .Perfmon,
+ .FpArmv8,
+ .Crc,
+ .UsePostraScheduler,
+ .PredictableSelectExpensive,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Thunderx2t99, "thunderx2t99", "Cavium ThunderX2 processors", "thunderx2t99", &[_]@This() {
+ .Pan,
+ .Rdm,
+ .Vh,
+ .AggressiveFma,
+ .FpArmv8,
+ .Lse,
+ .Crc,
+ .Lor,
+ .UsePostraScheduler,
+ .ArithBccFusion,
+ .PredictableSelectExpensive,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Thunderxt81, "thunderxt81", "Cavium ThunderX processors", "thunderxt81", &[_]@This() {
+ .Perfmon,
+ .FpArmv8,
+ .Crc,
+ .UsePostraScheduler,
+ .PredictableSelectExpensive,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Thunderxt83, "thunderxt83", "Cavium ThunderX processors", "thunderxt83", &[_]@This() {
+ .Perfmon,
+ .FpArmv8,
+ .Crc,
+ .UsePostraScheduler,
+ .PredictableSelectExpensive,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Thunderxt88, "thunderxt88", "Cavium ThunderX processors", "thunderxt88", &[_]@This() {
+ .Perfmon,
+ .FpArmv8,
+ .Crc,
+ .UsePostraScheduler,
+ .PredictableSelectExpensive,
+ }),
+ };
+};
lib/std/target/feature/AmdGpuFeature.zig
@@ -0,0 +1,343 @@
+const FeatureInfo = @import("std").target.feature.FeatureInfo;
+
+pub const AmdGpuFeature = enum {
+ BitInsts16,
+ AddNoCarryInsts,
+ ApertureRegs,
+ AtomicFaddInsts,
+ AutoWaitcntBeforeBarrier,
+ CiInsts,
+ CodeObjectV3,
+ Cumode,
+ DlInsts,
+ Dpp,
+ Dpp8,
+ NoSramEccSupport,
+ NoXnackSupport,
+ Dot1Insts,
+ Dot2Insts,
+ Dot3Insts,
+ Dot4Insts,
+ Dot5Insts,
+ Dot6Insts,
+ DumpCode,
+ Dumpcode,
+ EnableDs128,
+ LoadStoreOpt,
+ EnablePrtStrictNull,
+ SiScheduler,
+ UnsafeDsOffsetFolding,
+ Fmaf,
+ Fp16Denormals,
+ Fp32Denormals,
+ Fp64,
+ Fp64Denormals,
+ Fp64Fp16Denormals,
+ FpExceptions,
+ FastFmaf,
+ FlatAddressSpace,
+ FlatForGlobal,
+ FlatGlobalInsts,
+ FlatInstOffsets,
+ FlatScratchInsts,
+ FlatSegmentOffsetBug,
+ FmaMixInsts,
+ Gcn3Encoding,
+ Gfx7Gfx8Gfx9Insts,
+ Gfx8Insts,
+ Gfx9,
+ Gfx9Insts,
+ Gfx10,
+ Gfx10Insts,
+ InstFwdPrefetchBug,
+ IntClampInsts,
+ Inv2piInlineImm,
+ Ldsbankcount16,
+ Ldsbankcount32,
+ LdsBranchVmemWarHazard,
+ LdsMisalignedBug,
+ Localmemorysize0,
+ Localmemorysize32768,
+ Localmemorysize65536,
+ MaiInsts,
+ MfmaInlineLiteralBug,
+ MimgR128,
+ MadMixInsts,
+ MaxPrivateElementSize4,
+ MaxPrivateElementSize8,
+ MaxPrivateElementSize16,
+ Movrel,
+ NsaEncoding,
+ NsaToVmemBug,
+ NoDataDepHazard,
+ NoSdstCmpx,
+ Offset3fBug,
+ PkFmacF16Inst,
+ PromoteAlloca,
+ R128A16,
+ RegisterBanking,
+ Sdwa,
+ SdwaMav,
+ SdwaOmod,
+ SdwaOutModsVopc,
+ SdwaScalar,
+ SdwaSdst,
+ SgprInitBug,
+ SmemToVectorWriteHazard,
+ SMemrealtime,
+ SramEcc,
+ ScalarAtomics,
+ ScalarFlatScratchInsts,
+ ScalarStores,
+ SeaIslands,
+ SouthernIslands,
+ TrapHandler,
+ TrigReducedRange,
+ UnalignedBufferAccess,
+ UnalignedScratchAccess,
+ UnpackedD16Vmem,
+ VgprIndexMode,
+ VmemToScalarWriteHazard,
+ Vop3Literal,
+ Vop3p,
+ VcmpxExecWarHazard,
+ VcmpxPermlaneHazard,
+ VolcanicIslands,
+ Vscnt,
+ Wavefrontsize16,
+ Wavefrontsize32,
+ Wavefrontsize64,
+ Xnack,
+ HalfRate64Ops,
+
+ pub fn getInfo(self: @This()) FeatureInfo {
+ return feature_infos[@enumToInt(self)];
+ }
+
+ pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
+ FeatureInfo(@This()).create(.BitInsts16, "16-bit-insts", "Has i16/f16 instructions", "16-bit-insts"),
+ FeatureInfo(@This()).create(.AddNoCarryInsts, "add-no-carry-insts", "Have VALU add/sub instructions without carry out", "add-no-carry-insts"),
+ FeatureInfo(@This()).create(.ApertureRegs, "aperture-regs", "Has Memory Aperture Base and Size Registers", "aperture-regs"),
+ FeatureInfo(@This()).create(.AtomicFaddInsts, "atomic-fadd-insts", "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, global_atomic_pk_add_f16 instructions", "atomic-fadd-insts"),
+ FeatureInfo(@This()).create(.AutoWaitcntBeforeBarrier, "auto-waitcnt-before-barrier", "Hardware automatically inserts waitcnt before barrier", "auto-waitcnt-before-barrier"),
+ FeatureInfo(@This()).create(.CiInsts, "ci-insts", "Additional instructions for CI+", "ci-insts"),
+ FeatureInfo(@This()).create(.CodeObjectV3, "code-object-v3", "Generate code object version 3", "code-object-v3"),
+ FeatureInfo(@This()).create(.Cumode, "cumode", "Enable CU wavefront execution mode", "cumode"),
+ FeatureInfo(@This()).create(.DlInsts, "dl-insts", "Has v_fmac_f32 and v_xnor_b32 instructions", "dl-insts"),
+ FeatureInfo(@This()).create(.Dpp, "dpp", "Support DPP (Data Parallel Primitives) extension", "dpp"),
+ FeatureInfo(@This()).create(.Dpp8, "dpp8", "Support DPP8 (Data Parallel Primitives) extension", "dpp8"),
+ FeatureInfo(@This()).create(.NoSramEccSupport, "no-sram-ecc-support", "Hardware does not support SRAM ECC", "no-sram-ecc-support"),
+ FeatureInfo(@This()).create(.NoXnackSupport, "no-xnack-support", "Hardware does not support XNACK", "no-xnack-support"),
+ FeatureInfo(@This()).create(.Dot1Insts, "dot1-insts", "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions", "dot1-insts"),
+ FeatureInfo(@This()).create(.Dot2Insts, "dot2-insts", "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions", "dot2-insts"),
+ FeatureInfo(@This()).create(.Dot3Insts, "dot3-insts", "Has v_dot8c_i32_i4 instruction", "dot3-insts"),
+ FeatureInfo(@This()).create(.Dot4Insts, "dot4-insts", "Has v_dot2c_i32_i16 instruction", "dot4-insts"),
+ FeatureInfo(@This()).create(.Dot5Insts, "dot5-insts", "Has v_dot2c_f32_f16 instruction", "dot5-insts"),
+ FeatureInfo(@This()).create(.Dot6Insts, "dot6-insts", "Has v_dot4c_i32_i8 instruction", "dot6-insts"),
+ FeatureInfo(@This()).create(.DumpCode, "DumpCode", "Dump MachineInstrs in the CodeEmitter", "DumpCode"),
+ FeatureInfo(@This()).create(.Dumpcode, "dumpcode", "Dump MachineInstrs in the CodeEmitter", "dumpcode"),
+ FeatureInfo(@This()).create(.EnableDs128, "enable-ds128", "Use ds_{read|write}_b128", "enable-ds128"),
+ FeatureInfo(@This()).create(.LoadStoreOpt, "load-store-opt", "Enable SI load/store optimizer pass", "load-store-opt"),
+ FeatureInfo(@This()).create(.EnablePrtStrictNull, "enable-prt-strict-null", "Enable zeroing of result registers for sparse texture fetches", "enable-prt-strict-null"),
+ FeatureInfo(@This()).create(.SiScheduler, "si-scheduler", "Enable SI Machine Scheduler", "si-scheduler"),
+ FeatureInfo(@This()).create(.UnsafeDsOffsetFolding, "unsafe-ds-offset-folding", "Force using DS instruction immediate offsets on SI", "unsafe-ds-offset-folding"),
+ FeatureInfo(@This()).create(.Fmaf, "fmaf", "Enable single precision FMA (not as fast as mul+add, but fused)", "fmaf"),
+ FeatureInfo(@This()).createWithSubfeatures(.Fp16Denormals, "fp16-denormals", "Enable half precision denormal handling", "fp16-denormals", &[_]@This() {
+ .Fp64,
+ }),
+ FeatureInfo(@This()).create(.Fp32Denormals, "fp32-denormals", "Enable single precision denormal handling", "fp32-denormals"),
+ FeatureInfo(@This()).create(.Fp64, "fp64", "Enable double precision operations", "fp64"),
+ FeatureInfo(@This()).createWithSubfeatures(.Fp64Denormals, "fp64-denormals", "Enable double and half precision denormal handling", "fp64-denormals", &[_]@This() {
+ .Fp64,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Fp64Fp16Denormals, "fp64-fp16-denormals", "Enable double and half precision denormal handling", "fp64-fp16-denormals", &[_]@This() {
+ .Fp64,
+ }),
+ FeatureInfo(@This()).create(.FpExceptions, "fp-exceptions", "Enable floating point exceptions", "fp-exceptions"),
+ FeatureInfo(@This()).create(.FastFmaf, "fast-fmaf", "Assuming f32 fma is at least as fast as mul + add", "fast-fmaf"),
+ FeatureInfo(@This()).create(.FlatAddressSpace, "flat-address-space", "Support flat address space", "flat-address-space"),
+ FeatureInfo(@This()).create(.FlatForGlobal, "flat-for-global", "Force to generate flat instruction for global", "flat-for-global"),
+ FeatureInfo(@This()).create(.FlatGlobalInsts, "flat-global-insts", "Have global_* flat memory instructions", "flat-global-insts"),
+ FeatureInfo(@This()).create(.FlatInstOffsets, "flat-inst-offsets", "Flat instructions have immediate offset addressing mode", "flat-inst-offsets"),
+ FeatureInfo(@This()).create(.FlatScratchInsts, "flat-scratch-insts", "Have scratch_* flat memory instructions", "flat-scratch-insts"),
+ FeatureInfo(@This()).create(.FlatSegmentOffsetBug, "flat-segment-offset-bug", "GFX10 bug, inst_offset ignored in flat segment", "flat-segment-offset-bug"),
+ FeatureInfo(@This()).create(.FmaMixInsts, "fma-mix-insts", "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions", "fma-mix-insts"),
+ FeatureInfo(@This()).create(.Gcn3Encoding, "gcn3-encoding", "Encoding format for VI", "gcn3-encoding"),
+ FeatureInfo(@This()).create(.Gfx7Gfx8Gfx9Insts, "gfx7-gfx8-gfx9-insts", "Instructions shared in GFX7, GFX8, GFX9", "gfx7-gfx8-gfx9-insts"),
+ FeatureInfo(@This()).create(.Gfx8Insts, "gfx8-insts", "Additional instructions for GFX8+", "gfx8-insts"),
+ FeatureInfo(@This()).createWithSubfeatures(.Gfx9, "gfx9", "GFX9 GPU generation", "gfx9", &[_]@This() {
+ .Gfx9Insts,
+ .Wavefrontsize64,
+ .Fp64,
+ .Gcn3Encoding,
+ .FastFmaf,
+ .Sdwa,
+ .SdwaScalar,
+ .VgprIndexMode,
+ .Dpp,
+ .AddNoCarryInsts,
+ .SdwaOmod,
+ .SdwaSdst,
+ .ScalarAtomics,
+ .FlatAddressSpace,
+ .ScalarFlatScratchInsts,
+ .Gfx8Insts,
+ .Gfx7Gfx8Gfx9Insts,
+ .R128A16,
+ .IntClampInsts,
+ .ScalarStores,
+ .ApertureRegs,
+ .CiInsts,
+ .FlatGlobalInsts,
+ .BitInsts16,
+ .FlatScratchInsts,
+ .SMemrealtime,
+ .Vop3p,
+ .FlatInstOffsets,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ }),
+ FeatureInfo(@This()).create(.Gfx9Insts, "gfx9-insts", "Additional instructions for GFX9+", "gfx9-insts"),
+ FeatureInfo(@This()).createWithSubfeatures(.Gfx10, "gfx10", "GFX10 GPU generation", "gfx10", &[_]@This() {
+ .Gfx9Insts,
+ .NoSdstCmpx,
+ .Fp64,
+ .FastFmaf,
+ .Sdwa,
+ .SdwaScalar,
+ .Dpp,
+ .RegisterBanking,
+ .Gfx10Insts,
+ .AddNoCarryInsts,
+ .SdwaOmod,
+ .SdwaSdst,
+ .FlatAddressSpace,
+ .Gfx8Insts,
+ .FmaMixInsts,
+ .PkFmacF16Inst,
+ .Vop3Literal,
+ .MimgR128,
+ .NoSramEccSupport,
+ .IntClampInsts,
+ .Movrel,
+ .Dpp8,
+ .ApertureRegs,
+ .NoDataDepHazard,
+ .CiInsts,
+ .FlatGlobalInsts,
+ .BitInsts16,
+ .FlatScratchInsts,
+ .SMemrealtime,
+ .Vop3p,
+ .FlatInstOffsets,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .Vscnt,
+ }),
+ FeatureInfo(@This()).create(.Gfx10Insts, "gfx10-insts", "Additional instructions for GFX10+", "gfx10-insts"),
+ FeatureInfo(@This()).create(.InstFwdPrefetchBug, "inst-fwd-prefetch-bug", "S_INST_PREFETCH instruction causes shader to hang", "inst-fwd-prefetch-bug"),
+ FeatureInfo(@This()).create(.IntClampInsts, "int-clamp-insts", "Support clamp for integer destination", "int-clamp-insts"),
+ FeatureInfo(@This()).create(.Inv2piInlineImm, "inv-2pi-inline-imm", "Has 1 / (2 * pi) as inline immediate", "inv-2pi-inline-imm"),
+ FeatureInfo(@This()).create(.Ldsbankcount16, "ldsbankcount16", "The number of LDS banks per compute unit.", "ldsbankcount16"),
+ FeatureInfo(@This()).create(.Ldsbankcount32, "ldsbankcount32", "The number of LDS banks per compute unit.", "ldsbankcount32"),
+ FeatureInfo(@This()).create(.LdsBranchVmemWarHazard, "lds-branch-vmem-war-hazard", "Switching between LDS and VMEM-tex not waiting VM_VSRC=0", "lds-branch-vmem-war-hazard"),
+ FeatureInfo(@This()).create(.LdsMisalignedBug, "lds-misaligned-bug", "Some GFX10 bug with misaligned multi-dword LDS access in WGP mode", "lds-misaligned-bug"),
+ FeatureInfo(@This()).create(.Localmemorysize0, "localmemorysize0", "The size of local memory in bytes", "localmemorysize0"),
+ FeatureInfo(@This()).create(.Localmemorysize32768, "localmemorysize32768", "The size of local memory in bytes", "localmemorysize32768"),
+ FeatureInfo(@This()).create(.Localmemorysize65536, "localmemorysize65536", "The size of local memory in bytes", "localmemorysize65536"),
+ FeatureInfo(@This()).create(.MaiInsts, "mai-insts", "Has mAI instructions", "mai-insts"),
+ FeatureInfo(@This()).create(.MfmaInlineLiteralBug, "mfma-inline-literal-bug", "MFMA cannot use inline literal as SrcC", "mfma-inline-literal-bug"),
+ FeatureInfo(@This()).create(.MimgR128, "mimg-r128", "Support 128-bit texture resources", "mimg-r128"),
+ FeatureInfo(@This()).create(.MadMixInsts, "mad-mix-insts", "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions", "mad-mix-insts"),
+ FeatureInfo(@This()).create(.MaxPrivateElementSize4, "max-private-element-size-4", "Maximum private access size may be 4", "max-private-element-size-4"),
+ FeatureInfo(@This()).create(.MaxPrivateElementSize8, "max-private-element-size-8", "Maximum private access size may be 8", "max-private-element-size-8"),
+ FeatureInfo(@This()).create(.MaxPrivateElementSize16, "max-private-element-size-16", "Maximum private access size may be 16", "max-private-element-size-16"),
+ FeatureInfo(@This()).create(.Movrel, "movrel", "Has v_movrel*_b32 instructions", "movrel"),
+ FeatureInfo(@This()).create(.NsaEncoding, "nsa-encoding", "Support NSA encoding for image instructions", "nsa-encoding"),
+ FeatureInfo(@This()).create(.NsaToVmemBug, "nsa-to-vmem-bug", "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero", "nsa-to-vmem-bug"),
+ FeatureInfo(@This()).create(.NoDataDepHazard, "no-data-dep-hazard", "Does not need SW waitstates", "no-data-dep-hazard"),
+ FeatureInfo(@This()).create(.NoSdstCmpx, "no-sdst-cmpx", "V_CMPX does not write VCC/SGPR in addition to EXEC", "no-sdst-cmpx"),
+ FeatureInfo(@This()).create(.Offset3fBug, "offset-3f-bug", "Branch offset of 3f hardware bug", "offset-3f-bug"),
+ FeatureInfo(@This()).create(.PkFmacF16Inst, "pk-fmac-f16-inst", "Has v_pk_fmac_f16 instruction", "pk-fmac-f16-inst"),
+ FeatureInfo(@This()).create(.PromoteAlloca, "promote-alloca", "Enable promote alloca pass", "promote-alloca"),
+ FeatureInfo(@This()).create(.R128A16, "r128-a16", "Support 16 bit coordindates/gradients/lod/clamp/mip types on gfx9", "r128-a16"),
+ FeatureInfo(@This()).create(.RegisterBanking, "register-banking", "Has register banking", "register-banking"),
+ FeatureInfo(@This()).create(.Sdwa, "sdwa", "Support SDWA (Sub-DWORD Addressing) extension", "sdwa"),
+ FeatureInfo(@This()).create(.SdwaMav, "sdwa-mav", "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension", "sdwa-mav"),
+ FeatureInfo(@This()).create(.SdwaOmod, "sdwa-omod", "Support OMod with SDWA (Sub-DWORD Addressing) extension", "sdwa-omod"),
+ FeatureInfo(@This()).create(.SdwaOutModsVopc, "sdwa-out-mods-vopc", "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension", "sdwa-out-mods-vopc"),
+ FeatureInfo(@This()).create(.SdwaScalar, "sdwa-scalar", "Support scalar register with SDWA (Sub-DWORD Addressing) extension", "sdwa-scalar"),
+ FeatureInfo(@This()).create(.SdwaSdst, "sdwa-sdst", "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension", "sdwa-sdst"),
+ FeatureInfo(@This()).create(.SgprInitBug, "sgpr-init-bug", "VI SGPR initialization bug requiring a fixed SGPR allocation size", "sgpr-init-bug"),
+ FeatureInfo(@This()).create(.SmemToVectorWriteHazard, "smem-to-vector-write-hazard", "s_load_dword followed by v_cmp page faults", "smem-to-vector-write-hazard"),
+ FeatureInfo(@This()).create(.SMemrealtime, "s-memrealtime", "Has s_memrealtime instruction", "s-memrealtime"),
+ FeatureInfo(@This()).create(.SramEcc, "sram-ecc", "Enable SRAM ECC", "sram-ecc"),
+ FeatureInfo(@This()).create(.ScalarAtomics, "scalar-atomics", "Has atomic scalar memory instructions", "scalar-atomics"),
+ FeatureInfo(@This()).create(.ScalarFlatScratchInsts, "scalar-flat-scratch-insts", "Have s_scratch_* flat memory instructions", "scalar-flat-scratch-insts"),
+ FeatureInfo(@This()).create(.ScalarStores, "scalar-stores", "Has store scalar memory instructions", "scalar-stores"),
+ FeatureInfo(@This()).createWithSubfeatures(.SeaIslands, "sea-islands", "SEA_ISLANDS GPU generation", "sea-islands", &[_]@This() {
+ .Wavefrontsize64,
+ .MimgR128,
+ .Fp64,
+ .CiInsts,
+ .FlatAddressSpace,
+ .TrigReducedRange,
+ .NoSramEccSupport,
+ .Movrel,
+ .Localmemorysize65536,
+ .Gfx7Gfx8Gfx9Insts,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.SouthernIslands, "southern-islands", "SOUTHERN_ISLANDS GPU generation", "southern-islands", &[_]@This() {
+ .Wavefrontsize64,
+ .MimgR128,
+ .Fp64,
+ .NoXnackSupport,
+ .TrigReducedRange,
+ .NoSramEccSupport,
+ .Movrel,
+ .Ldsbankcount32,
+ .Localmemorysize32768,
+ }),
+ FeatureInfo(@This()).create(.TrapHandler, "trap-handler", "Trap handler support", "trap-handler"),
+ FeatureInfo(@This()).create(.TrigReducedRange, "trig-reduced-range", "Requires use of fract on arguments to trig instructions", "trig-reduced-range"),
+ FeatureInfo(@This()).create(.UnalignedBufferAccess, "unaligned-buffer-access", "Support unaligned global loads and stores", "unaligned-buffer-access"),
+ FeatureInfo(@This()).create(.UnalignedScratchAccess, "unaligned-scratch-access", "Support unaligned scratch loads and stores", "unaligned-scratch-access"),
+ FeatureInfo(@This()).create(.UnpackedD16Vmem, "unpacked-d16-vmem", "Has unpacked d16 vmem instructions", "unpacked-d16-vmem"),
+ FeatureInfo(@This()).create(.VgprIndexMode, "vgpr-index-mode", "Has VGPR mode register indexing", "vgpr-index-mode"),
+ FeatureInfo(@This()).create(.VmemToScalarWriteHazard, "vmem-to-scalar-write-hazard", "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.", "vmem-to-scalar-write-hazard"),
+ FeatureInfo(@This()).create(.Vop3Literal, "vop3-literal", "Can use one literal in VOP3", "vop3-literal"),
+ FeatureInfo(@This()).create(.Vop3p, "vop3p", "Has VOP3P packed instructions", "vop3p"),
+ FeatureInfo(@This()).create(.VcmpxExecWarHazard, "vcmpx-exec-war-hazard", "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)", "vcmpx-exec-war-hazard"),
+ FeatureInfo(@This()).create(.VcmpxPermlaneHazard, "vcmpx-permlane-hazard", "TODO: describe me", "vcmpx-permlane-hazard"),
+ FeatureInfo(@This()).createWithSubfeatures(.VolcanicIslands, "volcanic-islands", "VOLCANIC_ISLANDS GPU generation", "volcanic-islands", &[_]@This() {
+ .Wavefrontsize64,
+ .Fp64,
+ .Gcn3Encoding,
+ .TrigReducedRange,
+ .Sdwa,
+ .VgprIndexMode,
+ .Dpp,
+ .FlatAddressSpace,
+ .Gfx8Insts,
+ .Gfx7Gfx8Gfx9Insts,
+ .MimgR128,
+ .NoSramEccSupport,
+ .IntClampInsts,
+ .ScalarStores,
+ .Movrel,
+ .SdwaMav,
+ .CiInsts,
+ .BitInsts16,
+ .SMemrealtime,
+ .Inv2piInlineImm,
+ .Localmemorysize65536,
+ .SdwaOutModsVopc,
+ }),
+ FeatureInfo(@This()).create(.Vscnt, "vscnt", "Has separate store vscnt counter", "vscnt"),
+ FeatureInfo(@This()).create(.Wavefrontsize16, "wavefrontsize16", "The number of threads per wavefront", "wavefrontsize16"),
+ FeatureInfo(@This()).create(.Wavefrontsize32, "wavefrontsize32", "The number of threads per wavefront", "wavefrontsize32"),
+ FeatureInfo(@This()).create(.Wavefrontsize64, "wavefrontsize64", "The number of threads per wavefront", "wavefrontsize64"),
+ FeatureInfo(@This()).create(.Xnack, "xnack", "Enable XNACK support", "xnack"),
+ FeatureInfo(@This()).create(.HalfRate64Ops, "half-rate-64-ops", "Most fp64 instructions are half rate instead of quarter", "half-rate-64-ops"),
+ };
+};
lib/std/target/feature/ArmFeature.zig
@@ -0,0 +1,818 @@
+const FeatureInfo = @import("std").target.feature.FeatureInfo;
+
+pub const ArmFeature = enum {
+ Armv2,
+ Armv2a,
+ Armv3,
+ Armv3m,
+ Armv4,
+ Armv4t,
+ Armv5t,
+ Armv5te,
+ Armv5tej,
+ Armv6,
+ Armv6j,
+ Armv6k,
+ Armv6kz,
+ Armv6M,
+ Armv6sM,
+ Armv6t2,
+ Armv7A,
+ Armv7eM,
+ Armv7k,
+ Armv7M,
+ Armv7R,
+ Armv7s,
+ Armv7ve,
+ Armv8A,
+ Armv8Mbase,
+ Armv8Mmain,
+ Armv8R,
+ Armv81A,
+ Armv81Mmain,
+ Armv82A,
+ Armv83A,
+ Armv84A,
+ Armv85A,
+ Msecext8,
+ Aclass,
+ Aes,
+ AcquireRelease,
+ AvoidMovsShop,
+ AvoidPartialCpsr,
+ Crc,
+ CheapPredicableCpsr,
+ VldnAlign,
+ Crypto,
+ D32,
+ Db,
+ Dfb,
+ Dsp,
+ DontWidenVmovs,
+ Dotprod,
+ ExecuteOnly,
+ ExpandFpMlx,
+ Fp16,
+ Fp16fml,
+ Fp64,
+ Fpao,
+ FpArmv8,
+ FpArmv8d16,
+ FpArmv8d16sp,
+ FpArmv8sp,
+ Fpregs,
+ Fpregs16,
+ Fpregs64,
+ Fullfp16,
+ FuseAes,
+ FuseLiterals,
+ HwdivArm,
+ Hwdiv,
+ NoBranchPredictor,
+ RetAddrStack,
+ Slowfpvmlx,
+ VmlxHazards,
+ Lob,
+ LongCalls,
+ Mclass,
+ Mp,
+ Mve1beat,
+ Mve2beat,
+ Mve4beat,
+ MuxedUnits,
+ Neon,
+ Neonfp,
+ NeonFpmovs,
+ NaclTrap,
+ Noarm,
+ NoMovt,
+ NoNegImmediates,
+ DisablePostraScheduler,
+ NonpipelinedVfp,
+ Perfmon,
+ Bit32,
+ PreferIshst,
+ LoopAlign,
+ PreferVmovsr,
+ ProfUnpr,
+ Ras,
+ Rclass,
+ ReadTpHard,
+ ReserveR9,
+ Sb,
+ Sha2,
+ SlowFpBrcc,
+ SlowLoadDSubreg,
+ SlowOddReg,
+ SlowVdup32,
+ SlowVgetlni32,
+ SplatVfpNeon,
+ StrictAlign,
+ Thumb2,
+ Trustzone,
+ UseAa,
+ UseMisched,
+ WideStrideVfp,
+ V7clrex,
+ Vfp2,
+ Vfp2sp,
+ Vfp3,
+ Vfp3d16,
+ Vfp3d16sp,
+ Vfp3sp,
+ Vfp4,
+ Vfp4d16,
+ Vfp4d16sp,
+ Vfp4sp,
+ VmlxForwarding,
+ Virtualization,
+ Zcz,
+ Mvefp,
+ Mve,
+ V4t,
+ V5te,
+ V5t,
+ V6k,
+ V6m,
+ V6,
+ V6t2,
+ V7,
+ V8m,
+ V8mmain,
+ V8,
+ V81mmain,
+ V81a,
+ V82a,
+ V83a,
+ V84a,
+ V85a,
+ Iwmmxt,
+ Iwmmxt2,
+ SoftFloat,
+ ThumbMode,
+ A5,
+ A7,
+ A8,
+ A9,
+ A12,
+ A15,
+ A17,
+ A32,
+ A35,
+ A53,
+ A55,
+ A57,
+ A72,
+ A73,
+ A75,
+ A76,
+ Exynos,
+ Krait,
+ Kryo,
+ M3,
+ R4,
+ R5,
+ R7,
+ R52,
+ Swift,
+ Xscale,
+
+ pub fn getInfo(self: @This()) FeatureInfo {
+ return feature_infos[@enumToInt(self)];
+ }
+
+ pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
+ FeatureInfo(@This()).create(.Armv2, "armv2", "ARMv2 architecture", "armv2"),
+ FeatureInfo(@This()).create(.Armv2a, "armv2a", "ARMv2a architecture", "armv2a"),
+ FeatureInfo(@This()).create(.Armv3, "armv3", "ARMv3 architecture", "armv3"),
+ FeatureInfo(@This()).create(.Armv3m, "armv3m", "ARMv3m architecture", "armv3m"),
+ FeatureInfo(@This()).create(.Armv4, "armv4", "ARMv4 architecture", "armv4"),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv4t, "armv4t", "ARMv4t architecture", "armv4t", &[_]@This() {
+ .V4t,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv5t, "armv5t", "ARMv5t architecture", "armv5t", &[_]@This() {
+ .V4t,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv5te, "armv5te", "ARMv5te architecture", "armv5te", &[_]@This() {
+ .V4t,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv5tej, "armv5tej", "ARMv5tej architecture", "armv5tej", &[_]@This() {
+ .V4t,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv6, "armv6", "ARMv6 architecture", "armv6", &[_]@This() {
+ .V4t,
+ .Dsp,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv6j, "armv6j", "ARMv7a architecture", "armv6j", &[_]@This() {
+ .V4t,
+ .Dsp,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv6k, "armv6k", "ARMv6k architecture", "armv6k", &[_]@This() {
+ .V4t,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv6kz, "armv6kz", "ARMv6kz architecture", "armv6kz", &[_]@This() {
+ .V4t,
+ .Trustzone,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv6M, "armv6-m", "ARMv6m architecture", "armv6-m", &[_]@This() {
+ .Mclass,
+ .StrictAlign,
+ .ThumbMode,
+ .Db,
+ .V4t,
+ .Noarm,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv6sM, "armv6s-m", "ARMv6sm architecture", "armv6s-m", &[_]@This() {
+ .Mclass,
+ .StrictAlign,
+ .ThumbMode,
+ .Db,
+ .V4t,
+ .Noarm,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv6t2, "armv6t2", "ARMv6t2 architecture", "armv6t2", &[_]@This() {
+ .Thumb2,
+ .V4t,
+ .Dsp,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv7A, "armv7-a", "ARMv7a architecture", "armv7-a", &[_]@This() {
+ .Thumb2,
+ .Perfmon,
+ .Db,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Aclass,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv7eM, "armv7e-m", "ARMv7em architecture", "armv7e-m", &[_]@This() {
+ .Thumb2,
+ .Mclass,
+ .Perfmon,
+ .ThumbMode,
+ .Db,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Hwdiv,
+ .Noarm,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv7k, "armv7k", "ARMv7a architecture", "armv7k", &[_]@This() {
+ .Thumb2,
+ .Perfmon,
+ .Db,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Aclass,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv7M, "armv7-m", "ARMv7m architecture", "armv7-m", &[_]@This() {
+ .Thumb2,
+ .Mclass,
+ .Perfmon,
+ .ThumbMode,
+ .Db,
+ .V7clrex,
+ .V4t,
+ .Hwdiv,
+ .Noarm,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv7R, "armv7-r", "ARMv7r architecture", "armv7-r", &[_]@This() {
+ .Thumb2,
+ .Perfmon,
+ .Db,
+ .Dsp,
+ .Rclass,
+ .V7clrex,
+ .V4t,
+ .Hwdiv,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv7s, "armv7s", "ARMv7a architecture", "armv7s", &[_]@This() {
+ .Thumb2,
+ .Perfmon,
+ .Db,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Aclass,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv7ve, "armv7ve", "ARMv7ve architecture", "armv7ve", &[_]@This() {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv8A, "armv8-a", "ARMv8a architecture", "armv8-a", &[_]@This() {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv8Mbase, "armv8-m.base", "ARMv8mBaseline architecture", "armv8-m.base", &[_]@This() {
+ .Mclass,
+ .StrictAlign,
+ .ThumbMode,
+ .Db,
+ .Msecext8,
+ .V7clrex,
+ .V4t,
+ .Hwdiv,
+ .Noarm,
+ .AcquireRelease,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv8Mmain, "armv8-m.main", "ARMv8mMainline architecture", "armv8-m.main", &[_]@This() {
+ .Thumb2,
+ .Mclass,
+ .Perfmon,
+ .ThumbMode,
+ .Db,
+ .Msecext8,
+ .V7clrex,
+ .V4t,
+ .Hwdiv,
+ .Noarm,
+ .AcquireRelease,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv8R, "armv8-r", "ARMv8r architecture", "armv8-r", &[_]@This() {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Dfb,
+ .Dsp,
+ .Rclass,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .AcquireRelease,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv81A, "armv8.1-a", "ARMv81a architecture", "armv8.1-a", &[_]@This() {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv81Mmain, "armv8.1-m.main", "ARMv81mMainline architecture", "armv8.1-m.main", &[_]@This() {
+ .Thumb2,
+ .Mclass,
+ .Perfmon,
+ .ThumbMode,
+ .Db,
+ .Msecext8,
+ .Ras,
+ .V7clrex,
+ .V4t,
+ .Hwdiv,
+ .Noarm,
+ .Lob,
+ .AcquireRelease,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv82A, "armv8.2-a", "ARMv82a architecture", "armv8.2-a", &[_]@This() {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Ras,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv83A, "armv8.3-a", "ARMv83a architecture", "armv8.3-a", &[_]@This() {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Ras,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv84A, "armv8.4-a", "ARMv84a architecture", "armv8.4-a", &[_]@This() {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Ras,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Armv85A, "armv8.5-a", "ARMv85a architecture", "armv8.5-a", &[_]@This() {
+ .Thumb2,
+ .Mp,
+ .Perfmon,
+ .Sb,
+ .Db,
+ .Crc,
+ .Fp16,
+ .Ras,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .Hwdiv,
+ .HwdivArm,
+ .Aclass,
+ .Trustzone,
+ .AcquireRelease,
+ }),
+ FeatureInfo(@This()).create(.Msecext8, "8msecext", "Enable support for ARMv8-M Security Extensions", "8msecext"),
+ FeatureInfo(@This()).create(.Aclass, "aclass", "Is application profile ('A' series)", "aclass"),
+ FeatureInfo(@This()).createWithSubfeatures(.Aes, "aes", "Enable AES support", "aes", &[_]@This() {
+ .Fpregs,
+ .D32,
+ }),
+ FeatureInfo(@This()).create(.AcquireRelease, "acquire-release", "Has v8 acquire/release (lda/ldaex etc) instructions", "acquire-release"),
+ FeatureInfo(@This()).create(.AvoidMovsShop, "avoid-movs-shop", "Avoid movs instructions with shifter operand", "avoid-movs-shop"),
+ FeatureInfo(@This()).create(.AvoidPartialCpsr, "avoid-partial-cpsr", "Avoid CPSR partial update for OOO execution", "avoid-partial-cpsr"),
+ FeatureInfo(@This()).create(.Crc, "crc", "Enable support for CRC instructions", "crc"),
+ FeatureInfo(@This()).create(.CheapPredicableCpsr, "cheap-predicable-cpsr", "Disable +1 predication cost for instructions updating CPSR", "cheap-predicable-cpsr"),
+ FeatureInfo(@This()).create(.VldnAlign, "vldn-align", "Check for VLDn unaligned access", "vldn-align"),
+ FeatureInfo(@This()).createWithSubfeatures(.Crypto, "crypto", "Enable support for Cryptography extensions", "crypto", &[_]@This() {
+ .Fpregs,
+ .D32,
+ }),
+ FeatureInfo(@This()).create(.D32, "d32", "Extend FP to 32 double registers", "d32"),
+ FeatureInfo(@This()).create(.Db, "db", "Has data barrier (dmb/dsb) instructions", "db"),
+ FeatureInfo(@This()).create(.Dfb, "dfb", "Has full data barrier (dfb) instruction", "dfb"),
+ FeatureInfo(@This()).create(.Dsp, "dsp", "Supports DSP instructions in ARM and/or Thumb2", "dsp"),
+ FeatureInfo(@This()).create(.DontWidenVmovs, "dont-widen-vmovs", "Don't widen VMOVS to VMOVD", "dont-widen-vmovs"),
+ FeatureInfo(@This()).createWithSubfeatures(.Dotprod, "dotprod", "Enable support for dot product instructions", "dotprod", &[_]@This() {
+ .Fpregs,
+ .D32,
+ }),
+ FeatureInfo(@This()).create(.ExecuteOnly, "execute-only", "Enable the generation of execute only code.", "execute-only"),
+ FeatureInfo(@This()).create(.ExpandFpMlx, "expand-fp-mlx", "Expand VFP/NEON MLA/MLS instructions", "expand-fp-mlx"),
+ FeatureInfo(@This()).create(.Fp16, "fp16", "Enable half-precision floating point", "fp16"),
+ FeatureInfo(@This()).createWithSubfeatures(.Fp16fml, "fp16fml", "Enable full half-precision floating point fml instructions", "fp16fml", &[_]@This() {
+ .Fp16,
+ .Fpregs,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Fp64, "fp64", "Floating point unit supports double precision", "fp64", &[_]@This() {
+ .Fpregs,
+ }),
+ FeatureInfo(@This()).create(.Fpao, "fpao", "Enable fast computation of positive address offsets", "fpao"),
+ FeatureInfo(@This()).createWithSubfeatures(.FpArmv8, "fp-armv8", "Enable ARMv8 FP", "fp-armv8", &[_]@This() {
+ .Fp16,
+ .Fpregs,
+ .D32,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.FpArmv8d16, "fp-armv8d16", "Enable ARMv8 FP with only 16 d-registers", "fp-armv8d16", &[_]@This() {
+ .Fp16,
+ .Fpregs,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.FpArmv8d16sp, "fp-armv8d16sp", "Enable ARMv8 FP with only 16 d-registers and no double precision", "fp-armv8d16sp", &[_]@This() {
+ .Fp16,
+ .Fpregs,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.FpArmv8sp, "fp-armv8sp", "Enable ARMv8 FP with no double precision", "fp-armv8sp", &[_]@This() {
+ .Fp16,
+ .Fpregs,
+ .D32,
+ }),
+ FeatureInfo(@This()).create(.Fpregs, "fpregs", "Enable FP registers", "fpregs"),
+ FeatureInfo(@This()).createWithSubfeatures(.Fpregs16, "fpregs16", "Enable 16-bit FP registers", "fpregs16", &[_]@This() {
+ .Fpregs,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Fpregs64, "fpregs64", "Enable 64-bit FP registers", "fpregs64", &[_]@This() {
+ .Fpregs,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Fullfp16, "fullfp16", "Enable full half-precision floating point", "fullfp16", &[_]@This() {
+ .Fp16,
+ .Fpregs,
+ }),
+ FeatureInfo(@This()).create(.FuseAes, "fuse-aes", "CPU fuses AES crypto operations", "fuse-aes"),
+ FeatureInfo(@This()).create(.FuseLiterals, "fuse-literals", "CPU fuses literal generation operations", "fuse-literals"),
+ FeatureInfo(@This()).create(.HwdivArm, "hwdiv-arm", "Enable divide instructions in ARM mode", "hwdiv-arm"),
+ FeatureInfo(@This()).create(.Hwdiv, "hwdiv", "Enable divide instructions in Thumb", "hwdiv"),
+ FeatureInfo(@This()).create(.NoBranchPredictor, "no-branch-predictor", "Has no branch predictor", "no-branch-predictor"),
+ FeatureInfo(@This()).create(.RetAddrStack, "ret-addr-stack", "Has return address stack", "ret-addr-stack"),
+ FeatureInfo(@This()).create(.Slowfpvmlx, "slowfpvmlx", "Disable VFP / NEON MAC instructions", "slowfpvmlx"),
+ FeatureInfo(@This()).create(.VmlxHazards, "vmlx-hazards", "Has VMLx hazards", "vmlx-hazards"),
+ FeatureInfo(@This()).create(.Lob, "lob", "Enable Low Overhead Branch extensions", "lob"),
+ FeatureInfo(@This()).create(.LongCalls, "long-calls", "Generate calls via indirect call instructions", "long-calls"),
+ FeatureInfo(@This()).create(.Mclass, "mclass", "Is microcontroller profile ('M' series)", "mclass"),
+ FeatureInfo(@This()).create(.Mp, "mp", "Supports Multiprocessing extension", "mp"),
+ FeatureInfo(@This()).create(.Mve1beat, "mve1beat", "Model MVE instructions as a 1 beat per tick architecture", "mve1beat"),
+ FeatureInfo(@This()).create(.Mve2beat, "mve2beat", "Model MVE instructions as a 2 beats per tick architecture", "mve2beat"),
+ FeatureInfo(@This()).create(.Mve4beat, "mve4beat", "Model MVE instructions as a 4 beats per tick architecture", "mve4beat"),
+ FeatureInfo(@This()).create(.MuxedUnits, "muxed-units", "Has muxed AGU and NEON/FPU", "muxed-units"),
+ FeatureInfo(@This()).createWithSubfeatures(.Neon, "neon", "Enable NEON instructions", "neon", &[_]@This() {
+ .Fpregs,
+ .D32,
+ }),
+ FeatureInfo(@This()).create(.Neonfp, "neonfp", "Use NEON for single precision FP", "neonfp"),
+ FeatureInfo(@This()).create(.NeonFpmovs, "neon-fpmovs", "Convert VMOVSR, VMOVRS, VMOVS to NEON", "neon-fpmovs"),
+ FeatureInfo(@This()).create(.NaclTrap, "nacl-trap", "NaCl trap", "nacl-trap"),
+ FeatureInfo(@This()).create(.Noarm, "noarm", "Does not support ARM mode execution", "noarm"),
+ FeatureInfo(@This()).create(.NoMovt, "no-movt", "Don't use movt/movw pairs for 32-bit imms", "no-movt"),
+ FeatureInfo(@This()).create(.NoNegImmediates, "no-neg-immediates", "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.", "no-neg-immediates"),
+ FeatureInfo(@This()).create(.DisablePostraScheduler, "disable-postra-scheduler", "Don't schedule again after register allocation", "disable-postra-scheduler"),
+ FeatureInfo(@This()).create(.NonpipelinedVfp, "nonpipelined-vfp", "VFP instructions are not pipelined", "nonpipelined-vfp"),
+ FeatureInfo(@This()).create(.Perfmon, "perfmon", "Enable support for Performance Monitor extensions", "perfmon"),
+ FeatureInfo(@This()).create(.Bit32, "32bit", "Prefer 32-bit Thumb instrs", "32bit"),
+ FeatureInfo(@This()).create(.PreferIshst, "prefer-ishst", "Prefer ISHST barriers", "prefer-ishst"),
+ FeatureInfo(@This()).create(.LoopAlign, "loop-align", "Prefer 32-bit alignment for loops", "loop-align"),
+ FeatureInfo(@This()).create(.PreferVmovsr, "prefer-vmovsr", "Prefer VMOVSR", "prefer-vmovsr"),
+ FeatureInfo(@This()).create(.ProfUnpr, "prof-unpr", "Is profitable to unpredicate", "prof-unpr"),
+ FeatureInfo(@This()).create(.Ras, "ras", "Enable Reliability, Availability and Serviceability extensions", "ras"),
+ FeatureInfo(@This()).create(.Rclass, "rclass", "Is realtime profile ('R' series)", "rclass"),
+ FeatureInfo(@This()).create(.ReadTpHard, "read-tp-hard", "Reading thread pointer from register", "read-tp-hard"),
+ FeatureInfo(@This()).create(.ReserveR9, "reserve-r9", "Reserve R9, making it unavailable as GPR", "reserve-r9"),
+ FeatureInfo(@This()).create(.Sb, "sb", "Enable v8.5a Speculation Barrier", "sb"),
+ FeatureInfo(@This()).createWithSubfeatures(.Sha2, "sha2", "Enable SHA1 and SHA256 support", "sha2", &[_]@This() {
+ .Fpregs,
+ .D32,
+ }),
+ FeatureInfo(@This()).create(.SlowFpBrcc, "slow-fp-brcc", "FP compare + branch is slow", "slow-fp-brcc"),
+ FeatureInfo(@This()).create(.SlowLoadDSubreg, "slow-load-D-subreg", "Loading into D subregs is slow", "slow-load-D-subreg"),
+ FeatureInfo(@This()).create(.SlowOddReg, "slow-odd-reg", "VLDM/VSTM starting with an odd register is slow", "slow-odd-reg"),
+ FeatureInfo(@This()).create(.SlowVdup32, "slow-vdup32", "Has slow VDUP32 - prefer VMOV", "slow-vdup32"),
+ FeatureInfo(@This()).create(.SlowVgetlni32, "slow-vgetlni32", "Has slow VGETLNi32 - prefer VMOV", "slow-vgetlni32"),
+ FeatureInfo(@This()).createWithSubfeatures(.SplatVfpNeon, "splat-vfp-neon", "Splat register from VFP to NEON", "splat-vfp-neon", &[_]@This() {
+ .DontWidenVmovs,
+ }),
+ FeatureInfo(@This()).create(.StrictAlign, "strict-align", "Disallow all unaligned memory access", "strict-align"),
+ FeatureInfo(@This()).create(.Thumb2, "thumb2", "Enable Thumb2 instructions", "thumb2"),
+ FeatureInfo(@This()).create(.Trustzone, "trustzone", "Enable support for TrustZone security extensions", "trustzone"),
+ FeatureInfo(@This()).create(.UseAa, "use-aa", "Use alias analysis during codegen", "use-aa"),
+ FeatureInfo(@This()).create(.UseMisched, "use-misched", "Use the MachineScheduler", "use-misched"),
+ FeatureInfo(@This()).create(.WideStrideVfp, "wide-stride-vfp", "Use a wide stride when allocating VFP registers", "wide-stride-vfp"),
+ FeatureInfo(@This()).create(.V7clrex, "v7clrex", "Has v7 clrex instruction", "v7clrex"),
+ FeatureInfo(@This()).createWithSubfeatures(.Vfp2, "vfp2", "Enable VFP2 instructions", "vfp2", &[_]@This() {
+ .Fpregs,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Vfp2sp, "vfp2sp", "Enable VFP2 instructions with no double precision", "vfp2sp", &[_]@This() {
+ .Fpregs,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Vfp3, "vfp3", "Enable VFP3 instructions", "vfp3", &[_]@This() {
+ .Fpregs,
+ .D32,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Vfp3d16, "vfp3d16", "Enable VFP3 instructions with only 16 d-registers", "vfp3d16", &[_]@This() {
+ .Fpregs,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Vfp3d16sp, "vfp3d16sp", "Enable VFP3 instructions with only 16 d-registers and no double precision", "vfp3d16sp", &[_]@This() {
+ .Fpregs,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Vfp3sp, "vfp3sp", "Enable VFP3 instructions with no double precision", "vfp3sp", &[_]@This() {
+ .Fpregs,
+ .D32,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Vfp4, "vfp4", "Enable VFP4 instructions", "vfp4", &[_]@This() {
+ .Fp16,
+ .Fpregs,
+ .D32,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Vfp4d16, "vfp4d16", "Enable VFP4 instructions with only 16 d-registers", "vfp4d16", &[_]@This() {
+ .Fp16,
+ .Fpregs,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Vfp4d16sp, "vfp4d16sp", "Enable VFP4 instructions with only 16 d-registers and no double precision", "vfp4d16sp", &[_]@This() {
+ .Fp16,
+ .Fpregs,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Vfp4sp, "vfp4sp", "Enable VFP4 instructions with no double precision", "vfp4sp", &[_]@This() {
+ .Fp16,
+ .Fpregs,
+ .D32,
+ }),
+ FeatureInfo(@This()).create(.VmlxForwarding, "vmlx-forwarding", "Has multiplier accumulator forwarding", "vmlx-forwarding"),
+ FeatureInfo(@This()).createWithSubfeatures(.Virtualization, "virtualization", "Supports Virtualization extension", "virtualization", &[_]@This() {
+ .HwdivArm,
+ .Hwdiv,
+ }),
+ FeatureInfo(@This()).create(.Zcz, "zcz", "Has zero-cycle zeroing instructions", "zcz"),
+ FeatureInfo(@This()).createWithSubfeatures(.Mvefp, "mve.fp", "Support M-Class Vector Extension with integer and floating ops", "mve.fp", &[_]@This() {
+ .Thumb2,
+ .Perfmon,
+ .Fp16,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Mve, "mve", "Support M-Class Vector Extension with integer ops", "mve", &[_]@This() {
+ .Thumb2,
+ .Perfmon,
+ .Dsp,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ }),
+ FeatureInfo(@This()).create(.V4t, "v4t", "Support ARM v4T instructions", "v4t"),
+ FeatureInfo(@This()).createWithSubfeatures(.V5te, "v5te", "Support ARM v5TE, v5TEj, and v5TExp instructions", "v5te", &[_]@This() {
+ .V4t,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.V5t, "v5t", "Support ARM v5T instructions", "v5t", &[_]@This() {
+ .V4t,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.V6k, "v6k", "Support ARM v6k instructions", "v6k", &[_]@This() {
+ .V4t,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.V6m, "v6m", "Support ARM v6M instructions", "v6m", &[_]@This() {
+ .V4t,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.V6, "v6", "Support ARM v6 instructions", "v6", &[_]@This() {
+ .V4t,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.V6t2, "v6t2", "Support ARM v6t2 instructions", "v6t2", &[_]@This() {
+ .Thumb2,
+ .V4t,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.V7, "v7", "Support ARM v7 instructions", "v7", &[_]@This() {
+ .V7clrex,
+ .V4t,
+ .Perfmon,
+ .Thumb2,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.V8m, "v8m", "Support ARM v8M Baseline instructions", "v8m", &[_]@This() {
+ .V4t,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.V8mmain, "v8m.main", "Support ARM v8M Mainline instructions", "v8m.main", &[_]@This() {
+ .V7clrex,
+ .V4t,
+ .Perfmon,
+ .Thumb2,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.V8, "v8", "Support ARM v8 instructions", "v8", &[_]@This() {
+ .Thumb2,
+ .Perfmon,
+ .V7clrex,
+ .V4t,
+ .AcquireRelease,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.V81mmain, "v8.1m.main", "Support ARM v8-1M Mainline instructions", "v8.1m.main", &[_]@This() {
+ .V7clrex,
+ .V4t,
+ .Perfmon,
+ .Thumb2,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.V81a, "v8.1a", "Support ARM v8.1a instructions", "v8.1a", &[_]@This() {
+ .Thumb2,
+ .Perfmon,
+ .V7clrex,
+ .V4t,
+ .AcquireRelease,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.V82a, "v8.2a", "Support ARM v8.2a instructions", "v8.2a", &[_]@This() {
+ .Thumb2,
+ .Perfmon,
+ .V7clrex,
+ .V4t,
+ .AcquireRelease,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.V83a, "v8.3a", "Support ARM v8.3a instructions", "v8.3a", &[_]@This() {
+ .Thumb2,
+ .Perfmon,
+ .V7clrex,
+ .V4t,
+ .AcquireRelease,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.V84a, "v8.4a", "Support ARM v8.4a instructions", "v8.4a", &[_]@This() {
+ .Thumb2,
+ .Perfmon,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .AcquireRelease,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.V85a, "v8.5a", "Support ARM v8.5a instructions", "v8.5a", &[_]@This() {
+ .Thumb2,
+ .Perfmon,
+ .Sb,
+ .V7clrex,
+ .V4t,
+ .Fpregs,
+ .D32,
+ .AcquireRelease,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Iwmmxt, "iwmmxt", "ARMv5te architecture", "iwmmxt", &[_]@This() {
+ .V4t,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Iwmmxt2, "iwmmxt2", "ARMv5te architecture", "iwmmxt2", &[_]@This() {
+ .V4t,
+ }),
+ FeatureInfo(@This()).create(.SoftFloat, "soft-float", "Use software floating point features.", "soft-float"),
+ FeatureInfo(@This()).create(.ThumbMode, "thumb-mode", "Thumb mode", "thumb-mode"),
+ FeatureInfo(@This()).create(.A5, "a5", "Cortex-A5 ARM processors", "a5"),
+ FeatureInfo(@This()).create(.A7, "a7", "Cortex-A7 ARM processors", "a7"),
+ FeatureInfo(@This()).create(.A8, "a8", "Cortex-A8 ARM processors", "a8"),
+ FeatureInfo(@This()).create(.A9, "a9", "Cortex-A9 ARM processors", "a9"),
+ FeatureInfo(@This()).create(.A12, "a12", "Cortex-A12 ARM processors", "a12"),
+ FeatureInfo(@This()).create(.A15, "a15", "Cortex-A15 ARM processors", "a15"),
+ FeatureInfo(@This()).create(.A17, "a17", "Cortex-A17 ARM processors", "a17"),
+ FeatureInfo(@This()).create(.A32, "a32", "Cortex-A32 ARM processors", "a32"),
+ FeatureInfo(@This()).create(.A35, "a35", "Cortex-A35 ARM processors", "a35"),
+ FeatureInfo(@This()).create(.A53, "a53", "Cortex-A53 ARM processors", "a53"),
+ FeatureInfo(@This()).create(.A55, "a55", "Cortex-A55 ARM processors", "a55"),
+ FeatureInfo(@This()).create(.A57, "a57", "Cortex-A57 ARM processors", "a57"),
+ FeatureInfo(@This()).create(.A72, "a72", "Cortex-A72 ARM processors", "a72"),
+ FeatureInfo(@This()).create(.A73, "a73", "Cortex-A73 ARM processors", "a73"),
+ FeatureInfo(@This()).create(.A75, "a75", "Cortex-A75 ARM processors", "a75"),
+ FeatureInfo(@This()).create(.A76, "a76", "Cortex-A76 ARM processors", "a76"),
+ FeatureInfo(@This()).createWithSubfeatures(.Exynos, "exynos", "Samsung Exynos processors", "exynos", &[_]@This() {
+ .Zcz,
+ .SlowVdup32,
+ .SlowVgetlni32,
+ .DontWidenVmovs,
+ .Crc,
+ .FuseAes,
+ .WideStrideVfp,
+ .ProfUnpr,
+ .Slowfpvmlx,
+ .SlowFpBrcc,
+ .FuseLiterals,
+ .Fpregs,
+ .D32,
+ .ExpandFpMlx,
+ .Hwdiv,
+ .HwdivArm,
+ .RetAddrStack,
+ .UseAa,
+ }),
+ FeatureInfo(@This()).create(.Krait, "krait", "Qualcomm Krait processors", "krait"),
+ FeatureInfo(@This()).create(.Kryo, "kryo", "Qualcomm Kryo processors", "kryo"),
+ FeatureInfo(@This()).create(.M3, "m3", "Cortex-M3 ARM processors", "m3"),
+ FeatureInfo(@This()).create(.R4, "r4", "Cortex-R4 ARM processors", "r4"),
+ FeatureInfo(@This()).create(.R5, "r5", "Cortex-R5 ARM processors", "r5"),
+ FeatureInfo(@This()).create(.R7, "r7", "Cortex-R7 ARM processors", "r7"),
+ FeatureInfo(@This()).create(.R52, "r52", "Cortex-R52 ARM processors", "r52"),
+ FeatureInfo(@This()).create(.Swift, "swift", "Swift ARM processors", "swift"),
+ FeatureInfo(@This()).createWithSubfeatures(.Xscale, "xscale", "ARMv5te architecture", "xscale", &[_]@This() {
+ .V4t,
+ }),
+ };
+};
lib/std/target/feature/AvrFeature.zig
@@ -0,0 +1,230 @@
+const FeatureInfo = @import("std").target.feature.FeatureInfo;
+
+pub const AvrFeature = enum {
+ Avr0,
+ Avr1,
+ Avr2,
+ Avr3,
+ Avr4,
+ Avr5,
+ Avr6,
+ Avr25,
+ Avr31,
+ Avr35,
+ Avr51,
+ Avrtiny,
+ Xmega,
+ Xmegau,
+ Addsubiw,
+ Break,
+ Des,
+ Eijmpcall,
+ Elpm,
+ Elpmx,
+ Ijmpcall,
+ Jmpcall,
+ Lpm,
+ Lpmx,
+ Movw,
+ Mul,
+ Rmw,
+ Spm,
+ Spmx,
+ Sram,
+ Special,
+ Smallstack,
+ Tinyencoding,
+
+ pub fn getInfo(self: @This()) FeatureInfo {
+ return feature_infos[@enumToInt(self)];
+ }
+
+ pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
+ FeatureInfo(@This()).create(.Avr0, "avr0", "The device is a part of the avr0 family", "avr0"),
+ FeatureInfo(@This()).createWithSubfeatures(.Avr1, "avr1", "The device is a part of the avr1 family", "avr1", &[_]@This() {
+ .Lpm,
+ .Avr0,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avr2, "avr2", "The device is a part of the avr2 family", "avr2", &[_]@This() {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avr3, "avr3", "The device is a part of the avr3 family", "avr3", &[_]@This() {
+ .Ijmpcall,
+ .Sram,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avr4, "avr4", "The device is a part of the avr4 family", "avr4", &[_]@This() {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avr5, "avr5", "The device is a part of the avr5 family", "avr5", &[_]@This() {
+ .Ijmpcall,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avr6, "avr6", "The device is a part of the avr6 family", "avr6", &[_]@This() {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avr25, "avr25", "The device is a part of the avr25 family", "avr25", &[_]@This() {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Addsubiw,
+ .Lpm,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avr31, "avr31", "The device is a part of the avr31 family", "avr31", &[_]@This() {
+ .Ijmpcall,
+ .Sram,
+ .Elpm,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avr35, "avr35", "The device is a part of the avr35 family", "avr35", &[_]@This() {
+ .Ijmpcall,
+ .Movw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avr51, "avr51", "The device is a part of the avr51 family", "avr51", &[_]@This() {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avrtiny, "avrtiny", "The device is a part of the avrtiny family", "avrtiny", &[_]@This() {
+ .Break,
+ .Tinyencoding,
+ .Avr0,
+ .Sram,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Xmega, "xmega", "The device is a part of the xmega family", "xmega", &[_]@This() {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Xmegau, "xmegau", "The device is a part of the xmegau family", "xmegau", &[_]@This() {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Spm,
+ .Elpm,
+ .Lpmx,
+ .Spmx,
+ .Avr0,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ }),
+ FeatureInfo(@This()).create(.Addsubiw, "addsubiw", "Enable 16-bit register-immediate addition and subtraction instructions", "addsubiw"),
+ FeatureInfo(@This()).create(.Break, "break", "The device supports the `BREAK` debugging instruction", "break"),
+ FeatureInfo(@This()).create(.Des, "des", "The device supports the `DES k` encryption instruction", "des"),
+ FeatureInfo(@This()).create(.Eijmpcall, "eijmpcall", "The device supports the `EIJMP`/`EICALL` instructions", "eijmpcall"),
+ FeatureInfo(@This()).create(.Elpm, "elpm", "The device supports the ELPM instruction", "elpm"),
+ FeatureInfo(@This()).create(.Elpmx, "elpmx", "The device supports the `ELPM Rd, Z[+]` instructions", "elpmx"),
+ FeatureInfo(@This()).create(.Ijmpcall, "ijmpcall", "The device supports `IJMP`/`ICALL`instructions", "ijmpcall"),
+ FeatureInfo(@This()).create(.Jmpcall, "jmpcall", "The device supports the `JMP` and `CALL` instructions", "jmpcall"),
+ FeatureInfo(@This()).create(.Lpm, "lpm", "The device supports the `LPM` instruction", "lpm"),
+ FeatureInfo(@This()).create(.Lpmx, "lpmx", "The device supports the `LPM Rd, Z[+]` instruction", "lpmx"),
+ FeatureInfo(@This()).create(.Movw, "movw", "The device supports the 16-bit MOVW instruction", "movw"),
+ FeatureInfo(@This()).create(.Mul, "mul", "The device supports the multiplication instructions", "mul"),
+ FeatureInfo(@This()).create(.Rmw, "rmw", "The device supports the read-write-modify instructions: XCH, LAS, LAC, LAT", "rmw"),
+ FeatureInfo(@This()).create(.Spm, "spm", "The device supports the `SPM` instruction", "spm"),
+ FeatureInfo(@This()).create(.Spmx, "spmx", "The device supports the `SPM Z+` instruction", "spmx"),
+ FeatureInfo(@This()).create(.Sram, "sram", "The device has random access memory", "sram"),
+ FeatureInfo(@This()).createWithSubfeatures(.Special, "special", "Enable use of the entire instruction set - used for debugging", "special", &[_]@This() {
+ .Ijmpcall,
+ .Elpmx,
+ .Movw,
+ .Eijmpcall,
+ .Mul,
+ .Rmw,
+ .Sram,
+ .Break,
+ .Elpm,
+ .Spm,
+ .Lpmx,
+ .Spmx,
+ .Jmpcall,
+ .Addsubiw,
+ .Lpm,
+ .Des,
+ }),
+ FeatureInfo(@This()).create(.Smallstack, "smallstack", "The device has an 8-bit stack pointer", "smallstack"),
+ FeatureInfo(@This()).create(.Tinyencoding, "tinyencoding", "The device has Tiny core specific instruction encodings", "tinyencoding"),
+ };
+};
lib/std/target/feature/BpfFeature.zig
@@ -0,0 +1,17 @@
+const FeatureInfo = @import("std").target.feature.FeatureInfo;
+
+pub const BpfFeature = enum {
+ Alu32,
+ Dummy,
+ Dwarfris,
+
+ pub fn getInfo(self: @This()) FeatureInfo {
+ return feature_infos[@enumToInt(self)];
+ }
+
+ pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
+ FeatureInfo(@This()).create(.Alu32, "alu32", "Enable ALU32 instructions", "alu32"),
+ FeatureInfo(@This()).create(.Dummy, "dummy", "unused feature", "dummy"),
+ FeatureInfo(@This()).create(.Dwarfris, "dwarfris", "Disable MCAsmInfo DwarfUsesRelocationsAcrossSections", "dwarfris"),
+ };
+};
lib/std/target/feature/empty.zig
@@ -0,0 +1,5 @@
+const FeatureInfo = @import("std").target.feature.FeatureInfo;
+
+pub const EmptyFeature = enum {
+ pub const feature_infos = [0]FeatureInfo(@This()) {};
+}
lib/std/target/feature/HexagonFeature.zig
@@ -0,0 +1,76 @@
+const FeatureInfo = @import("std").target.feature.FeatureInfo;
+
+pub const HexagonFeature = enum {
+ V5,
+ V55,
+ V60,
+ V62,
+ V65,
+ V66,
+ Hvx,
+ HvxLength64b,
+ HvxLength128b,
+ Hvxv60,
+ Hvxv62,
+ Hvxv65,
+ Hvxv66,
+ Zreg,
+ Duplex,
+ LongCalls,
+ Mem_noshuf,
+ Memops,
+ Nvj,
+ Nvs,
+ NoreturnStackElim,
+ Packets,
+ ReservedR19,
+ SmallData,
+
+ pub fn getInfo(self: @This()) FeatureInfo {
+ return feature_infos[@enumToInt(self)];
+ }
+
+ pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
+ FeatureInfo(@This()).create(.V5, "v5", "Enable Hexagon V5 architecture", "v5"),
+ FeatureInfo(@This()).create(.V55, "v55", "Enable Hexagon V55 architecture", "v55"),
+ FeatureInfo(@This()).create(.V60, "v60", "Enable Hexagon V60 architecture", "v60"),
+ FeatureInfo(@This()).create(.V62, "v62", "Enable Hexagon V62 architecture", "v62"),
+ FeatureInfo(@This()).create(.V65, "v65", "Enable Hexagon V65 architecture", "v65"),
+ FeatureInfo(@This()).create(.V66, "v66", "Enable Hexagon V66 architecture", "v66"),
+ FeatureInfo(@This()).create(.Hvx, "hvx", "Hexagon HVX instructions", "hvx"),
+ FeatureInfo(@This()).createWithSubfeatures(.HvxLength64b, "hvx-length64b", "Hexagon HVX 64B instructions", "hvx-length64b", &[_]@This() {
+ .Hvx,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.HvxLength128b, "hvx-length128b", "Hexagon HVX 128B instructions", "hvx-length128b", &[_]@This() {
+ .Hvx,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Hvxv60, "hvxv60", "Hexagon HVX instructions", "hvxv60", &[_]@This() {
+ .Hvx,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Hvxv62, "hvxv62", "Hexagon HVX instructions", "hvxv62", &[_]@This() {
+ .Hvx,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Hvxv65, "hvxv65", "Hexagon HVX instructions", "hvxv65", &[_]@This() {
+ .Hvx,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Hvxv66, "hvxv66", "Hexagon HVX instructions", "hvxv66", &[_]@This() {
+ .Hvx,
+ .Zreg,
+ }),
+ FeatureInfo(@This()).create(.Zreg, "zreg", "Hexagon ZReg extension instructions", "zreg"),
+ FeatureInfo(@This()).create(.Duplex, "duplex", "Enable generation of duplex instruction", "duplex"),
+ FeatureInfo(@This()).create(.LongCalls, "long-calls", "Use constant-extended calls", "long-calls"),
+ FeatureInfo(@This()).create(.Mem_noshuf, "mem_noshuf", "Supports mem_noshuf feature", "mem_noshuf"),
+ FeatureInfo(@This()).create(.Memops, "memops", "Use memop instructions", "memops"),
+ FeatureInfo(@This()).createWithSubfeatures(.Nvj, "nvj", "Support for new-value jumps", "nvj", &[_]@This() {
+ .Packets,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Nvs, "nvs", "Support for new-value stores", "nvs", &[_]@This() {
+ .Packets,
+ }),
+ FeatureInfo(@This()).create(.NoreturnStackElim, "noreturn-stack-elim", "Eliminate stack allocation in a noreturn function when possible", "noreturn-stack-elim"),
+ FeatureInfo(@This()).create(.Packets, "packets", "Support for instruction packets", "packets"),
+ FeatureInfo(@This()).create(.ReservedR19, "reserved-r19", "Reserve register R19", "reserved-r19"),
+ FeatureInfo(@This()).create(.SmallData, "small-data", "Allow GP-relative addressing of global variables", "small-data"),
+ };
+};
lib/std/target/feature/MipsFeature.zig
@@ -0,0 +1,238 @@
+const FeatureInfo = @import("std").target.feature.FeatureInfo;
+
+pub const MipsFeature = enum {
+ Abs2008,
+ Crc,
+ Cnmips,
+ Dsp,
+ Dspr2,
+ Dspr3,
+ Eva,
+ Fp64,
+ Fpxx,
+ Ginv,
+ Gp64,
+ LongCalls,
+ Msa,
+ Mt,
+ Nomadd4,
+ Micromips,
+ Mips1,
+ Mips2,
+ Mips3,
+ Mips3_32,
+ Mips3_32r2,
+ Mips4,
+ Mips4_32,
+ Mips4_32r2,
+ Mips5,
+ Mips5_32r2,
+ Mips16,
+ Mips32,
+ Mips32r2,
+ Mips32r3,
+ Mips32r5,
+ Mips32r6,
+ Mips64,
+ Mips64r2,
+ Mips64r3,
+ Mips64r5,
+ Mips64r6,
+ Nan2008,
+ Noabicalls,
+ Nooddspreg,
+ Ptr64,
+ SingleFloat,
+ SoftFloat,
+ Sym32,
+ UseIndirectJumpHazard,
+ UseTccInDiv,
+ Vfpu,
+ Virt,
+ Xgot,
+ P5600,
+
+ pub fn getInfo(self: @This()) FeatureInfo {
+ return feature_infos[@enumToInt(self)];
+ }
+
+ pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
+ FeatureInfo(@This()).create(.Abs2008, "abs2008", "Disable IEEE 754-2008 abs.fmt mode", "abs2008"),
+ FeatureInfo(@This()).create(.Crc, "crc", "Mips R6 CRC ASE", "crc"),
+ FeatureInfo(@This()).createWithSubfeatures(.Cnmips, "cnmips", "Octeon cnMIPS Support", "cnmips", &[_]@This() {
+ .Mips3_32,
+ .Fp64,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Gp64,
+ .Mips5_32r2,
+ }),
+ FeatureInfo(@This()).create(.Dsp, "dsp", "Mips DSP ASE", "dsp"),
+ FeatureInfo(@This()).createWithSubfeatures(.Dspr2, "dspr2", "Mips DSP-R2 ASE", "dspr2", &[_]@This() {
+ .Dsp,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Dspr3, "dspr3", "Mips DSP-R3 ASE", "dspr3", &[_]@This() {
+ .Dsp,
+ }),
+ FeatureInfo(@This()).create(.Eva, "eva", "Mips EVA ASE", "eva"),
+ FeatureInfo(@This()).create(.Fp64, "fp64", "Support 64-bit FP registers", "fp64"),
+ FeatureInfo(@This()).create(.Fpxx, "fpxx", "Support for FPXX", "fpxx"),
+ FeatureInfo(@This()).create(.Ginv, "ginv", "Mips Global Invalidate ASE", "ginv"),
+ FeatureInfo(@This()).create(.Gp64, "gp64", "General Purpose Registers are 64-bit wide", "gp64"),
+ FeatureInfo(@This()).create(.LongCalls, "long-calls", "Disable use of the jal instruction", "long-calls"),
+ FeatureInfo(@This()).create(.Msa, "msa", "Mips MSA ASE", "msa"),
+ FeatureInfo(@This()).create(.Mt, "mt", "Mips MT ASE", "mt"),
+ FeatureInfo(@This()).create(.Nomadd4, "nomadd4", "Disable 4-operand madd.fmt and related instructions", "nomadd4"),
+ FeatureInfo(@This()).create(.Micromips, "micromips", "microMips mode", "micromips"),
+ FeatureInfo(@This()).create(.Mips1, "mips1", "Mips I ISA Support [highly experimental]", "mips1"),
+ FeatureInfo(@This()).createWithSubfeatures(.Mips2, "mips2", "Mips II ISA Support [highly experimental]", "mips2", &[_]@This() {
+ .Mips1,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Mips3, "mips3", "MIPS III ISA Support [highly experimental]", "mips3", &[_]@This() {
+ .Mips3_32,
+ .Fp64,
+ .Mips3_32r2,
+ .Mips1,
+ .Gp64,
+ }),
+ FeatureInfo(@This()).create(.Mips3_32, "mips3_32", "Subset of MIPS-III that is also in MIPS32 [highly experimental]", "mips3_32"),
+ FeatureInfo(@This()).create(.Mips3_32r2, "mips3_32r2", "Subset of MIPS-III that is also in MIPS32r2 [highly experimental]", "mips3_32r2"),
+ FeatureInfo(@This()).createWithSubfeatures(.Mips4, "mips4", "MIPS IV ISA Support", "mips4", &[_]@This() {
+ .Mips3_32,
+ .Fp64,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Gp64,
+ }),
+ FeatureInfo(@This()).create(.Mips4_32, "mips4_32", "Subset of MIPS-IV that is also in MIPS32 [highly experimental]", "mips4_32"),
+ FeatureInfo(@This()).create(.Mips4_32r2, "mips4_32r2", "Subset of MIPS-IV that is also in MIPS32r2 [highly experimental]", "mips4_32r2"),
+ FeatureInfo(@This()).createWithSubfeatures(.Mips5, "mips5", "MIPS V ISA Support [highly experimental]", "mips5", &[_]@This() {
+ .Mips3_32,
+ .Fp64,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Gp64,
+ .Mips5_32r2,
+ }),
+ FeatureInfo(@This()).create(.Mips5_32r2, "mips5_32r2", "Subset of MIPS-V that is also in MIPS32r2 [highly experimental]", "mips5_32r2"),
+ FeatureInfo(@This()).create(.Mips16, "mips16", "Mips16 mode", "mips16"),
+ FeatureInfo(@This()).createWithSubfeatures(.Mips32, "mips32", "Mips32 ISA Support", "mips32", &[_]@This() {
+ .Mips3_32,
+ .Mips4_32,
+ .Mips1,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Mips32r2, "mips32r2", "Mips32r2 ISA Support", "mips32r2", &[_]@This() {
+ .Mips3_32,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Mips5_32r2,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Mips32r3, "mips32r3", "Mips32r3 ISA Support", "mips32r3", &[_]@This() {
+ .Mips3_32,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Mips5_32r2,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Mips32r5, "mips32r5", "Mips32r5 ISA Support", "mips32r5", &[_]@This() {
+ .Mips3_32,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Mips5_32r2,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Mips32r6, "mips32r6", "Mips32r6 ISA Support [experimental]", "mips32r6", &[_]@This() {
+ .Mips3_32,
+ .Fp64,
+ .Mips4_32r2,
+ .Abs2008,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Nan2008,
+ .Mips5_32r2,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Mips64, "mips64", "Mips64 ISA Support", "mips64", &[_]@This() {
+ .Mips3_32,
+ .Fp64,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Gp64,
+ .Mips5_32r2,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Mips64r2, "mips64r2", "Mips64r2 ISA Support", "mips64r2", &[_]@This() {
+ .Mips3_32,
+ .Fp64,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Gp64,
+ .Mips5_32r2,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Mips64r3, "mips64r3", "Mips64r3 ISA Support", "mips64r3", &[_]@This() {
+ .Mips3_32,
+ .Fp64,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Gp64,
+ .Mips5_32r2,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Mips64r5, "mips64r5", "Mips64r5 ISA Support", "mips64r5", &[_]@This() {
+ .Mips3_32,
+ .Fp64,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Gp64,
+ .Mips5_32r2,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Mips64r6, "mips64r6", "Mips64r6 ISA Support [experimental]", "mips64r6", &[_]@This() {
+ .Mips3_32,
+ .Fp64,
+ .Mips4_32r2,
+ .Abs2008,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Nan2008,
+ .Gp64,
+ .Mips5_32r2,
+ }),
+ FeatureInfo(@This()).create(.Nan2008, "nan2008", "IEEE 754-2008 NaN encoding", "nan2008"),
+ FeatureInfo(@This()).create(.Noabicalls, "noabicalls", "Disable SVR4-style position-independent code", "noabicalls"),
+ FeatureInfo(@This()).create(.Nooddspreg, "nooddspreg", "Disable odd numbered single-precision registers", "nooddspreg"),
+ FeatureInfo(@This()).create(.Ptr64, "ptr64", "Pointers are 64-bit wide", "ptr64"),
+ FeatureInfo(@This()).create(.SingleFloat, "single-float", "Only supports single precision float", "single-float"),
+ FeatureInfo(@This()).create(.SoftFloat, "soft-float", "Does not support floating point instructions", "soft-float"),
+ FeatureInfo(@This()).create(.Sym32, "sym32", "Symbols are 32 bit on Mips64", "sym32"),
+ FeatureInfo(@This()).create(.UseIndirectJumpHazard, "use-indirect-jump-hazard", "Use indirect jump guards to prevent certain speculation based attacks", "use-indirect-jump-hazard"),
+ FeatureInfo(@This()).create(.UseTccInDiv, "use-tcc-in-div", "Force the assembler to use trapping", "use-tcc-in-div"),
+ FeatureInfo(@This()).create(.Vfpu, "vfpu", "Enable vector FPU instructions", "vfpu"),
+ FeatureInfo(@This()).create(.Virt, "virt", "Mips Virtualization ASE", "virt"),
+ FeatureInfo(@This()).create(.Xgot, "xgot", "Assume 32-bit GOT", "xgot"),
+ FeatureInfo(@This()).createWithSubfeatures(.P5600, "p5600", "The P5600 Processor", "p5600", &[_]@This() {
+ .Mips3_32,
+ .Mips4_32r2,
+ .Mips3_32r2,
+ .Mips1,
+ .Mips4_32,
+ .Mips5_32r2,
+ }),
+ };
+};
lib/std/target/feature/Msp430Feature.zig
@@ -0,0 +1,19 @@
+const FeatureInfo = @import("std").target.feature.FeatureInfo;
+
+pub const Msp430Feature = enum {
+ Hwmult16,
+ Hwmult32,
+ Hwmultf5,
+ Ext,
+
+ pub fn getInfo(self: @This()) FeatureInfo {
+ return feature_infos[@enumToInt(self)];
+ }
+
+ pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
+ FeatureInfo(@This()).create(.Hwmult16, "hwmult16", "Enable 16-bit hardware multiplier", "hwmult16"),
+ FeatureInfo(@This()).create(.Hwmult32, "hwmult32", "Enable 32-bit hardware multiplier", "hwmult32"),
+ FeatureInfo(@This()).create(.Hwmultf5, "hwmultf5", "Enable F5 series hardware multiplier", "hwmultf5"),
+ FeatureInfo(@This()).create(.Ext, "ext", "Enable MSP430-X extensions", "ext"),
+ };
+};
lib/std/target/feature/NvptxFeature.zig
@@ -0,0 +1,61 @@
+const FeatureInfo = @import("std").target.feature.FeatureInfo;
+
+pub const NvptxFeature = enum {
+ Ptx32,
+ Ptx40,
+ Ptx41,
+ Ptx42,
+ Ptx43,
+ Ptx50,
+ Ptx60,
+ Ptx61,
+ Ptx63,
+ Ptx64,
+ Sm_20,
+ Sm_21,
+ Sm_30,
+ Sm_32,
+ Sm_35,
+ Sm_37,
+ Sm_50,
+ Sm_52,
+ Sm_53,
+ Sm_60,
+ Sm_61,
+ Sm_62,
+ Sm_70,
+ Sm_72,
+ Sm_75,
+
+ pub fn getInfo(self: @This()) FeatureInfo {
+ return feature_infos[@enumToInt(self)];
+ }
+
+ pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
+ FeatureInfo(@This()).create(.Ptx32, "ptx32", "Use PTX version 3.2", "ptx32"),
+ FeatureInfo(@This()).create(.Ptx40, "ptx40", "Use PTX version 4.0", "ptx40"),
+ FeatureInfo(@This()).create(.Ptx41, "ptx41", "Use PTX version 4.1", "ptx41"),
+ FeatureInfo(@This()).create(.Ptx42, "ptx42", "Use PTX version 4.2", "ptx42"),
+ FeatureInfo(@This()).create(.Ptx43, "ptx43", "Use PTX version 4.3", "ptx43"),
+ FeatureInfo(@This()).create(.Ptx50, "ptx50", "Use PTX version 5.0", "ptx50"),
+ FeatureInfo(@This()).create(.Ptx60, "ptx60", "Use PTX version 6.0", "ptx60"),
+ FeatureInfo(@This()).create(.Ptx61, "ptx61", "Use PTX version 6.1", "ptx61"),
+ FeatureInfo(@This()).create(.Ptx63, "ptx63", "Use PTX version 6.3", "ptx63"),
+ FeatureInfo(@This()).create(.Ptx64, "ptx64", "Use PTX version 6.4", "ptx64"),
+ FeatureInfo(@This()).create(.Sm_20, "sm_20", "Target SM 2.0", "sm_20"),
+ FeatureInfo(@This()).create(.Sm_21, "sm_21", "Target SM 2.1", "sm_21"),
+ FeatureInfo(@This()).create(.Sm_30, "sm_30", "Target SM 3.0", "sm_30"),
+ FeatureInfo(@This()).create(.Sm_32, "sm_32", "Target SM 3.2", "sm_32"),
+ FeatureInfo(@This()).create(.Sm_35, "sm_35", "Target SM 3.5", "sm_35"),
+ FeatureInfo(@This()).create(.Sm_37, "sm_37", "Target SM 3.7", "sm_37"),
+ FeatureInfo(@This()).create(.Sm_50, "sm_50", "Target SM 5.0", "sm_50"),
+ FeatureInfo(@This()).create(.Sm_52, "sm_52", "Target SM 5.2", "sm_52"),
+ FeatureInfo(@This()).create(.Sm_53, "sm_53", "Target SM 5.3", "sm_53"),
+ FeatureInfo(@This()).create(.Sm_60, "sm_60", "Target SM 6.0", "sm_60"),
+ FeatureInfo(@This()).create(.Sm_61, "sm_61", "Target SM 6.1", "sm_61"),
+ FeatureInfo(@This()).create(.Sm_62, "sm_62", "Target SM 6.2", "sm_62"),
+ FeatureInfo(@This()).create(.Sm_70, "sm_70", "Target SM 7.0", "sm_70"),
+ FeatureInfo(@This()).create(.Sm_72, "sm_72", "Target SM 7.2", "sm_72"),
+ FeatureInfo(@This()).create(.Sm_75, "sm_75", "Target SM 7.5", "sm_75"),
+ };
+};
lib/std/target/feature/PowerPcFeature.zig
@@ -0,0 +1,163 @@
+const FeatureInfo = @import("std").target.feature.FeatureInfo;
+
+pub const PowerPcFeature = enum {
+ Bit64,
+ Bitregs64,
+ Altivec,
+ Bpermd,
+ Booke,
+ Cmpb,
+ Crbits,
+ DirectMove,
+ E500,
+ Extdiv,
+ Fcpsgn,
+ Fpcvt,
+ Fprnd,
+ Fpu,
+ Fre,
+ Fres,
+ Frsqrte,
+ Frsqrtes,
+ Fsqrt,
+ Float128,
+ Htm,
+ HardFloat,
+ Icbt,
+ IsaV30Instructions,
+ Isel,
+ InvariantFunctionDescriptors,
+ Ldbrx,
+ Lfiwax,
+ Longcall,
+ Mfocrf,
+ Msync,
+ Power8Altivec,
+ Crypto,
+ Power8Vector,
+ Power9Altivec,
+ Power9Vector,
+ Popcntd,
+ Ppc4xx,
+ Ppc6xx,
+ PpcPostraSched,
+ PpcPreraSched,
+ PartwordAtomics,
+ Qpx,
+ Recipprec,
+ Spe,
+ Stfiwx,
+ SecurePlt,
+ SlowPopcntd,
+ TwoConstNr,
+ Vsx,
+ VectorsUseTwoUnits,
+
+ pub fn getInfo(self: @This()) FeatureInfo {
+ return feature_infos[@enumToInt(self)];
+ }
+
+ pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
+ FeatureInfo(@This()).create(.Bit64, "64bit", "Enable 64-bit instructions", "64bit"),
+ FeatureInfo(@This()).create(.Bitregs64, "64bitregs", "Enable 64-bit registers usage for ppc32 [beta]", "64bitregs"),
+ FeatureInfo(@This()).createWithSubfeatures(.Altivec, "altivec", "Enable Altivec instructions", "altivec", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).create(.Bpermd, "bpermd", "Enable the bpermd instruction", "bpermd"),
+ FeatureInfo(@This()).createWithSubfeatures(.Booke, "booke", "Enable Book E instructions", "booke", &[_]@This() {
+ .Icbt,
+ }),
+ FeatureInfo(@This()).create(.Cmpb, "cmpb", "Enable the cmpb instruction", "cmpb"),
+ FeatureInfo(@This()).create(.Crbits, "crbits", "Use condition-register bits individually", "crbits"),
+ FeatureInfo(@This()).createWithSubfeatures(.DirectMove, "direct-move", "Enable Power8 direct move instructions", "direct-move", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).create(.E500, "e500", "Enable E500/E500mc instructions", "e500"),
+ FeatureInfo(@This()).create(.Extdiv, "extdiv", "Enable extended divide instructions", "extdiv"),
+ FeatureInfo(@This()).createWithSubfeatures(.Fcpsgn, "fcpsgn", "Enable the fcpsgn instruction", "fcpsgn", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Fpcvt, "fpcvt", "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", "fpcvt", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Fprnd, "fprnd", "Enable the fri[mnpz] instructions", "fprnd", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Fpu, "fpu", "Enable classic FPU instructions", "fpu", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Fre, "fre", "Enable the fre instruction", "fre", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Fres, "fres", "Enable the fres instruction", "fres", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Frsqrte, "frsqrte", "Enable the frsqrte instruction", "frsqrte", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Frsqrtes, "frsqrtes", "Enable the frsqrtes instruction", "frsqrtes", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Fsqrt, "fsqrt", "Enable the fsqrt instruction", "fsqrt", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Float128, "float128", "Enable the __float128 data type for IEEE-754R Binary128.", "float128", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).create(.Htm, "htm", "Enable Hardware Transactional Memory instructions", "htm"),
+ FeatureInfo(@This()).create(.HardFloat, "hard-float", "Enable floating-point instructions", "hard-float"),
+ FeatureInfo(@This()).create(.Icbt, "icbt", "Enable icbt instruction", "icbt"),
+ FeatureInfo(@This()).create(.IsaV30Instructions, "isa-v30-instructions", "Enable instructions added in ISA 3.0.", "isa-v30-instructions"),
+ FeatureInfo(@This()).create(.Isel, "isel", "Enable the isel instruction", "isel"),
+ FeatureInfo(@This()).create(.InvariantFunctionDescriptors, "invariant-function-descriptors", "Assume function descriptors are invariant", "invariant-function-descriptors"),
+ FeatureInfo(@This()).create(.Ldbrx, "ldbrx", "Enable the ldbrx instruction", "ldbrx"),
+ FeatureInfo(@This()).createWithSubfeatures(.Lfiwax, "lfiwax", "Enable the lfiwax instruction", "lfiwax", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).create(.Longcall, "longcall", "Always use indirect calls", "longcall"),
+ FeatureInfo(@This()).create(.Mfocrf, "mfocrf", "Enable the MFOCRF instruction", "mfocrf"),
+ FeatureInfo(@This()).createWithSubfeatures(.Msync, "msync", "Has only the msync instruction instead of sync", "msync", &[_]@This() {
+ .Icbt,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Power8Altivec, "power8-altivec", "Enable POWER8 Altivec instructions", "power8-altivec", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Crypto, "crypto", "Enable POWER8 Crypto instructions", "crypto", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Power8Vector, "power8-vector", "Enable POWER8 vector instructions", "power8-vector", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Power9Altivec, "power9-altivec", "Enable POWER9 Altivec instructions", "power9-altivec", &[_]@This() {
+ .IsaV30Instructions,
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Power9Vector, "power9-vector", "Enable POWER9 vector instructions", "power9-vector", &[_]@This() {
+ .IsaV30Instructions,
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).create(.Popcntd, "popcntd", "Enable the popcnt[dw] instructions", "popcntd"),
+ FeatureInfo(@This()).create(.Ppc4xx, "ppc4xx", "Enable PPC 4xx instructions", "ppc4xx"),
+ FeatureInfo(@This()).create(.Ppc6xx, "ppc6xx", "Enable PPC 6xx instructions", "ppc6xx"),
+ FeatureInfo(@This()).create(.PpcPostraSched, "ppc-postra-sched", "Use PowerPC post-RA scheduling strategy", "ppc-postra-sched"),
+ FeatureInfo(@This()).create(.PpcPreraSched, "ppc-prera-sched", "Use PowerPC pre-RA scheduling strategy", "ppc-prera-sched"),
+ FeatureInfo(@This()).create(.PartwordAtomics, "partword-atomics", "Enable l[bh]arx and st[bh]cx.", "partword-atomics"),
+ FeatureInfo(@This()).createWithSubfeatures(.Qpx, "qpx", "Enable QPX instructions", "qpx", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).create(.Recipprec, "recipprec", "Assume higher precision reciprocal estimates", "recipprec"),
+ FeatureInfo(@This()).createWithSubfeatures(.Spe, "spe", "Enable SPE instructions", "spe", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Stfiwx, "stfiwx", "Enable the stfiwx instruction", "stfiwx", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).create(.SecurePlt, "secure-plt", "Enable secure plt mode", "secure-plt"),
+ FeatureInfo(@This()).create(.SlowPopcntd, "slow-popcntd", "Has slow popcnt[dw] instructions", "slow-popcntd"),
+ FeatureInfo(@This()).create(.TwoConstNr, "two-const-nr", "Requires two constant Newton-Raphson computation", "two-const-nr"),
+ FeatureInfo(@This()).createWithSubfeatures(.Vsx, "vsx", "Enable VSX instructions", "vsx", &[_]@This() {
+ .HardFloat,
+ }),
+ FeatureInfo(@This()).create(.VectorsUseTwoUnits, "vectors-use-two-units", "Vectors use two units", "vectors-use-two-units"),
+ };
+};
lib/std/target/feature/RiscVFeature.zig
@@ -0,0 +1,31 @@
+const FeatureInfo = @import("std").target.feature.FeatureInfo;
+
+pub const RiscVFeature = enum {
+ Bit64,
+ E,
+ RvcHints,
+ Relax,
+ A,
+ C,
+ D,
+ F,
+ M,
+
+ pub fn getInfo(self: @This()) FeatureInfo {
+ return feature_infos[@enumToInt(self)];
+ }
+
+ pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
+ FeatureInfo(@This()).create(.Bit64, "64bit", "Implements RV64", "64bit"),
+ FeatureInfo(@This()).create(.E, "e", "Implements RV32E (provides 16 rather than 32 GPRs)", "e"),
+ FeatureInfo(@This()).create(.RvcHints, "rvc-hints", "Enable RVC Hint Instructions.", "rvc-hints"),
+ FeatureInfo(@This()).create(.Relax, "relax", "Enable Linker relaxation.", "relax"),
+ FeatureInfo(@This()).create(.A, "a", "'A' (Atomic Instructions)", "a"),
+ FeatureInfo(@This()).create(.C, "c", "'C' (Compressed Instructions)", "c"),
+ FeatureInfo(@This()).createWithSubfeatures(.D, "d", "'D' (Double-Precision Floating-Point)", "d", &[_]@This() {
+ .F,
+ }),
+ FeatureInfo(@This()).create(.F, "f", "'F' (Single-Precision Floating-Point)", "f"),
+ FeatureInfo(@This()).create(.M, "m", "'M' (Integer Multiplication and Division)", "m"),
+ };
+};
lib/std/target/feature/SparcFeature.zig
@@ -0,0 +1,49 @@
+const FeatureInfo = @import("std").target.feature.FeatureInfo;
+
+pub const SparcFeature = enum {
+ Detectroundchange,
+ HardQuadFloat,
+ Leon,
+ NoFmuls,
+ NoFsmuld,
+ Leonpwrpsr,
+ SoftFloat,
+ SoftMulDiv,
+ DeprecatedV8,
+ V9,
+ Vis,
+ Vis2,
+ Vis3,
+ Fixallfdivsqrt,
+ Insertnopload,
+ Hasleoncasa,
+ Leoncyclecounter,
+ Hasumacsmac,
+ Popc,
+
+ pub fn getInfo(self: @This()) FeatureInfo {
+ return feature_infos[@enumToInt(self)];
+ }
+
+ pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
+ FeatureInfo(@This()).create(.Detectroundchange, "detectroundchange", "LEON3 erratum detection: Detects any rounding mode change request: use only the round-to-nearest rounding mode", "detectroundchange"),
+ FeatureInfo(@This()).create(.HardQuadFloat, "hard-quad-float", "Enable quad-word floating point instructions", "hard-quad-float"),
+ FeatureInfo(@This()).create(.Leon, "leon", "Enable LEON extensions", "leon"),
+ FeatureInfo(@This()).create(.NoFmuls, "no-fmuls", "Disable the fmuls instruction.", "no-fmuls"),
+ FeatureInfo(@This()).create(.NoFsmuld, "no-fsmuld", "Disable the fsmuld instruction.", "no-fsmuld"),
+ FeatureInfo(@This()).create(.Leonpwrpsr, "leonpwrpsr", "Enable the PWRPSR instruction", "leonpwrpsr"),
+ FeatureInfo(@This()).create(.SoftFloat, "soft-float", "Use software emulation for floating point", "soft-float"),
+ FeatureInfo(@This()).create(.SoftMulDiv, "soft-mul-div", "Use software emulation for integer multiply and divide", "soft-mul-div"),
+ FeatureInfo(@This()).create(.DeprecatedV8, "deprecated-v8", "Enable deprecated V8 instructions in V9 mode", "deprecated-v8"),
+ FeatureInfo(@This()).create(.V9, "v9", "Enable SPARC-V9 instructions", "v9"),
+ FeatureInfo(@This()).create(.Vis, "vis", "Enable UltraSPARC Visual Instruction Set extensions", "vis"),
+ FeatureInfo(@This()).create(.Vis2, "vis2", "Enable Visual Instruction Set extensions II", "vis2"),
+ FeatureInfo(@This()).create(.Vis3, "vis3", "Enable Visual Instruction Set extensions III", "vis3"),
+ FeatureInfo(@This()).create(.Fixallfdivsqrt, "fixallfdivsqrt", "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store", "fixallfdivsqrt"),
+ FeatureInfo(@This()).create(.Insertnopload, "insertnopload", "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction", "insertnopload"),
+ FeatureInfo(@This()).create(.Hasleoncasa, "hasleoncasa", "Enable CASA instruction for LEON3 and LEON4 processors", "hasleoncasa"),
+ FeatureInfo(@This()).create(.Leoncyclecounter, "leoncyclecounter", "Use the Leon cycle counter register", "leoncyclecounter"),
+ FeatureInfo(@This()).create(.Hasumacsmac, "hasumacsmac", "Enable UMAC and SMAC for LEON3 and LEON4 processors", "hasumacsmac"),
+ FeatureInfo(@This()).create(.Popc, "popc", "Use the popc (population count) instruction", "popc"),
+ };
+};
lib/std/target/feature/SystemZFeature.zig
@@ -0,0 +1,81 @@
+const FeatureInfo = @import("std").target.feature.FeatureInfo;
+
+pub const SystemZFeature = enum {
+ DfpPackedConversion,
+ DfpZonedConversion,
+ DeflateConversion,
+ DistinctOps,
+ EnhancedDat2,
+ EnhancedSort,
+ ExecutionHint,
+ FpExtension,
+ FastSerialization,
+ GuardedStorage,
+ HighWord,
+ InsertReferenceBitsMultiple,
+ InterlockedAccess1,
+ LoadAndTrap,
+ LoadAndZeroRightmostByte,
+ LoadStoreOnCond,
+ LoadStoreOnCond2,
+ MessageSecurityAssistExtension3,
+ MessageSecurityAssistExtension4,
+ MessageSecurityAssistExtension5,
+ MessageSecurityAssistExtension7,
+ MessageSecurityAssistExtension8,
+ MessageSecurityAssistExtension9,
+ MiscellaneousExtensions,
+ MiscellaneousExtensions2,
+ MiscellaneousExtensions3,
+ PopulationCount,
+ ProcessorAssist,
+ ResetReferenceBitsMultiple,
+ TransactionalExecution,
+ Vector,
+ VectorEnhancements1,
+ VectorEnhancements2,
+ VectorPackedDecimal,
+ VectorPackedDecimalEnhancement,
+
+ pub fn getInfo(self: @This()) FeatureInfo {
+ return feature_infos[@enumToInt(self)];
+ }
+
+ pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
+ FeatureInfo(@This()).create(.DfpPackedConversion, "dfp-packed-conversion", "Assume that the DFP packed-conversion facility is installed", "dfp-packed-conversion"),
+ FeatureInfo(@This()).create(.DfpZonedConversion, "dfp-zoned-conversion", "Assume that the DFP zoned-conversion facility is installed", "dfp-zoned-conversion"),
+ FeatureInfo(@This()).create(.DeflateConversion, "deflate-conversion", "Assume that the deflate-conversion facility is installed", "deflate-conversion"),
+ FeatureInfo(@This()).create(.DistinctOps, "distinct-ops", "Assume that the distinct-operands facility is installed", "distinct-ops"),
+ FeatureInfo(@This()).create(.EnhancedDat2, "enhanced-dat-2", "Assume that the enhanced-DAT facility 2 is installed", "enhanced-dat-2"),
+ FeatureInfo(@This()).create(.EnhancedSort, "enhanced-sort", "Assume that the enhanced-sort facility is installed", "enhanced-sort"),
+ FeatureInfo(@This()).create(.ExecutionHint, "execution-hint", "Assume that the execution-hint facility is installed", "execution-hint"),
+ FeatureInfo(@This()).create(.FpExtension, "fp-extension", "Assume that the floating-point extension facility is installed", "fp-extension"),
+ FeatureInfo(@This()).create(.FastSerialization, "fast-serialization", "Assume that the fast-serialization facility is installed", "fast-serialization"),
+ FeatureInfo(@This()).create(.GuardedStorage, "guarded-storage", "Assume that the guarded-storage facility is installed", "guarded-storage"),
+ FeatureInfo(@This()).create(.HighWord, "high-word", "Assume that the high-word facility is installed", "high-word"),
+ FeatureInfo(@This()).create(.InsertReferenceBitsMultiple, "insert-reference-bits-multiple", "Assume that the insert-reference-bits-multiple facility is installed", "insert-reference-bits-multiple"),
+ FeatureInfo(@This()).create(.InterlockedAccess1, "interlocked-access1", "Assume that interlocked-access facility 1 is installed", "interlocked-access1"),
+ FeatureInfo(@This()).create(.LoadAndTrap, "load-and-trap", "Assume that the load-and-trap facility is installed", "load-and-trap"),
+ FeatureInfo(@This()).create(.LoadAndZeroRightmostByte, "load-and-zero-rightmost-byte", "Assume that the load-and-zero-rightmost-byte facility is installed", "load-and-zero-rightmost-byte"),
+ FeatureInfo(@This()).create(.LoadStoreOnCond, "load-store-on-cond", "Assume that the load/store-on-condition facility is installed", "load-store-on-cond"),
+ FeatureInfo(@This()).create(.LoadStoreOnCond2, "load-store-on-cond-2", "Assume that the load/store-on-condition facility 2 is installed", "load-store-on-cond-2"),
+ FeatureInfo(@This()).create(.MessageSecurityAssistExtension3, "message-security-assist-extension3", "Assume that the message-security-assist extension facility 3 is installed", "message-security-assist-extension3"),
+ FeatureInfo(@This()).create(.MessageSecurityAssistExtension4, "message-security-assist-extension4", "Assume that the message-security-assist extension facility 4 is installed", "message-security-assist-extension4"),
+ FeatureInfo(@This()).create(.MessageSecurityAssistExtension5, "message-security-assist-extension5", "Assume that the message-security-assist extension facility 5 is installed", "message-security-assist-extension5"),
+ FeatureInfo(@This()).create(.MessageSecurityAssistExtension7, "message-security-assist-extension7", "Assume that the message-security-assist extension facility 7 is installed", "message-security-assist-extension7"),
+ FeatureInfo(@This()).create(.MessageSecurityAssistExtension8, "message-security-assist-extension8", "Assume that the message-security-assist extension facility 8 is installed", "message-security-assist-extension8"),
+ FeatureInfo(@This()).create(.MessageSecurityAssistExtension9, "message-security-assist-extension9", "Assume that the message-security-assist extension facility 9 is installed", "message-security-assist-extension9"),
+ FeatureInfo(@This()).create(.MiscellaneousExtensions, "miscellaneous-extensions", "Assume that the miscellaneous-extensions facility is installed", "miscellaneous-extensions"),
+ FeatureInfo(@This()).create(.MiscellaneousExtensions2, "miscellaneous-extensions-2", "Assume that the miscellaneous-extensions facility 2 is installed", "miscellaneous-extensions-2"),
+ FeatureInfo(@This()).create(.MiscellaneousExtensions3, "miscellaneous-extensions-3", "Assume that the miscellaneous-extensions facility 3 is installed", "miscellaneous-extensions-3"),
+ FeatureInfo(@This()).create(.PopulationCount, "population-count", "Assume that the population-count facility is installed", "population-count"),
+ FeatureInfo(@This()).create(.ProcessorAssist, "processor-assist", "Assume that the processor-assist facility is installed", "processor-assist"),
+ FeatureInfo(@This()).create(.ResetReferenceBitsMultiple, "reset-reference-bits-multiple", "Assume that the reset-reference-bits-multiple facility is installed", "reset-reference-bits-multiple"),
+ FeatureInfo(@This()).create(.TransactionalExecution, "transactional-execution", "Assume that the transactional-execution facility is installed", "transactional-execution"),
+ FeatureInfo(@This()).create(.Vector, "vector", "Assume that the vectory facility is installed", "vector"),
+ FeatureInfo(@This()).create(.VectorEnhancements1, "vector-enhancements-1", "Assume that the vector enhancements facility 1 is installed", "vector-enhancements-1"),
+ FeatureInfo(@This()).create(.VectorEnhancements2, "vector-enhancements-2", "Assume that the vector enhancements facility 2 is installed", "vector-enhancements-2"),
+ FeatureInfo(@This()).create(.VectorPackedDecimal, "vector-packed-decimal", "Assume that the vector packed decimal facility is installed", "vector-packed-decimal"),
+ FeatureInfo(@This()).create(.VectorPackedDecimalEnhancement, "vector-packed-decimal-enhancement", "Assume that the vector packed decimal enhancement facility is installed", "vector-packed-decimal-enhancement"),
+ };
+};
lib/std/target/feature/WebAssemblyFeature.zig
@@ -0,0 +1,33 @@
+const FeatureInfo = @import("std").target.feature.FeatureInfo;
+
+pub const WebAssemblyFeature = enum {
+ Atomics,
+ BulkMemory,
+ ExceptionHandling,
+ Multivalue,
+ MutableGlobals,
+ NontrappingFptoint,
+ Simd128,
+ SignExt,
+ TailCall,
+ UnimplementedSimd128,
+
+ pub fn getInfo(self: @This()) FeatureInfo {
+ return feature_infos[@enumToInt(self)];
+ }
+
+ pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
+ FeatureInfo(@This()).create(.Atomics, "atomics", "Enable Atomics", "atomics"),
+ FeatureInfo(@This()).create(.BulkMemory, "bulk-memory", "Enable bulk memory operations", "bulk-memory"),
+ FeatureInfo(@This()).create(.ExceptionHandling, "exception-handling", "Enable Wasm exception handling", "exception-handling"),
+ FeatureInfo(@This()).create(.Multivalue, "multivalue", "Enable multivalue blocks, instructions, and functions", "multivalue"),
+ FeatureInfo(@This()).create(.MutableGlobals, "mutable-globals", "Enable mutable globals", "mutable-globals"),
+ FeatureInfo(@This()).create(.NontrappingFptoint, "nontrapping-fptoint", "Enable non-trapping float-to-int conversion operators", "nontrapping-fptoint"),
+ FeatureInfo(@This()).create(.Simd128, "simd128", "Enable 128-bit SIMD", "simd128"),
+ FeatureInfo(@This()).create(.SignExt, "sign-ext", "Enable sign extension operators", "sign-ext"),
+ FeatureInfo(@This()).create(.TailCall, "tail-call", "Enable tail call instructions", "tail-call"),
+ FeatureInfo(@This()).createWithSubfeatures(.UnimplementedSimd128, "unimplemented-simd128", "Enable 128-bit SIMD not yet implemented in engines", "unimplemented-simd128", &[_]@This() {
+ .Simd128,
+ }),
+ };
+};
lib/std/target/feature/X86Feature.zig
@@ -0,0 +1,342 @@
+const FeatureInfo = @import("std").target.feature.FeatureInfo;
+
+pub const X86Feature = enum {
+ Dnow3,
+ Dnowa3,
+ Bit64,
+ Adx,
+ Aes,
+ Avx,
+ Avx2,
+ Avx512f,
+ Avx512bf16,
+ Avx512bitalg,
+ Bmi,
+ Bmi2,
+ Avx512bw,
+ Branchfusion,
+ Avx512cd,
+ Cldemote,
+ Clflushopt,
+ Clwb,
+ Clzero,
+ Cmov,
+ Cx8,
+ Cx16,
+ Avx512dq,
+ Mpx,
+ Enqcmd,
+ Avx512er,
+ Ermsb,
+ F16c,
+ Fma,
+ Fma4,
+ Fsgsbase,
+ Fxsr,
+ Fast11bytenop,
+ Fast15bytenop,
+ FastBextr,
+ FastHops,
+ FastLzcnt,
+ FastPartialYmmOrZmmWrite,
+ FastShldRotate,
+ FastScalarFsqrt,
+ FastScalarShiftMasks,
+ FastVariableShuffle,
+ FastVectorFsqrt,
+ FastVectorShiftMasks,
+ Gfni,
+ FastGather,
+ Avx512ifma,
+ Invpcid,
+ Sahf,
+ LeaSp,
+ LeaUsesAg,
+ Lwp,
+ Lzcnt,
+ FalseDepsLzcntTzcnt,
+ Mmx,
+ Movbe,
+ Movdir64b,
+ Movdiri,
+ Mwaitx,
+ Macrofusion,
+ MergeToThreewayBranch,
+ Nopl,
+ Pclmul,
+ Pconfig,
+ Avx512pf,
+ Pku,
+ Popcnt,
+ FalseDepsPopcnt,
+ Prefetchwt1,
+ Prfchw,
+ Ptwrite,
+ PadShortFunctions,
+ Prefer128Bit,
+ Prefer256Bit,
+ Rdpid,
+ Rdrnd,
+ Rdseed,
+ Rtm,
+ Retpoline,
+ RetpolineExternalThunk,
+ RetpolineIndirectBranches,
+ RetpolineIndirectCalls,
+ Sgx,
+ Sha,
+ Shstk,
+ Sse,
+ Sse2,
+ Sse3,
+ Sse4a,
+ Sse41,
+ Sse42,
+ SseUnalignedMem,
+ Ssse3,
+ Slow3opsLea,
+ IdivlToDivb,
+ IdivqToDivl,
+ SlowIncdec,
+ SlowLea,
+ SlowPmaddwd,
+ SlowPmulld,
+ SlowShld,
+ SlowTwoMemOps,
+ SlowUnalignedMem16,
+ SlowUnalignedMem32,
+ SoftFloat,
+ Tbm,
+ UseAa,
+ Vaes,
+ Avx512vbmi,
+ Avx512vbmi2,
+ Avx512vl,
+ Avx512vnni,
+ Avx512vp2intersect,
+ Vpclmulqdq,
+ Avx512vpopcntdq,
+ Waitpkg,
+ Wbnoinvd,
+ X87,
+ Xop,
+ Xsave,
+ Xsavec,
+ Xsaveopt,
+ Xsaves,
+ BitMode16,
+ BitMode32,
+ BitMode64,
+
+ pub fn getInfo(self: @This()) FeatureInfo {
+ return feature_infos[@enumToInt(self)];
+ }
+
+ pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
+ FeatureInfo(@This()).createWithSubfeatures(.Dnow3, "3dnow", "Enable 3DNow! instructions", "3dnow", &[_]@This() {
+ .Mmx,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Dnowa3, "3dnowa", "Enable 3DNow! Athlon instructions", "3dnowa", &[_]@This() {
+ .Mmx,
+ }),
+ FeatureInfo(@This()).create(.Bit64, "64bit", "Support 64-bit instructions", "64bit"),
+ FeatureInfo(@This()).create(.Adx, "adx", "Support ADX instructions", "adx"),
+ FeatureInfo(@This()).createWithSubfeatures(.Aes, "aes", "Enable AES instructions", "aes", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avx, "avx", "Enable AVX instructions", "avx", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avx2, "avx2", "Enable AVX2 instructions", "avx2", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avx512f, "avx512f", "Enable AVX-512 instructions", "avx512f", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avx512bf16, "avx512bf16", "Support bfloat16 floating point", "avx512bf16", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avx512bitalg, "avx512bitalg", "Enable AVX-512 Bit Algorithms", "avx512bitalg", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).create(.Bmi, "bmi", "Support BMI instructions", "bmi"),
+ FeatureInfo(@This()).create(.Bmi2, "bmi2", "Support BMI2 instructions", "bmi2"),
+ FeatureInfo(@This()).createWithSubfeatures(.Avx512bw, "avx512bw", "Enable AVX-512 Byte and Word Instructions", "avx512bw", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).create(.Branchfusion, "branchfusion", "CMP/TEST can be fused with conditional branches", "branchfusion"),
+ FeatureInfo(@This()).createWithSubfeatures(.Avx512cd, "avx512cd", "Enable AVX-512 Conflict Detection Instructions", "avx512cd", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).create(.Cldemote, "cldemote", "Enable Cache Demote", "cldemote"),
+ FeatureInfo(@This()).create(.Clflushopt, "clflushopt", "Flush A Cache Line Optimized", "clflushopt"),
+ FeatureInfo(@This()).create(.Clwb, "clwb", "Cache Line Write Back", "clwb"),
+ FeatureInfo(@This()).create(.Clzero, "clzero", "Enable Cache Line Zero", "clzero"),
+ FeatureInfo(@This()).create(.Cmov, "cmov", "Enable conditional move instructions", "cmov"),
+ FeatureInfo(@This()).create(.Cx8, "cx8", "Support CMPXCHG8B instructions", "cx8"),
+ FeatureInfo(@This()).createWithSubfeatures(.Cx16, "cx16", "64-bit with cmpxchg16b", "cx16", &[_]@This() {
+ .Cx8,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avx512dq, "avx512dq", "Enable AVX-512 Doubleword and Quadword Instructions", "avx512dq", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).create(.Mpx, "mpx", "Deprecated. Support MPX instructions", "mpx"),
+ FeatureInfo(@This()).create(.Enqcmd, "enqcmd", "Has ENQCMD instructions", "enqcmd"),
+ FeatureInfo(@This()).createWithSubfeatures(.Avx512er, "avx512er", "Enable AVX-512 Exponential and Reciprocal Instructions", "avx512er", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).create(.Ermsb, "ermsb", "REP MOVS/STOS are fast", "ermsb"),
+ FeatureInfo(@This()).createWithSubfeatures(.F16c, "f16c", "Support 16-bit floating point conversion instructions", "f16c", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Fma, "fma", "Enable three-operand fused multiple-add", "fma", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Fma4, "fma4", "Enable four-operand fused multiple-add", "fma4", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).create(.Fsgsbase, "fsgsbase", "Support FS/GS Base instructions", "fsgsbase"),
+ FeatureInfo(@This()).create(.Fxsr, "fxsr", "Support fxsave/fxrestore instructions", "fxsr"),
+ FeatureInfo(@This()).create(.Fast11bytenop, "fast-11bytenop", "Target can quickly decode up to 11 byte NOPs", "fast-11bytenop"),
+ FeatureInfo(@This()).create(.Fast15bytenop, "fast-15bytenop", "Target can quickly decode up to 15 byte NOPs", "fast-15bytenop"),
+ FeatureInfo(@This()).create(.FastBextr, "fast-bextr", "Indicates that the BEXTR instruction is implemented as a single uop with good throughput", "fast-bextr"),
+ FeatureInfo(@This()).createWithSubfeatures(.FastHops, "fast-hops", "Prefer horizontal vector math instructions (haddp, phsub, etc.) over normal vector instructions with shuffles", "fast-hops", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).create(.FastLzcnt, "fast-lzcnt", "LZCNT instructions are as fast as most simple integer ops", "fast-lzcnt"),
+ FeatureInfo(@This()).create(.FastPartialYmmOrZmmWrite, "fast-partial-ymm-or-zmm-write", "Partial writes to YMM/ZMM registers are fast", "fast-partial-ymm-or-zmm-write"),
+ FeatureInfo(@This()).create(.FastShldRotate, "fast-shld-rotate", "SHLD can be used as a faster rotate", "fast-shld-rotate"),
+ FeatureInfo(@This()).create(.FastScalarFsqrt, "fast-scalar-fsqrt", "Scalar SQRT is fast (disable Newton-Raphson)", "fast-scalar-fsqrt"),
+ FeatureInfo(@This()).create(.FastScalarShiftMasks, "fast-scalar-shift-masks", "Prefer a left/right scalar logical shift pair over a shift+and pair", "fast-scalar-shift-masks"),
+ FeatureInfo(@This()).create(.FastVariableShuffle, "fast-variable-shuffle", "Shuffles with variable masks are fast", "fast-variable-shuffle"),
+ FeatureInfo(@This()).create(.FastVectorFsqrt, "fast-vector-fsqrt", "Vector SQRT is fast (disable Newton-Raphson)", "fast-vector-fsqrt"),
+ FeatureInfo(@This()).create(.FastVectorShiftMasks, "fast-vector-shift-masks", "Prefer a left/right vector logical shift pair over a shift+and pair", "fast-vector-shift-masks"),
+ FeatureInfo(@This()).createWithSubfeatures(.Gfni, "gfni", "Enable Galois Field Arithmetic Instructions", "gfni", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).create(.FastGather, "fast-gather", "Indicates if gather is reasonably fast", "fast-gather"),
+ FeatureInfo(@This()).createWithSubfeatures(.Avx512ifma, "avx512ifma", "Enable AVX-512 Integer Fused Multiple-Add", "avx512ifma", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).create(.Invpcid, "invpcid", "Invalidate Process-Context Identifier", "invpcid"),
+ FeatureInfo(@This()).create(.Sahf, "sahf", "Support LAHF and SAHF instructions", "sahf"),
+ FeatureInfo(@This()).create(.LeaSp, "lea-sp", "Use LEA for adjusting the stack pointer", "lea-sp"),
+ FeatureInfo(@This()).create(.LeaUsesAg, "lea-uses-ag", "LEA instruction needs inputs at AG stage", "lea-uses-ag"),
+ FeatureInfo(@This()).create(.Lwp, "lwp", "Enable LWP instructions", "lwp"),
+ FeatureInfo(@This()).create(.Lzcnt, "lzcnt", "Support LZCNT instruction", "lzcnt"),
+ FeatureInfo(@This()).create(.FalseDepsLzcntTzcnt, "false-deps-lzcnt-tzcnt", "LZCNT/TZCNT have a false dependency on dest register", "false-deps-lzcnt-tzcnt"),
+ FeatureInfo(@This()).create(.Mmx, "mmx", "Enable MMX instructions", "mmx"),
+ FeatureInfo(@This()).create(.Movbe, "movbe", "Support MOVBE instruction", "movbe"),
+ FeatureInfo(@This()).create(.Movdir64b, "movdir64b", "Support movdir64b instruction", "movdir64b"),
+ FeatureInfo(@This()).create(.Movdiri, "movdiri", "Support movdiri instruction", "movdiri"),
+ FeatureInfo(@This()).create(.Mwaitx, "mwaitx", "Enable MONITORX/MWAITX timer functionality", "mwaitx"),
+ FeatureInfo(@This()).create(.Macrofusion, "macrofusion", "Various instructions can be fused with conditional branches", "macrofusion"),
+ FeatureInfo(@This()).create(.MergeToThreewayBranch, "merge-to-threeway-branch", "Merge branches to a three-way conditional branch", "merge-to-threeway-branch"),
+ FeatureInfo(@This()).create(.Nopl, "nopl", "Enable NOPL instruction", "nopl"),
+ FeatureInfo(@This()).createWithSubfeatures(.Pclmul, "pclmul", "Enable packed carry-less multiplication instructions", "pclmul", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).create(.Pconfig, "pconfig", "platform configuration instruction", "pconfig"),
+ FeatureInfo(@This()).createWithSubfeatures(.Avx512pf, "avx512pf", "Enable AVX-512 PreFetch Instructions", "avx512pf", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).create(.Pku, "pku", "Enable protection keys", "pku"),
+ FeatureInfo(@This()).create(.Popcnt, "popcnt", "Support POPCNT instruction", "popcnt"),
+ FeatureInfo(@This()).create(.FalseDepsPopcnt, "false-deps-popcnt", "POPCNT has a false dependency on dest register", "false-deps-popcnt"),
+ FeatureInfo(@This()).create(.Prefetchwt1, "prefetchwt1", "Prefetch with Intent to Write and T1 Hint", "prefetchwt1"),
+ FeatureInfo(@This()).create(.Prfchw, "prfchw", "Support PRFCHW instructions", "prfchw"),
+ FeatureInfo(@This()).create(.Ptwrite, "ptwrite", "Support ptwrite instruction", "ptwrite"),
+ FeatureInfo(@This()).create(.PadShortFunctions, "pad-short-functions", "Pad short functions", "pad-short-functions"),
+ FeatureInfo(@This()).create(.Prefer128Bit, "prefer-128-bit", "Prefer 128-bit AVX instructions", "prefer-128-bit"),
+ FeatureInfo(@This()).create(.Prefer256Bit, "prefer-256-bit", "Prefer 256-bit AVX instructions", "prefer-256-bit"),
+ FeatureInfo(@This()).create(.Rdpid, "rdpid", "Support RDPID instructions", "rdpid"),
+ FeatureInfo(@This()).create(.Rdrnd, "rdrnd", "Support RDRAND instruction", "rdrnd"),
+ FeatureInfo(@This()).create(.Rdseed, "rdseed", "Support RDSEED instruction", "rdseed"),
+ FeatureInfo(@This()).create(.Rtm, "rtm", "Support RTM instructions", "rtm"),
+ FeatureInfo(@This()).createWithSubfeatures(.Retpoline, "retpoline", "Remove speculation of indirect branches from the generated code, either by avoiding them entirely or lowering them with a speculation blocking construct", "retpoline", &[_]@This() {
+ .RetpolineIndirectBranches,
+ .RetpolineIndirectCalls,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.RetpolineExternalThunk, "retpoline-external-thunk", "When lowering an indirect call or branch using a `retpoline`, rely on the specified user provided thunk rather than emitting one ourselves. Only has effect when combined with some other retpoline feature", "retpoline-external-thunk", &[_]@This() {
+ .RetpolineIndirectCalls,
+ }),
+ FeatureInfo(@This()).create(.RetpolineIndirectBranches, "retpoline-indirect-branches", "Remove speculation of indirect branches from the generated code", "retpoline-indirect-branches"),
+ FeatureInfo(@This()).create(.RetpolineIndirectCalls, "retpoline-indirect-calls", "Remove speculation of indirect calls from the generated code", "retpoline-indirect-calls"),
+ FeatureInfo(@This()).create(.Sgx, "sgx", "Enable Software Guard Extensions", "sgx"),
+ FeatureInfo(@This()).createWithSubfeatures(.Sha, "sha", "Enable SHA instructions", "sha", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).create(.Shstk, "shstk", "Support CET Shadow-Stack instructions", "shstk"),
+ FeatureInfo(@This()).create(.Sse, "sse", "Enable SSE instructions", "sse"),
+ FeatureInfo(@This()).createWithSubfeatures(.Sse2, "sse2", "Enable SSE2 instructions", "sse2", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Sse3, "sse3", "Enable SSE3 instructions", "sse3", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Sse4a, "sse4a", "Support SSE 4a instructions", "sse4a", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Sse41, "sse4.1", "Enable SSE 4.1 instructions", "sse4.1", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Sse42, "sse4.2", "Enable SSE 4.2 instructions", "sse4.2", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).create(.SseUnalignedMem, "sse-unaligned-mem", "Allow unaligned memory operands with SSE instructions", "sse-unaligned-mem"),
+ FeatureInfo(@This()).createWithSubfeatures(.Ssse3, "ssse3", "Enable SSSE3 instructions", "ssse3", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).create(.Slow3opsLea, "slow-3ops-lea", "LEA instruction with 3 ops or certain registers is slow", "slow-3ops-lea"),
+ FeatureInfo(@This()).create(.IdivlToDivb, "idivl-to-divb", "Use 8-bit divide for positive values less than 256", "idivl-to-divb"),
+ FeatureInfo(@This()).create(.IdivqToDivl, "idivq-to-divl", "Use 32-bit divide for positive values less than 2^32", "idivq-to-divl"),
+ FeatureInfo(@This()).create(.SlowIncdec, "slow-incdec", "INC and DEC instructions are slower than ADD and SUB", "slow-incdec"),
+ FeatureInfo(@This()).create(.SlowLea, "slow-lea", "LEA instruction with certain arguments is slow", "slow-lea"),
+ FeatureInfo(@This()).create(.SlowPmaddwd, "slow-pmaddwd", "PMADDWD is slower than PMULLD", "slow-pmaddwd"),
+ FeatureInfo(@This()).create(.SlowPmulld, "slow-pmulld", "PMULLD instruction is slow", "slow-pmulld"),
+ FeatureInfo(@This()).create(.SlowShld, "slow-shld", "SHLD instruction is slow", "slow-shld"),
+ FeatureInfo(@This()).create(.SlowTwoMemOps, "slow-two-mem-ops", "Two memory operand instructions are slow", "slow-two-mem-ops"),
+ FeatureInfo(@This()).create(.SlowUnalignedMem16, "slow-unaligned-mem-16", "Slow unaligned 16-byte memory access", "slow-unaligned-mem-16"),
+ FeatureInfo(@This()).create(.SlowUnalignedMem32, "slow-unaligned-mem-32", "Slow unaligned 32-byte memory access", "slow-unaligned-mem-32"),
+ FeatureInfo(@This()).create(.SoftFloat, "soft-float", "Use software floating point features", "soft-float"),
+ FeatureInfo(@This()).create(.Tbm, "tbm", "Enable TBM instructions", "tbm"),
+ FeatureInfo(@This()).create(.UseAa, "use-aa", "Use alias analysis during codegen", "use-aa"),
+ FeatureInfo(@This()).createWithSubfeatures(.Vaes, "vaes", "Promote selected AES instructions to AVX512/AVX registers", "vaes", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avx512vbmi, "avx512vbmi", "Enable AVX-512 Vector Byte Manipulation Instructions", "avx512vbmi", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avx512vbmi2, "avx512vbmi2", "Enable AVX-512 further Vector Byte Manipulation Instructions", "avx512vbmi2", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avx512vl, "avx512vl", "Enable AVX-512 Vector Length eXtensions", "avx512vl", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avx512vnni, "avx512vnni", "Enable AVX-512 Vector Neural Network Instructions", "avx512vnni", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avx512vp2intersect, "avx512vp2intersect", "Enable AVX-512 vp2intersect", "avx512vp2intersect", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Vpclmulqdq, "vpclmulqdq", "Enable vpclmulqdq instructions", "vpclmulqdq", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).createWithSubfeatures(.Avx512vpopcntdq, "avx512vpopcntdq", "Enable AVX-512 Population Count Instructions", "avx512vpopcntdq", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).create(.Waitpkg, "waitpkg", "Wait and pause enhancements", "waitpkg"),
+ FeatureInfo(@This()).create(.Wbnoinvd, "wbnoinvd", "Write Back No Invalidate", "wbnoinvd"),
+ FeatureInfo(@This()).create(.X87, "x87", "Enable X87 float instructions", "x87"),
+ FeatureInfo(@This()).createWithSubfeatures(.Xop, "xop", "Enable XOP instructions", "xop", &[_]@This() {
+ .Sse,
+ }),
+ FeatureInfo(@This()).create(.Xsave, "xsave", "Support xsave instructions", "xsave"),
+ FeatureInfo(@This()).create(.Xsavec, "xsavec", "Support xsavec instructions", "xsavec"),
+ FeatureInfo(@This()).create(.Xsaveopt, "xsaveopt", "Support xsaveopt instructions", "xsaveopt"),
+ FeatureInfo(@This()).create(.Xsaves, "xsaves", "Support xsaves instructions", "xsaves"),
+ FeatureInfo(@This()).create(.BitMode16, "16bit-mode", "16-bit mode (i8086)", "16bit-mode"),
+ FeatureInfo(@This()).create(.BitMode32, "32bit-mode", "32-bit mode (80386)", "32bit-mode"),
+ FeatureInfo(@This()).create(.BitMode64, "64bit-mode", "64-bit mode (x86_64)", "64bit-mode"),
+ };
+};
lib/std/target/cpu.zig
@@ -0,0 +1,65 @@
+const std = @import("std");
+
+const feature = @import("feature.zig");
+const Arch = @import("arch.zig").Arch;
+
+pub const AArch64Cpu = @import("cpu/AArch64Cpu.zig").AArch64Cpu;
+pub const AmdGpuCpu = @import("cpu/AmdGpuCpu.zig").AmdGpuCpu;
+pub const ArmCpu = @import("cpu/ArmCpu.zig").ArmCpu;
+pub const AvrCpu = @import("cpu/AvrCpu.zig").AvrCpu;
+pub const BpfCpu = @import("cpu/BpfCpu.zig").BpfCpu;
+pub const HexagonCpu = @import("cpu/HexagonCpu.zig").HexagonCpu;
+pub const MipsCpu = @import("cpu/MipsCpu.zig").MipsCpu;
+pub const Msp430Cpu = @import("cpu/Msp430Cpu.zig").Msp430Cpu;
+pub const NvptxCpu = @import("cpu/NvptxCpu.zig").NvptxCpu;
+pub const PowerPcCpu = @import("cpu/PowerPcCpu.zig").PowerPcCpu;
+pub const RiscVCpu = @import("cpu/RiscVCpu.zig").RiscVCpu;
+pub const SparcCpu = @import("cpu/SparcCpu.zig").SparcCpu;
+pub const SystemZCpu = @import("cpu/SystemZCpu.zig").SystemZCpu;
+pub const WebAssemblyCpu = @import("cpu/WebAssemblyCpu.zig").WebAssemblyCpu;
+pub const X86Cpu = @import("cpu/X86Cpu.zig").X86Cpu;
+
+const EmptyCpu = @import("feature/empty.zig").EmptyCpu;
+
+pub fn ArchCpu(comptime arch: @TagType(Arch)) type {
+ return switch (arch) {
+ .arm, .armeb, .thumb, .thumbeb => ArmCpu,
+ .aarch64, .aarch64_be, .aarch64_32 => AArch64Cpu,
+ .avr => AvrCpu,
+ .bpfel, .bpfeb => BpfCpu,
+ .hexagon => HexagonCpu,
+ .mips, .mipsel, .mips64, .mips64el => MipsCpu,
+ .msp430 => Msp430Cpu,
+ .powerpc, .powerpc64, .powerpc64le => PowerPcCpu,
+ .amdgcn => AmdGpuCpu,
+ .riscv32, .riscv64 => RiscVCpu,
+ .sparc, .sparcv9, .sparcel => SparcCpu,
+ .s390x => SystemZCpu,
+ .i386, .x86_64 => X86Cpu,
+ .nvptx, .nvptx64 => NvptxCpu,
+ .wasm32, .wasm64 => WebAssemblyCpu,
+
+ else => EmptyCpu,
+ };
+}
+
+pub fn ArchCpuInfo(comptime arch: @TagType(Arch)) type {
+ return CpuInfo(feature.ArchFeature(arch));
+}
+
+pub fn CpuInfo(comptime FeatureType: type) type {
+ return struct {
+ name: []const u8,
+
+ features: []const FeatureType,
+
+ const Self = @This();
+
+ fn create(name: []const u8, features: []const FeatureType) Self {
+ return Self {
+ .name = name,
+ .features = features,
+ };
+ }
+ };
+}
lib/std/target/feature.zig
@@ -0,0 +1,76 @@
+const builtin = @import("builtin");
+const std = @import("std");
+const Arch = std.Target.Arch;
+
+pub const AArch64Feature = @import("feature/AArch64Feature.zig").AArch64Feature;
+pub const AmdGpuFeature = @import("feature/AmdGpuFeature.zig").AmdGpuFeature;
+pub const ArmFeature = @import("feature/ArmFeature.zig").ArmFeature;
+pub const AvrFeature = @import("feature/AvrFeature.zig").AvrFeature;
+pub const BpfFeature = @import("feature/BpfFeature.zig").BpfFeature;
+pub const HexagonFeature = @import("feature/HexagonFeature.zig").HexagonFeature;
+pub const MipsFeature = @import("feature/MipsFeature.zig").MipsFeature;
+pub const Msp430Feature = @import("feature/Msp430Feature.zig").Msp430Feature;
+pub const NvptxFeature = @import("feature/NvptxFeature.zig").NvptxFeature;
+pub const PowerPcFeature = @import("feature/PowerPcFeature.zig").PowerPcFeature;
+pub const RiscVFeature = @import("feature/RiscVFeature.zig").RiscVFeature;
+pub const SparcFeature = @import("feature/SparcFeature.zig").SparcFeature;
+pub const SystemZFeature = @import("feature/SystemZFeature.zig").SystemZFeature;
+pub const WebAssemblyFeature = @import("feature/WebAssemblyFeature.zig").WebAssemblyFeature;
+pub const X86Feature = @import("feature/X86Feature.zig").X86Feature;
+
+const EmptyFeature = @import("feature/empty.zig").EmptyFeature;
+
+pub fn ArchFeature(comptime arch: @TagType(Arch)) type {
+ return switch (arch) {
+ .arm, .armeb, .thumb, .thumbeb => ArmFeature,
+ .aarch64, .aarch64_be, .aarch64_32 => AArch64Feature,
+ .avr => AvrFeature,
+ .bpfel, .bpfeb => BpfFeature,
+ .hexagon => HexagonFeature,
+ .mips, .mipsel, .mips64, .mips64el => MipsFeature,
+ .msp430 => Msp430Feature,
+ .powerpc, .powerpc64, .powerpc64le => PowerPcFeature,
+ .amdgcn => AmdGpuFeature,
+ .riscv32, .riscv64 => RiscVFeature,
+ .sparc, .sparcv9, .sparcel => SparcFeature,
+ .s390x => SystemZFeature,
+ .i386, .x86_64 => X86Feature,
+ .nvptx, .nvptx64 => NvptxFeature,
+ .wasm32, .wasm64 => WebAssemblyFeature,
+
+ else => EmptyFeature,
+ };
+}
+
+pub fn ArchFeatureInfo(comptime arch: @TagType(Arch)) type {
+ return FeatureInfo(ArchFeature(arch));
+}
+
+pub fn FeatureInfo(comptime EnumType: type) type {
+ return struct {
+ value: EnumType,
+ name: []const u8,
+
+ dependencies: []const EnumType,
+
+ const Self = @This();
+
+ fn create(value: EnumType, name: []const u8) Self {
+ return Self {
+ .value = value,
+ .name = name,
+
+ .dependencies = &[_]EnumType{},
+ };
+ }
+
+ fn createWithDeps(value: EnumType, name: []const u8, dependencies: []const EnumType) Self {
+ return Self {
+ .value = value,
+ .name = name,
+
+ .dependencies = dependencies,
+ };
+ }
+ };
+}
lib/std/std.zig
@@ -60,6 +60,7 @@ pub const rand = @import("rand.zig");
pub const rb = @import("rb.zig");
pub const sort = @import("sort.zig");
pub const ascii = @import("ascii.zig");
+pub const target = @import("target.zig");
pub const testing = @import("testing.zig");
pub const time = @import("time.zig");
pub const unicode = @import("unicode.zig");
lib/std/target.zig
@@ -2,6 +2,9 @@ const std = @import("std.zig");
const mem = std.mem;
const builtin = std.builtin;
+pub const feature = @import("target/feature.zig");
+pub const cpu = @import("target/cpu.zig");
+
/// TODO Nearly all the functions in this namespace would be
/// better off if https://github.com/ziglang/zig/issues/425
/// was solved.