Commit 0e118ed0ac

LeRoyce Pearson <contact@leroycepearson.dev>
2022-08-10 00:08:59
stage2: add compile error for shlExact overflow
- moves a stage1 test case and makes it target `llvm` backend instead of `stage1` backend
master
1 parent 8fd20a5
Changed files (2)
src
Sema.zig
test
cases
compile_errors
shlExact_shifts_out_1_bits.zig
src/Sema.zig
@@ -10269,16 +10269,14 @@ fn zirShl(
 
         const val = switch (air_tag) {
             .shl_exact => val: {
-                const shifted = try lhs_val.shl(rhs_val, lhs_ty, sema.arena, target);
+                const shifted = try lhs_val.shlWithOverflow(rhs_val, lhs_ty, sema.arena, target);
                 if (scalar_ty.zigTypeTag() == .ComptimeInt) {
-                    break :val shifted;
+                    break :val shifted.wrapped_result;
                 }
-                const int_info = scalar_ty.intInfo(target);
-                const truncated = try shifted.intTrunc(lhs_ty, sema.arena, int_info.signedness, int_info.bits, target);
-                if (try sema.compare(block, src, truncated, .eq, shifted, lhs_ty)) {
-                    break :val shifted;
+                if (shifted.overflowed.compareWithZero(.eq)) {
+                    break :val shifted.wrapped_result;
                 }
-                return sema.addConstUndef(lhs_ty);
+                return sema.fail(block, src, "operation caused overflow", .{});
             },
 
             .shl_sat => if (scalar_ty.zigTypeTag() == .ComptimeInt)
test/cases/compile_errors/stage1/obj/shlExact_shifts_out_1_bits.zig → test/cases/compile_errors/shlExact_shifts_out_1_bits.zig
@@ -4,7 +4,7 @@ comptime {
 }
 
 // error
-// backend=stage1
+// backend=llvm
 // target=native
 //
-// tmp.zig:2:15: error: operation caused overflow
+// :2:15: error: operation caused overflow