Commit 04ce5376a8

Andrew Kelley <andrew@ziglang.org>
2019-07-18 17:43:39
carry some upstream patches to musl to fix riscv inline asm
Upstream commits: * 8eb49e0485fc547eead9e47200bbee6d81f391c1 * 2dcbeabd917e404a0dde0195388da401b849b9a4 * f0eb2e77b2132a88e2f00d8e06ffa7638c40b4bc These will be in the next version of musl, so no harm carrying them here.
master
1 parent aaa4bf7
Changed files (2)
lib
libc
musl
arch
riscv64
atomic_arch.h
syscall_arch.h
lib/libc/musl/arch/riscv64/atomic_arch.h
@@ -8,13 +8,15 @@ static inline void a_barrier()
 static inline int a_cas(volatile int *p, int t, int s)
 {
 	int old, tmp;
-	__asm__("\n1:	lr.w.aqrl %0, %2\n"
+	__asm__ __volatile__ (
+		"\n1:	lr.w.aqrl %0, (%2)\n"
 		"	bne %0, %3, 1f\n"
-		"	sc.w.aqrl %1, %4, %2\n"
+		"	sc.w.aqrl %1, %4, (%2)\n"
 		"	bnez %1, 1b\n"
 		"1:"
-		: "=&r"(old), "+r"(tmp), "+A"(*p)
-		: "r"(t), "r"(s));
+		: "=&r"(old), "=r"(tmp)
+		: "r"(p), "r"(t), "r"(s)
+		: "memory");
 	return old;
 }
 
@@ -23,12 +25,14 @@ static inline void *a_cas_p(volatile void *p, void *t, void *s)
 {
 	void *old;
 	int tmp;
-	__asm__("\n1:	lr.d.aqrl %0, %2\n"
+	__asm__ __volatile__ (
+		"\n1:	lr.d.aqrl %0, (%2)\n"
 		"	bne %0, %3, 1f\n"
-		"	sc.d.aqrl %1, %4, %2\n"
+		"	sc.d.aqrl %1, %4, (%2)\n"
 		"	bnez %1, 1b\n"
 		"1:"
-		: "=&r"(old), "+r"(tmp), "+A"(*(long *)p)
-		: "r"(t), "r"(s));
+		: "=&r"(old), "=r"(tmp)
+		: "r"(p), "r"(t), "r"(s)
+		: "memory");
 	return old;
 }
lib/libc/musl/arch/riscv64/syscall_arch.h
@@ -3,7 +3,7 @@
 
 #define __asm_syscall(...) \
 	__asm__ __volatile__ ("ecall\n\t" \
-	: "+r"(a0) : __VA_ARGS__ : "memory"); \
+	: "=r"(a0) : __VA_ARGS__ : "memory"); \
 	return a0; \
 
 static inline long __syscall0(long n)