Commit 0478446377

Jakub Konka <kubkon@jakubkonka.com>
2021-12-15 17:18:38
stage2: fix register size selection
This actually needs proper rework, and I'll get to that when refactoring MIR.
master
1 parent 5103573
Changed files (1)
src
arch
x86_64
CodeGen.zig
src/arch/x86_64/CodeGen.zig
@@ -1635,7 +1635,7 @@ fn genBinMathOpMir(
                         .tag = mir_tag,
                         .ops = (Mir.Ops{
                             .reg1 = registerAlias(dst_reg, @intCast(u32, abi_size)),
-                            .reg2 = .ebp,
+                            .reg2 = registerAlias(.rbp, @intCast(u32, abi_size)),
                             .flags = 0b01,
                         }).encode(),
                         .data = .{ .imm = -@intCast(i32, adj_off) },
@@ -1666,7 +1666,7 @@ fn genBinMathOpMir(
                         .tag = mir_tag,
                         .ops = (Mir.Ops{
                             .reg1 = registerAlias(src_reg, @intCast(u32, abi_size)),
-                            .reg2 = .ebp,
+                            .reg2 = registerAlias(.rbp, @intCast(u32, abi_size)),
                             .flags = 0b10,
                         }).encode(),
                         .data = .{ .imm = -@intCast(i32, adj_off) },
@@ -2835,12 +2835,11 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
             }
             const abi_size = ty.abiSize(self.target.*);
             const adj_off = stack_offset + abi_size;
-            // TODO select instruction size
             _ = try self.addInst(.{
                 .tag = .mov,
                 .ops = (Mir.Ops{
                     .reg1 = registerAlias(reg, @intCast(u32, abi_size)),
-                    .reg2 = .rbp,
+                    .reg2 = registerAlias(.rbp, @intCast(u32, abi_size)),
                     .flags = 0b10,
                 }).encode(),
                 .data = .{ .imm = -@intCast(i32, adj_off) },
@@ -3061,7 +3060,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
                 .tag = .mov,
                 .ops = (Mir.Ops{
                     .reg1 = registerAlias(reg, @intCast(u32, abi_size)),
-                    .reg2 = .ebp,
+                    .reg2 = registerAlias(.rbp, @intCast(u32, abi_size)),
                     .flags = 0b01,
                 }).encode(),
                 .data = .{ .imm = ioff },