master
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
3const std = @import("../std.zig");
4const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;
6
7pub const Feature = enum {
8 @"32bit",
9 @"64bit",
10 a,
11 andes45,
12 auipc_addi_fusion,
13 b,
14 c,
15 conditional_cmv_fusion,
16 d,
17 disable_latency_sched_heuristic,
18 dlen_factor_2,
19 e,
20 exact_asm,
21 experimental,
22 experimental_p,
23 experimental_rvm23u32,
24 experimental_smctr,
25 experimental_ssctr,
26 experimental_svukte,
27 experimental_xqccmp,
28 experimental_xqcia,
29 experimental_xqciac,
30 experimental_xqcibi,
31 experimental_xqcibm,
32 experimental_xqcicli,
33 experimental_xqcicm,
34 experimental_xqcics,
35 experimental_xqcicsr,
36 experimental_xqciint,
37 experimental_xqciio,
38 experimental_xqcilb,
39 experimental_xqcili,
40 experimental_xqcilia,
41 experimental_xqcilo,
42 experimental_xqcilsm,
43 experimental_xqcisim,
44 experimental_xqcisls,
45 experimental_xqcisync,
46 experimental_xrivosvisni,
47 experimental_xrivosvizip,
48 experimental_xsfmclic,
49 experimental_xsfsclic,
50 experimental_zalasr,
51 experimental_zicfilp,
52 experimental_zicfiss,
53 experimental_zvbc32e,
54 experimental_zvkgs,
55 experimental_zvqdotq,
56 f,
57 forced_atomics,
58 h,
59 i,
60 ld_add_fusion,
61 log_vrgather,
62 lui_addi_fusion,
63 m,
64 mips_p8700,
65 no_default_unroll,
66 no_sink_splat_operands,
67 no_trailing_seq_cst_fence,
68 optimized_nf2_segment_load_store,
69 optimized_nf3_segment_load_store,
70 optimized_nf4_segment_load_store,
71 optimized_nf5_segment_load_store,
72 optimized_nf6_segment_load_store,
73 optimized_nf7_segment_load_store,
74 optimized_nf8_segment_load_store,
75 optimized_zero_stride_load,
76 predictable_select_expensive,
77 prefer_vsetvli_over_read_vlenb,
78 prefer_w_inst,
79 q,
80 relax,
81 reserve_x1,
82 reserve_x10,
83 reserve_x11,
84 reserve_x12,
85 reserve_x13,
86 reserve_x14,
87 reserve_x15,
88 reserve_x16,
89 reserve_x17,
90 reserve_x18,
91 reserve_x19,
92 reserve_x2,
93 reserve_x20,
94 reserve_x21,
95 reserve_x22,
96 reserve_x23,
97 reserve_x24,
98 reserve_x25,
99 reserve_x26,
100 reserve_x27,
101 reserve_x28,
102 reserve_x29,
103 reserve_x3,
104 reserve_x30,
105 reserve_x31,
106 reserve_x4,
107 reserve_x5,
108 reserve_x6,
109 reserve_x7,
110 reserve_x8,
111 reserve_x9,
112 rva20s64,
113 rva20u64,
114 rva22s64,
115 rva22u64,
116 rva23s64,
117 rva23u64,
118 rvb23s64,
119 rvb23u64,
120 rvi20u32,
121 rvi20u64,
122 save_restore,
123 sdext,
124 sdtrig,
125 sha,
126 shcounterenw,
127 shgatpa,
128 shifted_zextw_fusion,
129 shlcofideleg,
130 short_forward_branch_opt,
131 shtvala,
132 shvsatpa,
133 shvstvala,
134 shvstvecd,
135 smaia,
136 smcdeleg,
137 smcntrpmf,
138 smcsrind,
139 smdbltrp,
140 smepmp,
141 smmpm,
142 smnpm,
143 smrnmi,
144 smstateen,
145 ssaia,
146 ssccfg,
147 ssccptr,
148 sscofpmf,
149 sscounterenw,
150 sscsrind,
151 ssdbltrp,
152 ssnpm,
153 sspm,
154 ssqosid,
155 ssstateen,
156 ssstrict,
157 sstc,
158 sstvala,
159 sstvecd,
160 ssu64xl,
161 supm,
162 svade,
163 svadu,
164 svbare,
165 svinval,
166 svnapot,
167 svpbmt,
168 svvptc,
169 tagged_globals,
170 unaligned_scalar_mem,
171 unaligned_vector_mem,
172 use_postra_scheduler,
173 v,
174 ventana_veyron,
175 vl_dependent_latency,
176 vxrm_pipeline_flush,
177 xandesbfhcvt,
178 xandesperf,
179 xandesvbfhcvt,
180 xandesvdot,
181 xandesvpackfph,
182 xandesvsintload,
183 xcvalu,
184 xcvbi,
185 xcvbitmanip,
186 xcvelw,
187 xcvmac,
188 xcvmem,
189 xcvsimd,
190 xmipscbop,
191 xmipscmov,
192 xmipslsp,
193 xsfcease,
194 xsfmm128t,
195 xsfmm16t,
196 xsfmm32a16f,
197 xsfmm32a32f,
198 xsfmm32a8f,
199 xsfmm32a8i,
200 xsfmm32t,
201 xsfmm64a64f,
202 xsfmm64t,
203 xsfmmbase,
204 xsfvcp,
205 xsfvfnrclipxfqf,
206 xsfvfwmaccqqq,
207 xsfvqmaccdod,
208 xsfvqmaccqoq,
209 xsifivecdiscarddlone,
210 xsifivecflushdlone,
211 xtheadba,
212 xtheadbb,
213 xtheadbs,
214 xtheadcmo,
215 xtheadcondmov,
216 xtheadfmemidx,
217 xtheadmac,
218 xtheadmemidx,
219 xtheadmempair,
220 xtheadsync,
221 xtheadvdot,
222 xventanacondops,
223 xwchc,
224 za128rs,
225 za64rs,
226 zaamo,
227 zabha,
228 zacas,
229 zalrsc,
230 zama16b,
231 zawrs,
232 zba,
233 zbb,
234 zbc,
235 zbkb,
236 zbkc,
237 zbkx,
238 zbs,
239 zca,
240 zcb,
241 zcd,
242 zce,
243 zcf,
244 zclsd,
245 zcmop,
246 zcmp,
247 zcmt,
248 zdinx,
249 zexth_fusion,
250 zextw_fusion,
251 zfa,
252 zfbfmin,
253 zfh,
254 zfhmin,
255 zfinx,
256 zhinx,
257 zhinxmin,
258 zic64b,
259 zicbom,
260 zicbop,
261 zicboz,
262 ziccamoa,
263 ziccamoc,
264 ziccif,
265 zicclsm,
266 ziccrse,
267 zicntr,
268 zicond,
269 zicsr,
270 zifencei,
271 zihintntl,
272 zihintpause,
273 zihpm,
274 zilsd,
275 zimop,
276 zk,
277 zkn,
278 zknd,
279 zkne,
280 zknh,
281 zkr,
282 zks,
283 zksed,
284 zksh,
285 zkt,
286 zmmul,
287 ztso,
288 zvbb,
289 zvbc,
290 zve32f,
291 zve32x,
292 zve64d,
293 zve64f,
294 zve64x,
295 zvfbfmin,
296 zvfbfwma,
297 zvfh,
298 zvfhmin,
299 zvkb,
300 zvkg,
301 zvkn,
302 zvknc,
303 zvkned,
304 zvkng,
305 zvknha,
306 zvknhb,
307 zvks,
308 zvksc,
309 zvksed,
310 zvksg,
311 zvksh,
312 zvkt,
313 zvl1024b,
314 zvl128b,
315 zvl16384b,
316 zvl2048b,
317 zvl256b,
318 zvl32768b,
319 zvl32b,
320 zvl4096b,
321 zvl512b,
322 zvl64b,
323 zvl65536b,
324 zvl8192b,
325};
326
327pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
328pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
329pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
330pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
331
332pub const all_features = blk: {
333 @setEvalBranchQuota(2000);
334 const len = @typeInfo(Feature).@"enum".fields.len;
335 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
336 var result: [len]CpuFeature = undefined;
337 result[@intFromEnum(Feature.@"32bit")] = .{
338 .llvm_name = "32bit",
339 .description = "Implements RV32",
340 .dependencies = featureSet(&[_]Feature{}),
341 };
342 result[@intFromEnum(Feature.@"64bit")] = .{
343 .llvm_name = "64bit",
344 .description = "Implements RV64",
345 .dependencies = featureSet(&[_]Feature{}),
346 };
347 result[@intFromEnum(Feature.a)] = .{
348 .llvm_name = "a",
349 .description = "'A' (Atomic Instructions)",
350 .dependencies = featureSet(&[_]Feature{
351 .zaamo,
352 .zalrsc,
353 }),
354 };
355 result[@intFromEnum(Feature.andes45)] = .{
356 .llvm_name = "andes45",
357 .description = "Andes 45-Series processors",
358 .dependencies = featureSet(&[_]Feature{}),
359 };
360 result[@intFromEnum(Feature.auipc_addi_fusion)] = .{
361 .llvm_name = "auipc-addi-fusion",
362 .description = "Enable AUIPC+ADDI macrofusion",
363 .dependencies = featureSet(&[_]Feature{}),
364 };
365 result[@intFromEnum(Feature.b)] = .{
366 .llvm_name = "b",
367 .description = "'B' (the collection of the Zba, Zbb, Zbs extensions)",
368 .dependencies = featureSet(&[_]Feature{
369 .zba,
370 .zbb,
371 .zbs,
372 }),
373 };
374 result[@intFromEnum(Feature.c)] = .{
375 .llvm_name = "c",
376 .description = "'C' (Compressed Instructions)",
377 .dependencies = featureSet(&[_]Feature{
378 .zca,
379 }),
380 };
381 result[@intFromEnum(Feature.conditional_cmv_fusion)] = .{
382 .llvm_name = "conditional-cmv-fusion",
383 .description = "Enable branch+c.mv fusion",
384 .dependencies = featureSet(&[_]Feature{}),
385 };
386 result[@intFromEnum(Feature.d)] = .{
387 .llvm_name = "d",
388 .description = "'D' (Double-Precision Floating-Point)",
389 .dependencies = featureSet(&[_]Feature{
390 .f,
391 }),
392 };
393 result[@intFromEnum(Feature.disable_latency_sched_heuristic)] = .{
394 .llvm_name = "disable-latency-sched-heuristic",
395 .description = "Disable latency scheduling heuristic",
396 .dependencies = featureSet(&[_]Feature{}),
397 };
398 result[@intFromEnum(Feature.dlen_factor_2)] = .{
399 .llvm_name = "dlen-factor-2",
400 .description = "Vector unit DLEN(data path width) is half of VLEN",
401 .dependencies = featureSet(&[_]Feature{}),
402 };
403 result[@intFromEnum(Feature.e)] = .{
404 .llvm_name = "e",
405 .description = "'E' (Embedded Instruction Set with 16 GPRs)",
406 .dependencies = featureSet(&[_]Feature{}),
407 };
408 result[@intFromEnum(Feature.exact_asm)] = .{
409 .llvm_name = "exact-asm",
410 .description = "Enable Exact Assembly (Disables Compression and Relaxation)",
411 .dependencies = featureSet(&[_]Feature{}),
412 };
413 result[@intFromEnum(Feature.experimental)] = .{
414 .llvm_name = "experimental",
415 .description = "Experimental intrinsics",
416 .dependencies = featureSet(&[_]Feature{}),
417 };
418 result[@intFromEnum(Feature.experimental_p)] = .{
419 .llvm_name = "experimental-p",
420 .description = "'P' ('Base P' (Packed SIMD))",
421 .dependencies = featureSet(&[_]Feature{}),
422 };
423 result[@intFromEnum(Feature.experimental_rvm23u32)] = .{
424 .llvm_name = "experimental-rvm23u32",
425 .description = "RISC-V experimental-rvm23u32 profile",
426 .dependencies = featureSet(&[_]Feature{
427 .@"32bit",
428 .b,
429 .i,
430 .m,
431 .zce,
432 .zcmop,
433 .zicbop,
434 .zicond,
435 .zihintntl,
436 .zihintpause,
437 .zimop,
438 }),
439 };
440 result[@intFromEnum(Feature.experimental_smctr)] = .{
441 .llvm_name = "experimental-smctr",
442 .description = "'Smctr' (Control Transfer Records Machine Level)",
443 .dependencies = featureSet(&[_]Feature{
444 .sscsrind,
445 }),
446 };
447 result[@intFromEnum(Feature.experimental_ssctr)] = .{
448 .llvm_name = "experimental-ssctr",
449 .description = "'Ssctr' (Control Transfer Records Supervisor Level)",
450 .dependencies = featureSet(&[_]Feature{
451 .sscsrind,
452 }),
453 };
454 result[@intFromEnum(Feature.experimental_svukte)] = .{
455 .llvm_name = "experimental-svukte",
456 .description = "'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)",
457 .dependencies = featureSet(&[_]Feature{}),
458 };
459 result[@intFromEnum(Feature.experimental_xqccmp)] = .{
460 .llvm_name = "experimental-xqccmp",
461 .description = "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)",
462 .dependencies = featureSet(&[_]Feature{
463 .zca,
464 }),
465 };
466 result[@intFromEnum(Feature.experimental_xqcia)] = .{
467 .llvm_name = "experimental-xqcia",
468 .description = "'Xqcia' (Qualcomm uC Arithmetic Extension)",
469 .dependencies = featureSet(&[_]Feature{}),
470 };
471 result[@intFromEnum(Feature.experimental_xqciac)] = .{
472 .llvm_name = "experimental-xqciac",
473 .description = "'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)",
474 .dependencies = featureSet(&[_]Feature{
475 .zca,
476 }),
477 };
478 result[@intFromEnum(Feature.experimental_xqcibi)] = .{
479 .llvm_name = "experimental-xqcibi",
480 .description = "'Xqcibi' (Qualcomm uC Branch Immediate Extension)",
481 .dependencies = featureSet(&[_]Feature{
482 .zca,
483 }),
484 };
485 result[@intFromEnum(Feature.experimental_xqcibm)] = .{
486 .llvm_name = "experimental-xqcibm",
487 .description = "'Xqcibm' (Qualcomm uC Bit Manipulation Extension)",
488 .dependencies = featureSet(&[_]Feature{
489 .zca,
490 }),
491 };
492 result[@intFromEnum(Feature.experimental_xqcicli)] = .{
493 .llvm_name = "experimental-xqcicli",
494 .description = "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)",
495 .dependencies = featureSet(&[_]Feature{}),
496 };
497 result[@intFromEnum(Feature.experimental_xqcicm)] = .{
498 .llvm_name = "experimental-xqcicm",
499 .description = "'Xqcicm' (Qualcomm uC Conditional Move Extension)",
500 .dependencies = featureSet(&[_]Feature{
501 .zca,
502 }),
503 };
504 result[@intFromEnum(Feature.experimental_xqcics)] = .{
505 .llvm_name = "experimental-xqcics",
506 .description = "'Xqcics' (Qualcomm uC Conditional Select Extension)",
507 .dependencies = featureSet(&[_]Feature{}),
508 };
509 result[@intFromEnum(Feature.experimental_xqcicsr)] = .{
510 .llvm_name = "experimental-xqcicsr",
511 .description = "'Xqcicsr' (Qualcomm uC CSR Extension)",
512 .dependencies = featureSet(&[_]Feature{}),
513 };
514 result[@intFromEnum(Feature.experimental_xqciint)] = .{
515 .llvm_name = "experimental-xqciint",
516 .description = "'Xqciint' (Qualcomm uC Interrupts Extension)",
517 .dependencies = featureSet(&[_]Feature{
518 .zca,
519 }),
520 };
521 result[@intFromEnum(Feature.experimental_xqciio)] = .{
522 .llvm_name = "experimental-xqciio",
523 .description = "'Xqciio' (Qualcomm uC External Input Output Extension)",
524 .dependencies = featureSet(&[_]Feature{}),
525 };
526 result[@intFromEnum(Feature.experimental_xqcilb)] = .{
527 .llvm_name = "experimental-xqcilb",
528 .description = "'Xqcilb' (Qualcomm uC Long Branch Extension)",
529 .dependencies = featureSet(&[_]Feature{
530 .zca,
531 }),
532 };
533 result[@intFromEnum(Feature.experimental_xqcili)] = .{
534 .llvm_name = "experimental-xqcili",
535 .description = "'Xqcili' (Qualcomm uC Load Large Immediate Extension)",
536 .dependencies = featureSet(&[_]Feature{
537 .zca,
538 }),
539 };
540 result[@intFromEnum(Feature.experimental_xqcilia)] = .{
541 .llvm_name = "experimental-xqcilia",
542 .description = "'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)",
543 .dependencies = featureSet(&[_]Feature{
544 .zca,
545 }),
546 };
547 result[@intFromEnum(Feature.experimental_xqcilo)] = .{
548 .llvm_name = "experimental-xqcilo",
549 .description = "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)",
550 .dependencies = featureSet(&[_]Feature{
551 .zca,
552 }),
553 };
554 result[@intFromEnum(Feature.experimental_xqcilsm)] = .{
555 .llvm_name = "experimental-xqcilsm",
556 .description = "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)",
557 .dependencies = featureSet(&[_]Feature{}),
558 };
559 result[@intFromEnum(Feature.experimental_xqcisim)] = .{
560 .llvm_name = "experimental-xqcisim",
561 .description = "'Xqcisim' (Qualcomm uC Simulation Hint Extension)",
562 .dependencies = featureSet(&[_]Feature{
563 .zca,
564 }),
565 };
566 result[@intFromEnum(Feature.experimental_xqcisls)] = .{
567 .llvm_name = "experimental-xqcisls",
568 .description = "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)",
569 .dependencies = featureSet(&[_]Feature{}),
570 };
571 result[@intFromEnum(Feature.experimental_xqcisync)] = .{
572 .llvm_name = "experimental-xqcisync",
573 .description = "'Xqcisync' (Qualcomm uC Sync Delay Extension)",
574 .dependencies = featureSet(&[_]Feature{
575 .zca,
576 }),
577 };
578 result[@intFromEnum(Feature.experimental_xrivosvisni)] = .{
579 .llvm_name = "experimental-xrivosvisni",
580 .description = "'XRivosVisni' (Rivos Vector Integer Small New)",
581 .dependencies = featureSet(&[_]Feature{}),
582 };
583 result[@intFromEnum(Feature.experimental_xrivosvizip)] = .{
584 .llvm_name = "experimental-xrivosvizip",
585 .description = "'XRivosVizip' (Rivos Vector Register Zips)",
586 .dependencies = featureSet(&[_]Feature{}),
587 };
588 result[@intFromEnum(Feature.experimental_xsfmclic)] = .{
589 .llvm_name = "experimental-xsfmclic",
590 .description = "'XSfmclic' (SiFive CLIC Machine-mode CSRs)",
591 .dependencies = featureSet(&[_]Feature{}),
592 };
593 result[@intFromEnum(Feature.experimental_xsfsclic)] = .{
594 .llvm_name = "experimental-xsfsclic",
595 .description = "'XSfsclic' (SiFive CLIC Supervisor-mode CSRs)",
596 .dependencies = featureSet(&[_]Feature{}),
597 };
598 result[@intFromEnum(Feature.experimental_zalasr)] = .{
599 .llvm_name = "experimental-zalasr",
600 .description = "'Zalasr' (Load-Acquire and Store-Release Instructions)",
601 .dependencies = featureSet(&[_]Feature{}),
602 };
603 result[@intFromEnum(Feature.experimental_zicfilp)] = .{
604 .llvm_name = "experimental-zicfilp",
605 .description = "'Zicfilp' (Landing pad)",
606 .dependencies = featureSet(&[_]Feature{
607 .zicsr,
608 }),
609 };
610 result[@intFromEnum(Feature.experimental_zicfiss)] = .{
611 .llvm_name = "experimental-zicfiss",
612 .description = "'Zicfiss' (Shadow stack)",
613 .dependencies = featureSet(&[_]Feature{
614 .zicsr,
615 .zimop,
616 }),
617 };
618 result[@intFromEnum(Feature.experimental_zvbc32e)] = .{
619 .llvm_name = "experimental-zvbc32e",
620 .description = "'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)",
621 .dependencies = featureSet(&[_]Feature{
622 .zve32x,
623 }),
624 };
625 result[@intFromEnum(Feature.experimental_zvkgs)] = .{
626 .llvm_name = "experimental-zvkgs",
627 .description = "'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)",
628 .dependencies = featureSet(&[_]Feature{
629 .zvkg,
630 }),
631 };
632 result[@intFromEnum(Feature.experimental_zvqdotq)] = .{
633 .llvm_name = "experimental-zvqdotq",
634 .description = "'Zvqdotq' (Vector quad widening 4D Dot Product)",
635 .dependencies = featureSet(&[_]Feature{
636 .zve32x,
637 }),
638 };
639 result[@intFromEnum(Feature.f)] = .{
640 .llvm_name = "f",
641 .description = "'F' (Single-Precision Floating-Point)",
642 .dependencies = featureSet(&[_]Feature{
643 .zicsr,
644 }),
645 };
646 result[@intFromEnum(Feature.forced_atomics)] = .{
647 .llvm_name = "forced-atomics",
648 .description = "Assume that lock-free native-width atomics are available",
649 .dependencies = featureSet(&[_]Feature{}),
650 };
651 result[@intFromEnum(Feature.h)] = .{
652 .llvm_name = "h",
653 .description = "'H' (Hypervisor)",
654 .dependencies = featureSet(&[_]Feature{}),
655 };
656 result[@intFromEnum(Feature.i)] = .{
657 .llvm_name = "i",
658 .description = "'I' (Base Integer Instruction Set)",
659 .dependencies = featureSet(&[_]Feature{}),
660 };
661 result[@intFromEnum(Feature.ld_add_fusion)] = .{
662 .llvm_name = "ld-add-fusion",
663 .description = "Enable LD+ADD macrofusion",
664 .dependencies = featureSet(&[_]Feature{}),
665 };
666 result[@intFromEnum(Feature.log_vrgather)] = .{
667 .llvm_name = "log-vrgather",
668 .description = "Has vrgather.vv with LMUL*log2(LMUL) latency",
669 .dependencies = featureSet(&[_]Feature{}),
670 };
671 result[@intFromEnum(Feature.lui_addi_fusion)] = .{
672 .llvm_name = "lui-addi-fusion",
673 .description = "Enable LUI+ADDI macro fusion",
674 .dependencies = featureSet(&[_]Feature{}),
675 };
676 result[@intFromEnum(Feature.m)] = .{
677 .llvm_name = "m",
678 .description = "'M' (Integer Multiplication and Division)",
679 .dependencies = featureSet(&[_]Feature{
680 .zmmul,
681 }),
682 };
683 result[@intFromEnum(Feature.mips_p8700)] = .{
684 .llvm_name = "mips-p8700",
685 .description = "MIPS p8700 processor",
686 .dependencies = featureSet(&[_]Feature{}),
687 };
688 result[@intFromEnum(Feature.no_default_unroll)] = .{
689 .llvm_name = "no-default-unroll",
690 .description = "Disable default unroll preference.",
691 .dependencies = featureSet(&[_]Feature{}),
692 };
693 result[@intFromEnum(Feature.no_sink_splat_operands)] = .{
694 .llvm_name = "no-sink-splat-operands",
695 .description = "Disable sink splat operands to enable .vx, .vf,.wx, and .wf instructions",
696 .dependencies = featureSet(&[_]Feature{}),
697 };
698 result[@intFromEnum(Feature.no_trailing_seq_cst_fence)] = .{
699 .llvm_name = "no-trailing-seq-cst-fence",
700 .description = "Disable trailing fence for seq-cst store.",
701 .dependencies = featureSet(&[_]Feature{}),
702 };
703 result[@intFromEnum(Feature.optimized_nf2_segment_load_store)] = .{
704 .llvm_name = "optimized-nf2-segment-load-store",
705 .description = "vlseg2eN.v and vsseg2eN.v are implemented as a wide memory op and shuffle",
706 .dependencies = featureSet(&[_]Feature{}),
707 };
708 result[@intFromEnum(Feature.optimized_nf3_segment_load_store)] = .{
709 .llvm_name = "optimized-nf3-segment-load-store",
710 .description = "vlseg3eN.v and vsseg3eN.v are implemented as a wide memory op and shuffle",
711 .dependencies = featureSet(&[_]Feature{}),
712 };
713 result[@intFromEnum(Feature.optimized_nf4_segment_load_store)] = .{
714 .llvm_name = "optimized-nf4-segment-load-store",
715 .description = "vlseg4eN.v and vsseg4eN.v are implemented as a wide memory op and shuffle",
716 .dependencies = featureSet(&[_]Feature{}),
717 };
718 result[@intFromEnum(Feature.optimized_nf5_segment_load_store)] = .{
719 .llvm_name = "optimized-nf5-segment-load-store",
720 .description = "vlseg5eN.v and vsseg5eN.v are implemented as a wide memory op and shuffle",
721 .dependencies = featureSet(&[_]Feature{}),
722 };
723 result[@intFromEnum(Feature.optimized_nf6_segment_load_store)] = .{
724 .llvm_name = "optimized-nf6-segment-load-store",
725 .description = "vlseg6eN.v and vsseg6eN.v are implemented as a wide memory op and shuffle",
726 .dependencies = featureSet(&[_]Feature{}),
727 };
728 result[@intFromEnum(Feature.optimized_nf7_segment_load_store)] = .{
729 .llvm_name = "optimized-nf7-segment-load-store",
730 .description = "vlseg7eN.v and vsseg7eN.v are implemented as a wide memory op and shuffle",
731 .dependencies = featureSet(&[_]Feature{}),
732 };
733 result[@intFromEnum(Feature.optimized_nf8_segment_load_store)] = .{
734 .llvm_name = "optimized-nf8-segment-load-store",
735 .description = "vlseg8eN.v and vsseg8eN.v are implemented as a wide memory op and shuffle",
736 .dependencies = featureSet(&[_]Feature{}),
737 };
738 result[@intFromEnum(Feature.optimized_zero_stride_load)] = .{
739 .llvm_name = "optimized-zero-stride-load",
740 .description = "Optimized (perform fewer memory operations)zero-stride vector load",
741 .dependencies = featureSet(&[_]Feature{}),
742 };
743 result[@intFromEnum(Feature.predictable_select_expensive)] = .{
744 .llvm_name = "predictable-select-expensive",
745 .description = "Prefer likely predicted branches over selects",
746 .dependencies = featureSet(&[_]Feature{}),
747 };
748 result[@intFromEnum(Feature.prefer_vsetvli_over_read_vlenb)] = .{
749 .llvm_name = "prefer-vsetvli-over-read-vlenb",
750 .description = "Prefer vsetvli over read vlenb CSR to calculate VLEN",
751 .dependencies = featureSet(&[_]Feature{}),
752 };
753 result[@intFromEnum(Feature.prefer_w_inst)] = .{
754 .llvm_name = "prefer-w-inst",
755 .description = "Prefer instructions with W suffix",
756 .dependencies = featureSet(&[_]Feature{}),
757 };
758 result[@intFromEnum(Feature.q)] = .{
759 .llvm_name = "q",
760 .description = "'Q' (Quad-Precision Floating-Point)",
761 .dependencies = featureSet(&[_]Feature{
762 .d,
763 }),
764 };
765 result[@intFromEnum(Feature.relax)] = .{
766 .llvm_name = "relax",
767 .description = "Enable Linker relaxation.",
768 .dependencies = featureSet(&[_]Feature{}),
769 };
770 result[@intFromEnum(Feature.reserve_x1)] = .{
771 .llvm_name = "reserve-x1",
772 .description = "Reserve X1",
773 .dependencies = featureSet(&[_]Feature{}),
774 };
775 result[@intFromEnum(Feature.reserve_x10)] = .{
776 .llvm_name = "reserve-x10",
777 .description = "Reserve X10",
778 .dependencies = featureSet(&[_]Feature{}),
779 };
780 result[@intFromEnum(Feature.reserve_x11)] = .{
781 .llvm_name = "reserve-x11",
782 .description = "Reserve X11",
783 .dependencies = featureSet(&[_]Feature{}),
784 };
785 result[@intFromEnum(Feature.reserve_x12)] = .{
786 .llvm_name = "reserve-x12",
787 .description = "Reserve X12",
788 .dependencies = featureSet(&[_]Feature{}),
789 };
790 result[@intFromEnum(Feature.reserve_x13)] = .{
791 .llvm_name = "reserve-x13",
792 .description = "Reserve X13",
793 .dependencies = featureSet(&[_]Feature{}),
794 };
795 result[@intFromEnum(Feature.reserve_x14)] = .{
796 .llvm_name = "reserve-x14",
797 .description = "Reserve X14",
798 .dependencies = featureSet(&[_]Feature{}),
799 };
800 result[@intFromEnum(Feature.reserve_x15)] = .{
801 .llvm_name = "reserve-x15",
802 .description = "Reserve X15",
803 .dependencies = featureSet(&[_]Feature{}),
804 };
805 result[@intFromEnum(Feature.reserve_x16)] = .{
806 .llvm_name = "reserve-x16",
807 .description = "Reserve X16",
808 .dependencies = featureSet(&[_]Feature{}),
809 };
810 result[@intFromEnum(Feature.reserve_x17)] = .{
811 .llvm_name = "reserve-x17",
812 .description = "Reserve X17",
813 .dependencies = featureSet(&[_]Feature{}),
814 };
815 result[@intFromEnum(Feature.reserve_x18)] = .{
816 .llvm_name = "reserve-x18",
817 .description = "Reserve X18",
818 .dependencies = featureSet(&[_]Feature{}),
819 };
820 result[@intFromEnum(Feature.reserve_x19)] = .{
821 .llvm_name = "reserve-x19",
822 .description = "Reserve X19",
823 .dependencies = featureSet(&[_]Feature{}),
824 };
825 result[@intFromEnum(Feature.reserve_x2)] = .{
826 .llvm_name = "reserve-x2",
827 .description = "Reserve X2",
828 .dependencies = featureSet(&[_]Feature{}),
829 };
830 result[@intFromEnum(Feature.reserve_x20)] = .{
831 .llvm_name = "reserve-x20",
832 .description = "Reserve X20",
833 .dependencies = featureSet(&[_]Feature{}),
834 };
835 result[@intFromEnum(Feature.reserve_x21)] = .{
836 .llvm_name = "reserve-x21",
837 .description = "Reserve X21",
838 .dependencies = featureSet(&[_]Feature{}),
839 };
840 result[@intFromEnum(Feature.reserve_x22)] = .{
841 .llvm_name = "reserve-x22",
842 .description = "Reserve X22",
843 .dependencies = featureSet(&[_]Feature{}),
844 };
845 result[@intFromEnum(Feature.reserve_x23)] = .{
846 .llvm_name = "reserve-x23",
847 .description = "Reserve X23",
848 .dependencies = featureSet(&[_]Feature{}),
849 };
850 result[@intFromEnum(Feature.reserve_x24)] = .{
851 .llvm_name = "reserve-x24",
852 .description = "Reserve X24",
853 .dependencies = featureSet(&[_]Feature{}),
854 };
855 result[@intFromEnum(Feature.reserve_x25)] = .{
856 .llvm_name = "reserve-x25",
857 .description = "Reserve X25",
858 .dependencies = featureSet(&[_]Feature{}),
859 };
860 result[@intFromEnum(Feature.reserve_x26)] = .{
861 .llvm_name = "reserve-x26",
862 .description = "Reserve X26",
863 .dependencies = featureSet(&[_]Feature{}),
864 };
865 result[@intFromEnum(Feature.reserve_x27)] = .{
866 .llvm_name = "reserve-x27",
867 .description = "Reserve X27",
868 .dependencies = featureSet(&[_]Feature{}),
869 };
870 result[@intFromEnum(Feature.reserve_x28)] = .{
871 .llvm_name = "reserve-x28",
872 .description = "Reserve X28",
873 .dependencies = featureSet(&[_]Feature{}),
874 };
875 result[@intFromEnum(Feature.reserve_x29)] = .{
876 .llvm_name = "reserve-x29",
877 .description = "Reserve X29",
878 .dependencies = featureSet(&[_]Feature{}),
879 };
880 result[@intFromEnum(Feature.reserve_x3)] = .{
881 .llvm_name = "reserve-x3",
882 .description = "Reserve X3",
883 .dependencies = featureSet(&[_]Feature{}),
884 };
885 result[@intFromEnum(Feature.reserve_x30)] = .{
886 .llvm_name = "reserve-x30",
887 .description = "Reserve X30",
888 .dependencies = featureSet(&[_]Feature{}),
889 };
890 result[@intFromEnum(Feature.reserve_x31)] = .{
891 .llvm_name = "reserve-x31",
892 .description = "Reserve X31",
893 .dependencies = featureSet(&[_]Feature{}),
894 };
895 result[@intFromEnum(Feature.reserve_x4)] = .{
896 .llvm_name = "reserve-x4",
897 .description = "Reserve X4",
898 .dependencies = featureSet(&[_]Feature{}),
899 };
900 result[@intFromEnum(Feature.reserve_x5)] = .{
901 .llvm_name = "reserve-x5",
902 .description = "Reserve X5",
903 .dependencies = featureSet(&[_]Feature{}),
904 };
905 result[@intFromEnum(Feature.reserve_x6)] = .{
906 .llvm_name = "reserve-x6",
907 .description = "Reserve X6",
908 .dependencies = featureSet(&[_]Feature{}),
909 };
910 result[@intFromEnum(Feature.reserve_x7)] = .{
911 .llvm_name = "reserve-x7",
912 .description = "Reserve X7",
913 .dependencies = featureSet(&[_]Feature{}),
914 };
915 result[@intFromEnum(Feature.reserve_x8)] = .{
916 .llvm_name = "reserve-x8",
917 .description = "Reserve X8",
918 .dependencies = featureSet(&[_]Feature{}),
919 };
920 result[@intFromEnum(Feature.reserve_x9)] = .{
921 .llvm_name = "reserve-x9",
922 .description = "Reserve X9",
923 .dependencies = featureSet(&[_]Feature{}),
924 };
925 result[@intFromEnum(Feature.rva20s64)] = .{
926 .llvm_name = "rva20s64",
927 .description = "RISC-V rva20s64 profile",
928 .dependencies = featureSet(&[_]Feature{
929 .@"64bit",
930 .a,
931 .c,
932 .d,
933 .i,
934 .m,
935 .ssccptr,
936 .sstvala,
937 .sstvecd,
938 .svade,
939 .svbare,
940 .za128rs,
941 .ziccamoa,
942 .ziccif,
943 .zicclsm,
944 .ziccrse,
945 .zicntr,
946 .zifencei,
947 }),
948 };
949 result[@intFromEnum(Feature.rva20u64)] = .{
950 .llvm_name = "rva20u64",
951 .description = "RISC-V rva20u64 profile",
952 .dependencies = featureSet(&[_]Feature{
953 .@"64bit",
954 .a,
955 .c,
956 .d,
957 .i,
958 .m,
959 .za128rs,
960 .ziccamoa,
961 .ziccif,
962 .zicclsm,
963 .ziccrse,
964 .zicntr,
965 }),
966 };
967 result[@intFromEnum(Feature.rva22s64)] = .{
968 .llvm_name = "rva22s64",
969 .description = "RISC-V rva22s64 profile",
970 .dependencies = featureSet(&[_]Feature{
971 .@"64bit",
972 .a,
973 .b,
974 .c,
975 .d,
976 .i,
977 .m,
978 .ssccptr,
979 .sscounterenw,
980 .sstvala,
981 .sstvecd,
982 .svade,
983 .svbare,
984 .svinval,
985 .svpbmt,
986 .za64rs,
987 .zfhmin,
988 .zic64b,
989 .zicbom,
990 .zicbop,
991 .zicboz,
992 .ziccamoa,
993 .ziccif,
994 .zicclsm,
995 .ziccrse,
996 .zicntr,
997 .zifencei,
998 .zihintpause,
999 .zihpm,
1000 .zkt,
1001 }),
1002 };
1003 result[@intFromEnum(Feature.rva22u64)] = .{
1004 .llvm_name = "rva22u64",
1005 .description = "RISC-V rva22u64 profile",
1006 .dependencies = featureSet(&[_]Feature{
1007 .@"64bit",
1008 .a,
1009 .b,
1010 .c,
1011 .d,
1012 .i,
1013 .m,
1014 .za64rs,
1015 .zfhmin,
1016 .zic64b,
1017 .zicbom,
1018 .zicbop,
1019 .zicboz,
1020 .ziccamoa,
1021 .ziccif,
1022 .zicclsm,
1023 .ziccrse,
1024 .zicntr,
1025 .zihintpause,
1026 .zihpm,
1027 .zkt,
1028 }),
1029 };
1030 result[@intFromEnum(Feature.rva23s64)] = .{
1031 .llvm_name = "rva23s64",
1032 .description = "RISC-V rva23s64 profile",
1033 .dependencies = featureSet(&[_]Feature{
1034 .@"64bit",
1035 .a,
1036 .b,
1037 .c,
1038 .i,
1039 .m,
1040 .sha,
1041 .ssccptr,
1042 .sscofpmf,
1043 .sscounterenw,
1044 .ssnpm,
1045 .sstc,
1046 .sstvala,
1047 .sstvecd,
1048 .ssu64xl,
1049 .supm,
1050 .svade,
1051 .svbare,
1052 .svinval,
1053 .svnapot,
1054 .svpbmt,
1055 .v,
1056 .za64rs,
1057 .zawrs,
1058 .zcb,
1059 .zcmop,
1060 .zfa,
1061 .zfhmin,
1062 .zic64b,
1063 .zicbom,
1064 .zicbop,
1065 .zicboz,
1066 .ziccamoa,
1067 .ziccif,
1068 .zicclsm,
1069 .ziccrse,
1070 .zicntr,
1071 .zicond,
1072 .zifencei,
1073 .zihintntl,
1074 .zihintpause,
1075 .zihpm,
1076 .zimop,
1077 .zkt,
1078 .zvbb,
1079 .zvfhmin,
1080 .zvkt,
1081 }),
1082 };
1083 result[@intFromEnum(Feature.rva23u64)] = .{
1084 .llvm_name = "rva23u64",
1085 .description = "RISC-V rva23u64 profile",
1086 .dependencies = featureSet(&[_]Feature{
1087 .@"64bit",
1088 .a,
1089 .b,
1090 .c,
1091 .i,
1092 .m,
1093 .supm,
1094 .v,
1095 .za64rs,
1096 .zawrs,
1097 .zcb,
1098 .zcmop,
1099 .zfa,
1100 .zfhmin,
1101 .zic64b,
1102 .zicbom,
1103 .zicbop,
1104 .zicboz,
1105 .ziccamoa,
1106 .ziccif,
1107 .zicclsm,
1108 .ziccrse,
1109 .zicntr,
1110 .zicond,
1111 .zihintntl,
1112 .zihintpause,
1113 .zihpm,
1114 .zimop,
1115 .zkt,
1116 .zvbb,
1117 .zvfhmin,
1118 .zvkt,
1119 }),
1120 };
1121 result[@intFromEnum(Feature.rvb23s64)] = .{
1122 .llvm_name = "rvb23s64",
1123 .description = "RISC-V rvb23s64 profile",
1124 .dependencies = featureSet(&[_]Feature{
1125 .@"64bit",
1126 .a,
1127 .b,
1128 .c,
1129 .d,
1130 .i,
1131 .m,
1132 .ssccptr,
1133 .sscofpmf,
1134 .sscounterenw,
1135 .sstc,
1136 .sstvala,
1137 .sstvecd,
1138 .ssu64xl,
1139 .svade,
1140 .svbare,
1141 .svinval,
1142 .svnapot,
1143 .svpbmt,
1144 .za64rs,
1145 .zawrs,
1146 .zcb,
1147 .zcmop,
1148 .zfa,
1149 .zic64b,
1150 .zicbom,
1151 .zicbop,
1152 .zicboz,
1153 .ziccamoa,
1154 .ziccif,
1155 .zicclsm,
1156 .ziccrse,
1157 .zicntr,
1158 .zicond,
1159 .zifencei,
1160 .zihintntl,
1161 .zihintpause,
1162 .zihpm,
1163 .zimop,
1164 .zkt,
1165 }),
1166 };
1167 result[@intFromEnum(Feature.rvb23u64)] = .{
1168 .llvm_name = "rvb23u64",
1169 .description = "RISC-V rvb23u64 profile",
1170 .dependencies = featureSet(&[_]Feature{
1171 .@"64bit",
1172 .a,
1173 .b,
1174 .c,
1175 .d,
1176 .i,
1177 .m,
1178 .za64rs,
1179 .zawrs,
1180 .zcb,
1181 .zcmop,
1182 .zfa,
1183 .zic64b,
1184 .zicbom,
1185 .zicbop,
1186 .zicboz,
1187 .ziccamoa,
1188 .ziccif,
1189 .zicclsm,
1190 .ziccrse,
1191 .zicntr,
1192 .zicond,
1193 .zihintntl,
1194 .zihintpause,
1195 .zihpm,
1196 .zimop,
1197 .zkt,
1198 }),
1199 };
1200 result[@intFromEnum(Feature.rvi20u32)] = .{
1201 .llvm_name = "rvi20u32",
1202 .description = "RISC-V rvi20u32 profile",
1203 .dependencies = featureSet(&[_]Feature{
1204 .@"32bit",
1205 .i,
1206 }),
1207 };
1208 result[@intFromEnum(Feature.rvi20u64)] = .{
1209 .llvm_name = "rvi20u64",
1210 .description = "RISC-V rvi20u64 profile",
1211 .dependencies = featureSet(&[_]Feature{
1212 .@"64bit",
1213 .i,
1214 }),
1215 };
1216 result[@intFromEnum(Feature.save_restore)] = .{
1217 .llvm_name = "save-restore",
1218 .description = "Enable save/restore.",
1219 .dependencies = featureSet(&[_]Feature{}),
1220 };
1221 result[@intFromEnum(Feature.sdext)] = .{
1222 .llvm_name = "sdext",
1223 .description = "'Sdext' (External debugger)",
1224 .dependencies = featureSet(&[_]Feature{}),
1225 };
1226 result[@intFromEnum(Feature.sdtrig)] = .{
1227 .llvm_name = "sdtrig",
1228 .description = "'Sdtrig' (Debugger triggers)",
1229 .dependencies = featureSet(&[_]Feature{}),
1230 };
1231 result[@intFromEnum(Feature.sha)] = .{
1232 .llvm_name = "sha",
1233 .description = "'Sha' (Augmented Hypervisor)",
1234 .dependencies = featureSet(&[_]Feature{
1235 .h,
1236 .shcounterenw,
1237 .shgatpa,
1238 .shtvala,
1239 .shvsatpa,
1240 .shvstvala,
1241 .shvstvecd,
1242 .ssstateen,
1243 }),
1244 };
1245 result[@intFromEnum(Feature.shcounterenw)] = .{
1246 .llvm_name = "shcounterenw",
1247 .description = "'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero)",
1248 .dependencies = featureSet(&[_]Feature{}),
1249 };
1250 result[@intFromEnum(Feature.shgatpa)] = .{
1251 .llvm_name = "shgatpa",
1252 .description = "'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)",
1253 .dependencies = featureSet(&[_]Feature{}),
1254 };
1255 result[@intFromEnum(Feature.shifted_zextw_fusion)] = .{
1256 .llvm_name = "shifted-zextw-fusion",
1257 .description = "Enable SLLI+SRLI to be fused when computing (shifted) word zero extension",
1258 .dependencies = featureSet(&[_]Feature{}),
1259 };
1260 result[@intFromEnum(Feature.shlcofideleg)] = .{
1261 .llvm_name = "shlcofideleg",
1262 .description = "'Shlcofideleg' (Delegating LCOFI Interrupts to VS-mode)",
1263 .dependencies = featureSet(&[_]Feature{}),
1264 };
1265 result[@intFromEnum(Feature.short_forward_branch_opt)] = .{
1266 .llvm_name = "short-forward-branch-opt",
1267 .description = "Enable short forward branch optimization",
1268 .dependencies = featureSet(&[_]Feature{}),
1269 };
1270 result[@intFromEnum(Feature.shtvala)] = .{
1271 .llvm_name = "shtvala",
1272 .description = "'Shtvala' (htval provides all needed values)",
1273 .dependencies = featureSet(&[_]Feature{}),
1274 };
1275 result[@intFromEnum(Feature.shvsatpa)] = .{
1276 .llvm_name = "shvsatpa",
1277 .description = "'Shvsatpa' (vsatp supports all modes supported by satp)",
1278 .dependencies = featureSet(&[_]Feature{}),
1279 };
1280 result[@intFromEnum(Feature.shvstvala)] = .{
1281 .llvm_name = "shvstvala",
1282 .description = "'Shvstvala' (vstval provides all needed values)",
1283 .dependencies = featureSet(&[_]Feature{}),
1284 };
1285 result[@intFromEnum(Feature.shvstvecd)] = .{
1286 .llvm_name = "shvstvecd",
1287 .description = "'Shvstvecd' (vstvec supports Direct mode)",
1288 .dependencies = featureSet(&[_]Feature{}),
1289 };
1290 result[@intFromEnum(Feature.smaia)] = .{
1291 .llvm_name = "smaia",
1292 .description = "'Smaia' (Advanced Interrupt Architecture Machine Level)",
1293 .dependencies = featureSet(&[_]Feature{}),
1294 };
1295 result[@intFromEnum(Feature.smcdeleg)] = .{
1296 .llvm_name = "smcdeleg",
1297 .description = "'Smcdeleg' (Counter Delegation Machine Level)",
1298 .dependencies = featureSet(&[_]Feature{}),
1299 };
1300 result[@intFromEnum(Feature.smcntrpmf)] = .{
1301 .llvm_name = "smcntrpmf",
1302 .description = "'Smcntrpmf' (Cycle and Instret Privilege Mode Filtering)",
1303 .dependencies = featureSet(&[_]Feature{}),
1304 };
1305 result[@intFromEnum(Feature.smcsrind)] = .{
1306 .llvm_name = "smcsrind",
1307 .description = "'Smcsrind' (Indirect CSR Access Machine Level)",
1308 .dependencies = featureSet(&[_]Feature{}),
1309 };
1310 result[@intFromEnum(Feature.smdbltrp)] = .{
1311 .llvm_name = "smdbltrp",
1312 .description = "'Smdbltrp' (Double Trap Machine Level)",
1313 .dependencies = featureSet(&[_]Feature{
1314 .zicsr,
1315 }),
1316 };
1317 result[@intFromEnum(Feature.smepmp)] = .{
1318 .llvm_name = "smepmp",
1319 .description = "'Smepmp' (Enhanced Physical Memory Protection)",
1320 .dependencies = featureSet(&[_]Feature{}),
1321 };
1322 result[@intFromEnum(Feature.smmpm)] = .{
1323 .llvm_name = "smmpm",
1324 .description = "'Smmpm' (Machine-level Pointer Masking for M-mode)",
1325 .dependencies = featureSet(&[_]Feature{}),
1326 };
1327 result[@intFromEnum(Feature.smnpm)] = .{
1328 .llvm_name = "smnpm",
1329 .description = "'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)",
1330 .dependencies = featureSet(&[_]Feature{}),
1331 };
1332 result[@intFromEnum(Feature.smrnmi)] = .{
1333 .llvm_name = "smrnmi",
1334 .description = "'Smrnmi' (Resumable Non-Maskable Interrupts)",
1335 .dependencies = featureSet(&[_]Feature{}),
1336 };
1337 result[@intFromEnum(Feature.smstateen)] = .{
1338 .llvm_name = "smstateen",
1339 .description = "'Smstateen' (Machine-mode view of the state-enable extension)",
1340 .dependencies = featureSet(&[_]Feature{}),
1341 };
1342 result[@intFromEnum(Feature.ssaia)] = .{
1343 .llvm_name = "ssaia",
1344 .description = "'Ssaia' (Advanced Interrupt Architecture Supervisor Level)",
1345 .dependencies = featureSet(&[_]Feature{}),
1346 };
1347 result[@intFromEnum(Feature.ssccfg)] = .{
1348 .llvm_name = "ssccfg",
1349 .description = "'Ssccfg' (Counter Configuration Supervisor Level)",
1350 .dependencies = featureSet(&[_]Feature{}),
1351 };
1352 result[@intFromEnum(Feature.ssccptr)] = .{
1353 .llvm_name = "ssccptr",
1354 .description = "'Ssccptr' (Main memory supports page table reads)",
1355 .dependencies = featureSet(&[_]Feature{}),
1356 };
1357 result[@intFromEnum(Feature.sscofpmf)] = .{
1358 .llvm_name = "sscofpmf",
1359 .description = "'Sscofpmf' (Count Overflow and Mode-Based Filtering)",
1360 .dependencies = featureSet(&[_]Feature{}),
1361 };
1362 result[@intFromEnum(Feature.sscounterenw)] = .{
1363 .llvm_name = "sscounterenw",
1364 .description = "'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero)",
1365 .dependencies = featureSet(&[_]Feature{}),
1366 };
1367 result[@intFromEnum(Feature.sscsrind)] = .{
1368 .llvm_name = "sscsrind",
1369 .description = "'Sscsrind' (Indirect CSR Access Supervisor Level)",
1370 .dependencies = featureSet(&[_]Feature{}),
1371 };
1372 result[@intFromEnum(Feature.ssdbltrp)] = .{
1373 .llvm_name = "ssdbltrp",
1374 .description = "'Ssdbltrp' (Double Trap Supervisor Level)",
1375 .dependencies = featureSet(&[_]Feature{
1376 .zicsr,
1377 }),
1378 };
1379 result[@intFromEnum(Feature.ssnpm)] = .{
1380 .llvm_name = "ssnpm",
1381 .description = "'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)",
1382 .dependencies = featureSet(&[_]Feature{}),
1383 };
1384 result[@intFromEnum(Feature.sspm)] = .{
1385 .llvm_name = "sspm",
1386 .description = "'Sspm' (Indicates Supervisor-mode Pointer Masking)",
1387 .dependencies = featureSet(&[_]Feature{}),
1388 };
1389 result[@intFromEnum(Feature.ssqosid)] = .{
1390 .llvm_name = "ssqosid",
1391 .description = "'Ssqosid' (Quality-of-Service (QoS) Identifiers)",
1392 .dependencies = featureSet(&[_]Feature{}),
1393 };
1394 result[@intFromEnum(Feature.ssstateen)] = .{
1395 .llvm_name = "ssstateen",
1396 .description = "'Ssstateen' (Supervisor-mode view of the state-enable extension)",
1397 .dependencies = featureSet(&[_]Feature{}),
1398 };
1399 result[@intFromEnum(Feature.ssstrict)] = .{
1400 .llvm_name = "ssstrict",
1401 .description = "'Ssstrict' (No non-conforming extensions are present)",
1402 .dependencies = featureSet(&[_]Feature{}),
1403 };
1404 result[@intFromEnum(Feature.sstc)] = .{
1405 .llvm_name = "sstc",
1406 .description = "'Sstc' (Supervisor-mode timer interrupts)",
1407 .dependencies = featureSet(&[_]Feature{}),
1408 };
1409 result[@intFromEnum(Feature.sstvala)] = .{
1410 .llvm_name = "sstvala",
1411 .description = "'Sstvala' (stval provides all needed values)",
1412 .dependencies = featureSet(&[_]Feature{}),
1413 };
1414 result[@intFromEnum(Feature.sstvecd)] = .{
1415 .llvm_name = "sstvecd",
1416 .description = "'Sstvecd' (stvec supports Direct mode)",
1417 .dependencies = featureSet(&[_]Feature{}),
1418 };
1419 result[@intFromEnum(Feature.ssu64xl)] = .{
1420 .llvm_name = "ssu64xl",
1421 .description = "'Ssu64xl' (UXLEN=64 supported)",
1422 .dependencies = featureSet(&[_]Feature{}),
1423 };
1424 result[@intFromEnum(Feature.supm)] = .{
1425 .llvm_name = "supm",
1426 .description = "'Supm' (Indicates User-mode Pointer Masking)",
1427 .dependencies = featureSet(&[_]Feature{}),
1428 };
1429 result[@intFromEnum(Feature.svade)] = .{
1430 .llvm_name = "svade",
1431 .description = "'Svade' (Raise exceptions on improper A/D bits)",
1432 .dependencies = featureSet(&[_]Feature{}),
1433 };
1434 result[@intFromEnum(Feature.svadu)] = .{
1435 .llvm_name = "svadu",
1436 .description = "'Svadu' (Hardware A/D updates)",
1437 .dependencies = featureSet(&[_]Feature{}),
1438 };
1439 result[@intFromEnum(Feature.svbare)] = .{
1440 .llvm_name = "svbare",
1441 .description = "'Svbare' (satp mode Bare supported)",
1442 .dependencies = featureSet(&[_]Feature{}),
1443 };
1444 result[@intFromEnum(Feature.svinval)] = .{
1445 .llvm_name = "svinval",
1446 .description = "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)",
1447 .dependencies = featureSet(&[_]Feature{}),
1448 };
1449 result[@intFromEnum(Feature.svnapot)] = .{
1450 .llvm_name = "svnapot",
1451 .description = "'Svnapot' (NAPOT Translation Contiguity)",
1452 .dependencies = featureSet(&[_]Feature{}),
1453 };
1454 result[@intFromEnum(Feature.svpbmt)] = .{
1455 .llvm_name = "svpbmt",
1456 .description = "'Svpbmt' (Page-Based Memory Types)",
1457 .dependencies = featureSet(&[_]Feature{}),
1458 };
1459 result[@intFromEnum(Feature.svvptc)] = .{
1460 .llvm_name = "svvptc",
1461 .description = "'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)",
1462 .dependencies = featureSet(&[_]Feature{}),
1463 };
1464 result[@intFromEnum(Feature.tagged_globals)] = .{
1465 .llvm_name = "tagged-globals",
1466 .description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits",
1467 .dependencies = featureSet(&[_]Feature{}),
1468 };
1469 result[@intFromEnum(Feature.unaligned_scalar_mem)] = .{
1470 .llvm_name = "unaligned-scalar-mem",
1471 .description = "Has reasonably performant unaligned scalar loads and stores",
1472 .dependencies = featureSet(&[_]Feature{}),
1473 };
1474 result[@intFromEnum(Feature.unaligned_vector_mem)] = .{
1475 .llvm_name = "unaligned-vector-mem",
1476 .description = "Has reasonably performant unaligned vector loads and stores",
1477 .dependencies = featureSet(&[_]Feature{}),
1478 };
1479 result[@intFromEnum(Feature.use_postra_scheduler)] = .{
1480 .llvm_name = "use-postra-scheduler",
1481 .description = "Schedule again after register allocation",
1482 .dependencies = featureSet(&[_]Feature{}),
1483 };
1484 result[@intFromEnum(Feature.v)] = .{
1485 .llvm_name = "v",
1486 .description = "'V' (Vector Extension for Application Processors)",
1487 .dependencies = featureSet(&[_]Feature{
1488 .zve64d,
1489 .zvl128b,
1490 }),
1491 };
1492 result[@intFromEnum(Feature.ventana_veyron)] = .{
1493 .llvm_name = "ventana-veyron",
1494 .description = "Ventana Veyron-Series processors",
1495 .dependencies = featureSet(&[_]Feature{}),
1496 };
1497 result[@intFromEnum(Feature.vl_dependent_latency)] = .{
1498 .llvm_name = "vl-dependent-latency",
1499 .description = "Latency of vector instructions is dependent on the dynamic value of vl",
1500 .dependencies = featureSet(&[_]Feature{}),
1501 };
1502 result[@intFromEnum(Feature.vxrm_pipeline_flush)] = .{
1503 .llvm_name = "vxrm-pipeline-flush",
1504 .description = "VXRM writes causes pipeline flush",
1505 .dependencies = featureSet(&[_]Feature{}),
1506 };
1507 result[@intFromEnum(Feature.xandesbfhcvt)] = .{
1508 .llvm_name = "xandesbfhcvt",
1509 .description = "'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension)",
1510 .dependencies = featureSet(&[_]Feature{
1511 .f,
1512 }),
1513 };
1514 result[@intFromEnum(Feature.xandesperf)] = .{
1515 .llvm_name = "xandesperf",
1516 .description = "'XAndesPerf' (Andes Performance Extension)",
1517 .dependencies = featureSet(&[_]Feature{}),
1518 };
1519 result[@intFromEnum(Feature.xandesvbfhcvt)] = .{
1520 .llvm_name = "xandesvbfhcvt",
1521 .description = "'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)",
1522 .dependencies = featureSet(&[_]Feature{
1523 .zve32f,
1524 }),
1525 };
1526 result[@intFromEnum(Feature.xandesvdot)] = .{
1527 .llvm_name = "xandesvdot",
1528 .description = "'XAndesVDot' (Andes Vector Dot Product Extension)",
1529 .dependencies = featureSet(&[_]Feature{
1530 .zve32x,
1531 }),
1532 };
1533 result[@intFromEnum(Feature.xandesvpackfph)] = .{
1534 .llvm_name = "xandesvpackfph",
1535 .description = "'XAndesVPackFPH' (Andes Vector Packed FP16 Extension)",
1536 .dependencies = featureSet(&[_]Feature{
1537 .f,
1538 }),
1539 };
1540 result[@intFromEnum(Feature.xandesvsintload)] = .{
1541 .llvm_name = "xandesvsintload",
1542 .description = "'XAndesVSIntLoad' (Andes Vector INT4 Load Extension)",
1543 .dependencies = featureSet(&[_]Feature{
1544 .zve32x,
1545 }),
1546 };
1547 result[@intFromEnum(Feature.xcvalu)] = .{
1548 .llvm_name = "xcvalu",
1549 .description = "'XCValu' (CORE-V ALU Operations)",
1550 .dependencies = featureSet(&[_]Feature{}),
1551 };
1552 result[@intFromEnum(Feature.xcvbi)] = .{
1553 .llvm_name = "xcvbi",
1554 .description = "'XCVbi' (CORE-V Immediate Branching)",
1555 .dependencies = featureSet(&[_]Feature{}),
1556 };
1557 result[@intFromEnum(Feature.xcvbitmanip)] = .{
1558 .llvm_name = "xcvbitmanip",
1559 .description = "'XCVbitmanip' (CORE-V Bit Manipulation)",
1560 .dependencies = featureSet(&[_]Feature{}),
1561 };
1562 result[@intFromEnum(Feature.xcvelw)] = .{
1563 .llvm_name = "xcvelw",
1564 .description = "'XCVelw' (CORE-V Event Load Word)",
1565 .dependencies = featureSet(&[_]Feature{}),
1566 };
1567 result[@intFromEnum(Feature.xcvmac)] = .{
1568 .llvm_name = "xcvmac",
1569 .description = "'XCVmac' (CORE-V Multiply-Accumulate)",
1570 .dependencies = featureSet(&[_]Feature{}),
1571 };
1572 result[@intFromEnum(Feature.xcvmem)] = .{
1573 .llvm_name = "xcvmem",
1574 .description = "'XCVmem' (CORE-V Post-incrementing Load & Store)",
1575 .dependencies = featureSet(&[_]Feature{}),
1576 };
1577 result[@intFromEnum(Feature.xcvsimd)] = .{
1578 .llvm_name = "xcvsimd",
1579 .description = "'XCVsimd' (CORE-V SIMD ALU)",
1580 .dependencies = featureSet(&[_]Feature{}),
1581 };
1582 result[@intFromEnum(Feature.xmipscbop)] = .{
1583 .llvm_name = "xmipscbop",
1584 .description = "'XMIPSCBOP' (MIPS Software Prefetch)",
1585 .dependencies = featureSet(&[_]Feature{}),
1586 };
1587 result[@intFromEnum(Feature.xmipscmov)] = .{
1588 .llvm_name = "xmipscmov",
1589 .description = "'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov))",
1590 .dependencies = featureSet(&[_]Feature{}),
1591 };
1592 result[@intFromEnum(Feature.xmipslsp)] = .{
1593 .llvm_name = "xmipslsp",
1594 .description = "'XMIPSLSP' (MIPS optimization for hardware load-store bonding)",
1595 .dependencies = featureSet(&[_]Feature{}),
1596 };
1597 result[@intFromEnum(Feature.xsfcease)] = .{
1598 .llvm_name = "xsfcease",
1599 .description = "'XSfcease' (SiFive sf.cease Instruction)",
1600 .dependencies = featureSet(&[_]Feature{}),
1601 };
1602 result[@intFromEnum(Feature.xsfmm128t)] = .{
1603 .llvm_name = "xsfmm128t",
1604 .description = "'XSfmm128t' (TE=128 configuration)",
1605 .dependencies = featureSet(&[_]Feature{
1606 .xsfmmbase,
1607 .zvl512b,
1608 }),
1609 };
1610 result[@intFromEnum(Feature.xsfmm16t)] = .{
1611 .llvm_name = "xsfmm16t",
1612 .description = "'XSfmm16t' (TE=16 configuration)",
1613 .dependencies = featureSet(&[_]Feature{
1614 .xsfmmbase,
1615 .zvl64b,
1616 }),
1617 };
1618 result[@intFromEnum(Feature.xsfmm32a16f)] = .{
1619 .llvm_name = "xsfmm32a16f",
1620 .description = "'XSfmm32a16f' (TEW=32-bit accumulation, operands - float: 16b, widen=2 (IEEE, BF))",
1621 .dependencies = featureSet(&[_]Feature{
1622 .xsfmmbase,
1623 .zve32f,
1624 }),
1625 };
1626 result[@intFromEnum(Feature.xsfmm32a32f)] = .{
1627 .llvm_name = "xsfmm32a32f",
1628 .description = "'XSfmm32a32f' (TEW=32-bit accumulation, operands - float: 32b)",
1629 .dependencies = featureSet(&[_]Feature{
1630 .xsfmmbase,
1631 .zve32f,
1632 }),
1633 };
1634 result[@intFromEnum(Feature.xsfmm32a8f)] = .{
1635 .llvm_name = "xsfmm32a8f",
1636 .description = "'XSfmm32a8f' (TEW=32-bit accumulation, operands - float: fp8)",
1637 .dependencies = featureSet(&[_]Feature{
1638 .xsfmmbase,
1639 .zve32f,
1640 }),
1641 };
1642 result[@intFromEnum(Feature.xsfmm32a8i)] = .{
1643 .llvm_name = "xsfmm32a8i",
1644 .description = "'XSfmm32a8i' (TEW=32-bit accumulation, operands - int: 8b)",
1645 .dependencies = featureSet(&[_]Feature{
1646 .xsfmmbase,
1647 }),
1648 };
1649 result[@intFromEnum(Feature.xsfmm32t)] = .{
1650 .llvm_name = "xsfmm32t",
1651 .description = "'XSfmm32t' (TE=32 configuration)",
1652 .dependencies = featureSet(&[_]Feature{
1653 .xsfmmbase,
1654 .zvl128b,
1655 }),
1656 };
1657 result[@intFromEnum(Feature.xsfmm64a64f)] = .{
1658 .llvm_name = "xsfmm64a64f",
1659 .description = "'XSfmm64a64f' (TEW=64-bit accumulation, operands - float: fp64)",
1660 .dependencies = featureSet(&[_]Feature{
1661 .xsfmmbase,
1662 .zve64d,
1663 }),
1664 };
1665 result[@intFromEnum(Feature.xsfmm64t)] = .{
1666 .llvm_name = "xsfmm64t",
1667 .description = "'XSfmm64t' (TE=64 configuration)",
1668 .dependencies = featureSet(&[_]Feature{
1669 .xsfmmbase,
1670 .zvl256b,
1671 }),
1672 };
1673 result[@intFromEnum(Feature.xsfmmbase)] = .{
1674 .llvm_name = "xsfmmbase",
1675 .description = "'XSfmmbase' (All non arithmetic instructions for all TEWs and sf.vtzero)",
1676 .dependencies = featureSet(&[_]Feature{
1677 .zve32x,
1678 }),
1679 };
1680 result[@intFromEnum(Feature.xsfvcp)] = .{
1681 .llvm_name = "xsfvcp",
1682 .description = "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)",
1683 .dependencies = featureSet(&[_]Feature{
1684 .zve32x,
1685 }),
1686 };
1687 result[@intFromEnum(Feature.xsfvfnrclipxfqf)] = .{
1688 .llvm_name = "xsfvfnrclipxfqf",
1689 .description = "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)",
1690 .dependencies = featureSet(&[_]Feature{
1691 .zve32f,
1692 }),
1693 };
1694 result[@intFromEnum(Feature.xsfvfwmaccqqq)] = .{
1695 .llvm_name = "xsfvfwmaccqqq",
1696 .description = "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction (4-by-4))",
1697 .dependencies = featureSet(&[_]Feature{
1698 .zvfbfmin,
1699 }),
1700 };
1701 result[@intFromEnum(Feature.xsfvqmaccdod)] = .{
1702 .llvm_name = "xsfvqmaccdod",
1703 .description = "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))",
1704 .dependencies = featureSet(&[_]Feature{
1705 .zve32x,
1706 }),
1707 };
1708 result[@intFromEnum(Feature.xsfvqmaccqoq)] = .{
1709 .llvm_name = "xsfvqmaccqoq",
1710 .description = "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))",
1711 .dependencies = featureSet(&[_]Feature{
1712 .zve32x,
1713 }),
1714 };
1715 result[@intFromEnum(Feature.xsifivecdiscarddlone)] = .{
1716 .llvm_name = "xsifivecdiscarddlone",
1717 .description = "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)",
1718 .dependencies = featureSet(&[_]Feature{}),
1719 };
1720 result[@intFromEnum(Feature.xsifivecflushdlone)] = .{
1721 .llvm_name = "xsifivecflushdlone",
1722 .description = "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)",
1723 .dependencies = featureSet(&[_]Feature{}),
1724 };
1725 result[@intFromEnum(Feature.xtheadba)] = .{
1726 .llvm_name = "xtheadba",
1727 .description = "'XTHeadBa' (T-Head address calculation instructions)",
1728 .dependencies = featureSet(&[_]Feature{}),
1729 };
1730 result[@intFromEnum(Feature.xtheadbb)] = .{
1731 .llvm_name = "xtheadbb",
1732 .description = "'XTHeadBb' (T-Head basic bit-manipulation instructions)",
1733 .dependencies = featureSet(&[_]Feature{}),
1734 };
1735 result[@intFromEnum(Feature.xtheadbs)] = .{
1736 .llvm_name = "xtheadbs",
1737 .description = "'XTHeadBs' (T-Head single-bit instructions)",
1738 .dependencies = featureSet(&[_]Feature{}),
1739 };
1740 result[@intFromEnum(Feature.xtheadcmo)] = .{
1741 .llvm_name = "xtheadcmo",
1742 .description = "'XTHeadCmo' (T-Head cache management instructions)",
1743 .dependencies = featureSet(&[_]Feature{}),
1744 };
1745 result[@intFromEnum(Feature.xtheadcondmov)] = .{
1746 .llvm_name = "xtheadcondmov",
1747 .description = "'XTHeadCondMov' (T-Head conditional move instructions)",
1748 .dependencies = featureSet(&[_]Feature{}),
1749 };
1750 result[@intFromEnum(Feature.xtheadfmemidx)] = .{
1751 .llvm_name = "xtheadfmemidx",
1752 .description = "'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)",
1753 .dependencies = featureSet(&[_]Feature{}),
1754 };
1755 result[@intFromEnum(Feature.xtheadmac)] = .{
1756 .llvm_name = "xtheadmac",
1757 .description = "'XTHeadMac' (T-Head Multiply-Accumulate Instructions)",
1758 .dependencies = featureSet(&[_]Feature{}),
1759 };
1760 result[@intFromEnum(Feature.xtheadmemidx)] = .{
1761 .llvm_name = "xtheadmemidx",
1762 .description = "'XTHeadMemIdx' (T-Head Indexed Memory Operations)",
1763 .dependencies = featureSet(&[_]Feature{}),
1764 };
1765 result[@intFromEnum(Feature.xtheadmempair)] = .{
1766 .llvm_name = "xtheadmempair",
1767 .description = "'XTHeadMemPair' (T-Head two-GPR Memory Operations)",
1768 .dependencies = featureSet(&[_]Feature{}),
1769 };
1770 result[@intFromEnum(Feature.xtheadsync)] = .{
1771 .llvm_name = "xtheadsync",
1772 .description = "'XTHeadSync' (T-Head multicore synchronization instructions)",
1773 .dependencies = featureSet(&[_]Feature{}),
1774 };
1775 result[@intFromEnum(Feature.xtheadvdot)] = .{
1776 .llvm_name = "xtheadvdot",
1777 .description = "'XTHeadVdot' (T-Head Vector Extensions for Dot)",
1778 .dependencies = featureSet(&[_]Feature{
1779 .v,
1780 }),
1781 };
1782 result[@intFromEnum(Feature.xventanacondops)] = .{
1783 .llvm_name = "xventanacondops",
1784 .description = "'XVentanaCondOps' (Ventana Conditional Ops)",
1785 .dependencies = featureSet(&[_]Feature{}),
1786 };
1787 result[@intFromEnum(Feature.xwchc)] = .{
1788 .llvm_name = "xwchc",
1789 .description = "'Xwchc' (WCH/QingKe additional compressed opcodes)",
1790 .dependencies = featureSet(&[_]Feature{
1791 .zca,
1792 }),
1793 };
1794 result[@intFromEnum(Feature.za128rs)] = .{
1795 .llvm_name = "za128rs",
1796 .description = "'Za128rs' (Reservation Set Size of at Most 128 Bytes)",
1797 .dependencies = featureSet(&[_]Feature{}),
1798 };
1799 result[@intFromEnum(Feature.za64rs)] = .{
1800 .llvm_name = "za64rs",
1801 .description = "'Za64rs' (Reservation Set Size of at Most 64 Bytes)",
1802 .dependencies = featureSet(&[_]Feature{}),
1803 };
1804 result[@intFromEnum(Feature.zaamo)] = .{
1805 .llvm_name = "zaamo",
1806 .description = "'Zaamo' (Atomic Memory Operations)",
1807 .dependencies = featureSet(&[_]Feature{}),
1808 };
1809 result[@intFromEnum(Feature.zabha)] = .{
1810 .llvm_name = "zabha",
1811 .description = "'Zabha' (Byte and Halfword Atomic Memory Operations)",
1812 .dependencies = featureSet(&[_]Feature{
1813 .zaamo,
1814 }),
1815 };
1816 result[@intFromEnum(Feature.zacas)] = .{
1817 .llvm_name = "zacas",
1818 .description = "'Zacas' (Atomic Compare-And-Swap Instructions)",
1819 .dependencies = featureSet(&[_]Feature{
1820 .zaamo,
1821 }),
1822 };
1823 result[@intFromEnum(Feature.zalrsc)] = .{
1824 .llvm_name = "zalrsc",
1825 .description = "'Zalrsc' (Load-Reserved/Store-Conditional)",
1826 .dependencies = featureSet(&[_]Feature{}),
1827 };
1828 result[@intFromEnum(Feature.zama16b)] = .{
1829 .llvm_name = "zama16b",
1830 .description = "'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)",
1831 .dependencies = featureSet(&[_]Feature{}),
1832 };
1833 result[@intFromEnum(Feature.zawrs)] = .{
1834 .llvm_name = "zawrs",
1835 .description = "'Zawrs' (Wait on Reservation Set)",
1836 .dependencies = featureSet(&[_]Feature{}),
1837 };
1838 result[@intFromEnum(Feature.zba)] = .{
1839 .llvm_name = "zba",
1840 .description = "'Zba' (Address Generation Instructions)",
1841 .dependencies = featureSet(&[_]Feature{}),
1842 };
1843 result[@intFromEnum(Feature.zbb)] = .{
1844 .llvm_name = "zbb",
1845 .description = "'Zbb' (Basic Bit-Manipulation)",
1846 .dependencies = featureSet(&[_]Feature{}),
1847 };
1848 result[@intFromEnum(Feature.zbc)] = .{
1849 .llvm_name = "zbc",
1850 .description = "'Zbc' (Carry-Less Multiplication)",
1851 .dependencies = featureSet(&[_]Feature{}),
1852 };
1853 result[@intFromEnum(Feature.zbkb)] = .{
1854 .llvm_name = "zbkb",
1855 .description = "'Zbkb' (Bitmanip instructions for Cryptography)",
1856 .dependencies = featureSet(&[_]Feature{}),
1857 };
1858 result[@intFromEnum(Feature.zbkc)] = .{
1859 .llvm_name = "zbkc",
1860 .description = "'Zbkc' (Carry-less multiply instructions for Cryptography)",
1861 .dependencies = featureSet(&[_]Feature{}),
1862 };
1863 result[@intFromEnum(Feature.zbkx)] = .{
1864 .llvm_name = "zbkx",
1865 .description = "'Zbkx' (Crossbar permutation instructions)",
1866 .dependencies = featureSet(&[_]Feature{}),
1867 };
1868 result[@intFromEnum(Feature.zbs)] = .{
1869 .llvm_name = "zbs",
1870 .description = "'Zbs' (Single-Bit Instructions)",
1871 .dependencies = featureSet(&[_]Feature{}),
1872 };
1873 result[@intFromEnum(Feature.zca)] = .{
1874 .llvm_name = "zca",
1875 .description = "'Zca' (part of the C extension, excluding compressed floating point loads/stores)",
1876 .dependencies = featureSet(&[_]Feature{}),
1877 };
1878 result[@intFromEnum(Feature.zcb)] = .{
1879 .llvm_name = "zcb",
1880 .description = "'Zcb' (Compressed basic bit manipulation instructions)",
1881 .dependencies = featureSet(&[_]Feature{
1882 .zca,
1883 }),
1884 };
1885 result[@intFromEnum(Feature.zcd)] = .{
1886 .llvm_name = "zcd",
1887 .description = "'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
1888 .dependencies = featureSet(&[_]Feature{
1889 .d,
1890 .zca,
1891 }),
1892 };
1893 result[@intFromEnum(Feature.zce)] = .{
1894 .llvm_name = "zce",
1895 .description = "'Zce' (Compressed extensions for microcontrollers)",
1896 .dependencies = featureSet(&[_]Feature{
1897 .zcb,
1898 .zcmp,
1899 .zcmt,
1900 }),
1901 };
1902 result[@intFromEnum(Feature.zcf)] = .{
1903 .llvm_name = "zcf",
1904 .description = "'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
1905 .dependencies = featureSet(&[_]Feature{
1906 .f,
1907 .zca,
1908 }),
1909 };
1910 result[@intFromEnum(Feature.zclsd)] = .{
1911 .llvm_name = "zclsd",
1912 .description = "'Zclsd' (Compressed Load/Store Pair Instructions)",
1913 .dependencies = featureSet(&[_]Feature{
1914 .zca,
1915 .zilsd,
1916 }),
1917 };
1918 result[@intFromEnum(Feature.zcmop)] = .{
1919 .llvm_name = "zcmop",
1920 .description = "'Zcmop' (Compressed May-Be-Operations)",
1921 .dependencies = featureSet(&[_]Feature{
1922 .zca,
1923 }),
1924 };
1925 result[@intFromEnum(Feature.zcmp)] = .{
1926 .llvm_name = "zcmp",
1927 .description = "'Zcmp' (sequenced instructions for code-size reduction)",
1928 .dependencies = featureSet(&[_]Feature{
1929 .zca,
1930 }),
1931 };
1932 result[@intFromEnum(Feature.zcmt)] = .{
1933 .llvm_name = "zcmt",
1934 .description = "'Zcmt' (table jump instructions for code-size reduction)",
1935 .dependencies = featureSet(&[_]Feature{
1936 .zca,
1937 .zicsr,
1938 }),
1939 };
1940 result[@intFromEnum(Feature.zdinx)] = .{
1941 .llvm_name = "zdinx",
1942 .description = "'Zdinx' (Double in Integer)",
1943 .dependencies = featureSet(&[_]Feature{
1944 .zfinx,
1945 }),
1946 };
1947 result[@intFromEnum(Feature.zexth_fusion)] = .{
1948 .llvm_name = "zexth-fusion",
1949 .description = "Enable SLLI+SRLI to be fused to zero extension of halfword",
1950 .dependencies = featureSet(&[_]Feature{}),
1951 };
1952 result[@intFromEnum(Feature.zextw_fusion)] = .{
1953 .llvm_name = "zextw-fusion",
1954 .description = "Enable SLLI+SRLI to be fused to zero extension of word",
1955 .dependencies = featureSet(&[_]Feature{}),
1956 };
1957 result[@intFromEnum(Feature.zfa)] = .{
1958 .llvm_name = "zfa",
1959 .description = "'Zfa' (Additional Floating-Point)",
1960 .dependencies = featureSet(&[_]Feature{
1961 .f,
1962 }),
1963 };
1964 result[@intFromEnum(Feature.zfbfmin)] = .{
1965 .llvm_name = "zfbfmin",
1966 .description = "'Zfbfmin' (Scalar BF16 Converts)",
1967 .dependencies = featureSet(&[_]Feature{
1968 .f,
1969 }),
1970 };
1971 result[@intFromEnum(Feature.zfh)] = .{
1972 .llvm_name = "zfh",
1973 .description = "'Zfh' (Half-Precision Floating-Point)",
1974 .dependencies = featureSet(&[_]Feature{
1975 .zfhmin,
1976 }),
1977 };
1978 result[@intFromEnum(Feature.zfhmin)] = .{
1979 .llvm_name = "zfhmin",
1980 .description = "'Zfhmin' (Half-Precision Floating-Point Minimal)",
1981 .dependencies = featureSet(&[_]Feature{
1982 .f,
1983 }),
1984 };
1985 result[@intFromEnum(Feature.zfinx)] = .{
1986 .llvm_name = "zfinx",
1987 .description = "'Zfinx' (Float in Integer)",
1988 .dependencies = featureSet(&[_]Feature{
1989 .zicsr,
1990 }),
1991 };
1992 result[@intFromEnum(Feature.zhinx)] = .{
1993 .llvm_name = "zhinx",
1994 .description = "'Zhinx' (Half Float in Integer)",
1995 .dependencies = featureSet(&[_]Feature{
1996 .zhinxmin,
1997 }),
1998 };
1999 result[@intFromEnum(Feature.zhinxmin)] = .{
2000 .llvm_name = "zhinxmin",
2001 .description = "'Zhinxmin' (Half Float in Integer Minimal)",
2002 .dependencies = featureSet(&[_]Feature{
2003 .zfinx,
2004 }),
2005 };
2006 result[@intFromEnum(Feature.zic64b)] = .{
2007 .llvm_name = "zic64b",
2008 .description = "'Zic64b' (Cache Block Size Is 64 Bytes)",
2009 .dependencies = featureSet(&[_]Feature{}),
2010 };
2011 result[@intFromEnum(Feature.zicbom)] = .{
2012 .llvm_name = "zicbom",
2013 .description = "'Zicbom' (Cache-Block Management Instructions)",
2014 .dependencies = featureSet(&[_]Feature{}),
2015 };
2016 result[@intFromEnum(Feature.zicbop)] = .{
2017 .llvm_name = "zicbop",
2018 .description = "'Zicbop' (Cache-Block Prefetch Instructions)",
2019 .dependencies = featureSet(&[_]Feature{}),
2020 };
2021 result[@intFromEnum(Feature.zicboz)] = .{
2022 .llvm_name = "zicboz",
2023 .description = "'Zicboz' (Cache-Block Zero Instructions)",
2024 .dependencies = featureSet(&[_]Feature{}),
2025 };
2026 result[@intFromEnum(Feature.ziccamoa)] = .{
2027 .llvm_name = "ziccamoa",
2028 .description = "'Ziccamoa' (Main Memory Supports All Atomics in A)",
2029 .dependencies = featureSet(&[_]Feature{}),
2030 };
2031 result[@intFromEnum(Feature.ziccamoc)] = .{
2032 .llvm_name = "ziccamoc",
2033 .description = "'Ziccamoc' (Main Memory Supports Atomics in Zacas)",
2034 .dependencies = featureSet(&[_]Feature{}),
2035 };
2036 result[@intFromEnum(Feature.ziccif)] = .{
2037 .llvm_name = "ziccif",
2038 .description = "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)",
2039 .dependencies = featureSet(&[_]Feature{}),
2040 };
2041 result[@intFromEnum(Feature.zicclsm)] = .{
2042 .llvm_name = "zicclsm",
2043 .description = "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)",
2044 .dependencies = featureSet(&[_]Feature{}),
2045 };
2046 result[@intFromEnum(Feature.ziccrse)] = .{
2047 .llvm_name = "ziccrse",
2048 .description = "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)",
2049 .dependencies = featureSet(&[_]Feature{}),
2050 };
2051 result[@intFromEnum(Feature.zicntr)] = .{
2052 .llvm_name = "zicntr",
2053 .description = "'Zicntr' (Base Counters and Timers)",
2054 .dependencies = featureSet(&[_]Feature{
2055 .zicsr,
2056 }),
2057 };
2058 result[@intFromEnum(Feature.zicond)] = .{
2059 .llvm_name = "zicond",
2060 .description = "'Zicond' (Integer Conditional Operations)",
2061 .dependencies = featureSet(&[_]Feature{}),
2062 };
2063 result[@intFromEnum(Feature.zicsr)] = .{
2064 .llvm_name = "zicsr",
2065 .description = "'Zicsr' (CSRs)",
2066 .dependencies = featureSet(&[_]Feature{}),
2067 };
2068 result[@intFromEnum(Feature.zifencei)] = .{
2069 .llvm_name = "zifencei",
2070 .description = "'Zifencei' (fence.i)",
2071 .dependencies = featureSet(&[_]Feature{}),
2072 };
2073 result[@intFromEnum(Feature.zihintntl)] = .{
2074 .llvm_name = "zihintntl",
2075 .description = "'Zihintntl' (Non-Temporal Locality Hints)",
2076 .dependencies = featureSet(&[_]Feature{}),
2077 };
2078 result[@intFromEnum(Feature.zihintpause)] = .{
2079 .llvm_name = "zihintpause",
2080 .description = "'Zihintpause' (Pause Hint)",
2081 .dependencies = featureSet(&[_]Feature{}),
2082 };
2083 result[@intFromEnum(Feature.zihpm)] = .{
2084 .llvm_name = "zihpm",
2085 .description = "'Zihpm' (Hardware Performance Counters)",
2086 .dependencies = featureSet(&[_]Feature{
2087 .zicsr,
2088 }),
2089 };
2090 result[@intFromEnum(Feature.zilsd)] = .{
2091 .llvm_name = "zilsd",
2092 .description = "'Zilsd' (Load/Store Pair Instructions)",
2093 .dependencies = featureSet(&[_]Feature{}),
2094 };
2095 result[@intFromEnum(Feature.zimop)] = .{
2096 .llvm_name = "zimop",
2097 .description = "'Zimop' (May-Be-Operations)",
2098 .dependencies = featureSet(&[_]Feature{}),
2099 };
2100 result[@intFromEnum(Feature.zk)] = .{
2101 .llvm_name = "zk",
2102 .description = "'Zk' (Standard scalar cryptography extension)",
2103 .dependencies = featureSet(&[_]Feature{
2104 .zkn,
2105 .zkr,
2106 .zkt,
2107 }),
2108 };
2109 result[@intFromEnum(Feature.zkn)] = .{
2110 .llvm_name = "zkn",
2111 .description = "'Zkn' (NIST Algorithm Suite)",
2112 .dependencies = featureSet(&[_]Feature{
2113 .zbkb,
2114 .zbkc,
2115 .zbkx,
2116 .zknd,
2117 .zkne,
2118 .zknh,
2119 }),
2120 };
2121 result[@intFromEnum(Feature.zknd)] = .{
2122 .llvm_name = "zknd",
2123 .description = "'Zknd' (NIST Suite: AES Decryption)",
2124 .dependencies = featureSet(&[_]Feature{}),
2125 };
2126 result[@intFromEnum(Feature.zkne)] = .{
2127 .llvm_name = "zkne",
2128 .description = "'Zkne' (NIST Suite: AES Encryption)",
2129 .dependencies = featureSet(&[_]Feature{}),
2130 };
2131 result[@intFromEnum(Feature.zknh)] = .{
2132 .llvm_name = "zknh",
2133 .description = "'Zknh' (NIST Suite: Hash Function Instructions)",
2134 .dependencies = featureSet(&[_]Feature{}),
2135 };
2136 result[@intFromEnum(Feature.zkr)] = .{
2137 .llvm_name = "zkr",
2138 .description = "'Zkr' (Entropy Source Extension)",
2139 .dependencies = featureSet(&[_]Feature{}),
2140 };
2141 result[@intFromEnum(Feature.zks)] = .{
2142 .llvm_name = "zks",
2143 .description = "'Zks' (ShangMi Algorithm Suite)",
2144 .dependencies = featureSet(&[_]Feature{
2145 .zbkb,
2146 .zbkc,
2147 .zbkx,
2148 .zksed,
2149 .zksh,
2150 }),
2151 };
2152 result[@intFromEnum(Feature.zksed)] = .{
2153 .llvm_name = "zksed",
2154 .description = "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)",
2155 .dependencies = featureSet(&[_]Feature{}),
2156 };
2157 result[@intFromEnum(Feature.zksh)] = .{
2158 .llvm_name = "zksh",
2159 .description = "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)",
2160 .dependencies = featureSet(&[_]Feature{}),
2161 };
2162 result[@intFromEnum(Feature.zkt)] = .{
2163 .llvm_name = "zkt",
2164 .description = "'Zkt' (Data Independent Execution Latency)",
2165 .dependencies = featureSet(&[_]Feature{}),
2166 };
2167 result[@intFromEnum(Feature.zmmul)] = .{
2168 .llvm_name = "zmmul",
2169 .description = "'Zmmul' (Integer Multiplication)",
2170 .dependencies = featureSet(&[_]Feature{}),
2171 };
2172 result[@intFromEnum(Feature.ztso)] = .{
2173 .llvm_name = "ztso",
2174 .description = "'Ztso' (Memory Model - Total Store Order)",
2175 .dependencies = featureSet(&[_]Feature{}),
2176 };
2177 result[@intFromEnum(Feature.zvbb)] = .{
2178 .llvm_name = "zvbb",
2179 .description = "'Zvbb' (Vector basic bit-manipulation instructions)",
2180 .dependencies = featureSet(&[_]Feature{
2181 .zvkb,
2182 }),
2183 };
2184 result[@intFromEnum(Feature.zvbc)] = .{
2185 .llvm_name = "zvbc",
2186 .description = "'Zvbc' (Vector Carryless Multiplication)",
2187 .dependencies = featureSet(&[_]Feature{
2188 .zve64x,
2189 }),
2190 };
2191 result[@intFromEnum(Feature.zve32f)] = .{
2192 .llvm_name = "zve32f",
2193 .description = "'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)",
2194 .dependencies = featureSet(&[_]Feature{
2195 .f,
2196 .zve32x,
2197 }),
2198 };
2199 result[@intFromEnum(Feature.zve32x)] = .{
2200 .llvm_name = "zve32x",
2201 .description = "'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW)",
2202 .dependencies = featureSet(&[_]Feature{
2203 .zicsr,
2204 .zvl32b,
2205 }),
2206 };
2207 result[@intFromEnum(Feature.zve64d)] = .{
2208 .llvm_name = "zve64d",
2209 .description = "'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension)",
2210 .dependencies = featureSet(&[_]Feature{
2211 .d,
2212 .zve64f,
2213 }),
2214 };
2215 result[@intFromEnum(Feature.zve64f)] = .{
2216 .llvm_name = "zve64f",
2217 .description = "'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension)",
2218 .dependencies = featureSet(&[_]Feature{
2219 .zve32f,
2220 .zve64x,
2221 }),
2222 };
2223 result[@intFromEnum(Feature.zve64x)] = .{
2224 .llvm_name = "zve64x",
2225 .description = "'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW)",
2226 .dependencies = featureSet(&[_]Feature{
2227 .zve32x,
2228 .zvl64b,
2229 }),
2230 };
2231 result[@intFromEnum(Feature.zvfbfmin)] = .{
2232 .llvm_name = "zvfbfmin",
2233 .description = "'Zvfbfmin' (Vector BF16 Converts)",
2234 .dependencies = featureSet(&[_]Feature{
2235 .zve32f,
2236 }),
2237 };
2238 result[@intFromEnum(Feature.zvfbfwma)] = .{
2239 .llvm_name = "zvfbfwma",
2240 .description = "'Zvfbfwma' (Vector BF16 widening mul-add)",
2241 .dependencies = featureSet(&[_]Feature{
2242 .zfbfmin,
2243 .zvfbfmin,
2244 }),
2245 };
2246 result[@intFromEnum(Feature.zvfh)] = .{
2247 .llvm_name = "zvfh",
2248 .description = "'Zvfh' (Vector Half-Precision Floating-Point)",
2249 .dependencies = featureSet(&[_]Feature{
2250 .zfhmin,
2251 .zvfhmin,
2252 }),
2253 };
2254 result[@intFromEnum(Feature.zvfhmin)] = .{
2255 .llvm_name = "zvfhmin",
2256 .description = "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
2257 .dependencies = featureSet(&[_]Feature{
2258 .zve32f,
2259 }),
2260 };
2261 result[@intFromEnum(Feature.zvkb)] = .{
2262 .llvm_name = "zvkb",
2263 .description = "'Zvkb' (Vector Bit-manipulation used in Cryptography)",
2264 .dependencies = featureSet(&[_]Feature{
2265 .zve32x,
2266 }),
2267 };
2268 result[@intFromEnum(Feature.zvkg)] = .{
2269 .llvm_name = "zvkg",
2270 .description = "'Zvkg' (Vector GCM instructions for Cryptography)",
2271 .dependencies = featureSet(&[_]Feature{
2272 .zve32x,
2273 }),
2274 };
2275 result[@intFromEnum(Feature.zvkn)] = .{
2276 .llvm_name = "zvkn",
2277 .description = "'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt')",
2278 .dependencies = featureSet(&[_]Feature{
2279 .zvkb,
2280 .zvkned,
2281 .zvknhb,
2282 .zvkt,
2283 }),
2284 };
2285 result[@intFromEnum(Feature.zvknc)] = .{
2286 .llvm_name = "zvknc",
2287 .description = "'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')",
2288 .dependencies = featureSet(&[_]Feature{
2289 .zvbc,
2290 .zvkn,
2291 }),
2292 };
2293 result[@intFromEnum(Feature.zvkned)] = .{
2294 .llvm_name = "zvkned",
2295 .description = "'Zvkned' (Vector AES Encryption & Decryption (Single Round))",
2296 .dependencies = featureSet(&[_]Feature{
2297 .zve32x,
2298 }),
2299 };
2300 result[@intFromEnum(Feature.zvkng)] = .{
2301 .llvm_name = "zvkng",
2302 .description = "'Zvkng' (shorthand for 'Zvkn' and 'Zvkg')",
2303 .dependencies = featureSet(&[_]Feature{
2304 .zvkg,
2305 .zvkn,
2306 }),
2307 };
2308 result[@intFromEnum(Feature.zvknha)] = .{
2309 .llvm_name = "zvknha",
2310 .description = "'Zvknha' (Vector SHA-2 (SHA-256 only))",
2311 .dependencies = featureSet(&[_]Feature{
2312 .zve32x,
2313 }),
2314 };
2315 result[@intFromEnum(Feature.zvknhb)] = .{
2316 .llvm_name = "zvknhb",
2317 .description = "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
2318 .dependencies = featureSet(&[_]Feature{
2319 .zve64x,
2320 }),
2321 };
2322 result[@intFromEnum(Feature.zvks)] = .{
2323 .llvm_name = "zvks",
2324 .description = "'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt')",
2325 .dependencies = featureSet(&[_]Feature{
2326 .zvkb,
2327 .zvksed,
2328 .zvksh,
2329 .zvkt,
2330 }),
2331 };
2332 result[@intFromEnum(Feature.zvksc)] = .{
2333 .llvm_name = "zvksc",
2334 .description = "'Zvksc' (shorthand for 'Zvks' and 'Zvbc')",
2335 .dependencies = featureSet(&[_]Feature{
2336 .zvbc,
2337 .zvks,
2338 }),
2339 };
2340 result[@intFromEnum(Feature.zvksed)] = .{
2341 .llvm_name = "zvksed",
2342 .description = "'Zvksed' (SM4 Block Cipher Instructions)",
2343 .dependencies = featureSet(&[_]Feature{
2344 .zve32x,
2345 }),
2346 };
2347 result[@intFromEnum(Feature.zvksg)] = .{
2348 .llvm_name = "zvksg",
2349 .description = "'Zvksg' (shorthand for 'Zvks' and 'Zvkg')",
2350 .dependencies = featureSet(&[_]Feature{
2351 .zvkg,
2352 .zvks,
2353 }),
2354 };
2355 result[@intFromEnum(Feature.zvksh)] = .{
2356 .llvm_name = "zvksh",
2357 .description = "'Zvksh' (SM3 Hash Function Instructions)",
2358 .dependencies = featureSet(&[_]Feature{
2359 .zve32x,
2360 }),
2361 };
2362 result[@intFromEnum(Feature.zvkt)] = .{
2363 .llvm_name = "zvkt",
2364 .description = "'Zvkt' (Vector Data-Independent Execution Latency)",
2365 .dependencies = featureSet(&[_]Feature{}),
2366 };
2367 result[@intFromEnum(Feature.zvl1024b)] = .{
2368 .llvm_name = "zvl1024b",
2369 .description = "'Zvl1024b' (Minimum Vector Length 1024)",
2370 .dependencies = featureSet(&[_]Feature{
2371 .zvl512b,
2372 }),
2373 };
2374 result[@intFromEnum(Feature.zvl128b)] = .{
2375 .llvm_name = "zvl128b",
2376 .description = "'Zvl128b' (Minimum Vector Length 128)",
2377 .dependencies = featureSet(&[_]Feature{
2378 .zvl64b,
2379 }),
2380 };
2381 result[@intFromEnum(Feature.zvl16384b)] = .{
2382 .llvm_name = "zvl16384b",
2383 .description = "'Zvl16384b' (Minimum Vector Length 16384)",
2384 .dependencies = featureSet(&[_]Feature{
2385 .zvl8192b,
2386 }),
2387 };
2388 result[@intFromEnum(Feature.zvl2048b)] = .{
2389 .llvm_name = "zvl2048b",
2390 .description = "'Zvl2048b' (Minimum Vector Length 2048)",
2391 .dependencies = featureSet(&[_]Feature{
2392 .zvl1024b,
2393 }),
2394 };
2395 result[@intFromEnum(Feature.zvl256b)] = .{
2396 .llvm_name = "zvl256b",
2397 .description = "'Zvl256b' (Minimum Vector Length 256)",
2398 .dependencies = featureSet(&[_]Feature{
2399 .zvl128b,
2400 }),
2401 };
2402 result[@intFromEnum(Feature.zvl32768b)] = .{
2403 .llvm_name = "zvl32768b",
2404 .description = "'Zvl32768b' (Minimum Vector Length 32768)",
2405 .dependencies = featureSet(&[_]Feature{
2406 .zvl16384b,
2407 }),
2408 };
2409 result[@intFromEnum(Feature.zvl32b)] = .{
2410 .llvm_name = "zvl32b",
2411 .description = "'Zvl32b' (Minimum Vector Length 32)",
2412 .dependencies = featureSet(&[_]Feature{}),
2413 };
2414 result[@intFromEnum(Feature.zvl4096b)] = .{
2415 .llvm_name = "zvl4096b",
2416 .description = "'Zvl4096b' (Minimum Vector Length 4096)",
2417 .dependencies = featureSet(&[_]Feature{
2418 .zvl2048b,
2419 }),
2420 };
2421 result[@intFromEnum(Feature.zvl512b)] = .{
2422 .llvm_name = "zvl512b",
2423 .description = "'Zvl512b' (Minimum Vector Length 512)",
2424 .dependencies = featureSet(&[_]Feature{
2425 .zvl256b,
2426 }),
2427 };
2428 result[@intFromEnum(Feature.zvl64b)] = .{
2429 .llvm_name = "zvl64b",
2430 .description = "'Zvl64b' (Minimum Vector Length 64)",
2431 .dependencies = featureSet(&[_]Feature{
2432 .zvl32b,
2433 }),
2434 };
2435 result[@intFromEnum(Feature.zvl65536b)] = .{
2436 .llvm_name = "zvl65536b",
2437 .description = "'Zvl65536b' (Minimum Vector Length 65536)",
2438 .dependencies = featureSet(&[_]Feature{
2439 .zvl32768b,
2440 }),
2441 };
2442 result[@intFromEnum(Feature.zvl8192b)] = .{
2443 .llvm_name = "zvl8192b",
2444 .description = "'Zvl8192b' (Minimum Vector Length 8192)",
2445 .dependencies = featureSet(&[_]Feature{
2446 .zvl4096b,
2447 }),
2448 };
2449 const ti = @typeInfo(Feature);
2450 for (&result, 0..) |*elem, i| {
2451 elem.index = i;
2452 elem.name = ti.@"enum".fields[i].name;
2453 }
2454 break :blk result;
2455};
2456
2457pub const cpu = struct {
2458 pub const andes_45_series: CpuModel = .{
2459 .name = "andes_45_series",
2460 .llvm_name = "andes-45-series",
2461 .features = featureSet(&[_]Feature{
2462 .andes45,
2463 .no_default_unroll,
2464 .short_forward_branch_opt,
2465 .use_postra_scheduler,
2466 }),
2467 };
2468 pub const andes_a25: CpuModel = .{
2469 .name = "andes_a25",
2470 .llvm_name = "andes-a25",
2471 .features = featureSet(&[_]Feature{
2472 .@"32bit",
2473 .a,
2474 .c,
2475 .d,
2476 .i,
2477 .m,
2478 .xandesperf,
2479 .zifencei,
2480 }),
2481 };
2482 pub const andes_a45: CpuModel = .{
2483 .name = "andes_a45",
2484 .llvm_name = "andes-a45",
2485 .features = featureSet(&[_]Feature{
2486 .@"32bit",
2487 .a,
2488 .andes45,
2489 .c,
2490 .d,
2491 .i,
2492 .m,
2493 .no_default_unroll,
2494 .short_forward_branch_opt,
2495 .use_postra_scheduler,
2496 .xandesperf,
2497 .zifencei,
2498 }),
2499 };
2500 pub const andes_ax25: CpuModel = .{
2501 .name = "andes_ax25",
2502 .llvm_name = "andes-ax25",
2503 .features = featureSet(&[_]Feature{
2504 .@"64bit",
2505 .a,
2506 .c,
2507 .d,
2508 .i,
2509 .m,
2510 .xandesperf,
2511 .zifencei,
2512 }),
2513 };
2514 pub const andes_ax45: CpuModel = .{
2515 .name = "andes_ax45",
2516 .llvm_name = "andes-ax45",
2517 .features = featureSet(&[_]Feature{
2518 .@"64bit",
2519 .a,
2520 .andes45,
2521 .c,
2522 .d,
2523 .i,
2524 .m,
2525 .no_default_unroll,
2526 .short_forward_branch_opt,
2527 .use_postra_scheduler,
2528 .xandesperf,
2529 .zifencei,
2530 }),
2531 };
2532 pub const andes_ax45mpv: CpuModel = .{
2533 .name = "andes_ax45mpv",
2534 .llvm_name = "andes-ax45mpv",
2535 .features = featureSet(&[_]Feature{
2536 .@"64bit",
2537 .a,
2538 .andes45,
2539 .c,
2540 .i,
2541 .m,
2542 .no_default_unroll,
2543 .short_forward_branch_opt,
2544 .use_postra_scheduler,
2545 .v,
2546 .xandesperf,
2547 .zifencei,
2548 }),
2549 };
2550 pub const andes_n45: CpuModel = .{
2551 .name = "andes_n45",
2552 .llvm_name = "andes-n45",
2553 .features = featureSet(&[_]Feature{
2554 .@"32bit",
2555 .a,
2556 .andes45,
2557 .c,
2558 .d,
2559 .i,
2560 .m,
2561 .no_default_unroll,
2562 .short_forward_branch_opt,
2563 .use_postra_scheduler,
2564 .xandesperf,
2565 .zifencei,
2566 }),
2567 };
2568 pub const andes_nx45: CpuModel = .{
2569 .name = "andes_nx45",
2570 .llvm_name = "andes-nx45",
2571 .features = featureSet(&[_]Feature{
2572 .@"64bit",
2573 .a,
2574 .andes45,
2575 .c,
2576 .d,
2577 .i,
2578 .m,
2579 .no_default_unroll,
2580 .short_forward_branch_opt,
2581 .use_postra_scheduler,
2582 .xandesperf,
2583 .zifencei,
2584 }),
2585 };
2586 pub const baseline_rv32: CpuModel = .{
2587 .name = "baseline_rv32",
2588 .llvm_name = null,
2589 .features = featureSet(&[_]Feature{
2590 .@"32bit",
2591 .a,
2592 .c,
2593 .d,
2594 .i,
2595 .m,
2596 }),
2597 };
2598 pub const baseline_rv64: CpuModel = .{
2599 .name = "baseline_rv64",
2600 .llvm_name = null,
2601 .features = featureSet(&[_]Feature{
2602 .@"64bit",
2603 .a,
2604 .c,
2605 .d,
2606 .i,
2607 .m,
2608 }),
2609 };
2610 pub const generic: CpuModel = .{
2611 .name = "generic",
2612 .llvm_name = "generic",
2613 .features = featureSet(&[_]Feature{}),
2614 };
2615 pub const generic_ooo: CpuModel = .{
2616 .name = "generic_ooo",
2617 .llvm_name = "generic-ooo",
2618 .features = featureSet(&[_]Feature{}),
2619 };
2620 pub const generic_rv32: CpuModel = .{
2621 .name = "generic_rv32",
2622 .llvm_name = "generic-rv32",
2623 .features = featureSet(&[_]Feature{
2624 .@"32bit",
2625 .i,
2626 .optimized_nf2_segment_load_store,
2627 }),
2628 };
2629 pub const generic_rv64: CpuModel = .{
2630 .name = "generic_rv64",
2631 .llvm_name = "generic-rv64",
2632 .features = featureSet(&[_]Feature{
2633 .@"64bit",
2634 .i,
2635 .optimized_nf2_segment_load_store,
2636 }),
2637 };
2638 pub const mips_p8700: CpuModel = .{
2639 .name = "mips_p8700",
2640 .llvm_name = "mips-p8700",
2641 .features = featureSet(&[_]Feature{
2642 .@"64bit",
2643 .a,
2644 .c,
2645 .d,
2646 .i,
2647 .m,
2648 .mips_p8700,
2649 .xmipscbop,
2650 .xmipscmov,
2651 .xmipslsp,
2652 .zba,
2653 .zbb,
2654 .zifencei,
2655 }),
2656 };
2657 pub const rocket: CpuModel = .{
2658 .name = "rocket",
2659 .llvm_name = "rocket",
2660 .features = featureSet(&[_]Feature{}),
2661 };
2662 pub const rocket_rv32: CpuModel = .{
2663 .name = "rocket_rv32",
2664 .llvm_name = "rocket-rv32",
2665 .features = featureSet(&[_]Feature{
2666 .@"32bit",
2667 .i,
2668 .zicsr,
2669 .zifencei,
2670 }),
2671 };
2672 pub const rocket_rv64: CpuModel = .{
2673 .name = "rocket_rv64",
2674 .llvm_name = "rocket-rv64",
2675 .features = featureSet(&[_]Feature{
2676 .@"64bit",
2677 .i,
2678 .zicsr,
2679 .zifencei,
2680 }),
2681 };
2682 pub const rp2350_hazard3: CpuModel = .{
2683 .name = "rp2350_hazard3",
2684 .llvm_name = "rp2350-hazard3",
2685 .features = featureSet(&[_]Feature{
2686 .@"32bit",
2687 .a,
2688 .c,
2689 .i,
2690 .m,
2691 .zba,
2692 .zbb,
2693 .zbkb,
2694 .zbs,
2695 .zcb,
2696 .zcmp,
2697 .zicsr,
2698 .zifencei,
2699 }),
2700 };
2701 pub const sifive_7_series: CpuModel = .{
2702 .name = "sifive_7_series",
2703 .llvm_name = "sifive-7-series",
2704 .features = featureSet(&[_]Feature{
2705 .no_default_unroll,
2706 .short_forward_branch_opt,
2707 .use_postra_scheduler,
2708 }),
2709 };
2710 pub const sifive_e20: CpuModel = .{
2711 .name = "sifive_e20",
2712 .llvm_name = "sifive-e20",
2713 .features = featureSet(&[_]Feature{
2714 .@"32bit",
2715 .c,
2716 .i,
2717 .m,
2718 .zicsr,
2719 .zifencei,
2720 }),
2721 };
2722 pub const sifive_e21: CpuModel = .{
2723 .name = "sifive_e21",
2724 .llvm_name = "sifive-e21",
2725 .features = featureSet(&[_]Feature{
2726 .@"32bit",
2727 .a,
2728 .c,
2729 .i,
2730 .m,
2731 .zicsr,
2732 .zifencei,
2733 }),
2734 };
2735 pub const sifive_e24: CpuModel = .{
2736 .name = "sifive_e24",
2737 .llvm_name = "sifive-e24",
2738 .features = featureSet(&[_]Feature{
2739 .@"32bit",
2740 .a,
2741 .c,
2742 .f,
2743 .i,
2744 .m,
2745 .zifencei,
2746 }),
2747 };
2748 pub const sifive_e31: CpuModel = .{
2749 .name = "sifive_e31",
2750 .llvm_name = "sifive-e31",
2751 .features = featureSet(&[_]Feature{
2752 .@"32bit",
2753 .a,
2754 .c,
2755 .i,
2756 .m,
2757 .zicsr,
2758 .zifencei,
2759 }),
2760 };
2761 pub const sifive_e34: CpuModel = .{
2762 .name = "sifive_e34",
2763 .llvm_name = "sifive-e34",
2764 .features = featureSet(&[_]Feature{
2765 .@"32bit",
2766 .a,
2767 .c,
2768 .f,
2769 .i,
2770 .m,
2771 .zifencei,
2772 }),
2773 };
2774 pub const sifive_e76: CpuModel = .{
2775 .name = "sifive_e76",
2776 .llvm_name = "sifive-e76",
2777 .features = featureSet(&[_]Feature{
2778 .@"32bit",
2779 .a,
2780 .c,
2781 .f,
2782 .i,
2783 .m,
2784 .no_default_unroll,
2785 .short_forward_branch_opt,
2786 .use_postra_scheduler,
2787 .zifencei,
2788 }),
2789 };
2790 pub const sifive_p450: CpuModel = .{
2791 .name = "sifive_p450",
2792 .llvm_name = "sifive-p450",
2793 .features = featureSet(&[_]Feature{
2794 .@"64bit",
2795 .a,
2796 .auipc_addi_fusion,
2797 .b,
2798 .c,
2799 .conditional_cmv_fusion,
2800 .d,
2801 .i,
2802 .lui_addi_fusion,
2803 .m,
2804 .no_default_unroll,
2805 .unaligned_scalar_mem,
2806 .unaligned_vector_mem,
2807 .use_postra_scheduler,
2808 .za64rs,
2809 .zfhmin,
2810 .zic64b,
2811 .zicbom,
2812 .zicbop,
2813 .zicboz,
2814 .ziccamoa,
2815 .ziccif,
2816 .zicclsm,
2817 .ziccrse,
2818 .zicntr,
2819 .zifencei,
2820 .zihintntl,
2821 .zihintpause,
2822 .zihpm,
2823 .zkt,
2824 }),
2825 };
2826 pub const sifive_p470: CpuModel = .{
2827 .name = "sifive_p470",
2828 .llvm_name = "sifive-p470",
2829 .features = featureSet(&[_]Feature{
2830 .@"64bit",
2831 .a,
2832 .auipc_addi_fusion,
2833 .b,
2834 .c,
2835 .conditional_cmv_fusion,
2836 .i,
2837 .lui_addi_fusion,
2838 .m,
2839 .no_default_unroll,
2840 .no_sink_splat_operands,
2841 .unaligned_scalar_mem,
2842 .unaligned_vector_mem,
2843 .use_postra_scheduler,
2844 .v,
2845 .vxrm_pipeline_flush,
2846 .xsifivecdiscarddlone,
2847 .xsifivecflushdlone,
2848 .za64rs,
2849 .zfhmin,
2850 .zic64b,
2851 .zicbom,
2852 .zicbop,
2853 .zicboz,
2854 .ziccamoa,
2855 .ziccif,
2856 .zicclsm,
2857 .ziccrse,
2858 .zicntr,
2859 .zifencei,
2860 .zihintntl,
2861 .zihintpause,
2862 .zihpm,
2863 .zkt,
2864 .zvbb,
2865 .zvknc,
2866 .zvkng,
2867 .zvksc,
2868 .zvksg,
2869 }),
2870 };
2871 pub const sifive_p550: CpuModel = .{
2872 .name = "sifive_p550",
2873 .llvm_name = "sifive-p550",
2874 .features = featureSet(&[_]Feature{
2875 .@"64bit",
2876 .a,
2877 .auipc_addi_fusion,
2878 .c,
2879 .conditional_cmv_fusion,
2880 .d,
2881 .i,
2882 .lui_addi_fusion,
2883 .m,
2884 .no_default_unroll,
2885 .use_postra_scheduler,
2886 .zba,
2887 .zbb,
2888 .zifencei,
2889 }),
2890 };
2891 pub const sifive_p670: CpuModel = .{
2892 .name = "sifive_p670",
2893 .llvm_name = "sifive-p670",
2894 .features = featureSet(&[_]Feature{
2895 .@"64bit",
2896 .a,
2897 .auipc_addi_fusion,
2898 .b,
2899 .c,
2900 .conditional_cmv_fusion,
2901 .i,
2902 .lui_addi_fusion,
2903 .m,
2904 .no_default_unroll,
2905 .no_sink_splat_operands,
2906 .unaligned_scalar_mem,
2907 .unaligned_vector_mem,
2908 .use_postra_scheduler,
2909 .v,
2910 .vxrm_pipeline_flush,
2911 .za64rs,
2912 .zfhmin,
2913 .zic64b,
2914 .zicbom,
2915 .zicbop,
2916 .zicboz,
2917 .ziccamoa,
2918 .ziccif,
2919 .zicclsm,
2920 .ziccrse,
2921 .zicntr,
2922 .zifencei,
2923 .zihintntl,
2924 .zihintpause,
2925 .zihpm,
2926 .zkt,
2927 .zvbb,
2928 .zvknc,
2929 .zvkng,
2930 .zvksc,
2931 .zvksg,
2932 }),
2933 };
2934 pub const sifive_p870: CpuModel = .{
2935 .name = "sifive_p870",
2936 .llvm_name = "sifive-p870",
2937 .features = featureSet(&[_]Feature{
2938 .@"64bit",
2939 .a,
2940 .auipc_addi_fusion,
2941 .b,
2942 .c,
2943 .conditional_cmv_fusion,
2944 .i,
2945 .lui_addi_fusion,
2946 .m,
2947 .no_default_unroll,
2948 .no_sink_splat_operands,
2949 .supm,
2950 .unaligned_scalar_mem,
2951 .unaligned_vector_mem,
2952 .use_postra_scheduler,
2953 .v,
2954 .vxrm_pipeline_flush,
2955 .za64rs,
2956 .zama16b,
2957 .zawrs,
2958 .zcb,
2959 .zcmop,
2960 .zfa,
2961 .zfh,
2962 .zic64b,
2963 .zicbom,
2964 .zicbop,
2965 .zicboz,
2966 .ziccamoa,
2967 .ziccif,
2968 .zicclsm,
2969 .ziccrse,
2970 .zicntr,
2971 .zicond,
2972 .zifencei,
2973 .zihintntl,
2974 .zihintpause,
2975 .zihpm,
2976 .zimop,
2977 .zkr,
2978 .zkt,
2979 .zvbb,
2980 .zvfbfwma,
2981 .zvfh,
2982 .zvknc,
2983 .zvkng,
2984 .zvksc,
2985 .zvksg,
2986 }),
2987 };
2988 pub const sifive_s21: CpuModel = .{
2989 .name = "sifive_s21",
2990 .llvm_name = "sifive-s21",
2991 .features = featureSet(&[_]Feature{
2992 .@"64bit",
2993 .a,
2994 .c,
2995 .i,
2996 .m,
2997 .zicsr,
2998 .zifencei,
2999 }),
3000 };
3001 pub const sifive_s51: CpuModel = .{
3002 .name = "sifive_s51",
3003 .llvm_name = "sifive-s51",
3004 .features = featureSet(&[_]Feature{
3005 .@"64bit",
3006 .a,
3007 .c,
3008 .i,
3009 .m,
3010 .zicsr,
3011 .zifencei,
3012 }),
3013 };
3014 pub const sifive_s54: CpuModel = .{
3015 .name = "sifive_s54",
3016 .llvm_name = "sifive-s54",
3017 .features = featureSet(&[_]Feature{
3018 .@"64bit",
3019 .a,
3020 .c,
3021 .d,
3022 .i,
3023 .m,
3024 .zifencei,
3025 }),
3026 };
3027 pub const sifive_s76: CpuModel = .{
3028 .name = "sifive_s76",
3029 .llvm_name = "sifive-s76",
3030 .features = featureSet(&[_]Feature{
3031 .@"64bit",
3032 .a,
3033 .c,
3034 .d,
3035 .i,
3036 .m,
3037 .no_default_unroll,
3038 .short_forward_branch_opt,
3039 .use_postra_scheduler,
3040 .zifencei,
3041 .zihintpause,
3042 }),
3043 };
3044 pub const sifive_u54: CpuModel = .{
3045 .name = "sifive_u54",
3046 .llvm_name = "sifive-u54",
3047 .features = featureSet(&[_]Feature{
3048 .@"64bit",
3049 .a,
3050 .c,
3051 .d,
3052 .i,
3053 .m,
3054 .zifencei,
3055 }),
3056 };
3057 pub const sifive_u74: CpuModel = .{
3058 .name = "sifive_u74",
3059 .llvm_name = "sifive-u74",
3060 .features = featureSet(&[_]Feature{
3061 .@"64bit",
3062 .a,
3063 .c,
3064 .d,
3065 .i,
3066 .m,
3067 .no_default_unroll,
3068 .short_forward_branch_opt,
3069 .use_postra_scheduler,
3070 .zifencei,
3071 }),
3072 };
3073 pub const sifive_x280: CpuModel = .{
3074 .name = "sifive_x280",
3075 .llvm_name = "sifive-x280",
3076 .features = featureSet(&[_]Feature{
3077 .@"64bit",
3078 .a,
3079 .c,
3080 .dlen_factor_2,
3081 .i,
3082 .m,
3083 .no_default_unroll,
3084 .optimized_nf2_segment_load_store,
3085 .optimized_zero_stride_load,
3086 .short_forward_branch_opt,
3087 .use_postra_scheduler,
3088 .v,
3089 .vl_dependent_latency,
3090 .zba,
3091 .zbb,
3092 .zfh,
3093 .zifencei,
3094 .zvfh,
3095 .zvl512b,
3096 }),
3097 };
3098 pub const sifive_x390: CpuModel = .{
3099 .name = "sifive_x390",
3100 .llvm_name = "sifive-x390",
3101 .features = featureSet(&[_]Feature{
3102 .@"64bit",
3103 .a,
3104 .b,
3105 .c,
3106 .dlen_factor_2,
3107 .experimental_zicfilp,
3108 .experimental_zicfiss,
3109 .i,
3110 .m,
3111 .no_default_unroll,
3112 .optimized_nf2_segment_load_store,
3113 .optimized_zero_stride_load,
3114 .short_forward_branch_opt,
3115 .use_postra_scheduler,
3116 .v,
3117 .vl_dependent_latency,
3118 .xsifivecdiscarddlone,
3119 .xsifivecflushdlone,
3120 .za64rs,
3121 .zawrs,
3122 .zcb,
3123 .zcmop,
3124 .zfa,
3125 .zfh,
3126 .zic64b,
3127 .zicbom,
3128 .zicbop,
3129 .zicboz,
3130 .ziccamoa,
3131 .ziccif,
3132 .ziccrse,
3133 .zicntr,
3134 .zicond,
3135 .zifencei,
3136 .zihintntl,
3137 .zihintpause,
3138 .zihpm,
3139 .zkr,
3140 .zkt,
3141 .zvbb,
3142 .zvfbfwma,
3143 .zvfh,
3144 .zvkt,
3145 .zvl1024b,
3146 }),
3147 };
3148 pub const spacemit_x60: CpuModel = .{
3149 .name = "spacemit_x60",
3150 .llvm_name = "spacemit-x60",
3151 .features = featureSet(&[_]Feature{
3152 .@"64bit",
3153 .a,
3154 .b,
3155 .c,
3156 .dlen_factor_2,
3157 .i,
3158 .m,
3159 .optimized_nf2_segment_load_store,
3160 .optimized_nf3_segment_load_store,
3161 .optimized_nf4_segment_load_store,
3162 .ssccptr,
3163 .sscofpmf,
3164 .sscounterenw,
3165 .sstc,
3166 .sstvala,
3167 .sstvecd,
3168 .svade,
3169 .svbare,
3170 .svinval,
3171 .svnapot,
3172 .svpbmt,
3173 .unaligned_scalar_mem,
3174 .v,
3175 .vxrm_pipeline_flush,
3176 .za64rs,
3177 .zbc,
3178 .zbkc,
3179 .zfh,
3180 .zic64b,
3181 .zicbom,
3182 .zicbop,
3183 .zicboz,
3184 .ziccamoa,
3185 .ziccif,
3186 .zicclsm,
3187 .ziccrse,
3188 .zicntr,
3189 .zicond,
3190 .zifencei,
3191 .zihintpause,
3192 .zihpm,
3193 .zkt,
3194 .zvfh,
3195 .zvkt,
3196 .zvl256b,
3197 }),
3198 };
3199 pub const syntacore_scr1_base: CpuModel = .{
3200 .name = "syntacore_scr1_base",
3201 .llvm_name = "syntacore-scr1-base",
3202 .features = featureSet(&[_]Feature{
3203 .@"32bit",
3204 .c,
3205 .i,
3206 .no_default_unroll,
3207 .zicsr,
3208 .zifencei,
3209 }),
3210 };
3211 pub const syntacore_scr1_max: CpuModel = .{
3212 .name = "syntacore_scr1_max",
3213 .llvm_name = "syntacore-scr1-max",
3214 .features = featureSet(&[_]Feature{
3215 .@"32bit",
3216 .c,
3217 .i,
3218 .m,
3219 .no_default_unroll,
3220 .zicsr,
3221 .zifencei,
3222 }),
3223 };
3224 pub const syntacore_scr3_rv32: CpuModel = .{
3225 .name = "syntacore_scr3_rv32",
3226 .llvm_name = "syntacore-scr3-rv32",
3227 .features = featureSet(&[_]Feature{
3228 .@"32bit",
3229 .c,
3230 .i,
3231 .m,
3232 .no_default_unroll,
3233 .use_postra_scheduler,
3234 .zicsr,
3235 .zifencei,
3236 }),
3237 };
3238 pub const syntacore_scr3_rv64: CpuModel = .{
3239 .name = "syntacore_scr3_rv64",
3240 .llvm_name = "syntacore-scr3-rv64",
3241 .features = featureSet(&[_]Feature{
3242 .@"64bit",
3243 .a,
3244 .c,
3245 .i,
3246 .m,
3247 .no_default_unroll,
3248 .use_postra_scheduler,
3249 .zicsr,
3250 .zifencei,
3251 }),
3252 };
3253 pub const syntacore_scr4_rv32: CpuModel = .{
3254 .name = "syntacore_scr4_rv32",
3255 .llvm_name = "syntacore-scr4-rv32",
3256 .features = featureSet(&[_]Feature{
3257 .@"32bit",
3258 .c,
3259 .d,
3260 .i,
3261 .m,
3262 .no_default_unroll,
3263 .use_postra_scheduler,
3264 .zifencei,
3265 }),
3266 };
3267 pub const syntacore_scr4_rv64: CpuModel = .{
3268 .name = "syntacore_scr4_rv64",
3269 .llvm_name = "syntacore-scr4-rv64",
3270 .features = featureSet(&[_]Feature{
3271 .@"64bit",
3272 .a,
3273 .c,
3274 .d,
3275 .i,
3276 .m,
3277 .no_default_unroll,
3278 .use_postra_scheduler,
3279 .zifencei,
3280 }),
3281 };
3282 pub const syntacore_scr5_rv32: CpuModel = .{
3283 .name = "syntacore_scr5_rv32",
3284 .llvm_name = "syntacore-scr5-rv32",
3285 .features = featureSet(&[_]Feature{
3286 .@"32bit",
3287 .a,
3288 .c,
3289 .d,
3290 .i,
3291 .m,
3292 .no_default_unroll,
3293 .use_postra_scheduler,
3294 .zifencei,
3295 }),
3296 };
3297 pub const syntacore_scr5_rv64: CpuModel = .{
3298 .name = "syntacore_scr5_rv64",
3299 .llvm_name = "syntacore-scr5-rv64",
3300 .features = featureSet(&[_]Feature{
3301 .@"64bit",
3302 .a,
3303 .c,
3304 .d,
3305 .i,
3306 .m,
3307 .no_default_unroll,
3308 .use_postra_scheduler,
3309 .zifencei,
3310 }),
3311 };
3312 pub const syntacore_scr7: CpuModel = .{
3313 .name = "syntacore_scr7",
3314 .llvm_name = "syntacore-scr7",
3315 .features = featureSet(&[_]Feature{
3316 .@"64bit",
3317 .a,
3318 .c,
3319 .i,
3320 .m,
3321 .no_default_unroll,
3322 .use_postra_scheduler,
3323 .v,
3324 .zba,
3325 .zbb,
3326 .zbc,
3327 .zbs,
3328 .zifencei,
3329 .zkn,
3330 }),
3331 };
3332 pub const tt_ascalon_d8: CpuModel = .{
3333 .name = "tt_ascalon_d8",
3334 .llvm_name = "tt-ascalon-d8",
3335 .features = featureSet(&[_]Feature{
3336 .@"64bit",
3337 .a,
3338 .b,
3339 .c,
3340 .i,
3341 .log_vrgather,
3342 .m,
3343 .no_default_unroll,
3344 .optimized_zero_stride_load,
3345 .sha,
3346 .smaia,
3347 .ssaia,
3348 .ssccptr,
3349 .sscofpmf,
3350 .sscounterenw,
3351 .ssnpm,
3352 .ssstrict,
3353 .sstc,
3354 .sstvala,
3355 .sstvecd,
3356 .ssu64xl,
3357 .supm,
3358 .svade,
3359 .svbare,
3360 .svinval,
3361 .svnapot,
3362 .svpbmt,
3363 .unaligned_scalar_mem,
3364 .unaligned_vector_mem,
3365 .use_postra_scheduler,
3366 .v,
3367 .za64rs,
3368 .zawrs,
3369 .zcb,
3370 .zcmop,
3371 .zfa,
3372 .zfh,
3373 .zic64b,
3374 .zicbom,
3375 .zicbop,
3376 .zicboz,
3377 .ziccamoa,
3378 .ziccif,
3379 .zicclsm,
3380 .ziccrse,
3381 .zicntr,
3382 .zicond,
3383 .zifencei,
3384 .zihintntl,
3385 .zihintpause,
3386 .zihpm,
3387 .zimop,
3388 .zkt,
3389 .zvbb,
3390 .zvbc,
3391 .zvfbfwma,
3392 .zvfh,
3393 .zvkng,
3394 .zvl256b,
3395 }),
3396 };
3397 pub const veyron_v1: CpuModel = .{
3398 .name = "veyron_v1",
3399 .llvm_name = "veyron-v1",
3400 .features = featureSet(&[_]Feature{
3401 .@"64bit",
3402 .a,
3403 .auipc_addi_fusion,
3404 .c,
3405 .d,
3406 .i,
3407 .ld_add_fusion,
3408 .lui_addi_fusion,
3409 .m,
3410 .shifted_zextw_fusion,
3411 .ventana_veyron,
3412 .xventanacondops,
3413 .zba,
3414 .zbb,
3415 .zbc,
3416 .zbs,
3417 .zexth_fusion,
3418 .zextw_fusion,
3419 .zicbom,
3420 .zicbop,
3421 .zicboz,
3422 .zicntr,
3423 .zifencei,
3424 .zihintpause,
3425 .zihpm,
3426 }),
3427 };
3428 pub const xiangshan_kunminghu: CpuModel = .{
3429 .name = "xiangshan_kunminghu",
3430 .llvm_name = "xiangshan-kunminghu",
3431 .features = featureSet(&[_]Feature{
3432 .@"64bit",
3433 .a,
3434 .b,
3435 .c,
3436 .i,
3437 .m,
3438 .no_default_unroll,
3439 .sha,
3440 .shifted_zextw_fusion,
3441 .smaia,
3442 .smcsrind,
3443 .smdbltrp,
3444 .smmpm,
3445 .smnpm,
3446 .smrnmi,
3447 .smstateen,
3448 .ssaia,
3449 .ssccptr,
3450 .sscofpmf,
3451 .sscounterenw,
3452 .sscsrind,
3453 .ssdbltrp,
3454 .ssnpm,
3455 .sspm,
3456 .ssstrict,
3457 .sstc,
3458 .sstvala,
3459 .sstvecd,
3460 .ssu64xl,
3461 .supm,
3462 .svade,
3463 .svbare,
3464 .svinval,
3465 .svnapot,
3466 .svpbmt,
3467 .v,
3468 .za64rs,
3469 .zacas,
3470 .zawrs,
3471 .zbc,
3472 .zcb,
3473 .zcmop,
3474 .zexth_fusion,
3475 .zextw_fusion,
3476 .zfa,
3477 .zfh,
3478 .zic64b,
3479 .zicbom,
3480 .zicbop,
3481 .zicboz,
3482 .ziccamoa,
3483 .ziccif,
3484 .zicclsm,
3485 .ziccrse,
3486 .zicntr,
3487 .zicond,
3488 .zifencei,
3489 .zihintntl,
3490 .zihintpause,
3491 .zihpm,
3492 .zimop,
3493 .zkn,
3494 .zks,
3495 .zkt,
3496 .zvbb,
3497 .zvfh,
3498 .zvkt,
3499 }),
3500 };
3501 pub const xiangshan_nanhu: CpuModel = .{
3502 .name = "xiangshan_nanhu",
3503 .llvm_name = "xiangshan-nanhu",
3504 .features = featureSet(&[_]Feature{
3505 .@"64bit",
3506 .a,
3507 .c,
3508 .d,
3509 .i,
3510 .m,
3511 .no_default_unroll,
3512 .shifted_zextw_fusion,
3513 .svinval,
3514 .zba,
3515 .zbb,
3516 .zbc,
3517 .zbs,
3518 .zexth_fusion,
3519 .zextw_fusion,
3520 .zicbom,
3521 .zicboz,
3522 .zifencei,
3523 .zkn,
3524 .zksed,
3525 .zksh,
3526 }),
3527 };
3528};