master
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
3const std = @import("../std.zig");
4const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;
6
7pub const Feature = enum {
8 @"64bit",
9 @"64bitregs",
10 allow_unaligned_fp_access,
11 altivec,
12 booke,
13 bpermd,
14 cmpb,
15 crbits,
16 crypto,
17 direct_move,
18 e500,
19 efpu2,
20 extdiv,
21 fast_MFLR,
22 fcpsgn,
23 float128,
24 fpcvt,
25 fprnd,
26 fpu,
27 fre,
28 fres,
29 frsqrte,
30 frsqrtes,
31 fsqrt,
32 fuse_add_logical,
33 fuse_addi_load,
34 fuse_addis_load,
35 fuse_arith_add,
36 fuse_back2back,
37 fuse_cmp,
38 fuse_logical,
39 fuse_logical_add,
40 fuse_sha3,
41 fuse_store,
42 fuse_wideimm,
43 fuse_zeromove,
44 fusion,
45 hard_float,
46 htm,
47 icbt,
48 invariant_function_descriptors,
49 isa_future_instructions,
50 isa_v206_instructions,
51 isa_v207_instructions,
52 isa_v30_instructions,
53 isa_v31_instructions,
54 isel,
55 ldbrx,
56 lfiwax,
57 longcall,
58 mfocrf,
59 mma,
60 msync,
61 paired_vector_memops,
62 partword_atomics,
63 pcrelative_memops,
64 popcntd,
65 power10_vector,
66 power8_altivec,
67 power8_vector,
68 power9_altivec,
69 power9_vector,
70 ppc4xx,
71 ppc6xx,
72 ppc_postra_sched,
73 ppc_prera_sched,
74 predictable_select_expensive,
75 prefix_instrs,
76 privileged,
77 quadword_atomics,
78 recipprec,
79 rop_protect,
80 secure_plt,
81 slow_popcntd,
82 spe,
83 stfiwx,
84 two_const_nr,
85 vectors_use_two_units,
86 vsx,
87};
88
89pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
90pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
91pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
92pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
93
94pub const all_features = blk: {
95 const len = @typeInfo(Feature).@"enum".fields.len;
96 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
97 var result: [len]CpuFeature = undefined;
98 result[@intFromEnum(Feature.@"64bit")] = .{
99 .llvm_name = "64bit",
100 .description = "Enable 64-bit instructions",
101 .dependencies = featureSet(&[_]Feature{}),
102 };
103 result[@intFromEnum(Feature.@"64bitregs")] = .{
104 .llvm_name = "64bitregs",
105 .description = "Enable 64-bit registers usage for ppc32 [beta]",
106 .dependencies = featureSet(&[_]Feature{}),
107 };
108 result[@intFromEnum(Feature.allow_unaligned_fp_access)] = .{
109 .llvm_name = "allow-unaligned-fp-access",
110 .description = "CPU does not trap on unaligned FP access",
111 .dependencies = featureSet(&[_]Feature{}),
112 };
113 result[@intFromEnum(Feature.altivec)] = .{
114 .llvm_name = "altivec",
115 .description = "Enable Altivec instructions",
116 .dependencies = featureSet(&[_]Feature{
117 .fpu,
118 }),
119 };
120 result[@intFromEnum(Feature.booke)] = .{
121 .llvm_name = "booke",
122 .description = "Enable Book E instructions",
123 .dependencies = featureSet(&[_]Feature{
124 .icbt,
125 }),
126 };
127 result[@intFromEnum(Feature.bpermd)] = .{
128 .llvm_name = "bpermd",
129 .description = "Enable the bpermd instruction",
130 .dependencies = featureSet(&[_]Feature{}),
131 };
132 result[@intFromEnum(Feature.cmpb)] = .{
133 .llvm_name = "cmpb",
134 .description = "Enable the cmpb instruction",
135 .dependencies = featureSet(&[_]Feature{}),
136 };
137 result[@intFromEnum(Feature.crbits)] = .{
138 .llvm_name = "crbits",
139 .description = "Use condition-register bits individually",
140 .dependencies = featureSet(&[_]Feature{}),
141 };
142 result[@intFromEnum(Feature.crypto)] = .{
143 .llvm_name = "crypto",
144 .description = "Enable POWER8 Crypto instructions",
145 .dependencies = featureSet(&[_]Feature{
146 .power8_altivec,
147 }),
148 };
149 result[@intFromEnum(Feature.direct_move)] = .{
150 .llvm_name = "direct-move",
151 .description = "Enable Power8 direct move instructions",
152 .dependencies = featureSet(&[_]Feature{
153 .vsx,
154 }),
155 };
156 result[@intFromEnum(Feature.e500)] = .{
157 .llvm_name = "e500",
158 .description = "Enable E500/E500mc instructions",
159 .dependencies = featureSet(&[_]Feature{}),
160 };
161 result[@intFromEnum(Feature.efpu2)] = .{
162 .llvm_name = "efpu2",
163 .description = "Enable Embedded Floating-Point APU 2 instructions",
164 .dependencies = featureSet(&[_]Feature{
165 .spe,
166 }),
167 };
168 result[@intFromEnum(Feature.extdiv)] = .{
169 .llvm_name = "extdiv",
170 .description = "Enable extended divide instructions",
171 .dependencies = featureSet(&[_]Feature{}),
172 };
173 result[@intFromEnum(Feature.fast_MFLR)] = .{
174 .llvm_name = "fast-MFLR",
175 .description = "MFLR is a fast instruction",
176 .dependencies = featureSet(&[_]Feature{}),
177 };
178 result[@intFromEnum(Feature.fcpsgn)] = .{
179 .llvm_name = "fcpsgn",
180 .description = "Enable the fcpsgn instruction",
181 .dependencies = featureSet(&[_]Feature{
182 .fpu,
183 }),
184 };
185 result[@intFromEnum(Feature.float128)] = .{
186 .llvm_name = "float128",
187 .description = "Enable the __float128 data type for IEEE-754R Binary128.",
188 .dependencies = featureSet(&[_]Feature{
189 .vsx,
190 }),
191 };
192 result[@intFromEnum(Feature.fpcvt)] = .{
193 .llvm_name = "fpcvt",
194 .description = "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
195 .dependencies = featureSet(&[_]Feature{
196 .fpu,
197 }),
198 };
199 result[@intFromEnum(Feature.fprnd)] = .{
200 .llvm_name = "fprnd",
201 .description = "Enable the fri[mnpz] instructions",
202 .dependencies = featureSet(&[_]Feature{
203 .fpu,
204 }),
205 };
206 result[@intFromEnum(Feature.fpu)] = .{
207 .llvm_name = "fpu",
208 .description = "Enable classic FPU instructions",
209 .dependencies = featureSet(&[_]Feature{
210 .hard_float,
211 }),
212 };
213 result[@intFromEnum(Feature.fre)] = .{
214 .llvm_name = "fre",
215 .description = "Enable the fre instruction",
216 .dependencies = featureSet(&[_]Feature{
217 .fpu,
218 }),
219 };
220 result[@intFromEnum(Feature.fres)] = .{
221 .llvm_name = "fres",
222 .description = "Enable the fres instruction",
223 .dependencies = featureSet(&[_]Feature{
224 .fpu,
225 }),
226 };
227 result[@intFromEnum(Feature.frsqrte)] = .{
228 .llvm_name = "frsqrte",
229 .description = "Enable the frsqrte instruction",
230 .dependencies = featureSet(&[_]Feature{
231 .fpu,
232 }),
233 };
234 result[@intFromEnum(Feature.frsqrtes)] = .{
235 .llvm_name = "frsqrtes",
236 .description = "Enable the frsqrtes instruction",
237 .dependencies = featureSet(&[_]Feature{
238 .fpu,
239 }),
240 };
241 result[@intFromEnum(Feature.fsqrt)] = .{
242 .llvm_name = "fsqrt",
243 .description = "Enable the fsqrt instruction",
244 .dependencies = featureSet(&[_]Feature{
245 .fpu,
246 }),
247 };
248 result[@intFromEnum(Feature.fuse_add_logical)] = .{
249 .llvm_name = "fuse-add-logical",
250 .description = "Target supports Add with Logical Operations fusion",
251 .dependencies = featureSet(&[_]Feature{
252 .fusion,
253 }),
254 };
255 result[@intFromEnum(Feature.fuse_addi_load)] = .{
256 .llvm_name = "fuse-addi-load",
257 .description = "Power8 Addi-Load fusion",
258 .dependencies = featureSet(&[_]Feature{
259 .fusion,
260 }),
261 };
262 result[@intFromEnum(Feature.fuse_addis_load)] = .{
263 .llvm_name = "fuse-addis-load",
264 .description = "Power8 Addis-Load fusion",
265 .dependencies = featureSet(&[_]Feature{
266 .fusion,
267 }),
268 };
269 result[@intFromEnum(Feature.fuse_arith_add)] = .{
270 .llvm_name = "fuse-arith-add",
271 .description = "Target supports Arithmetic Operations with Add fusion",
272 .dependencies = featureSet(&[_]Feature{
273 .fusion,
274 }),
275 };
276 result[@intFromEnum(Feature.fuse_back2back)] = .{
277 .llvm_name = "fuse-back2back",
278 .description = "Target supports general back to back fusion",
279 .dependencies = featureSet(&[_]Feature{
280 .fusion,
281 }),
282 };
283 result[@intFromEnum(Feature.fuse_cmp)] = .{
284 .llvm_name = "fuse-cmp",
285 .description = "Target supports Comparison Operations fusion",
286 .dependencies = featureSet(&[_]Feature{
287 .fusion,
288 }),
289 };
290 result[@intFromEnum(Feature.fuse_logical)] = .{
291 .llvm_name = "fuse-logical",
292 .description = "Target supports Logical Operations fusion",
293 .dependencies = featureSet(&[_]Feature{
294 .fusion,
295 }),
296 };
297 result[@intFromEnum(Feature.fuse_logical_add)] = .{
298 .llvm_name = "fuse-logical-add",
299 .description = "Target supports Logical with Add Operations fusion",
300 .dependencies = featureSet(&[_]Feature{
301 .fusion,
302 }),
303 };
304 result[@intFromEnum(Feature.fuse_sha3)] = .{
305 .llvm_name = "fuse-sha3",
306 .description = "Target supports SHA3 assist fusion",
307 .dependencies = featureSet(&[_]Feature{
308 .fusion,
309 }),
310 };
311 result[@intFromEnum(Feature.fuse_store)] = .{
312 .llvm_name = "fuse-store",
313 .description = "Target supports store clustering",
314 .dependencies = featureSet(&[_]Feature{
315 .fusion,
316 }),
317 };
318 result[@intFromEnum(Feature.fuse_wideimm)] = .{
319 .llvm_name = "fuse-wideimm",
320 .description = "Target supports Wide-Immediate fusion",
321 .dependencies = featureSet(&[_]Feature{
322 .fusion,
323 }),
324 };
325 result[@intFromEnum(Feature.fuse_zeromove)] = .{
326 .llvm_name = "fuse-zeromove",
327 .description = "Target supports move to SPR with branch fusion",
328 .dependencies = featureSet(&[_]Feature{
329 .fusion,
330 }),
331 };
332 result[@intFromEnum(Feature.fusion)] = .{
333 .llvm_name = "fusion",
334 .description = "Target supports instruction fusion",
335 .dependencies = featureSet(&[_]Feature{}),
336 };
337 result[@intFromEnum(Feature.hard_float)] = .{
338 .llvm_name = "hard-float",
339 .description = "Enable floating-point instructions",
340 .dependencies = featureSet(&[_]Feature{}),
341 };
342 result[@intFromEnum(Feature.htm)] = .{
343 .llvm_name = "htm",
344 .description = "Enable Hardware Transactional Memory instructions",
345 .dependencies = featureSet(&[_]Feature{}),
346 };
347 result[@intFromEnum(Feature.icbt)] = .{
348 .llvm_name = "icbt",
349 .description = "Enable icbt instruction",
350 .dependencies = featureSet(&[_]Feature{}),
351 };
352 result[@intFromEnum(Feature.invariant_function_descriptors)] = .{
353 .llvm_name = "invariant-function-descriptors",
354 .description = "Assume function descriptors are invariant",
355 .dependencies = featureSet(&[_]Feature{}),
356 };
357 result[@intFromEnum(Feature.isa_future_instructions)] = .{
358 .llvm_name = "isa-future-instructions",
359 .description = "Enable instructions for Future ISA.",
360 .dependencies = featureSet(&[_]Feature{
361 .isa_v31_instructions,
362 }),
363 };
364 result[@intFromEnum(Feature.isa_v206_instructions)] = .{
365 .llvm_name = "isa-v206-instructions",
366 .description = "Enable instructions in ISA 2.06.",
367 .dependencies = featureSet(&[_]Feature{}),
368 };
369 result[@intFromEnum(Feature.isa_v207_instructions)] = .{
370 .llvm_name = "isa-v207-instructions",
371 .description = "Enable instructions in ISA 2.07.",
372 .dependencies = featureSet(&[_]Feature{}),
373 };
374 result[@intFromEnum(Feature.isa_v30_instructions)] = .{
375 .llvm_name = "isa-v30-instructions",
376 .description = "Enable instructions in ISA 3.0.",
377 .dependencies = featureSet(&[_]Feature{
378 .isa_v207_instructions,
379 }),
380 };
381 result[@intFromEnum(Feature.isa_v31_instructions)] = .{
382 .llvm_name = "isa-v31-instructions",
383 .description = "Enable instructions in ISA 3.1.",
384 .dependencies = featureSet(&[_]Feature{
385 .isa_v30_instructions,
386 }),
387 };
388 result[@intFromEnum(Feature.isel)] = .{
389 .llvm_name = "isel",
390 .description = "Enable the isel instruction",
391 .dependencies = featureSet(&[_]Feature{}),
392 };
393 result[@intFromEnum(Feature.ldbrx)] = .{
394 .llvm_name = "ldbrx",
395 .description = "Enable the ldbrx instruction",
396 .dependencies = featureSet(&[_]Feature{}),
397 };
398 result[@intFromEnum(Feature.lfiwax)] = .{
399 .llvm_name = "lfiwax",
400 .description = "Enable the lfiwax instruction",
401 .dependencies = featureSet(&[_]Feature{
402 .fpu,
403 }),
404 };
405 result[@intFromEnum(Feature.longcall)] = .{
406 .llvm_name = "longcall",
407 .description = "Always use indirect calls",
408 .dependencies = featureSet(&[_]Feature{}),
409 };
410 result[@intFromEnum(Feature.mfocrf)] = .{
411 .llvm_name = "mfocrf",
412 .description = "Enable the MFOCRF instruction",
413 .dependencies = featureSet(&[_]Feature{}),
414 };
415 result[@intFromEnum(Feature.mma)] = .{
416 .llvm_name = "mma",
417 .description = "Enable MMA instructions",
418 .dependencies = featureSet(&[_]Feature{
419 .paired_vector_memops,
420 .power8_vector,
421 .power9_altivec,
422 }),
423 };
424 result[@intFromEnum(Feature.msync)] = .{
425 .llvm_name = "msync",
426 .description = "Has only the msync instruction instead of sync",
427 .dependencies = featureSet(&[_]Feature{
428 .booke,
429 }),
430 };
431 result[@intFromEnum(Feature.paired_vector_memops)] = .{
432 .llvm_name = "paired-vector-memops",
433 .description = "32Byte load and store instructions",
434 .dependencies = featureSet(&[_]Feature{
435 .isa_v30_instructions,
436 }),
437 };
438 result[@intFromEnum(Feature.partword_atomics)] = .{
439 .llvm_name = "partword-atomics",
440 .description = "Enable l[bh]arx and st[bh]cx.",
441 .dependencies = featureSet(&[_]Feature{}),
442 };
443 result[@intFromEnum(Feature.pcrelative_memops)] = .{
444 .llvm_name = "pcrelative-memops",
445 .description = "Enable PC relative Memory Ops",
446 .dependencies = featureSet(&[_]Feature{
447 .prefix_instrs,
448 }),
449 };
450 result[@intFromEnum(Feature.popcntd)] = .{
451 .llvm_name = "popcntd",
452 .description = "Enable the popcnt[dw] instructions",
453 .dependencies = featureSet(&[_]Feature{}),
454 };
455 result[@intFromEnum(Feature.power10_vector)] = .{
456 .llvm_name = "power10-vector",
457 .description = "Enable POWER10 vector instructions",
458 .dependencies = featureSet(&[_]Feature{
459 .isa_v31_instructions,
460 .power9_vector,
461 }),
462 };
463 result[@intFromEnum(Feature.power8_altivec)] = .{
464 .llvm_name = "power8-altivec",
465 .description = "Enable POWER8 Altivec instructions",
466 .dependencies = featureSet(&[_]Feature{
467 .altivec,
468 }),
469 };
470 result[@intFromEnum(Feature.power8_vector)] = .{
471 .llvm_name = "power8-vector",
472 .description = "Enable POWER8 vector instructions",
473 .dependencies = featureSet(&[_]Feature{
474 .power8_altivec,
475 .vsx,
476 }),
477 };
478 result[@intFromEnum(Feature.power9_altivec)] = .{
479 .llvm_name = "power9-altivec",
480 .description = "Enable POWER9 Altivec instructions",
481 .dependencies = featureSet(&[_]Feature{
482 .isa_v30_instructions,
483 .power8_altivec,
484 }),
485 };
486 result[@intFromEnum(Feature.power9_vector)] = .{
487 .llvm_name = "power9-vector",
488 .description = "Enable POWER9 vector instructions",
489 .dependencies = featureSet(&[_]Feature{
490 .power8_vector,
491 .power9_altivec,
492 }),
493 };
494 result[@intFromEnum(Feature.ppc4xx)] = .{
495 .llvm_name = "ppc4xx",
496 .description = "Enable PPC 4xx instructions",
497 .dependencies = featureSet(&[_]Feature{}),
498 };
499 result[@intFromEnum(Feature.ppc6xx)] = .{
500 .llvm_name = "ppc6xx",
501 .description = "Enable PPC 6xx instructions",
502 .dependencies = featureSet(&[_]Feature{}),
503 };
504 result[@intFromEnum(Feature.ppc_postra_sched)] = .{
505 .llvm_name = "ppc-postra-sched",
506 .description = "Use PowerPC post-RA scheduling strategy",
507 .dependencies = featureSet(&[_]Feature{}),
508 };
509 result[@intFromEnum(Feature.ppc_prera_sched)] = .{
510 .llvm_name = "ppc-prera-sched",
511 .description = "Use PowerPC pre-RA scheduling strategy",
512 .dependencies = featureSet(&[_]Feature{}),
513 };
514 result[@intFromEnum(Feature.predictable_select_expensive)] = .{
515 .llvm_name = "predictable-select-expensive",
516 .description = "Prefer likely predicted branches over selects",
517 .dependencies = featureSet(&[_]Feature{}),
518 };
519 result[@intFromEnum(Feature.prefix_instrs)] = .{
520 .llvm_name = "prefix-instrs",
521 .description = "Enable prefixed instructions",
522 .dependencies = featureSet(&[_]Feature{
523 .isa_v31_instructions,
524 }),
525 };
526 result[@intFromEnum(Feature.privileged)] = .{
527 .llvm_name = "privileged",
528 .description = "Add privileged instructions",
529 .dependencies = featureSet(&[_]Feature{}),
530 };
531 result[@intFromEnum(Feature.quadword_atomics)] = .{
532 .llvm_name = "quadword-atomics",
533 .description = "Enable lqarx and stqcx.",
534 .dependencies = featureSet(&[_]Feature{}),
535 };
536 result[@intFromEnum(Feature.recipprec)] = .{
537 .llvm_name = "recipprec",
538 .description = "Assume higher precision reciprocal estimates",
539 .dependencies = featureSet(&[_]Feature{}),
540 };
541 result[@intFromEnum(Feature.rop_protect)] = .{
542 .llvm_name = "rop-protect",
543 .description = "Add ROP protect",
544 .dependencies = featureSet(&[_]Feature{}),
545 };
546 result[@intFromEnum(Feature.secure_plt)] = .{
547 .llvm_name = "secure-plt",
548 .description = "Enable secure plt mode",
549 .dependencies = featureSet(&[_]Feature{}),
550 };
551 result[@intFromEnum(Feature.slow_popcntd)] = .{
552 .llvm_name = "slow-popcntd",
553 .description = "Has slow popcnt[dw] instructions",
554 .dependencies = featureSet(&[_]Feature{}),
555 };
556 result[@intFromEnum(Feature.spe)] = .{
557 .llvm_name = "spe",
558 .description = "Enable SPE instructions",
559 .dependencies = featureSet(&[_]Feature{
560 .hard_float,
561 }),
562 };
563 result[@intFromEnum(Feature.stfiwx)] = .{
564 .llvm_name = "stfiwx",
565 .description = "Enable the stfiwx instruction",
566 .dependencies = featureSet(&[_]Feature{
567 .fpu,
568 }),
569 };
570 result[@intFromEnum(Feature.two_const_nr)] = .{
571 .llvm_name = "two-const-nr",
572 .description = "Requires two constant Newton-Raphson computation",
573 .dependencies = featureSet(&[_]Feature{}),
574 };
575 result[@intFromEnum(Feature.vectors_use_two_units)] = .{
576 .llvm_name = "vectors-use-two-units",
577 .description = "Vectors use two units",
578 .dependencies = featureSet(&[_]Feature{}),
579 };
580 result[@intFromEnum(Feature.vsx)] = .{
581 .llvm_name = "vsx",
582 .description = "Enable VSX instructions",
583 .dependencies = featureSet(&[_]Feature{
584 .altivec,
585 }),
586 };
587 const ti = @typeInfo(Feature);
588 for (&result, 0..) |*elem, i| {
589 elem.index = i;
590 elem.name = ti.@"enum".fields[i].name;
591 }
592 break :blk result;
593};
594
595pub const cpu = struct {
596 pub const @"440": CpuModel = .{
597 .name = "440",
598 .llvm_name = "440",
599 .features = featureSet(&[_]Feature{
600 .fres,
601 .frsqrte,
602 .isel,
603 .msync,
604 }),
605 };
606 pub const @"450": CpuModel = .{
607 .name = "450",
608 .llvm_name = "450",
609 .features = featureSet(&[_]Feature{
610 .fres,
611 .frsqrte,
612 .isel,
613 .msync,
614 }),
615 };
616 pub const @"601": CpuModel = .{
617 .name = "601",
618 .llvm_name = "601",
619 .features = featureSet(&[_]Feature{
620 .fpu,
621 }),
622 };
623 pub const @"602": CpuModel = .{
624 .name = "602",
625 .llvm_name = "602",
626 .features = featureSet(&[_]Feature{
627 .fpu,
628 }),
629 };
630 pub const @"603": CpuModel = .{
631 .name = "603",
632 .llvm_name = "603",
633 .features = featureSet(&[_]Feature{
634 .fres,
635 .frsqrte,
636 }),
637 };
638 pub const @"603e": CpuModel = .{
639 .name = "603e",
640 .llvm_name = "603e",
641 .features = featureSet(&[_]Feature{
642 .fres,
643 .frsqrte,
644 }),
645 };
646 pub const @"603ev": CpuModel = .{
647 .name = "603ev",
648 .llvm_name = "603ev",
649 .features = featureSet(&[_]Feature{
650 .fres,
651 .frsqrte,
652 }),
653 };
654 pub const @"604": CpuModel = .{
655 .name = "604",
656 .llvm_name = "604",
657 .features = featureSet(&[_]Feature{
658 .fres,
659 .frsqrte,
660 }),
661 };
662 pub const @"604e": CpuModel = .{
663 .name = "604e",
664 .llvm_name = "604e",
665 .features = featureSet(&[_]Feature{
666 .fres,
667 .frsqrte,
668 }),
669 };
670 pub const @"620": CpuModel = .{
671 .name = "620",
672 .llvm_name = "620",
673 .features = featureSet(&[_]Feature{
674 .fres,
675 .frsqrte,
676 }),
677 };
678 pub const @"7400": CpuModel = .{
679 .name = "7400",
680 .llvm_name = "7400",
681 .features = featureSet(&[_]Feature{
682 .altivec,
683 .fres,
684 .frsqrte,
685 }),
686 };
687 pub const @"7450": CpuModel = .{
688 .name = "7450",
689 .llvm_name = "7450",
690 .features = featureSet(&[_]Feature{
691 .altivec,
692 .fres,
693 .frsqrte,
694 }),
695 };
696 pub const @"750": CpuModel = .{
697 .name = "750",
698 .llvm_name = "750",
699 .features = featureSet(&[_]Feature{
700 .fres,
701 .frsqrte,
702 }),
703 };
704 pub const @"970": CpuModel = .{
705 .name = "970",
706 .llvm_name = "970",
707 .features = featureSet(&[_]Feature{
708 .@"64bit",
709 .altivec,
710 .fres,
711 .frsqrte,
712 .fsqrt,
713 .mfocrf,
714 .stfiwx,
715 }),
716 };
717 pub const a2: CpuModel = .{
718 .name = "a2",
719 .llvm_name = "a2",
720 .features = featureSet(&[_]Feature{
721 .@"64bit",
722 .booke,
723 .cmpb,
724 .fcpsgn,
725 .fpcvt,
726 .fprnd,
727 .fre,
728 .fres,
729 .frsqrte,
730 .frsqrtes,
731 .fsqrt,
732 .isa_v206_instructions,
733 .isel,
734 .ldbrx,
735 .lfiwax,
736 .mfocrf,
737 .recipprec,
738 .slow_popcntd,
739 .stfiwx,
740 }),
741 };
742 pub const e500: CpuModel = .{
743 .name = "e500",
744 .llvm_name = "e500",
745 .features = featureSet(&[_]Feature{
746 .isel,
747 .msync,
748 .spe,
749 }),
750 };
751 pub const e500mc: CpuModel = .{
752 .name = "e500mc",
753 .llvm_name = "e500mc",
754 .features = featureSet(&[_]Feature{
755 .booke,
756 .isel,
757 .stfiwx,
758 }),
759 };
760 pub const e5500: CpuModel = .{
761 .name = "e5500",
762 .llvm_name = "e5500",
763 .features = featureSet(&[_]Feature{
764 .@"64bit",
765 .booke,
766 .isel,
767 .mfocrf,
768 .stfiwx,
769 }),
770 };
771 pub const future: CpuModel = .{
772 .name = "future",
773 .llvm_name = "future",
774 .features = featureSet(&[_]Feature{
775 .@"64bit",
776 .allow_unaligned_fp_access,
777 .bpermd,
778 .cmpb,
779 .crbits,
780 .crypto,
781 .direct_move,
782 .extdiv,
783 .fast_MFLR,
784 .fcpsgn,
785 .fpcvt,
786 .fprnd,
787 .fre,
788 .fres,
789 .frsqrte,
790 .frsqrtes,
791 .fsqrt,
792 .fuse_add_logical,
793 .fuse_arith_add,
794 .fuse_logical,
795 .fuse_logical_add,
796 .fuse_sha3,
797 .fuse_store,
798 .icbt,
799 .isa_future_instructions,
800 .isa_v206_instructions,
801 .isel,
802 .ldbrx,
803 .lfiwax,
804 .mfocrf,
805 .mma,
806 .partword_atomics,
807 .pcrelative_memops,
808 .popcntd,
809 .power10_vector,
810 .ppc_postra_sched,
811 .ppc_prera_sched,
812 .predictable_select_expensive,
813 .quadword_atomics,
814 .recipprec,
815 .stfiwx,
816 .two_const_nr,
817 }),
818 };
819 pub const g3: CpuModel = .{
820 .name = "g3",
821 .llvm_name = "g3",
822 .features = featureSet(&[_]Feature{
823 .fres,
824 .frsqrte,
825 }),
826 };
827 pub const g4: CpuModel = .{
828 .name = "g4",
829 .llvm_name = "g4",
830 .features = featureSet(&[_]Feature{
831 .altivec,
832 .fres,
833 .frsqrte,
834 }),
835 };
836 pub const @"g4+": CpuModel = .{
837 .name = "g4+",
838 .llvm_name = "g4+",
839 .features = featureSet(&[_]Feature{
840 .altivec,
841 .fres,
842 .frsqrte,
843 }),
844 };
845 pub const g5: CpuModel = .{
846 .name = "g5",
847 .llvm_name = "g5",
848 .features = featureSet(&[_]Feature{
849 .@"64bit",
850 .altivec,
851 .fres,
852 .frsqrte,
853 .fsqrt,
854 .mfocrf,
855 .stfiwx,
856 }),
857 };
858 pub const generic: CpuModel = .{
859 .name = "generic",
860 .llvm_name = "generic",
861 .features = featureSet(&[_]Feature{
862 .hard_float,
863 }),
864 };
865 pub const ppc: CpuModel = .{
866 .name = "ppc",
867 .llvm_name = "ppc",
868 .features = featureSet(&[_]Feature{
869 .hard_float,
870 }),
871 };
872 pub const ppc64: CpuModel = .{
873 .name = "ppc64",
874 .llvm_name = "ppc64",
875 .features = featureSet(&[_]Feature{
876 .@"64bit",
877 .altivec,
878 .fres,
879 .frsqrte,
880 .fsqrt,
881 .mfocrf,
882 .stfiwx,
883 }),
884 };
885 pub const ppc64le: CpuModel = .{
886 .name = "ppc64le",
887 .llvm_name = "ppc64le",
888 .features = featureSet(&[_]Feature{
889 .@"64bit",
890 .allow_unaligned_fp_access,
891 .bpermd,
892 .cmpb,
893 .crbits,
894 .crypto,
895 .direct_move,
896 .extdiv,
897 .fcpsgn,
898 .fpcvt,
899 .fprnd,
900 .fre,
901 .fres,
902 .frsqrte,
903 .frsqrtes,
904 .fsqrt,
905 .fuse_addi_load,
906 .fuse_addis_load,
907 .htm,
908 .icbt,
909 .isa_v206_instructions,
910 .isa_v207_instructions,
911 .isel,
912 .ldbrx,
913 .lfiwax,
914 .mfocrf,
915 .partword_atomics,
916 .popcntd,
917 .power8_vector,
918 .predictable_select_expensive,
919 .quadword_atomics,
920 .recipprec,
921 .stfiwx,
922 .two_const_nr,
923 }),
924 };
925 pub const pwr10: CpuModel = .{
926 .name = "pwr10",
927 .llvm_name = "pwr10",
928 .features = featureSet(&[_]Feature{
929 .@"64bit",
930 .allow_unaligned_fp_access,
931 .bpermd,
932 .cmpb,
933 .crbits,
934 .crypto,
935 .direct_move,
936 .extdiv,
937 .fast_MFLR,
938 .fcpsgn,
939 .fpcvt,
940 .fprnd,
941 .fre,
942 .fres,
943 .frsqrte,
944 .frsqrtes,
945 .fsqrt,
946 .fuse_add_logical,
947 .fuse_arith_add,
948 .fuse_logical,
949 .fuse_logical_add,
950 .fuse_sha3,
951 .fuse_store,
952 .icbt,
953 .isa_v206_instructions,
954 .isel,
955 .ldbrx,
956 .lfiwax,
957 .mfocrf,
958 .mma,
959 .partword_atomics,
960 .pcrelative_memops,
961 .popcntd,
962 .power10_vector,
963 .ppc_postra_sched,
964 .ppc_prera_sched,
965 .predictable_select_expensive,
966 .quadword_atomics,
967 .recipprec,
968 .stfiwx,
969 .two_const_nr,
970 }),
971 };
972 pub const pwr11: CpuModel = .{
973 .name = "pwr11",
974 .llvm_name = "pwr11",
975 .features = featureSet(&[_]Feature{
976 .@"64bit",
977 .allow_unaligned_fp_access,
978 .bpermd,
979 .cmpb,
980 .crbits,
981 .crypto,
982 .direct_move,
983 .extdiv,
984 .fast_MFLR,
985 .fcpsgn,
986 .fpcvt,
987 .fprnd,
988 .fre,
989 .fres,
990 .frsqrte,
991 .frsqrtes,
992 .fsqrt,
993 .fuse_add_logical,
994 .fuse_arith_add,
995 .fuse_logical,
996 .fuse_logical_add,
997 .fuse_sha3,
998 .fuse_store,
999 .icbt,
1000 .isa_v206_instructions,
1001 .isel,
1002 .ldbrx,
1003 .lfiwax,
1004 .mfocrf,
1005 .mma,
1006 .partword_atomics,
1007 .pcrelative_memops,
1008 .popcntd,
1009 .power10_vector,
1010 .ppc_postra_sched,
1011 .ppc_prera_sched,
1012 .predictable_select_expensive,
1013 .quadword_atomics,
1014 .recipprec,
1015 .stfiwx,
1016 .two_const_nr,
1017 }),
1018 };
1019 pub const pwr3: CpuModel = .{
1020 .name = "pwr3",
1021 .llvm_name = "pwr3",
1022 .features = featureSet(&[_]Feature{
1023 .@"64bit",
1024 .altivec,
1025 .fres,
1026 .frsqrte,
1027 .mfocrf,
1028 .stfiwx,
1029 }),
1030 };
1031 pub const pwr4: CpuModel = .{
1032 .name = "pwr4",
1033 .llvm_name = "pwr4",
1034 .features = featureSet(&[_]Feature{
1035 .@"64bit",
1036 .altivec,
1037 .fres,
1038 .frsqrte,
1039 .fsqrt,
1040 .mfocrf,
1041 .stfiwx,
1042 }),
1043 };
1044 pub const pwr5: CpuModel = .{
1045 .name = "pwr5",
1046 .llvm_name = "pwr5",
1047 .features = featureSet(&[_]Feature{
1048 .@"64bit",
1049 .altivec,
1050 .fre,
1051 .fres,
1052 .frsqrte,
1053 .frsqrtes,
1054 .fsqrt,
1055 .mfocrf,
1056 .stfiwx,
1057 }),
1058 };
1059 pub const pwr5x: CpuModel = .{
1060 .name = "pwr5x",
1061 .llvm_name = "pwr5x",
1062 .features = featureSet(&[_]Feature{
1063 .@"64bit",
1064 .altivec,
1065 .fprnd,
1066 .fre,
1067 .fres,
1068 .frsqrte,
1069 .frsqrtes,
1070 .fsqrt,
1071 .mfocrf,
1072 .stfiwx,
1073 }),
1074 };
1075 pub const pwr6: CpuModel = .{
1076 .name = "pwr6",
1077 .llvm_name = "pwr6",
1078 .features = featureSet(&[_]Feature{
1079 .@"64bit",
1080 .altivec,
1081 .cmpb,
1082 .fcpsgn,
1083 .fprnd,
1084 .fre,
1085 .fres,
1086 .frsqrte,
1087 .frsqrtes,
1088 .fsqrt,
1089 .lfiwax,
1090 .mfocrf,
1091 .recipprec,
1092 .stfiwx,
1093 }),
1094 };
1095 pub const pwr6x: CpuModel = .{
1096 .name = "pwr6x",
1097 .llvm_name = "pwr6x",
1098 .features = featureSet(&[_]Feature{
1099 .@"64bit",
1100 .altivec,
1101 .cmpb,
1102 .fcpsgn,
1103 .fprnd,
1104 .fre,
1105 .fres,
1106 .frsqrte,
1107 .frsqrtes,
1108 .fsqrt,
1109 .lfiwax,
1110 .mfocrf,
1111 .recipprec,
1112 .stfiwx,
1113 }),
1114 };
1115 pub const pwr7: CpuModel = .{
1116 .name = "pwr7",
1117 .llvm_name = "pwr7",
1118 .features = featureSet(&[_]Feature{
1119 .@"64bit",
1120 .allow_unaligned_fp_access,
1121 .bpermd,
1122 .cmpb,
1123 .extdiv,
1124 .fcpsgn,
1125 .fpcvt,
1126 .fprnd,
1127 .fre,
1128 .fres,
1129 .frsqrte,
1130 .frsqrtes,
1131 .fsqrt,
1132 .isa_v206_instructions,
1133 .isel,
1134 .ldbrx,
1135 .lfiwax,
1136 .mfocrf,
1137 .popcntd,
1138 .recipprec,
1139 .stfiwx,
1140 .two_const_nr,
1141 .vsx,
1142 }),
1143 };
1144 pub const pwr8: CpuModel = .{
1145 .name = "pwr8",
1146 .llvm_name = "pwr8",
1147 .features = featureSet(&[_]Feature{
1148 .@"64bit",
1149 .allow_unaligned_fp_access,
1150 .bpermd,
1151 .cmpb,
1152 .crbits,
1153 .crypto,
1154 .direct_move,
1155 .extdiv,
1156 .fcpsgn,
1157 .fpcvt,
1158 .fprnd,
1159 .fre,
1160 .fres,
1161 .frsqrte,
1162 .frsqrtes,
1163 .fsqrt,
1164 .fuse_addi_load,
1165 .fuse_addis_load,
1166 .htm,
1167 .icbt,
1168 .isa_v206_instructions,
1169 .isa_v207_instructions,
1170 .isel,
1171 .ldbrx,
1172 .lfiwax,
1173 .mfocrf,
1174 .partword_atomics,
1175 .popcntd,
1176 .power8_vector,
1177 .predictable_select_expensive,
1178 .quadword_atomics,
1179 .recipprec,
1180 .stfiwx,
1181 .two_const_nr,
1182 }),
1183 };
1184 pub const pwr9: CpuModel = .{
1185 .name = "pwr9",
1186 .llvm_name = "pwr9",
1187 .features = featureSet(&[_]Feature{
1188 .@"64bit",
1189 .allow_unaligned_fp_access,
1190 .bpermd,
1191 .cmpb,
1192 .crbits,
1193 .crypto,
1194 .direct_move,
1195 .extdiv,
1196 .fcpsgn,
1197 .fpcvt,
1198 .fprnd,
1199 .fre,
1200 .fres,
1201 .frsqrte,
1202 .frsqrtes,
1203 .fsqrt,
1204 .htm,
1205 .icbt,
1206 .isa_v206_instructions,
1207 .isel,
1208 .ldbrx,
1209 .lfiwax,
1210 .mfocrf,
1211 .partword_atomics,
1212 .popcntd,
1213 .power9_vector,
1214 .ppc_postra_sched,
1215 .ppc_prera_sched,
1216 .predictable_select_expensive,
1217 .quadword_atomics,
1218 .recipprec,
1219 .stfiwx,
1220 .two_const_nr,
1221 .vectors_use_two_units,
1222 }),
1223 };
1224};