master
1//! This file is auto-generated by tools/update_cpu_features.zig.
2
3const std = @import("../std.zig");
4const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;
6
7pub const Feature = enum {
8 a320,
9 addr_lsl_slow_14,
10 aes,
11 aggressive_fma,
12 alternate_sextload_cvt_f32_pattern,
13 altnzcv,
14 alu_lsl_fast,
15 am,
16 amvs,
17 arith_bcc_fusion,
18 arith_cbz_fusion,
19 ascend_store_address,
20 avoid_ldapur,
21 balance_fp_ops,
22 bf16,
23 brbe,
24 bti,
25 call_saved_x10,
26 call_saved_x11,
27 call_saved_x12,
28 call_saved_x13,
29 call_saved_x14,
30 call_saved_x15,
31 call_saved_x18,
32 call_saved_x8,
33 call_saved_x9,
34 ccdp,
35 ccidx,
36 ccpp,
37 chk,
38 clrbhb,
39 cmp_bcc_fusion,
40 cmpbr,
41 complxnum,
42 contextidr_el2,
43 cpa,
44 crc,
45 crypto,
46 cssc,
47 d128,
48 disable_fast_inc_vl,
49 disable_latency_sched_heuristic,
50 disable_ldp,
51 disable_stp,
52 dit,
53 dotprod,
54 ecv,
55 el2vmsa,
56 el3,
57 enable_select_opt,
58 ete,
59 execute_only,
60 exynos_cheap_as_move,
61 f32mm,
62 f64mm,
63 f8f16mm,
64 f8f32mm,
65 faminmax,
66 fgt,
67 fix_cortex_a53_835769,
68 flagm,
69 fmv,
70 force_32bit_jump_tables,
71 fp16fml,
72 fp8,
73 fp8dot2,
74 fp8dot4,
75 fp8fma,
76 fp_armv8,
77 fpac,
78 fprcvt,
79 fptoint,
80 fujitsu_monaka,
81 fullfp16,
82 fuse_address,
83 fuse_addsub_2reg_const1,
84 fuse_adrp_add,
85 fuse_aes,
86 fuse_arith_logic,
87 fuse_crypto_eor,
88 fuse_csel,
89 fuse_literals,
90 gcs,
91 harden_sls_blr,
92 harden_sls_nocomdat,
93 harden_sls_retbr,
94 hbc,
95 hcx,
96 i8mm,
97 ite,
98 jsconv,
99 ldp_aligned_only,
100 lor,
101 ls64,
102 lse,
103 lse128,
104 lse2,
105 lsfe,
106 lsui,
107 lut,
108 mec,
109 mops,
110 mpam,
111 mte,
112 neon,
113 nmi,
114 no_bti_at_return_twice,
115 no_neg_immediates,
116 no_sve_fp_ld1r,
117 no_zcz_fp,
118 nv,
119 occmo,
120 olympus,
121 outline_atomics,
122 pan,
123 pan_rwv,
124 pauth,
125 pauth_lr,
126 pcdphint,
127 perfmon,
128 pops,
129 predictable_select_expensive,
130 predres,
131 prfm_slc_target,
132 rand,
133 ras,
134 rasv2,
135 rcpc,
136 rcpc3,
137 rcpc_immo,
138 rdm,
139 reserve_lr_for_ra,
140 reserve_x1,
141 reserve_x10,
142 reserve_x11,
143 reserve_x12,
144 reserve_x13,
145 reserve_x14,
146 reserve_x15,
147 reserve_x18,
148 reserve_x2,
149 reserve_x20,
150 reserve_x21,
151 reserve_x22,
152 reserve_x23,
153 reserve_x24,
154 reserve_x25,
155 reserve_x26,
156 reserve_x27,
157 reserve_x28,
158 reserve_x3,
159 reserve_x4,
160 reserve_x5,
161 reserve_x6,
162 reserve_x7,
163 reserve_x9,
164 rme,
165 sb,
166 sel2,
167 sha2,
168 sha3,
169 slow_misaligned_128store,
170 slow_paired_128,
171 slow_strqro_store,
172 sm4,
173 sme,
174 sme2,
175 sme2p1,
176 sme2p2,
177 sme_b16b16,
178 sme_f16f16,
179 sme_f64f64,
180 sme_f8f16,
181 sme_f8f32,
182 sme_fa64,
183 sme_i16i64,
184 sme_lutv2,
185 sme_mop4,
186 sme_tmop,
187 spe,
188 spe_eef,
189 specres2,
190 specrestrict,
191 ssbs,
192 ssve_aes,
193 ssve_bitperm,
194 ssve_fexpa,
195 ssve_fp8dot2,
196 ssve_fp8dot4,
197 ssve_fp8fma,
198 store_pair_suppress,
199 stp_aligned_only,
200 strict_align,
201 sve,
202 sve2,
203 sve2_aes,
204 sve2_bitperm,
205 sve2_sha3,
206 sve2_sm4,
207 sve2p1,
208 sve2p2,
209 sve_aes,
210 sve_aes2,
211 sve_b16b16,
212 sve_bfscale,
213 sve_bitperm,
214 sve_f16f32mm,
215 sve_sha3,
216 sve_sm4,
217 tagged_globals,
218 the,
219 tlb_rmi,
220 tlbiw,
221 tme,
222 tpidr_el1,
223 tpidr_el2,
224 tpidr_el3,
225 tpidrro_el0,
226 tracev8_4,
227 trbe,
228 uaops,
229 use_experimental_zeroing_pseudos,
230 use_fixed_over_scalable_if_equal_cost,
231 use_postra_scheduler,
232 use_reciprocal_square_root,
233 v8_1a,
234 v8_2a,
235 v8_3a,
236 v8_4a,
237 v8_5a,
238 v8_6a,
239 v8_7a,
240 v8_8a,
241 v8_9a,
242 v8a,
243 v8r,
244 v9_1a,
245 v9_2a,
246 v9_3a,
247 v9_4a,
248 v9_5a,
249 v9_6a,
250 v9a,
251 vh,
252 wfxt,
253 xs,
254 zcm_fpr32,
255 zcm_fpr64,
256 zcm_gpr32,
257 zcm_gpr64,
258 zcz,
259 zcz_fp_workaround,
260 zcz_gp,
261};
262
263pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
264pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
265pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
266pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
267
268pub const all_features = blk: {
269 @setEvalBranchQuota(2000);
270 const len = @typeInfo(Feature).@"enum".fields.len;
271 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
272 var result: [len]CpuFeature = undefined;
273 result[@intFromEnum(Feature.a320)] = .{
274 .llvm_name = "a320",
275 .description = "Cortex-A320 ARM processors",
276 .dependencies = featureSet(&[_]Feature{
277 .fuse_adrp_add,
278 .fuse_aes,
279 .use_postra_scheduler,
280 }),
281 };
282 result[@intFromEnum(Feature.addr_lsl_slow_14)] = .{
283 .llvm_name = "addr-lsl-slow-14",
284 .description = "Address operands with shift amount of 1 or 4 are slow",
285 .dependencies = featureSet(&[_]Feature{}),
286 };
287 result[@intFromEnum(Feature.aes)] = .{
288 .llvm_name = "aes",
289 .description = "Enable AES support",
290 .dependencies = featureSet(&[_]Feature{
291 .neon,
292 }),
293 };
294 result[@intFromEnum(Feature.aggressive_fma)] = .{
295 .llvm_name = "aggressive-fma",
296 .description = "Enable Aggressive FMA for floating-point.",
297 .dependencies = featureSet(&[_]Feature{}),
298 };
299 result[@intFromEnum(Feature.alternate_sextload_cvt_f32_pattern)] = .{
300 .llvm_name = "alternate-sextload-cvt-f32-pattern",
301 .description = "Use alternative pattern for sextload convert to f32",
302 .dependencies = featureSet(&[_]Feature{}),
303 };
304 result[@intFromEnum(Feature.altnzcv)] = .{
305 .llvm_name = "altnzcv",
306 .description = "Enable alternative NZCV format for floating point comparisons",
307 .dependencies = featureSet(&[_]Feature{
308 .flagm,
309 }),
310 };
311 result[@intFromEnum(Feature.alu_lsl_fast)] = .{
312 .llvm_name = "alu-lsl-fast",
313 .description = "Add/Sub operations with lsl shift <= 4 are cheap",
314 .dependencies = featureSet(&[_]Feature{}),
315 };
316 result[@intFromEnum(Feature.am)] = .{
317 .llvm_name = "am",
318 .description = "Enable Armv8.4-A Activity Monitors extension",
319 .dependencies = featureSet(&[_]Feature{}),
320 };
321 result[@intFromEnum(Feature.amvs)] = .{
322 .llvm_name = "amvs",
323 .description = "Enable Armv8.6-A Activity Monitors Virtualization support",
324 .dependencies = featureSet(&[_]Feature{
325 .am,
326 }),
327 };
328 result[@intFromEnum(Feature.arith_bcc_fusion)] = .{
329 .llvm_name = "arith-bcc-fusion",
330 .description = "CPU fuses arithmetic+bcc operations",
331 .dependencies = featureSet(&[_]Feature{}),
332 };
333 result[@intFromEnum(Feature.arith_cbz_fusion)] = .{
334 .llvm_name = "arith-cbz-fusion",
335 .description = "CPU fuses arithmetic + cbz/cbnz operations",
336 .dependencies = featureSet(&[_]Feature{}),
337 };
338 result[@intFromEnum(Feature.ascend_store_address)] = .{
339 .llvm_name = "ascend-store-address",
340 .description = "Schedule vector stores by ascending address",
341 .dependencies = featureSet(&[_]Feature{}),
342 };
343 result[@intFromEnum(Feature.avoid_ldapur)] = .{
344 .llvm_name = "avoid-ldapur",
345 .description = "Prefer add+ldapr to offset ldapur",
346 .dependencies = featureSet(&[_]Feature{}),
347 };
348 result[@intFromEnum(Feature.balance_fp_ops)] = .{
349 .llvm_name = "balance-fp-ops",
350 .description = "balance mix of odd and even D-registers for fp multiply(-accumulate) ops",
351 .dependencies = featureSet(&[_]Feature{}),
352 };
353 result[@intFromEnum(Feature.bf16)] = .{
354 .llvm_name = "bf16",
355 .description = "Enable BFloat16 Extension",
356 .dependencies = featureSet(&[_]Feature{
357 .neon,
358 }),
359 };
360 result[@intFromEnum(Feature.brbe)] = .{
361 .llvm_name = "brbe",
362 .description = "Enable Branch Record Buffer Extension",
363 .dependencies = featureSet(&[_]Feature{}),
364 };
365 result[@intFromEnum(Feature.bti)] = .{
366 .llvm_name = "bti",
367 .description = "Enable Branch Target Identification",
368 .dependencies = featureSet(&[_]Feature{}),
369 };
370 result[@intFromEnum(Feature.call_saved_x10)] = .{
371 .llvm_name = "call-saved-x10",
372 .description = "Make X10 callee saved.",
373 .dependencies = featureSet(&[_]Feature{}),
374 };
375 result[@intFromEnum(Feature.call_saved_x11)] = .{
376 .llvm_name = "call-saved-x11",
377 .description = "Make X11 callee saved.",
378 .dependencies = featureSet(&[_]Feature{}),
379 };
380 result[@intFromEnum(Feature.call_saved_x12)] = .{
381 .llvm_name = "call-saved-x12",
382 .description = "Make X12 callee saved.",
383 .dependencies = featureSet(&[_]Feature{}),
384 };
385 result[@intFromEnum(Feature.call_saved_x13)] = .{
386 .llvm_name = "call-saved-x13",
387 .description = "Make X13 callee saved.",
388 .dependencies = featureSet(&[_]Feature{}),
389 };
390 result[@intFromEnum(Feature.call_saved_x14)] = .{
391 .llvm_name = "call-saved-x14",
392 .description = "Make X14 callee saved.",
393 .dependencies = featureSet(&[_]Feature{}),
394 };
395 result[@intFromEnum(Feature.call_saved_x15)] = .{
396 .llvm_name = "call-saved-x15",
397 .description = "Make X15 callee saved.",
398 .dependencies = featureSet(&[_]Feature{}),
399 };
400 result[@intFromEnum(Feature.call_saved_x18)] = .{
401 .llvm_name = "call-saved-x18",
402 .description = "Make X18 callee saved.",
403 .dependencies = featureSet(&[_]Feature{}),
404 };
405 result[@intFromEnum(Feature.call_saved_x8)] = .{
406 .llvm_name = "call-saved-x8",
407 .description = "Make X8 callee saved.",
408 .dependencies = featureSet(&[_]Feature{}),
409 };
410 result[@intFromEnum(Feature.call_saved_x9)] = .{
411 .llvm_name = "call-saved-x9",
412 .description = "Make X9 callee saved.",
413 .dependencies = featureSet(&[_]Feature{}),
414 };
415 result[@intFromEnum(Feature.ccdp)] = .{
416 .llvm_name = "ccdp",
417 .description = "Enable Armv8.5-A Cache Clean to Point of Deep Persistence",
418 .dependencies = featureSet(&[_]Feature{
419 .ccpp,
420 }),
421 };
422 result[@intFromEnum(Feature.ccidx)] = .{
423 .llvm_name = "ccidx",
424 .description = "Enable Armv8.3-A Extend of the CCSIDR number of sets",
425 .dependencies = featureSet(&[_]Feature{}),
426 };
427 result[@intFromEnum(Feature.ccpp)] = .{
428 .llvm_name = "ccpp",
429 .description = "Enable Armv8.2-A data Cache Clean to Point of Persistence",
430 .dependencies = featureSet(&[_]Feature{}),
431 };
432 result[@intFromEnum(Feature.chk)] = .{
433 .llvm_name = "chk",
434 .description = "Enable Armv8.0-A Check Feature Status Extension",
435 .dependencies = featureSet(&[_]Feature{}),
436 };
437 result[@intFromEnum(Feature.clrbhb)] = .{
438 .llvm_name = "clrbhb",
439 .description = "Enable Clear BHB instruction",
440 .dependencies = featureSet(&[_]Feature{}),
441 };
442 result[@intFromEnum(Feature.cmp_bcc_fusion)] = .{
443 .llvm_name = "cmp-bcc-fusion",
444 .description = "CPU fuses cmp+bcc operations",
445 .dependencies = featureSet(&[_]Feature{}),
446 };
447 result[@intFromEnum(Feature.cmpbr)] = .{
448 .llvm_name = "cmpbr",
449 .description = "Enable Armv9.6-A base compare and branch instructions",
450 .dependencies = featureSet(&[_]Feature{}),
451 };
452 result[@intFromEnum(Feature.complxnum)] = .{
453 .llvm_name = "complxnum",
454 .description = "Enable Armv8.3-A Floating-point complex number support",
455 .dependencies = featureSet(&[_]Feature{
456 .neon,
457 }),
458 };
459 result[@intFromEnum(Feature.contextidr_el2)] = .{
460 .llvm_name = "CONTEXTIDREL2",
461 .description = "Enable RW operand Context ID Register (EL2)",
462 .dependencies = featureSet(&[_]Feature{}),
463 };
464 result[@intFromEnum(Feature.cpa)] = .{
465 .llvm_name = "cpa",
466 .description = "Enable Armv9.5-A Checked Pointer Arithmetic",
467 .dependencies = featureSet(&[_]Feature{}),
468 };
469 result[@intFromEnum(Feature.crc)] = .{
470 .llvm_name = "crc",
471 .description = "Enable Armv8.0-A CRC-32 checksum instructions",
472 .dependencies = featureSet(&[_]Feature{}),
473 };
474 result[@intFromEnum(Feature.crypto)] = .{
475 .llvm_name = "crypto",
476 .description = "Enable cryptographic instructions",
477 .dependencies = featureSet(&[_]Feature{
478 .aes,
479 .sha2,
480 }),
481 };
482 result[@intFromEnum(Feature.cssc)] = .{
483 .llvm_name = "cssc",
484 .description = "Enable Common Short Sequence Compression (CSSC) instructions",
485 .dependencies = featureSet(&[_]Feature{}),
486 };
487 result[@intFromEnum(Feature.d128)] = .{
488 .llvm_name = "d128",
489 .description = "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers and instructions",
490 .dependencies = featureSet(&[_]Feature{
491 .lse128,
492 }),
493 };
494 result[@intFromEnum(Feature.disable_fast_inc_vl)] = .{
495 .llvm_name = "disable-fast-inc-vl",
496 .description = "Do not prefer INC/DEC, ALL, { 1, 2, 4 } over ADDVL",
497 .dependencies = featureSet(&[_]Feature{}),
498 };
499 result[@intFromEnum(Feature.disable_latency_sched_heuristic)] = .{
500 .llvm_name = "disable-latency-sched-heuristic",
501 .description = "Disable latency scheduling heuristic",
502 .dependencies = featureSet(&[_]Feature{}),
503 };
504 result[@intFromEnum(Feature.disable_ldp)] = .{
505 .llvm_name = "disable-ldp",
506 .description = "Do not emit ldp",
507 .dependencies = featureSet(&[_]Feature{}),
508 };
509 result[@intFromEnum(Feature.disable_stp)] = .{
510 .llvm_name = "disable-stp",
511 .description = "Do not emit stp",
512 .dependencies = featureSet(&[_]Feature{}),
513 };
514 result[@intFromEnum(Feature.dit)] = .{
515 .llvm_name = "dit",
516 .description = "Enable Armv8.4-A Data Independent Timing instructions",
517 .dependencies = featureSet(&[_]Feature{}),
518 };
519 result[@intFromEnum(Feature.dotprod)] = .{
520 .llvm_name = "dotprod",
521 .description = "Enable dot product support",
522 .dependencies = featureSet(&[_]Feature{
523 .neon,
524 }),
525 };
526 result[@intFromEnum(Feature.ecv)] = .{
527 .llvm_name = "ecv",
528 .description = "Enable enhanced counter virtualization extension",
529 .dependencies = featureSet(&[_]Feature{}),
530 };
531 result[@intFromEnum(Feature.el2vmsa)] = .{
532 .llvm_name = "el2vmsa",
533 .description = "Enable Exception Level 2 Virtual Memory System Architecture",
534 .dependencies = featureSet(&[_]Feature{}),
535 };
536 result[@intFromEnum(Feature.el3)] = .{
537 .llvm_name = "el3",
538 .description = "Enable Exception Level 3",
539 .dependencies = featureSet(&[_]Feature{}),
540 };
541 result[@intFromEnum(Feature.enable_select_opt)] = .{
542 .llvm_name = "enable-select-opt",
543 .description = "Enable the select optimize pass for select loop heuristics",
544 .dependencies = featureSet(&[_]Feature{}),
545 };
546 result[@intFromEnum(Feature.ete)] = .{
547 .llvm_name = "ete",
548 .description = "Enable Embedded Trace Extension",
549 .dependencies = featureSet(&[_]Feature{
550 .trbe,
551 }),
552 };
553 result[@intFromEnum(Feature.execute_only)] = .{
554 .llvm_name = "execute-only",
555 .description = "Enable the generation of execute only code.",
556 .dependencies = featureSet(&[_]Feature{}),
557 };
558 result[@intFromEnum(Feature.exynos_cheap_as_move)] = .{
559 .llvm_name = "exynos-cheap-as-move",
560 .description = "Use Exynos specific handling of cheap instructions",
561 .dependencies = featureSet(&[_]Feature{}),
562 };
563 result[@intFromEnum(Feature.f32mm)] = .{
564 .llvm_name = "f32mm",
565 .description = "Enable Matrix Multiply FP32 Extension",
566 .dependencies = featureSet(&[_]Feature{
567 .sve,
568 }),
569 };
570 result[@intFromEnum(Feature.f64mm)] = .{
571 .llvm_name = "f64mm",
572 .description = "Enable Matrix Multiply FP64 Extension",
573 .dependencies = featureSet(&[_]Feature{
574 .sve,
575 }),
576 };
577 result[@intFromEnum(Feature.f8f16mm)] = .{
578 .llvm_name = "f8f16mm",
579 .description = "Enable Armv9.6-A FP8 to Half-Precision Matrix Multiplication",
580 .dependencies = featureSet(&[_]Feature{
581 .fp8,
582 }),
583 };
584 result[@intFromEnum(Feature.f8f32mm)] = .{
585 .llvm_name = "f8f32mm",
586 .description = "Enable Armv9.6-A FP8 to Single-Precision Matrix Multiplication",
587 .dependencies = featureSet(&[_]Feature{
588 .fp8,
589 }),
590 };
591 result[@intFromEnum(Feature.faminmax)] = .{
592 .llvm_name = "faminmax",
593 .description = "Enable FAMIN and FAMAX instructions",
594 .dependencies = featureSet(&[_]Feature{
595 .neon,
596 }),
597 };
598 result[@intFromEnum(Feature.fgt)] = .{
599 .llvm_name = "fgt",
600 .description = "Enable fine grained virtualization traps extension",
601 .dependencies = featureSet(&[_]Feature{}),
602 };
603 result[@intFromEnum(Feature.fix_cortex_a53_835769)] = .{
604 .llvm_name = "fix-cortex-a53-835769",
605 .description = "Mitigate Cortex-A53 Erratum 835769",
606 .dependencies = featureSet(&[_]Feature{}),
607 };
608 result[@intFromEnum(Feature.flagm)] = .{
609 .llvm_name = "flagm",
610 .description = "Enable Armv8.4-A Flag Manipulation instructions",
611 .dependencies = featureSet(&[_]Feature{}),
612 };
613 result[@intFromEnum(Feature.fmv)] = .{
614 .llvm_name = "fmv",
615 .description = "Enable Function Multi Versioning support.",
616 .dependencies = featureSet(&[_]Feature{}),
617 };
618 result[@intFromEnum(Feature.force_32bit_jump_tables)] = .{
619 .llvm_name = "force-32bit-jump-tables",
620 .description = "Force jump table entries to be 32-bits wide except at MinSize",
621 .dependencies = featureSet(&[_]Feature{}),
622 };
623 result[@intFromEnum(Feature.fp16fml)] = .{
624 .llvm_name = "fp16fml",
625 .description = "Enable FP16 FML instructions",
626 .dependencies = featureSet(&[_]Feature{
627 .fullfp16,
628 .neon,
629 }),
630 };
631 result[@intFromEnum(Feature.fp8)] = .{
632 .llvm_name = "fp8",
633 .description = "Enable FP8 instructions",
634 .dependencies = featureSet(&[_]Feature{
635 .neon,
636 }),
637 };
638 result[@intFromEnum(Feature.fp8dot2)] = .{
639 .llvm_name = "fp8dot2",
640 .description = "Enable FP8 2-way dot instructions",
641 .dependencies = featureSet(&[_]Feature{
642 .fp8,
643 }),
644 };
645 result[@intFromEnum(Feature.fp8dot4)] = .{
646 .llvm_name = "fp8dot4",
647 .description = "Enable FP8 4-way dot instructions",
648 .dependencies = featureSet(&[_]Feature{
649 .fp8,
650 }),
651 };
652 result[@intFromEnum(Feature.fp8fma)] = .{
653 .llvm_name = "fp8fma",
654 .description = "Enable Armv9.5-A FP8 multiply-add instructions",
655 .dependencies = featureSet(&[_]Feature{
656 .fp8,
657 }),
658 };
659 result[@intFromEnum(Feature.fp_armv8)] = .{
660 .llvm_name = "fp-armv8",
661 .description = "Enable Armv8.0-A Floating Point Extensions",
662 .dependencies = featureSet(&[_]Feature{}),
663 };
664 result[@intFromEnum(Feature.fpac)] = .{
665 .llvm_name = "fpac",
666 .description = "Enable Armv8.3-A Pointer Authentication Faulting enhancement",
667 .dependencies = featureSet(&[_]Feature{}),
668 };
669 result[@intFromEnum(Feature.fprcvt)] = .{
670 .llvm_name = "fprcvt",
671 .description = "Enable Armv9.6-A base convert instructions for SIMD&FP scalar register operands of different input and output sizes",
672 .dependencies = featureSet(&[_]Feature{
673 .fp_armv8,
674 }),
675 };
676 result[@intFromEnum(Feature.fptoint)] = .{
677 .llvm_name = "fptoint",
678 .description = "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int",
679 .dependencies = featureSet(&[_]Feature{
680 .fp_armv8,
681 }),
682 };
683 result[@intFromEnum(Feature.fujitsu_monaka)] = .{
684 .llvm_name = "fujitsu-monaka",
685 .description = "Fujitsu FUJITSU-MONAKA processors",
686 .dependencies = featureSet(&[_]Feature{
687 .arith_bcc_fusion,
688 .enable_select_opt,
689 .predictable_select_expensive,
690 .use_postra_scheduler,
691 }),
692 };
693 result[@intFromEnum(Feature.fullfp16)] = .{
694 .llvm_name = "fullfp16",
695 .description = "Enable half-precision floating-point data processing",
696 .dependencies = featureSet(&[_]Feature{
697 .fp_armv8,
698 }),
699 };
700 result[@intFromEnum(Feature.fuse_address)] = .{
701 .llvm_name = "fuse-address",
702 .description = "CPU fuses address generation and memory operations",
703 .dependencies = featureSet(&[_]Feature{}),
704 };
705 result[@intFromEnum(Feature.fuse_addsub_2reg_const1)] = .{
706 .llvm_name = "fuse-addsub-2reg-const1",
707 .description = "CPU fuses (a + b + 1) and (a - b - 1)",
708 .dependencies = featureSet(&[_]Feature{}),
709 };
710 result[@intFromEnum(Feature.fuse_adrp_add)] = .{
711 .llvm_name = "fuse-adrp-add",
712 .description = "CPU fuses adrp+add operations",
713 .dependencies = featureSet(&[_]Feature{}),
714 };
715 result[@intFromEnum(Feature.fuse_aes)] = .{
716 .llvm_name = "fuse-aes",
717 .description = "CPU fuses AES crypto operations",
718 .dependencies = featureSet(&[_]Feature{}),
719 };
720 result[@intFromEnum(Feature.fuse_arith_logic)] = .{
721 .llvm_name = "fuse-arith-logic",
722 .description = "CPU fuses arithmetic and logic operations",
723 .dependencies = featureSet(&[_]Feature{}),
724 };
725 result[@intFromEnum(Feature.fuse_crypto_eor)] = .{
726 .llvm_name = "fuse-crypto-eor",
727 .description = "CPU fuses AES/PMULL and EOR operations",
728 .dependencies = featureSet(&[_]Feature{}),
729 };
730 result[@intFromEnum(Feature.fuse_csel)] = .{
731 .llvm_name = "fuse-csel",
732 .description = "CPU fuses conditional select operations",
733 .dependencies = featureSet(&[_]Feature{}),
734 };
735 result[@intFromEnum(Feature.fuse_literals)] = .{
736 .llvm_name = "fuse-literals",
737 .description = "CPU fuses literal generation operations",
738 .dependencies = featureSet(&[_]Feature{}),
739 };
740 result[@intFromEnum(Feature.gcs)] = .{
741 .llvm_name = "gcs",
742 .description = "Enable Armv9.4-A Guarded Call Stack Extension",
743 .dependencies = featureSet(&[_]Feature{
744 .chk,
745 }),
746 };
747 result[@intFromEnum(Feature.harden_sls_blr)] = .{
748 .llvm_name = "harden-sls-blr",
749 .description = "Harden against straight line speculation across BLR instructions",
750 .dependencies = featureSet(&[_]Feature{}),
751 };
752 result[@intFromEnum(Feature.harden_sls_nocomdat)] = .{
753 .llvm_name = "harden-sls-nocomdat",
754 .description = "Generate thunk code for SLS mitigation in the normal text section",
755 .dependencies = featureSet(&[_]Feature{}),
756 };
757 result[@intFromEnum(Feature.harden_sls_retbr)] = .{
758 .llvm_name = "harden-sls-retbr",
759 .description = "Harden against straight line speculation across RET and BR instructions",
760 .dependencies = featureSet(&[_]Feature{}),
761 };
762 result[@intFromEnum(Feature.hbc)] = .{
763 .llvm_name = "hbc",
764 .description = "Enable Armv8.8-A Hinted Conditional Branches Extension",
765 .dependencies = featureSet(&[_]Feature{}),
766 };
767 result[@intFromEnum(Feature.hcx)] = .{
768 .llvm_name = "hcx",
769 .description = "Enable Armv8.7-A HCRX_EL2 system register",
770 .dependencies = featureSet(&[_]Feature{}),
771 };
772 result[@intFromEnum(Feature.i8mm)] = .{
773 .llvm_name = "i8mm",
774 .description = "Enable Matrix Multiply Int8 Extension",
775 .dependencies = featureSet(&[_]Feature{
776 .neon,
777 }),
778 };
779 result[@intFromEnum(Feature.ite)] = .{
780 .llvm_name = "ite",
781 .description = "Enable Armv9.4-A Instrumentation Extension",
782 .dependencies = featureSet(&[_]Feature{
783 .ete,
784 }),
785 };
786 result[@intFromEnum(Feature.jsconv)] = .{
787 .llvm_name = "jsconv",
788 .description = "Enable Armv8.3-A JavaScript FP conversion instructions",
789 .dependencies = featureSet(&[_]Feature{
790 .fp_armv8,
791 }),
792 };
793 result[@intFromEnum(Feature.ldp_aligned_only)] = .{
794 .llvm_name = "ldp-aligned-only",
795 .description = "In order to emit ldp, first check if the load will be aligned to 2 * element_size",
796 .dependencies = featureSet(&[_]Feature{}),
797 };
798 result[@intFromEnum(Feature.lor)] = .{
799 .llvm_name = "lor",
800 .description = "Enable Armv8.1-A Limited Ordering Regions extension",
801 .dependencies = featureSet(&[_]Feature{}),
802 };
803 result[@intFromEnum(Feature.ls64)] = .{
804 .llvm_name = "ls64",
805 .description = "Enable Armv8.7-A LD64B/ST64B Accelerator Extension",
806 .dependencies = featureSet(&[_]Feature{}),
807 };
808 result[@intFromEnum(Feature.lse)] = .{
809 .llvm_name = "lse",
810 .description = "Enable Armv8.1-A Large System Extension (LSE) atomic instructions",
811 .dependencies = featureSet(&[_]Feature{}),
812 };
813 result[@intFromEnum(Feature.lse128)] = .{
814 .llvm_name = "lse128",
815 .description = "Enable Armv9.4-A 128-bit Atomic instructions",
816 .dependencies = featureSet(&[_]Feature{
817 .lse,
818 }),
819 };
820 result[@intFromEnum(Feature.lse2)] = .{
821 .llvm_name = "lse2",
822 .description = "Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules",
823 .dependencies = featureSet(&[_]Feature{}),
824 };
825 result[@intFromEnum(Feature.lsfe)] = .{
826 .llvm_name = "lsfe",
827 .description = "Enable Armv9.6-A base Atomic floating-point in-memory instructions",
828 .dependencies = featureSet(&[_]Feature{
829 .fp_armv8,
830 }),
831 };
832 result[@intFromEnum(Feature.lsui)] = .{
833 .llvm_name = "lsui",
834 .description = "Enable Armv9.6-A unprivileged load/store instructions",
835 .dependencies = featureSet(&[_]Feature{}),
836 };
837 result[@intFromEnum(Feature.lut)] = .{
838 .llvm_name = "lut",
839 .description = "Enable Lookup Table instructions",
840 .dependencies = featureSet(&[_]Feature{
841 .neon,
842 }),
843 };
844 result[@intFromEnum(Feature.mec)] = .{
845 .llvm_name = "mec",
846 .description = "Enable Memory Encryption Contexts Extension",
847 .dependencies = featureSet(&[_]Feature{
848 .rme,
849 }),
850 };
851 result[@intFromEnum(Feature.mops)] = .{
852 .llvm_name = "mops",
853 .description = "Enable Armv8.8-A memcpy and memset acceleration instructions",
854 .dependencies = featureSet(&[_]Feature{}),
855 };
856 result[@intFromEnum(Feature.mpam)] = .{
857 .llvm_name = "mpam",
858 .description = "Enable Armv8.4-A Memory system Partitioning and Monitoring extension",
859 .dependencies = featureSet(&[_]Feature{}),
860 };
861 result[@intFromEnum(Feature.mte)] = .{
862 .llvm_name = "mte",
863 .description = "Enable Memory Tagging Extension",
864 .dependencies = featureSet(&[_]Feature{}),
865 };
866 result[@intFromEnum(Feature.neon)] = .{
867 .llvm_name = "neon",
868 .description = "Enable Advanced SIMD instructions",
869 .dependencies = featureSet(&[_]Feature{
870 .fp_armv8,
871 }),
872 };
873 result[@intFromEnum(Feature.nmi)] = .{
874 .llvm_name = "nmi",
875 .description = "Enable Armv8.8-A Non-maskable Interrupts",
876 .dependencies = featureSet(&[_]Feature{}),
877 };
878 result[@intFromEnum(Feature.no_bti_at_return_twice)] = .{
879 .llvm_name = "no-bti-at-return-twice",
880 .description = "Don't place a BTI instruction after a return-twice",
881 .dependencies = featureSet(&[_]Feature{}),
882 };
883 result[@intFromEnum(Feature.no_neg_immediates)] = .{
884 .llvm_name = "no-neg-immediates",
885 .description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.",
886 .dependencies = featureSet(&[_]Feature{}),
887 };
888 result[@intFromEnum(Feature.no_sve_fp_ld1r)] = .{
889 .llvm_name = "no-sve-fp-ld1r",
890 .description = "Avoid using LD1RX instructions for FP",
891 .dependencies = featureSet(&[_]Feature{}),
892 };
893 result[@intFromEnum(Feature.no_zcz_fp)] = .{
894 .llvm_name = "no-zcz-fp",
895 .description = "Has no zero-cycle zeroing instructions for FP registers",
896 .dependencies = featureSet(&[_]Feature{}),
897 };
898 result[@intFromEnum(Feature.nv)] = .{
899 .llvm_name = "nv",
900 .description = "Enable Armv8.4-A Nested Virtualization Enchancement",
901 .dependencies = featureSet(&[_]Feature{}),
902 };
903 result[@intFromEnum(Feature.occmo)] = .{
904 .llvm_name = "occmo",
905 .description = "Enable Armv9.6-A Outer cacheable cache maintenance operations",
906 .dependencies = featureSet(&[_]Feature{}),
907 };
908 result[@intFromEnum(Feature.olympus)] = .{
909 .llvm_name = "olympus",
910 .description = "NVIDIA Olympus processors",
911 .dependencies = featureSet(&[_]Feature{
912 .alu_lsl_fast,
913 .cmp_bcc_fusion,
914 .enable_select_opt,
915 .fuse_adrp_add,
916 .fuse_aes,
917 .predictable_select_expensive,
918 .use_fixed_over_scalable_if_equal_cost,
919 .use_postra_scheduler,
920 }),
921 };
922 result[@intFromEnum(Feature.outline_atomics)] = .{
923 .llvm_name = "outline-atomics",
924 .description = "Enable out of line atomics to support LSE instructions",
925 .dependencies = featureSet(&[_]Feature{}),
926 };
927 result[@intFromEnum(Feature.pan)] = .{
928 .llvm_name = "pan",
929 .description = "Enable Armv8.1-A Privileged Access-Never extension",
930 .dependencies = featureSet(&[_]Feature{}),
931 };
932 result[@intFromEnum(Feature.pan_rwv)] = .{
933 .llvm_name = "pan-rwv",
934 .description = "Enable Armv8.2-A PAN s1e1R and s1e1W Variants",
935 .dependencies = featureSet(&[_]Feature{
936 .pan,
937 }),
938 };
939 result[@intFromEnum(Feature.pauth)] = .{
940 .llvm_name = "pauth",
941 .description = "Enable Armv8.3-A Pointer Authentication extension",
942 .dependencies = featureSet(&[_]Feature{}),
943 };
944 result[@intFromEnum(Feature.pauth_lr)] = .{
945 .llvm_name = "pauth-lr",
946 .description = "Enable Armv9.5-A PAC enhancements",
947 .dependencies = featureSet(&[_]Feature{}),
948 };
949 result[@intFromEnum(Feature.pcdphint)] = .{
950 .llvm_name = "pcdphint",
951 .description = "Enable Armv9.6-A Producer Consumer Data Placement hints",
952 .dependencies = featureSet(&[_]Feature{}),
953 };
954 result[@intFromEnum(Feature.perfmon)] = .{
955 .llvm_name = "perfmon",
956 .description = "Enable Armv8.0-A PMUv3 Performance Monitors extension",
957 .dependencies = featureSet(&[_]Feature{}),
958 };
959 result[@intFromEnum(Feature.pops)] = .{
960 .llvm_name = "pops",
961 .description = "Enable Armv9.6-A Point Of Physical Storage (PoPS) DC instructions",
962 .dependencies = featureSet(&[_]Feature{}),
963 };
964 result[@intFromEnum(Feature.predictable_select_expensive)] = .{
965 .llvm_name = "predictable-select-expensive",
966 .description = "Prefer likely predicted branches over selects",
967 .dependencies = featureSet(&[_]Feature{}),
968 };
969 result[@intFromEnum(Feature.predres)] = .{
970 .llvm_name = "predres",
971 .description = "Enable Armv8.5-A execution and data prediction invalidation instructions",
972 .dependencies = featureSet(&[_]Feature{}),
973 };
974 result[@intFromEnum(Feature.prfm_slc_target)] = .{
975 .llvm_name = "prfm-slc-target",
976 .description = "Enable SLC target for PRFM instruction",
977 .dependencies = featureSet(&[_]Feature{}),
978 };
979 result[@intFromEnum(Feature.rand)] = .{
980 .llvm_name = "rand",
981 .description = "Enable Random Number generation instructions",
982 .dependencies = featureSet(&[_]Feature{}),
983 };
984 result[@intFromEnum(Feature.ras)] = .{
985 .llvm_name = "ras",
986 .description = "Enable Armv8.0-A Reliability, Availability and Serviceability Extensions",
987 .dependencies = featureSet(&[_]Feature{}),
988 };
989 result[@intFromEnum(Feature.rasv2)] = .{
990 .llvm_name = "rasv2",
991 .description = "Enable Armv8.9-A Reliability, Availability and Serviceability Extensions",
992 .dependencies = featureSet(&[_]Feature{
993 .ras,
994 }),
995 };
996 result[@intFromEnum(Feature.rcpc)] = .{
997 .llvm_name = "rcpc",
998 .description = "Enable support for RCPC extension",
999 .dependencies = featureSet(&[_]Feature{}),
1000 };
1001 result[@intFromEnum(Feature.rcpc3)] = .{
1002 .llvm_name = "rcpc3",
1003 .description = "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set",
1004 .dependencies = featureSet(&[_]Feature{
1005 .rcpc_immo,
1006 }),
1007 };
1008 result[@intFromEnum(Feature.rcpc_immo)] = .{
1009 .llvm_name = "rcpc-immo",
1010 .description = "Enable Armv8.4-A RCPC instructions with Immediate Offsets",
1011 .dependencies = featureSet(&[_]Feature{
1012 .rcpc,
1013 }),
1014 };
1015 result[@intFromEnum(Feature.rdm)] = .{
1016 .llvm_name = "rdm",
1017 .description = "Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions",
1018 .dependencies = featureSet(&[_]Feature{
1019 .neon,
1020 }),
1021 };
1022 result[@intFromEnum(Feature.reserve_lr_for_ra)] = .{
1023 .llvm_name = "reserve-lr-for-ra",
1024 .description = "Reserve LR for call use only",
1025 .dependencies = featureSet(&[_]Feature{}),
1026 };
1027 result[@intFromEnum(Feature.reserve_x1)] = .{
1028 .llvm_name = "reserve-x1",
1029 .description = "Reserve X1, making it unavailable as a GPR",
1030 .dependencies = featureSet(&[_]Feature{}),
1031 };
1032 result[@intFromEnum(Feature.reserve_x10)] = .{
1033 .llvm_name = "reserve-x10",
1034 .description = "Reserve X10, making it unavailable as a GPR",
1035 .dependencies = featureSet(&[_]Feature{}),
1036 };
1037 result[@intFromEnum(Feature.reserve_x11)] = .{
1038 .llvm_name = "reserve-x11",
1039 .description = "Reserve X11, making it unavailable as a GPR",
1040 .dependencies = featureSet(&[_]Feature{}),
1041 };
1042 result[@intFromEnum(Feature.reserve_x12)] = .{
1043 .llvm_name = "reserve-x12",
1044 .description = "Reserve X12, making it unavailable as a GPR",
1045 .dependencies = featureSet(&[_]Feature{}),
1046 };
1047 result[@intFromEnum(Feature.reserve_x13)] = .{
1048 .llvm_name = "reserve-x13",
1049 .description = "Reserve X13, making it unavailable as a GPR",
1050 .dependencies = featureSet(&[_]Feature{}),
1051 };
1052 result[@intFromEnum(Feature.reserve_x14)] = .{
1053 .llvm_name = "reserve-x14",
1054 .description = "Reserve X14, making it unavailable as a GPR",
1055 .dependencies = featureSet(&[_]Feature{}),
1056 };
1057 result[@intFromEnum(Feature.reserve_x15)] = .{
1058 .llvm_name = "reserve-x15",
1059 .description = "Reserve X15, making it unavailable as a GPR",
1060 .dependencies = featureSet(&[_]Feature{}),
1061 };
1062 result[@intFromEnum(Feature.reserve_x18)] = .{
1063 .llvm_name = "reserve-x18",
1064 .description = "Reserve X18, making it unavailable as a GPR",
1065 .dependencies = featureSet(&[_]Feature{}),
1066 };
1067 result[@intFromEnum(Feature.reserve_x2)] = .{
1068 .llvm_name = "reserve-x2",
1069 .description = "Reserve X2, making it unavailable as a GPR",
1070 .dependencies = featureSet(&[_]Feature{}),
1071 };
1072 result[@intFromEnum(Feature.reserve_x20)] = .{
1073 .llvm_name = "reserve-x20",
1074 .description = "Reserve X20, making it unavailable as a GPR",
1075 .dependencies = featureSet(&[_]Feature{}),
1076 };
1077 result[@intFromEnum(Feature.reserve_x21)] = .{
1078 .llvm_name = "reserve-x21",
1079 .description = "Reserve X21, making it unavailable as a GPR",
1080 .dependencies = featureSet(&[_]Feature{}),
1081 };
1082 result[@intFromEnum(Feature.reserve_x22)] = .{
1083 .llvm_name = "reserve-x22",
1084 .description = "Reserve X22, making it unavailable as a GPR",
1085 .dependencies = featureSet(&[_]Feature{}),
1086 };
1087 result[@intFromEnum(Feature.reserve_x23)] = .{
1088 .llvm_name = "reserve-x23",
1089 .description = "Reserve X23, making it unavailable as a GPR",
1090 .dependencies = featureSet(&[_]Feature{}),
1091 };
1092 result[@intFromEnum(Feature.reserve_x24)] = .{
1093 .llvm_name = "reserve-x24",
1094 .description = "Reserve X24, making it unavailable as a GPR",
1095 .dependencies = featureSet(&[_]Feature{}),
1096 };
1097 result[@intFromEnum(Feature.reserve_x25)] = .{
1098 .llvm_name = "reserve-x25",
1099 .description = "Reserve X25, making it unavailable as a GPR",
1100 .dependencies = featureSet(&[_]Feature{}),
1101 };
1102 result[@intFromEnum(Feature.reserve_x26)] = .{
1103 .llvm_name = "reserve-x26",
1104 .description = "Reserve X26, making it unavailable as a GPR",
1105 .dependencies = featureSet(&[_]Feature{}),
1106 };
1107 result[@intFromEnum(Feature.reserve_x27)] = .{
1108 .llvm_name = "reserve-x27",
1109 .description = "Reserve X27, making it unavailable as a GPR",
1110 .dependencies = featureSet(&[_]Feature{}),
1111 };
1112 result[@intFromEnum(Feature.reserve_x28)] = .{
1113 .llvm_name = "reserve-x28",
1114 .description = "Reserve X28, making it unavailable as a GPR",
1115 .dependencies = featureSet(&[_]Feature{}),
1116 };
1117 result[@intFromEnum(Feature.reserve_x3)] = .{
1118 .llvm_name = "reserve-x3",
1119 .description = "Reserve X3, making it unavailable as a GPR",
1120 .dependencies = featureSet(&[_]Feature{}),
1121 };
1122 result[@intFromEnum(Feature.reserve_x4)] = .{
1123 .llvm_name = "reserve-x4",
1124 .description = "Reserve X4, making it unavailable as a GPR",
1125 .dependencies = featureSet(&[_]Feature{}),
1126 };
1127 result[@intFromEnum(Feature.reserve_x5)] = .{
1128 .llvm_name = "reserve-x5",
1129 .description = "Reserve X5, making it unavailable as a GPR",
1130 .dependencies = featureSet(&[_]Feature{}),
1131 };
1132 result[@intFromEnum(Feature.reserve_x6)] = .{
1133 .llvm_name = "reserve-x6",
1134 .description = "Reserve X6, making it unavailable as a GPR",
1135 .dependencies = featureSet(&[_]Feature{}),
1136 };
1137 result[@intFromEnum(Feature.reserve_x7)] = .{
1138 .llvm_name = "reserve-x7",
1139 .description = "Reserve X7, making it unavailable as a GPR",
1140 .dependencies = featureSet(&[_]Feature{}),
1141 };
1142 result[@intFromEnum(Feature.reserve_x9)] = .{
1143 .llvm_name = "reserve-x9",
1144 .description = "Reserve X9, making it unavailable as a GPR",
1145 .dependencies = featureSet(&[_]Feature{}),
1146 };
1147 result[@intFromEnum(Feature.rme)] = .{
1148 .llvm_name = "rme",
1149 .description = "Enable Realm Management Extension",
1150 .dependencies = featureSet(&[_]Feature{}),
1151 };
1152 result[@intFromEnum(Feature.sb)] = .{
1153 .llvm_name = "sb",
1154 .description = "Enable Armv8.5-A Speculation Barrier",
1155 .dependencies = featureSet(&[_]Feature{}),
1156 };
1157 result[@intFromEnum(Feature.sel2)] = .{
1158 .llvm_name = "sel2",
1159 .description = "Enable Armv8.4-A Secure Exception Level 2 extension",
1160 .dependencies = featureSet(&[_]Feature{}),
1161 };
1162 result[@intFromEnum(Feature.sha2)] = .{
1163 .llvm_name = "sha2",
1164 .description = "Enable SHA1 and SHA256 support",
1165 .dependencies = featureSet(&[_]Feature{
1166 .neon,
1167 }),
1168 };
1169 result[@intFromEnum(Feature.sha3)] = .{
1170 .llvm_name = "sha3",
1171 .description = "Enable SHA512 and SHA3 support",
1172 .dependencies = featureSet(&[_]Feature{
1173 .sha2,
1174 }),
1175 };
1176 result[@intFromEnum(Feature.slow_misaligned_128store)] = .{
1177 .llvm_name = "slow-misaligned-128store",
1178 .description = "Misaligned 128 bit stores are slow",
1179 .dependencies = featureSet(&[_]Feature{}),
1180 };
1181 result[@intFromEnum(Feature.slow_paired_128)] = .{
1182 .llvm_name = "slow-paired-128",
1183 .description = "Paired 128 bit loads and stores are slow",
1184 .dependencies = featureSet(&[_]Feature{}),
1185 };
1186 result[@intFromEnum(Feature.slow_strqro_store)] = .{
1187 .llvm_name = "slow-strqro-store",
1188 .description = "STR of Q register with register offset is slow",
1189 .dependencies = featureSet(&[_]Feature{}),
1190 };
1191 result[@intFromEnum(Feature.sm4)] = .{
1192 .llvm_name = "sm4",
1193 .description = "Enable SM3 and SM4 support",
1194 .dependencies = featureSet(&[_]Feature{
1195 .neon,
1196 }),
1197 };
1198 result[@intFromEnum(Feature.sme)] = .{
1199 .llvm_name = "sme",
1200 .description = "Enable Scalable Matrix Extension (SME)",
1201 .dependencies = featureSet(&[_]Feature{
1202 .bf16,
1203 .fullfp16,
1204 }),
1205 };
1206 result[@intFromEnum(Feature.sme2)] = .{
1207 .llvm_name = "sme2",
1208 .description = "Enable Scalable Matrix Extension 2 (SME2) instructions",
1209 .dependencies = featureSet(&[_]Feature{
1210 .sme,
1211 }),
1212 };
1213 result[@intFromEnum(Feature.sme2p1)] = .{
1214 .llvm_name = "sme2p1",
1215 .description = "Enable Scalable Matrix Extension 2.1 instructions",
1216 .dependencies = featureSet(&[_]Feature{
1217 .sme2,
1218 }),
1219 };
1220 result[@intFromEnum(Feature.sme2p2)] = .{
1221 .llvm_name = "sme2p2",
1222 .description = "Enable Armv9.6-A Scalable Matrix Extension 2.2 instructions",
1223 .dependencies = featureSet(&[_]Feature{
1224 .sme2p1,
1225 }),
1226 };
1227 result[@intFromEnum(Feature.sme_b16b16)] = .{
1228 .llvm_name = "sme-b16b16",
1229 .description = "Enable SME2.1 ZA-targeting non-widening BFloat16 instructions",
1230 .dependencies = featureSet(&[_]Feature{
1231 .sme2,
1232 .sve_b16b16,
1233 }),
1234 };
1235 result[@intFromEnum(Feature.sme_f16f16)] = .{
1236 .llvm_name = "sme-f16f16",
1237 .description = "Enable SME non-widening Float16 instructions",
1238 .dependencies = featureSet(&[_]Feature{
1239 .sme2,
1240 }),
1241 };
1242 result[@intFromEnum(Feature.sme_f64f64)] = .{
1243 .llvm_name = "sme-f64f64",
1244 .description = "Enable Scalable Matrix Extension (SME) F64F64 instructions",
1245 .dependencies = featureSet(&[_]Feature{
1246 .sme,
1247 }),
1248 };
1249 result[@intFromEnum(Feature.sme_f8f16)] = .{
1250 .llvm_name = "sme-f8f16",
1251 .description = "Enable Scalable Matrix Extension (SME) F8F16 instructions",
1252 .dependencies = featureSet(&[_]Feature{
1253 .fp8,
1254 .sme2,
1255 }),
1256 };
1257 result[@intFromEnum(Feature.sme_f8f32)] = .{
1258 .llvm_name = "sme-f8f32",
1259 .description = "Enable Scalable Matrix Extension (SME) F8F32 instructions",
1260 .dependencies = featureSet(&[_]Feature{
1261 .fp8,
1262 .sme2,
1263 }),
1264 };
1265 result[@intFromEnum(Feature.sme_fa64)] = .{
1266 .llvm_name = "sme-fa64",
1267 .description = "Enable the full A64 instruction set in streaming SVE mode",
1268 .dependencies = featureSet(&[_]Feature{
1269 .sme,
1270 .sve2,
1271 }),
1272 };
1273 result[@intFromEnum(Feature.sme_i16i64)] = .{
1274 .llvm_name = "sme-i16i64",
1275 .description = "Enable Scalable Matrix Extension (SME) I16I64 instructions",
1276 .dependencies = featureSet(&[_]Feature{
1277 .sme,
1278 }),
1279 };
1280 result[@intFromEnum(Feature.sme_lutv2)] = .{
1281 .llvm_name = "sme-lutv2",
1282 .description = "Enable Scalable Matrix Extension (SME) LUTv2 instructions",
1283 .dependencies = featureSet(&[_]Feature{
1284 .sme2,
1285 }),
1286 };
1287 result[@intFromEnum(Feature.sme_mop4)] = .{
1288 .llvm_name = "sme-mop4",
1289 .description = "Enable SME Quarter-tile outer product instructions",
1290 .dependencies = featureSet(&[_]Feature{
1291 .sme2,
1292 }),
1293 };
1294 result[@intFromEnum(Feature.sme_tmop)] = .{
1295 .llvm_name = "sme-tmop",
1296 .description = "Enable SME Structured sparsity outer product instructions.",
1297 .dependencies = featureSet(&[_]Feature{
1298 .sme2,
1299 }),
1300 };
1301 result[@intFromEnum(Feature.spe)] = .{
1302 .llvm_name = "spe",
1303 .description = "Enable Statistical Profiling extension",
1304 .dependencies = featureSet(&[_]Feature{}),
1305 };
1306 result[@intFromEnum(Feature.spe_eef)] = .{
1307 .llvm_name = "spe-eef",
1308 .description = "Enable extra register in the Statistical Profiling Extension",
1309 .dependencies = featureSet(&[_]Feature{}),
1310 };
1311 result[@intFromEnum(Feature.specres2)] = .{
1312 .llvm_name = "specres2",
1313 .description = "Enable Speculation Restriction Instruction",
1314 .dependencies = featureSet(&[_]Feature{
1315 .predres,
1316 }),
1317 };
1318 result[@intFromEnum(Feature.specrestrict)] = .{
1319 .llvm_name = "specrestrict",
1320 .description = "Enable architectural speculation restriction",
1321 .dependencies = featureSet(&[_]Feature{}),
1322 };
1323 result[@intFromEnum(Feature.ssbs)] = .{
1324 .llvm_name = "ssbs",
1325 .description = "Enable Speculative Store Bypass Safe bit",
1326 .dependencies = featureSet(&[_]Feature{}),
1327 };
1328 result[@intFromEnum(Feature.ssve_aes)] = .{
1329 .llvm_name = "ssve-aes",
1330 .description = "Enable Armv9.6-A SVE AES support in streaming SVE mode",
1331 .dependencies = featureSet(&[_]Feature{
1332 .sme2,
1333 .sve_aes,
1334 }),
1335 };
1336 result[@intFromEnum(Feature.ssve_bitperm)] = .{
1337 .llvm_name = "ssve-bitperm",
1338 .description = "Enable Armv9.6-A SVE BitPerm support in streaming SVE mode",
1339 .dependencies = featureSet(&[_]Feature{
1340 .sme2,
1341 .sve_bitperm,
1342 }),
1343 };
1344 result[@intFromEnum(Feature.ssve_fexpa)] = .{
1345 .llvm_name = "ssve-fexpa",
1346 .description = "Enable SVE FEXPA instruction in Streaming SVE mode",
1347 .dependencies = featureSet(&[_]Feature{
1348 .sme2,
1349 }),
1350 };
1351 result[@intFromEnum(Feature.ssve_fp8dot2)] = .{
1352 .llvm_name = "ssve-fp8dot2",
1353 .description = "Enable SVE2 FP8 2-way dot product instructions",
1354 .dependencies = featureSet(&[_]Feature{
1355 .fp8,
1356 .sme2,
1357 }),
1358 };
1359 result[@intFromEnum(Feature.ssve_fp8dot4)] = .{
1360 .llvm_name = "ssve-fp8dot4",
1361 .description = "Enable SVE2 FP8 4-way dot product instructions",
1362 .dependencies = featureSet(&[_]Feature{
1363 .fp8,
1364 .sme2,
1365 }),
1366 };
1367 result[@intFromEnum(Feature.ssve_fp8fma)] = .{
1368 .llvm_name = "ssve-fp8fma",
1369 .description = "Enable SVE2 FP8 multiply-add instructions",
1370 .dependencies = featureSet(&[_]Feature{
1371 .fp8,
1372 .sme2,
1373 }),
1374 };
1375 result[@intFromEnum(Feature.store_pair_suppress)] = .{
1376 .llvm_name = "store-pair-suppress",
1377 .description = "Enable Store Pair Suppression heuristics",
1378 .dependencies = featureSet(&[_]Feature{}),
1379 };
1380 result[@intFromEnum(Feature.stp_aligned_only)] = .{
1381 .llvm_name = "stp-aligned-only",
1382 .description = "In order to emit stp, first check if the store will be aligned to 2 * element_size",
1383 .dependencies = featureSet(&[_]Feature{}),
1384 };
1385 result[@intFromEnum(Feature.strict_align)] = .{
1386 .llvm_name = "strict-align",
1387 .description = "Disallow all unaligned memory access",
1388 .dependencies = featureSet(&[_]Feature{}),
1389 };
1390 result[@intFromEnum(Feature.sve)] = .{
1391 .llvm_name = "sve",
1392 .description = "Enable Scalable Vector Extension (SVE) instructions",
1393 .dependencies = featureSet(&[_]Feature{
1394 .fullfp16,
1395 }),
1396 };
1397 result[@intFromEnum(Feature.sve2)] = .{
1398 .llvm_name = "sve2",
1399 .description = "Enable Scalable Vector Extension 2 (SVE2) instructions",
1400 .dependencies = featureSet(&[_]Feature{
1401 .sve,
1402 }),
1403 };
1404 result[@intFromEnum(Feature.sve2_aes)] = .{
1405 .llvm_name = "sve2-aes",
1406 .description = "Shorthand for +sve2+sve-aes",
1407 .dependencies = featureSet(&[_]Feature{
1408 .sve2,
1409 .sve_aes,
1410 }),
1411 };
1412 result[@intFromEnum(Feature.sve2_bitperm)] = .{
1413 .llvm_name = "sve2-bitperm",
1414 .description = "Shorthand for +sve2+sve-bitperm",
1415 .dependencies = featureSet(&[_]Feature{
1416 .sve2,
1417 .sve_bitperm,
1418 }),
1419 };
1420 result[@intFromEnum(Feature.sve2_sha3)] = .{
1421 .llvm_name = "sve2-sha3",
1422 .description = "Shorthand for +sve2+sve-sha3",
1423 .dependencies = featureSet(&[_]Feature{
1424 .sve2,
1425 .sve_sha3,
1426 }),
1427 };
1428 result[@intFromEnum(Feature.sve2_sm4)] = .{
1429 .llvm_name = "sve2-sm4",
1430 .description = "Shorthand for +sve2+sve-sm4",
1431 .dependencies = featureSet(&[_]Feature{
1432 .sve2,
1433 .sve_sm4,
1434 }),
1435 };
1436 result[@intFromEnum(Feature.sve2p1)] = .{
1437 .llvm_name = "sve2p1",
1438 .description = "Enable Scalable Vector Extension 2.1 instructions",
1439 .dependencies = featureSet(&[_]Feature{
1440 .sve2,
1441 }),
1442 };
1443 result[@intFromEnum(Feature.sve2p2)] = .{
1444 .llvm_name = "sve2p2",
1445 .description = "Enable Armv9.6-A Scalable Vector Extension 2.2 instructions",
1446 .dependencies = featureSet(&[_]Feature{
1447 .sve2p1,
1448 }),
1449 };
1450 result[@intFromEnum(Feature.sve_aes)] = .{
1451 .llvm_name = "sve-aes",
1452 .description = "Enable SVE AES and quadword SVE polynomial multiply instructions",
1453 .dependencies = featureSet(&[_]Feature{
1454 .aes,
1455 }),
1456 };
1457 result[@intFromEnum(Feature.sve_aes2)] = .{
1458 .llvm_name = "sve-aes2",
1459 .description = "Enable Armv9.6-A SVE multi-vector AES and multi-vector quadword polynomial multiply instructions",
1460 .dependencies = featureSet(&[_]Feature{}),
1461 };
1462 result[@intFromEnum(Feature.sve_b16b16)] = .{
1463 .llvm_name = "sve-b16b16",
1464 .description = "Enable SVE2 non-widening and SME2 Z-targeting non-widening BFloat16 instructions",
1465 .dependencies = featureSet(&[_]Feature{}),
1466 };
1467 result[@intFromEnum(Feature.sve_bfscale)] = .{
1468 .llvm_name = "sve-bfscale",
1469 .description = "Enable Armv9.6-A SVE BFloat16 scaling instructions",
1470 .dependencies = featureSet(&[_]Feature{}),
1471 };
1472 result[@intFromEnum(Feature.sve_bitperm)] = .{
1473 .llvm_name = "sve-bitperm",
1474 .description = "Enable bit permutation SVE2 instructions",
1475 .dependencies = featureSet(&[_]Feature{}),
1476 };
1477 result[@intFromEnum(Feature.sve_f16f32mm)] = .{
1478 .llvm_name = "sve-f16f32mm",
1479 .description = "Enable Armv9.6-A FP16 to FP32 Matrix Multiply instructions",
1480 .dependencies = featureSet(&[_]Feature{
1481 .sve,
1482 }),
1483 };
1484 result[@intFromEnum(Feature.sve_sha3)] = .{
1485 .llvm_name = "sve-sha3",
1486 .description = "Enable SVE SHA3 instructions",
1487 .dependencies = featureSet(&[_]Feature{
1488 .sha3,
1489 }),
1490 };
1491 result[@intFromEnum(Feature.sve_sm4)] = .{
1492 .llvm_name = "sve-sm4",
1493 .description = "Enable SVE SM4 instructions",
1494 .dependencies = featureSet(&[_]Feature{
1495 .sm4,
1496 }),
1497 };
1498 result[@intFromEnum(Feature.tagged_globals)] = .{
1499 .llvm_name = "tagged-globals",
1500 .description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits",
1501 .dependencies = featureSet(&[_]Feature{}),
1502 };
1503 result[@intFromEnum(Feature.the)] = .{
1504 .llvm_name = "the",
1505 .description = "Enable Armv8.9-A Translation Hardening Extension",
1506 .dependencies = featureSet(&[_]Feature{}),
1507 };
1508 result[@intFromEnum(Feature.tlb_rmi)] = .{
1509 .llvm_name = "tlb-rmi",
1510 .description = "Enable Armv8.4-A TLB Range and Maintenance instructions",
1511 .dependencies = featureSet(&[_]Feature{}),
1512 };
1513 result[@intFromEnum(Feature.tlbiw)] = .{
1514 .llvm_name = "tlbiw",
1515 .description = "Enable Armv9.5-A TLBI VMALL for Dirty State",
1516 .dependencies = featureSet(&[_]Feature{}),
1517 };
1518 result[@intFromEnum(Feature.tme)] = .{
1519 .llvm_name = "tme",
1520 .description = "Enable Transactional Memory Extension",
1521 .dependencies = featureSet(&[_]Feature{}),
1522 };
1523 result[@intFromEnum(Feature.tpidr_el1)] = .{
1524 .llvm_name = "tpidr-el1",
1525 .description = "Permit use of TPIDR_EL1 for the TLS base",
1526 .dependencies = featureSet(&[_]Feature{}),
1527 };
1528 result[@intFromEnum(Feature.tpidr_el2)] = .{
1529 .llvm_name = "tpidr-el2",
1530 .description = "Permit use of TPIDR_EL2 for the TLS base",
1531 .dependencies = featureSet(&[_]Feature{}),
1532 };
1533 result[@intFromEnum(Feature.tpidr_el3)] = .{
1534 .llvm_name = "tpidr-el3",
1535 .description = "Permit use of TPIDR_EL3 for the TLS base",
1536 .dependencies = featureSet(&[_]Feature{}),
1537 };
1538 result[@intFromEnum(Feature.tpidrro_el0)] = .{
1539 .llvm_name = "tpidrro-el0",
1540 .description = "Permit use of TPIDRRO_EL0 for the TLS base",
1541 .dependencies = featureSet(&[_]Feature{}),
1542 };
1543 result[@intFromEnum(Feature.tracev8_4)] = .{
1544 .llvm_name = "tracev8.4",
1545 .description = "Enable Armv8.4-A Trace extension",
1546 .dependencies = featureSet(&[_]Feature{}),
1547 };
1548 result[@intFromEnum(Feature.trbe)] = .{
1549 .llvm_name = "trbe",
1550 .description = "Enable Trace Buffer Extension",
1551 .dependencies = featureSet(&[_]Feature{}),
1552 };
1553 result[@intFromEnum(Feature.uaops)] = .{
1554 .llvm_name = "uaops",
1555 .description = "Enable Armv8.2-A UAO PState",
1556 .dependencies = featureSet(&[_]Feature{}),
1557 };
1558 result[@intFromEnum(Feature.use_experimental_zeroing_pseudos)] = .{
1559 .llvm_name = "use-experimental-zeroing-pseudos",
1560 .description = "Hint to the compiler that the MOVPRFX instruction is merged with destructive operations",
1561 .dependencies = featureSet(&[_]Feature{}),
1562 };
1563 result[@intFromEnum(Feature.use_fixed_over_scalable_if_equal_cost)] = .{
1564 .llvm_name = "use-fixed-over-scalable-if-equal-cost",
1565 .description = "Prefer fixed width loop vectorization over scalable if the cost-model assigns equal costs",
1566 .dependencies = featureSet(&[_]Feature{}),
1567 };
1568 result[@intFromEnum(Feature.use_postra_scheduler)] = .{
1569 .llvm_name = "use-postra-scheduler",
1570 .description = "Schedule again after register allocation",
1571 .dependencies = featureSet(&[_]Feature{}),
1572 };
1573 result[@intFromEnum(Feature.use_reciprocal_square_root)] = .{
1574 .llvm_name = "use-reciprocal-square-root",
1575 .description = "Use the reciprocal square root approximation",
1576 .dependencies = featureSet(&[_]Feature{}),
1577 };
1578 result[@intFromEnum(Feature.v8_1a)] = .{
1579 .llvm_name = "v8.1a",
1580 .description = "Support ARM v8.1a architecture",
1581 .dependencies = featureSet(&[_]Feature{
1582 .crc,
1583 .lor,
1584 .lse,
1585 .pan,
1586 .rdm,
1587 .v8a,
1588 .vh,
1589 }),
1590 };
1591 result[@intFromEnum(Feature.v8_2a)] = .{
1592 .llvm_name = "v8.2a",
1593 .description = "Support ARM v8.2a architecture",
1594 .dependencies = featureSet(&[_]Feature{
1595 .ccpp,
1596 .pan_rwv,
1597 .ras,
1598 .uaops,
1599 .v8_1a,
1600 }),
1601 };
1602 result[@intFromEnum(Feature.v8_3a)] = .{
1603 .llvm_name = "v8.3a",
1604 .description = "Support ARM v8.3a architecture",
1605 .dependencies = featureSet(&[_]Feature{
1606 .ccidx,
1607 .complxnum,
1608 .jsconv,
1609 .pauth,
1610 .rcpc,
1611 .v8_2a,
1612 }),
1613 };
1614 result[@intFromEnum(Feature.v8_4a)] = .{
1615 .llvm_name = "v8.4a",
1616 .description = "Support ARM v8.4a architecture",
1617 .dependencies = featureSet(&[_]Feature{
1618 .am,
1619 .dit,
1620 .dotprod,
1621 .flagm,
1622 .lse2,
1623 .mpam,
1624 .nv,
1625 .rcpc_immo,
1626 .sel2,
1627 .tlb_rmi,
1628 .tracev8_4,
1629 .v8_3a,
1630 }),
1631 };
1632 result[@intFromEnum(Feature.v8_5a)] = .{
1633 .llvm_name = "v8.5a",
1634 .description = "Support ARM v8.5a architecture",
1635 .dependencies = featureSet(&[_]Feature{
1636 .altnzcv,
1637 .bti,
1638 .ccdp,
1639 .fptoint,
1640 .predres,
1641 .sb,
1642 .specrestrict,
1643 .ssbs,
1644 .v8_4a,
1645 }),
1646 };
1647 result[@intFromEnum(Feature.v8_6a)] = .{
1648 .llvm_name = "v8.6a",
1649 .description = "Support ARM v8.6a architecture",
1650 .dependencies = featureSet(&[_]Feature{
1651 .amvs,
1652 .bf16,
1653 .ecv,
1654 .fgt,
1655 .i8mm,
1656 .v8_5a,
1657 }),
1658 };
1659 result[@intFromEnum(Feature.v8_7a)] = .{
1660 .llvm_name = "v8.7a",
1661 .description = "Support ARM v8.7a architecture",
1662 .dependencies = featureSet(&[_]Feature{
1663 .hcx,
1664 .spe_eef,
1665 .v8_6a,
1666 .wfxt,
1667 .xs,
1668 }),
1669 };
1670 result[@intFromEnum(Feature.v8_8a)] = .{
1671 .llvm_name = "v8.8a",
1672 .description = "Support ARM v8.8a architecture",
1673 .dependencies = featureSet(&[_]Feature{
1674 .hbc,
1675 .mops,
1676 .nmi,
1677 .v8_7a,
1678 }),
1679 };
1680 result[@intFromEnum(Feature.v8_9a)] = .{
1681 .llvm_name = "v8.9a",
1682 .description = "Support ARM v8.9a architecture",
1683 .dependencies = featureSet(&[_]Feature{
1684 .chk,
1685 .clrbhb,
1686 .cssc,
1687 .prfm_slc_target,
1688 .rasv2,
1689 .specres2,
1690 .v8_8a,
1691 }),
1692 };
1693 result[@intFromEnum(Feature.v8a)] = .{
1694 .llvm_name = "v8a",
1695 .description = "Support ARM v8a architecture",
1696 .dependencies = featureSet(&[_]Feature{
1697 .el2vmsa,
1698 .el3,
1699 .neon,
1700 }),
1701 };
1702 result[@intFromEnum(Feature.v8r)] = .{
1703 .llvm_name = "v8r",
1704 .description = "Support ARM v8r architecture",
1705 .dependencies = featureSet(&[_]Feature{
1706 .ccidx,
1707 .ccpp,
1708 .complxnum,
1709 .contextidr_el2,
1710 .crc,
1711 .dit,
1712 .dotprod,
1713 .flagm,
1714 .fp16fml,
1715 .jsconv,
1716 .lse,
1717 .pan_rwv,
1718 .pauth,
1719 .ras,
1720 .rcpc_immo,
1721 .rdm,
1722 .sb,
1723 .sel2,
1724 .specrestrict,
1725 .ssbs,
1726 .tlb_rmi,
1727 .tracev8_4,
1728 .uaops,
1729 }),
1730 };
1731 result[@intFromEnum(Feature.v9_1a)] = .{
1732 .llvm_name = "v9.1a",
1733 .description = "Support ARM v9.1a architecture",
1734 .dependencies = featureSet(&[_]Feature{
1735 .rme,
1736 .v8_6a,
1737 .v9a,
1738 }),
1739 };
1740 result[@intFromEnum(Feature.v9_2a)] = .{
1741 .llvm_name = "v9.2a",
1742 .description = "Support ARM v9.2a architecture",
1743 .dependencies = featureSet(&[_]Feature{
1744 .mec,
1745 .v8_7a,
1746 .v9_1a,
1747 }),
1748 };
1749 result[@intFromEnum(Feature.v9_3a)] = .{
1750 .llvm_name = "v9.3a",
1751 .description = "Support ARM v9.3a architecture",
1752 .dependencies = featureSet(&[_]Feature{
1753 .v8_8a,
1754 .v9_2a,
1755 }),
1756 };
1757 result[@intFromEnum(Feature.v9_4a)] = .{
1758 .llvm_name = "v9.4a",
1759 .description = "Support ARM v9.4a architecture",
1760 .dependencies = featureSet(&[_]Feature{
1761 .sve2p1,
1762 .v8_9a,
1763 .v9_3a,
1764 }),
1765 };
1766 result[@intFromEnum(Feature.v9_5a)] = .{
1767 .llvm_name = "v9.5a",
1768 .description = "Support ARM v9.5a architecture",
1769 .dependencies = featureSet(&[_]Feature{
1770 .cpa,
1771 .faminmax,
1772 .lut,
1773 .v9_4a,
1774 }),
1775 };
1776 result[@intFromEnum(Feature.v9_6a)] = .{
1777 .llvm_name = "v9.6a",
1778 .description = "Support ARM v9.6a architecture",
1779 .dependencies = featureSet(&[_]Feature{
1780 .cmpbr,
1781 .lsui,
1782 .occmo,
1783 .v9_5a,
1784 }),
1785 };
1786 result[@intFromEnum(Feature.v9a)] = .{
1787 .llvm_name = "v9a",
1788 .description = "Support ARM v9a architecture",
1789 .dependencies = featureSet(&[_]Feature{
1790 .sve2,
1791 .v8_5a,
1792 }),
1793 };
1794 result[@intFromEnum(Feature.vh)] = .{
1795 .llvm_name = "vh",
1796 .description = "Enable Armv8.1-A Virtual Host extension",
1797 .dependencies = featureSet(&[_]Feature{
1798 .contextidr_el2,
1799 }),
1800 };
1801 result[@intFromEnum(Feature.wfxt)] = .{
1802 .llvm_name = "wfxt",
1803 .description = "Enable Armv8.7-A WFET and WFIT instruction",
1804 .dependencies = featureSet(&[_]Feature{}),
1805 };
1806 result[@intFromEnum(Feature.xs)] = .{
1807 .llvm_name = "xs",
1808 .description = "Enable Armv8.7-A limited-TLB-maintenance instruction",
1809 .dependencies = featureSet(&[_]Feature{}),
1810 };
1811 result[@intFromEnum(Feature.zcm_fpr32)] = .{
1812 .llvm_name = "zcm-fpr32",
1813 .description = "Has zero-cycle register moves for FPR32 registers",
1814 .dependencies = featureSet(&[_]Feature{}),
1815 };
1816 result[@intFromEnum(Feature.zcm_fpr64)] = .{
1817 .llvm_name = "zcm-fpr64",
1818 .description = "Has zero-cycle register moves for FPR64 registers",
1819 .dependencies = featureSet(&[_]Feature{}),
1820 };
1821 result[@intFromEnum(Feature.zcm_gpr32)] = .{
1822 .llvm_name = "zcm-gpr32",
1823 .description = "Has zero-cycle register moves for GPR32 registers",
1824 .dependencies = featureSet(&[_]Feature{}),
1825 };
1826 result[@intFromEnum(Feature.zcm_gpr64)] = .{
1827 .llvm_name = "zcm-gpr64",
1828 .description = "Has zero-cycle register moves for GPR64 registers",
1829 .dependencies = featureSet(&[_]Feature{}),
1830 };
1831 result[@intFromEnum(Feature.zcz)] = .{
1832 .llvm_name = "zcz",
1833 .description = "Has zero-cycle zeroing instructions",
1834 .dependencies = featureSet(&[_]Feature{
1835 .zcz_gp,
1836 }),
1837 };
1838 result[@intFromEnum(Feature.zcz_fp_workaround)] = .{
1839 .llvm_name = "zcz-fp-workaround",
1840 .description = "The zero-cycle floating-point zeroing instruction has a bug",
1841 .dependencies = featureSet(&[_]Feature{}),
1842 };
1843 result[@intFromEnum(Feature.zcz_gp)] = .{
1844 .llvm_name = "zcz-gp",
1845 .description = "Has zero-cycle zeroing instructions for generic registers",
1846 .dependencies = featureSet(&[_]Feature{}),
1847 };
1848 const ti = @typeInfo(Feature);
1849 for (&result, 0..) |*elem, i| {
1850 elem.index = i;
1851 elem.name = ti.@"enum".fields[i].name;
1852 }
1853 break :blk result;
1854};
1855
1856pub const cpu = struct {
1857 pub const a64fx: CpuModel = .{
1858 .name = "a64fx",
1859 .llvm_name = "a64fx",
1860 .features = featureSet(&[_]Feature{
1861 .aes,
1862 .aggressive_fma,
1863 .arith_bcc_fusion,
1864 .complxnum,
1865 .perfmon,
1866 .predictable_select_expensive,
1867 .sha2,
1868 .store_pair_suppress,
1869 .sve,
1870 .use_postra_scheduler,
1871 .v8_2a,
1872 }),
1873 };
1874 pub const ampere1: CpuModel = .{
1875 .name = "ampere1",
1876 .llvm_name = "ampere1",
1877 .features = featureSet(&[_]Feature{
1878 .aes,
1879 .aggressive_fma,
1880 .alu_lsl_fast,
1881 .arith_bcc_fusion,
1882 .cmp_bcc_fusion,
1883 .fullfp16,
1884 .fuse_address,
1885 .fuse_adrp_add,
1886 .fuse_aes,
1887 .fuse_literals,
1888 .ldp_aligned_only,
1889 .perfmon,
1890 .rand,
1891 .sha3,
1892 .store_pair_suppress,
1893 .stp_aligned_only,
1894 .use_postra_scheduler,
1895 .v8_6a,
1896 }),
1897 };
1898 pub const ampere1a: CpuModel = .{
1899 .name = "ampere1a",
1900 .llvm_name = "ampere1a",
1901 .features = featureSet(&[_]Feature{
1902 .aes,
1903 .aggressive_fma,
1904 .alu_lsl_fast,
1905 .arith_bcc_fusion,
1906 .cmp_bcc_fusion,
1907 .fullfp16,
1908 .fuse_address,
1909 .fuse_addsub_2reg_const1,
1910 .fuse_adrp_add,
1911 .fuse_aes,
1912 .fuse_literals,
1913 .ldp_aligned_only,
1914 .mte,
1915 .perfmon,
1916 .rand,
1917 .sha3,
1918 .sm4,
1919 .store_pair_suppress,
1920 .stp_aligned_only,
1921 .use_postra_scheduler,
1922 .v8_6a,
1923 }),
1924 };
1925 pub const ampere1b: CpuModel = .{
1926 .name = "ampere1b",
1927 .llvm_name = "ampere1b",
1928 .features = featureSet(&[_]Feature{
1929 .aes,
1930 .aggressive_fma,
1931 .alu_lsl_fast,
1932 .arith_bcc_fusion,
1933 .cmp_bcc_fusion,
1934 .cssc,
1935 .enable_select_opt,
1936 .fullfp16,
1937 .fuse_address,
1938 .fuse_adrp_add,
1939 .fuse_aes,
1940 .fuse_literals,
1941 .ldp_aligned_only,
1942 .mte,
1943 .perfmon,
1944 .predictable_select_expensive,
1945 .rand,
1946 .sha3,
1947 .sm4,
1948 .store_pair_suppress,
1949 .stp_aligned_only,
1950 .use_postra_scheduler,
1951 .v8_7a,
1952 }),
1953 };
1954 pub const apple_a10: CpuModel = .{
1955 .name = "apple_a10",
1956 .llvm_name = "apple-a10",
1957 .features = featureSet(&[_]Feature{
1958 .aes,
1959 .alternate_sextload_cvt_f32_pattern,
1960 .arith_bcc_fusion,
1961 .arith_cbz_fusion,
1962 .crc,
1963 .disable_latency_sched_heuristic,
1964 .fuse_aes,
1965 .fuse_crypto_eor,
1966 .lor,
1967 .pan,
1968 .perfmon,
1969 .rdm,
1970 .sha2,
1971 .store_pair_suppress,
1972 .v8a,
1973 .vh,
1974 .zcm_fpr64,
1975 .zcm_gpr64,
1976 .zcz,
1977 }),
1978 };
1979 pub const apple_a11: CpuModel = .{
1980 .name = "apple_a11",
1981 .llvm_name = "apple-a11",
1982 .features = featureSet(&[_]Feature{
1983 .aes,
1984 .alternate_sextload_cvt_f32_pattern,
1985 .arith_bcc_fusion,
1986 .arith_cbz_fusion,
1987 .disable_latency_sched_heuristic,
1988 .fullfp16,
1989 .fuse_aes,
1990 .fuse_crypto_eor,
1991 .perfmon,
1992 .sha2,
1993 .store_pair_suppress,
1994 .v8_2a,
1995 .zcm_fpr64,
1996 .zcm_gpr64,
1997 .zcz,
1998 }),
1999 };
2000 pub const apple_a12: CpuModel = .{
2001 .name = "apple_a12",
2002 .llvm_name = "apple-a12",
2003 .features = featureSet(&[_]Feature{
2004 .aes,
2005 .alternate_sextload_cvt_f32_pattern,
2006 .arith_bcc_fusion,
2007 .arith_cbz_fusion,
2008 .disable_latency_sched_heuristic,
2009 .fullfp16,
2010 .fuse_aes,
2011 .fuse_crypto_eor,
2012 .perfmon,
2013 .sha2,
2014 .store_pair_suppress,
2015 .v8_3a,
2016 .zcm_fpr64,
2017 .zcm_gpr64,
2018 .zcz,
2019 }),
2020 };
2021 pub const apple_a13: CpuModel = .{
2022 .name = "apple_a13",
2023 .llvm_name = "apple-a13",
2024 .features = featureSet(&[_]Feature{
2025 .aes,
2026 .alternate_sextload_cvt_f32_pattern,
2027 .arith_bcc_fusion,
2028 .arith_cbz_fusion,
2029 .disable_latency_sched_heuristic,
2030 .fp16fml,
2031 .fuse_aes,
2032 .fuse_crypto_eor,
2033 .perfmon,
2034 .sha3,
2035 .store_pair_suppress,
2036 .v8_4a,
2037 .zcm_fpr64,
2038 .zcm_gpr64,
2039 .zcz,
2040 }),
2041 };
2042 pub const apple_a14: CpuModel = .{
2043 .name = "apple_a14",
2044 .llvm_name = "apple-a14",
2045 .features = featureSet(&[_]Feature{
2046 .aes,
2047 .aggressive_fma,
2048 .alternate_sextload_cvt_f32_pattern,
2049 .altnzcv,
2050 .arith_bcc_fusion,
2051 .arith_cbz_fusion,
2052 .ccdp,
2053 .disable_latency_sched_heuristic,
2054 .fp16fml,
2055 .fptoint,
2056 .fuse_address,
2057 .fuse_aes,
2058 .fuse_arith_logic,
2059 .fuse_crypto_eor,
2060 .fuse_csel,
2061 .fuse_literals,
2062 .perfmon,
2063 .predres,
2064 .sb,
2065 .sha3,
2066 .specrestrict,
2067 .ssbs,
2068 .store_pair_suppress,
2069 .v8_4a,
2070 .zcm_fpr64,
2071 .zcm_gpr64,
2072 .zcz,
2073 }),
2074 };
2075 pub const apple_a15: CpuModel = .{
2076 .name = "apple_a15",
2077 .llvm_name = "apple-a15",
2078 .features = featureSet(&[_]Feature{
2079 .aes,
2080 .alternate_sextload_cvt_f32_pattern,
2081 .arith_bcc_fusion,
2082 .arith_cbz_fusion,
2083 .disable_latency_sched_heuristic,
2084 .fp16fml,
2085 .fpac,
2086 .fuse_address,
2087 .fuse_adrp_add,
2088 .fuse_aes,
2089 .fuse_arith_logic,
2090 .fuse_crypto_eor,
2091 .fuse_csel,
2092 .fuse_literals,
2093 .perfmon,
2094 .sha3,
2095 .store_pair_suppress,
2096 .v8_6a,
2097 .zcm_fpr64,
2098 .zcm_gpr64,
2099 .zcz,
2100 }),
2101 };
2102 pub const apple_a16: CpuModel = .{
2103 .name = "apple_a16",
2104 .llvm_name = "apple-a16",
2105 .features = featureSet(&[_]Feature{
2106 .aes,
2107 .alternate_sextload_cvt_f32_pattern,
2108 .arith_bcc_fusion,
2109 .arith_cbz_fusion,
2110 .disable_latency_sched_heuristic,
2111 .fp16fml,
2112 .fpac,
2113 .fuse_address,
2114 .fuse_adrp_add,
2115 .fuse_aes,
2116 .fuse_arith_logic,
2117 .fuse_crypto_eor,
2118 .fuse_csel,
2119 .fuse_literals,
2120 .hcx,
2121 .perfmon,
2122 .sha3,
2123 .store_pair_suppress,
2124 .v8_6a,
2125 .zcm_fpr64,
2126 .zcm_gpr64,
2127 .zcz,
2128 }),
2129 };
2130 pub const apple_a17: CpuModel = .{
2131 .name = "apple_a17",
2132 .llvm_name = "apple-a17",
2133 .features = featureSet(&[_]Feature{
2134 .aes,
2135 .alternate_sextload_cvt_f32_pattern,
2136 .arith_bcc_fusion,
2137 .arith_cbz_fusion,
2138 .disable_latency_sched_heuristic,
2139 .fp16fml,
2140 .fpac,
2141 .fuse_address,
2142 .fuse_adrp_add,
2143 .fuse_aes,
2144 .fuse_arith_logic,
2145 .fuse_crypto_eor,
2146 .fuse_csel,
2147 .fuse_literals,
2148 .hcx,
2149 .perfmon,
2150 .sha3,
2151 .store_pair_suppress,
2152 .v8_6a,
2153 .zcm_fpr64,
2154 .zcm_gpr64,
2155 .zcz,
2156 }),
2157 };
2158 pub const apple_a18: CpuModel = .{
2159 .name = "apple_a18",
2160 .llvm_name = "apple-a18",
2161 .features = featureSet(&[_]Feature{
2162 .aes,
2163 .alternate_sextload_cvt_f32_pattern,
2164 .arith_bcc_fusion,
2165 .arith_cbz_fusion,
2166 .disable_latency_sched_heuristic,
2167 .fp16fml,
2168 .fpac,
2169 .fuse_address,
2170 .fuse_adrp_add,
2171 .fuse_aes,
2172 .fuse_arith_logic,
2173 .fuse_crypto_eor,
2174 .fuse_csel,
2175 .fuse_literals,
2176 .perfmon,
2177 .sha3,
2178 .sme2,
2179 .sme_f64f64,
2180 .sme_i16i64,
2181 .v8_7a,
2182 .zcm_fpr64,
2183 .zcm_gpr64,
2184 .zcz,
2185 }),
2186 };
2187 pub const apple_a7: CpuModel = .{
2188 .name = "apple_a7",
2189 .llvm_name = "apple-a7",
2190 .features = featureSet(&[_]Feature{
2191 .aes,
2192 .alternate_sextload_cvt_f32_pattern,
2193 .arith_bcc_fusion,
2194 .arith_cbz_fusion,
2195 .disable_latency_sched_heuristic,
2196 .fuse_aes,
2197 .fuse_crypto_eor,
2198 .perfmon,
2199 .sha2,
2200 .store_pair_suppress,
2201 .v8a,
2202 .zcm_fpr64,
2203 .zcm_gpr64,
2204 .zcz,
2205 .zcz_fp_workaround,
2206 }),
2207 };
2208 pub const apple_a8: CpuModel = .{
2209 .name = "apple_a8",
2210 .llvm_name = "apple-a8",
2211 .features = featureSet(&[_]Feature{
2212 .aes,
2213 .alternate_sextload_cvt_f32_pattern,
2214 .arith_bcc_fusion,
2215 .arith_cbz_fusion,
2216 .disable_latency_sched_heuristic,
2217 .fuse_aes,
2218 .fuse_crypto_eor,
2219 .perfmon,
2220 .sha2,
2221 .store_pair_suppress,
2222 .v8a,
2223 .zcm_fpr64,
2224 .zcm_gpr64,
2225 .zcz,
2226 .zcz_fp_workaround,
2227 }),
2228 };
2229 pub const apple_a9: CpuModel = .{
2230 .name = "apple_a9",
2231 .llvm_name = "apple-a9",
2232 .features = featureSet(&[_]Feature{
2233 .aes,
2234 .alternate_sextload_cvt_f32_pattern,
2235 .arith_bcc_fusion,
2236 .arith_cbz_fusion,
2237 .disable_latency_sched_heuristic,
2238 .fuse_aes,
2239 .fuse_crypto_eor,
2240 .perfmon,
2241 .sha2,
2242 .store_pair_suppress,
2243 .v8a,
2244 .zcm_fpr64,
2245 .zcm_gpr64,
2246 .zcz,
2247 .zcz_fp_workaround,
2248 }),
2249 };
2250 pub const apple_m1: CpuModel = .{
2251 .name = "apple_m1",
2252 .llvm_name = "apple-m1",
2253 .features = featureSet(&[_]Feature{
2254 .aes,
2255 .aggressive_fma,
2256 .alternate_sextload_cvt_f32_pattern,
2257 .altnzcv,
2258 .arith_bcc_fusion,
2259 .arith_cbz_fusion,
2260 .ccdp,
2261 .disable_latency_sched_heuristic,
2262 .fp16fml,
2263 .fptoint,
2264 .fuse_address,
2265 .fuse_aes,
2266 .fuse_arith_logic,
2267 .fuse_crypto_eor,
2268 .fuse_csel,
2269 .fuse_literals,
2270 .perfmon,
2271 .predres,
2272 .sb,
2273 .sha3,
2274 .specrestrict,
2275 .ssbs,
2276 .store_pair_suppress,
2277 .v8_4a,
2278 .zcm_fpr64,
2279 .zcm_gpr64,
2280 .zcz,
2281 }),
2282 };
2283 pub const apple_m2: CpuModel = .{
2284 .name = "apple_m2",
2285 .llvm_name = "apple-m2",
2286 .features = featureSet(&[_]Feature{
2287 .aes,
2288 .alternate_sextload_cvt_f32_pattern,
2289 .arith_bcc_fusion,
2290 .arith_cbz_fusion,
2291 .disable_latency_sched_heuristic,
2292 .fp16fml,
2293 .fpac,
2294 .fuse_address,
2295 .fuse_adrp_add,
2296 .fuse_aes,
2297 .fuse_arith_logic,
2298 .fuse_crypto_eor,
2299 .fuse_csel,
2300 .fuse_literals,
2301 .perfmon,
2302 .sha3,
2303 .store_pair_suppress,
2304 .v8_6a,
2305 .zcm_fpr64,
2306 .zcm_gpr64,
2307 .zcz,
2308 }),
2309 };
2310 pub const apple_m3: CpuModel = .{
2311 .name = "apple_m3",
2312 .llvm_name = "apple-m3",
2313 .features = featureSet(&[_]Feature{
2314 .aes,
2315 .alternate_sextload_cvt_f32_pattern,
2316 .arith_bcc_fusion,
2317 .arith_cbz_fusion,
2318 .disable_latency_sched_heuristic,
2319 .fp16fml,
2320 .fpac,
2321 .fuse_address,
2322 .fuse_adrp_add,
2323 .fuse_aes,
2324 .fuse_arith_logic,
2325 .fuse_crypto_eor,
2326 .fuse_csel,
2327 .fuse_literals,
2328 .hcx,
2329 .perfmon,
2330 .sha3,
2331 .store_pair_suppress,
2332 .v8_6a,
2333 .zcm_fpr64,
2334 .zcm_gpr64,
2335 .zcz,
2336 }),
2337 };
2338 pub const apple_m4: CpuModel = .{
2339 .name = "apple_m4",
2340 .llvm_name = "apple-m4",
2341 .features = featureSet(&[_]Feature{
2342 .aes,
2343 .alternate_sextload_cvt_f32_pattern,
2344 .arith_bcc_fusion,
2345 .arith_cbz_fusion,
2346 .disable_latency_sched_heuristic,
2347 .fp16fml,
2348 .fpac,
2349 .fuse_address,
2350 .fuse_adrp_add,
2351 .fuse_aes,
2352 .fuse_arith_logic,
2353 .fuse_crypto_eor,
2354 .fuse_csel,
2355 .fuse_literals,
2356 .perfmon,
2357 .sha3,
2358 .sme2,
2359 .sme_f64f64,
2360 .sme_i16i64,
2361 .v8_7a,
2362 .zcm_fpr64,
2363 .zcm_gpr64,
2364 .zcz,
2365 }),
2366 };
2367 pub const apple_s10: CpuModel = .{
2368 .name = "apple_s10",
2369 .llvm_name = "apple-s10",
2370 .features = featureSet(&[_]Feature{
2371 .aes,
2372 .alternate_sextload_cvt_f32_pattern,
2373 .arith_bcc_fusion,
2374 .arith_cbz_fusion,
2375 .disable_latency_sched_heuristic,
2376 .fp16fml,
2377 .fpac,
2378 .fuse_address,
2379 .fuse_adrp_add,
2380 .fuse_aes,
2381 .fuse_arith_logic,
2382 .fuse_crypto_eor,
2383 .fuse_csel,
2384 .fuse_literals,
2385 .hcx,
2386 .perfmon,
2387 .sha3,
2388 .store_pair_suppress,
2389 .v8_6a,
2390 .zcm_fpr64,
2391 .zcm_gpr64,
2392 .zcz,
2393 }),
2394 };
2395 pub const apple_s4: CpuModel = .{
2396 .name = "apple_s4",
2397 .llvm_name = "apple-s4",
2398 .features = featureSet(&[_]Feature{
2399 .aes,
2400 .alternate_sextload_cvt_f32_pattern,
2401 .arith_bcc_fusion,
2402 .arith_cbz_fusion,
2403 .disable_latency_sched_heuristic,
2404 .fullfp16,
2405 .fuse_aes,
2406 .fuse_crypto_eor,
2407 .perfmon,
2408 .sha2,
2409 .store_pair_suppress,
2410 .v8_3a,
2411 .zcm_fpr64,
2412 .zcm_gpr64,
2413 .zcz,
2414 }),
2415 };
2416 pub const apple_s5: CpuModel = .{
2417 .name = "apple_s5",
2418 .llvm_name = "apple-s5",
2419 .features = featureSet(&[_]Feature{
2420 .aes,
2421 .alternate_sextload_cvt_f32_pattern,
2422 .arith_bcc_fusion,
2423 .arith_cbz_fusion,
2424 .disable_latency_sched_heuristic,
2425 .fullfp16,
2426 .fuse_aes,
2427 .fuse_crypto_eor,
2428 .perfmon,
2429 .sha2,
2430 .store_pair_suppress,
2431 .v8_3a,
2432 .zcm_fpr64,
2433 .zcm_gpr64,
2434 .zcz,
2435 }),
2436 };
2437 pub const apple_s6: CpuModel = .{
2438 .name = "apple_s6",
2439 .llvm_name = "apple-s6",
2440 .features = featureSet(&[_]Feature{
2441 .aes,
2442 .alternate_sextload_cvt_f32_pattern,
2443 .arith_bcc_fusion,
2444 .arith_cbz_fusion,
2445 .disable_latency_sched_heuristic,
2446 .fp16fml,
2447 .fuse_aes,
2448 .fuse_crypto_eor,
2449 .perfmon,
2450 .sha3,
2451 .store_pair_suppress,
2452 .v8_4a,
2453 .zcm_fpr64,
2454 .zcm_gpr64,
2455 .zcz,
2456 }),
2457 };
2458 pub const apple_s7: CpuModel = .{
2459 .name = "apple_s7",
2460 .llvm_name = "apple-s7",
2461 .features = featureSet(&[_]Feature{
2462 .aes,
2463 .alternate_sextload_cvt_f32_pattern,
2464 .arith_bcc_fusion,
2465 .arith_cbz_fusion,
2466 .disable_latency_sched_heuristic,
2467 .fp16fml,
2468 .fuse_aes,
2469 .fuse_crypto_eor,
2470 .perfmon,
2471 .sha3,
2472 .store_pair_suppress,
2473 .v8_4a,
2474 .zcm_fpr64,
2475 .zcm_gpr64,
2476 .zcz,
2477 }),
2478 };
2479 pub const apple_s8: CpuModel = .{
2480 .name = "apple_s8",
2481 .llvm_name = "apple-s8",
2482 .features = featureSet(&[_]Feature{
2483 .aes,
2484 .alternate_sextload_cvt_f32_pattern,
2485 .arith_bcc_fusion,
2486 .arith_cbz_fusion,
2487 .disable_latency_sched_heuristic,
2488 .fp16fml,
2489 .fuse_aes,
2490 .fuse_crypto_eor,
2491 .perfmon,
2492 .sha3,
2493 .store_pair_suppress,
2494 .v8_4a,
2495 .zcm_fpr64,
2496 .zcm_gpr64,
2497 .zcz,
2498 }),
2499 };
2500 pub const apple_s9: CpuModel = .{
2501 .name = "apple_s9",
2502 .llvm_name = "apple-s9",
2503 .features = featureSet(&[_]Feature{
2504 .aes,
2505 .alternate_sextload_cvt_f32_pattern,
2506 .arith_bcc_fusion,
2507 .arith_cbz_fusion,
2508 .disable_latency_sched_heuristic,
2509 .fp16fml,
2510 .fpac,
2511 .fuse_address,
2512 .fuse_adrp_add,
2513 .fuse_aes,
2514 .fuse_arith_logic,
2515 .fuse_crypto_eor,
2516 .fuse_csel,
2517 .fuse_literals,
2518 .hcx,
2519 .perfmon,
2520 .sha3,
2521 .store_pair_suppress,
2522 .v8_6a,
2523 .zcm_fpr64,
2524 .zcm_gpr64,
2525 .zcz,
2526 }),
2527 };
2528 pub const carmel: CpuModel = .{
2529 .name = "carmel",
2530 .llvm_name = "carmel",
2531 .features = featureSet(&[_]Feature{
2532 .aes,
2533 .fullfp16,
2534 .sha2,
2535 .v8_2a,
2536 }),
2537 };
2538 pub const cobalt_100: CpuModel = .{
2539 .name = "cobalt_100",
2540 .llvm_name = "cobalt-100",
2541 .features = featureSet(&[_]Feature{
2542 .alu_lsl_fast,
2543 .bf16,
2544 .enable_select_opt,
2545 .ete,
2546 .fp16fml,
2547 .fpac,
2548 .fuse_adrp_add,
2549 .fuse_aes,
2550 .i8mm,
2551 .mte,
2552 .perfmon,
2553 .predictable_select_expensive,
2554 .sve_bitperm,
2555 .use_postra_scheduler,
2556 .v9a,
2557 }),
2558 };
2559 pub const cortex_a320: CpuModel = .{
2560 .name = "cortex_a320",
2561 .llvm_name = "cortex-a320",
2562 .features = featureSet(&[_]Feature{
2563 .a320,
2564 .ete,
2565 .fp16fml,
2566 .mte,
2567 .perfmon,
2568 .sve_bitperm,
2569 .v9_2a,
2570 }),
2571 };
2572 pub const cortex_a34: CpuModel = .{
2573 .name = "cortex_a34",
2574 .llvm_name = "cortex-a34",
2575 .features = featureSet(&[_]Feature{
2576 .aes,
2577 .crc,
2578 .perfmon,
2579 .sha2,
2580 .v8a,
2581 }),
2582 };
2583 pub const cortex_a35: CpuModel = .{
2584 .name = "cortex_a35",
2585 .llvm_name = "cortex-a35",
2586 .features = featureSet(&[_]Feature{
2587 .aes,
2588 .crc,
2589 .perfmon,
2590 .sha2,
2591 .v8a,
2592 }),
2593 };
2594 pub const cortex_a510: CpuModel = .{
2595 .name = "cortex_a510",
2596 .llvm_name = "cortex-a510",
2597 .features = featureSet(&[_]Feature{
2598 .bf16,
2599 .ete,
2600 .fp16fml,
2601 .fpac,
2602 .fuse_adrp_add,
2603 .fuse_aes,
2604 .i8mm,
2605 .mte,
2606 .perfmon,
2607 .sve_bitperm,
2608 .use_fixed_over_scalable_if_equal_cost,
2609 .use_postra_scheduler,
2610 .v9a,
2611 }),
2612 };
2613 pub const cortex_a520: CpuModel = .{
2614 .name = "cortex_a520",
2615 .llvm_name = "cortex-a520",
2616 .features = featureSet(&[_]Feature{
2617 .ete,
2618 .fp16fml,
2619 .fpac,
2620 .fuse_adrp_add,
2621 .fuse_aes,
2622 .mte,
2623 .perfmon,
2624 .sve_bitperm,
2625 .use_fixed_over_scalable_if_equal_cost,
2626 .use_postra_scheduler,
2627 .v9_2a,
2628 }),
2629 };
2630 pub const cortex_a520ae: CpuModel = .{
2631 .name = "cortex_a520ae",
2632 .llvm_name = "cortex-a520ae",
2633 .features = featureSet(&[_]Feature{
2634 .ete,
2635 .fp16fml,
2636 .fpac,
2637 .fuse_adrp_add,
2638 .fuse_aes,
2639 .mte,
2640 .perfmon,
2641 .sve_bitperm,
2642 .use_postra_scheduler,
2643 .v9_2a,
2644 }),
2645 };
2646 pub const cortex_a53: CpuModel = .{
2647 .name = "cortex_a53",
2648 .llvm_name = "cortex-a53",
2649 .features = featureSet(&[_]Feature{
2650 .aes,
2651 .balance_fp_ops,
2652 .crc,
2653 .fuse_adrp_add,
2654 .fuse_aes,
2655 .perfmon,
2656 .sha2,
2657 .use_postra_scheduler,
2658 .v8a,
2659 }),
2660 };
2661 pub const cortex_a55: CpuModel = .{
2662 .name = "cortex_a55",
2663 .llvm_name = "cortex-a55",
2664 .features = featureSet(&[_]Feature{
2665 .aes,
2666 .dotprod,
2667 .fullfp16,
2668 .fuse_address,
2669 .fuse_adrp_add,
2670 .fuse_aes,
2671 .perfmon,
2672 .rcpc,
2673 .sha2,
2674 .use_postra_scheduler,
2675 .v8_2a,
2676 }),
2677 };
2678 pub const cortex_a57: CpuModel = .{
2679 .name = "cortex_a57",
2680 .llvm_name = "cortex-a57",
2681 .features = featureSet(&[_]Feature{
2682 .addr_lsl_slow_14,
2683 .aes,
2684 .balance_fp_ops,
2685 .crc,
2686 .enable_select_opt,
2687 .fuse_adrp_add,
2688 .fuse_aes,
2689 .fuse_literals,
2690 .perfmon,
2691 .predictable_select_expensive,
2692 .sha2,
2693 .use_postra_scheduler,
2694 .v8a,
2695 }),
2696 };
2697 pub const cortex_a65: CpuModel = .{
2698 .name = "cortex_a65",
2699 .llvm_name = "cortex-a65",
2700 .features = featureSet(&[_]Feature{
2701 .aes,
2702 .dotprod,
2703 .enable_select_opt,
2704 .fullfp16,
2705 .fuse_address,
2706 .fuse_adrp_add,
2707 .fuse_aes,
2708 .fuse_literals,
2709 .perfmon,
2710 .predictable_select_expensive,
2711 .rcpc,
2712 .sha2,
2713 .ssbs,
2714 .v8_2a,
2715 }),
2716 };
2717 pub const cortex_a65ae: CpuModel = .{
2718 .name = "cortex_a65ae",
2719 .llvm_name = "cortex-a65ae",
2720 .features = featureSet(&[_]Feature{
2721 .aes,
2722 .dotprod,
2723 .enable_select_opt,
2724 .fullfp16,
2725 .fuse_address,
2726 .fuse_adrp_add,
2727 .fuse_aes,
2728 .fuse_literals,
2729 .perfmon,
2730 .predictable_select_expensive,
2731 .rcpc,
2732 .sha2,
2733 .ssbs,
2734 .v8_2a,
2735 }),
2736 };
2737 pub const cortex_a710: CpuModel = .{
2738 .name = "cortex_a710",
2739 .llvm_name = "cortex-a710",
2740 .features = featureSet(&[_]Feature{
2741 .alu_lsl_fast,
2742 .bf16,
2743 .cmp_bcc_fusion,
2744 .enable_select_opt,
2745 .ete,
2746 .fp16fml,
2747 .fpac,
2748 .fuse_adrp_add,
2749 .fuse_aes,
2750 .i8mm,
2751 .mte,
2752 .perfmon,
2753 .predictable_select_expensive,
2754 .sve_bitperm,
2755 .use_postra_scheduler,
2756 .v9a,
2757 }),
2758 };
2759 pub const cortex_a715: CpuModel = .{
2760 .name = "cortex_a715",
2761 .llvm_name = "cortex-a715",
2762 .features = featureSet(&[_]Feature{
2763 .alu_lsl_fast,
2764 .bf16,
2765 .cmp_bcc_fusion,
2766 .enable_select_opt,
2767 .ete,
2768 .fp16fml,
2769 .fpac,
2770 .fuse_adrp_add,
2771 .fuse_aes,
2772 .i8mm,
2773 .mte,
2774 .perfmon,
2775 .predictable_select_expensive,
2776 .spe,
2777 .sve_bitperm,
2778 .use_postra_scheduler,
2779 .v9a,
2780 }),
2781 };
2782 pub const cortex_a72: CpuModel = .{
2783 .name = "cortex_a72",
2784 .llvm_name = "cortex-a72",
2785 .features = featureSet(&[_]Feature{
2786 .addr_lsl_slow_14,
2787 .aes,
2788 .crc,
2789 .enable_select_opt,
2790 .fuse_adrp_add,
2791 .fuse_aes,
2792 .fuse_literals,
2793 .perfmon,
2794 .predictable_select_expensive,
2795 .sha2,
2796 .v8a,
2797 }),
2798 };
2799 pub const cortex_a720: CpuModel = .{
2800 .name = "cortex_a720",
2801 .llvm_name = "cortex-a720",
2802 .features = featureSet(&[_]Feature{
2803 .alu_lsl_fast,
2804 .cmp_bcc_fusion,
2805 .enable_select_opt,
2806 .ete,
2807 .fp16fml,
2808 .fpac,
2809 .fuse_adrp_add,
2810 .fuse_aes,
2811 .mte,
2812 .perfmon,
2813 .predictable_select_expensive,
2814 .spe,
2815 .sve_bitperm,
2816 .use_postra_scheduler,
2817 .v9_2a,
2818 }),
2819 };
2820 pub const cortex_a720ae: CpuModel = .{
2821 .name = "cortex_a720ae",
2822 .llvm_name = "cortex-a720ae",
2823 .features = featureSet(&[_]Feature{
2824 .alu_lsl_fast,
2825 .cmp_bcc_fusion,
2826 .enable_select_opt,
2827 .ete,
2828 .fp16fml,
2829 .fpac,
2830 .fuse_adrp_add,
2831 .fuse_aes,
2832 .mte,
2833 .perfmon,
2834 .predictable_select_expensive,
2835 .spe,
2836 .sve_bitperm,
2837 .use_postra_scheduler,
2838 .v9_2a,
2839 }),
2840 };
2841 pub const cortex_a725: CpuModel = .{
2842 .name = "cortex_a725",
2843 .llvm_name = "cortex-a725",
2844 .features = featureSet(&[_]Feature{
2845 .alu_lsl_fast,
2846 .cmp_bcc_fusion,
2847 .enable_select_opt,
2848 .ete,
2849 .fp16fml,
2850 .fpac,
2851 .fuse_adrp_add,
2852 .fuse_aes,
2853 .mte,
2854 .perfmon,
2855 .predictable_select_expensive,
2856 .spe,
2857 .sve_bitperm,
2858 .use_postra_scheduler,
2859 .v9_2a,
2860 }),
2861 };
2862 pub const cortex_a73: CpuModel = .{
2863 .name = "cortex_a73",
2864 .llvm_name = "cortex-a73",
2865 .features = featureSet(&[_]Feature{
2866 .addr_lsl_slow_14,
2867 .aes,
2868 .crc,
2869 .enable_select_opt,
2870 .fuse_adrp_add,
2871 .fuse_aes,
2872 .perfmon,
2873 .predictable_select_expensive,
2874 .sha2,
2875 .v8a,
2876 }),
2877 };
2878 pub const cortex_a75: CpuModel = .{
2879 .name = "cortex_a75",
2880 .llvm_name = "cortex-a75",
2881 .features = featureSet(&[_]Feature{
2882 .addr_lsl_slow_14,
2883 .aes,
2884 .dotprod,
2885 .enable_select_opt,
2886 .fullfp16,
2887 .fuse_adrp_add,
2888 .fuse_aes,
2889 .perfmon,
2890 .predictable_select_expensive,
2891 .rcpc,
2892 .sha2,
2893 .v8_2a,
2894 }),
2895 };
2896 pub const cortex_a76: CpuModel = .{
2897 .name = "cortex_a76",
2898 .llvm_name = "cortex-a76",
2899 .features = featureSet(&[_]Feature{
2900 .addr_lsl_slow_14,
2901 .aes,
2902 .alu_lsl_fast,
2903 .dotprod,
2904 .enable_select_opt,
2905 .fullfp16,
2906 .fuse_adrp_add,
2907 .fuse_aes,
2908 .perfmon,
2909 .predictable_select_expensive,
2910 .rcpc,
2911 .sha2,
2912 .ssbs,
2913 .v8_2a,
2914 }),
2915 };
2916 pub const cortex_a76ae: CpuModel = .{
2917 .name = "cortex_a76ae",
2918 .llvm_name = "cortex-a76ae",
2919 .features = featureSet(&[_]Feature{
2920 .addr_lsl_slow_14,
2921 .aes,
2922 .alu_lsl_fast,
2923 .dotprod,
2924 .enable_select_opt,
2925 .fullfp16,
2926 .fuse_adrp_add,
2927 .fuse_aes,
2928 .perfmon,
2929 .predictable_select_expensive,
2930 .rcpc,
2931 .sha2,
2932 .ssbs,
2933 .v8_2a,
2934 }),
2935 };
2936 pub const cortex_a77: CpuModel = .{
2937 .name = "cortex_a77",
2938 .llvm_name = "cortex-a77",
2939 .features = featureSet(&[_]Feature{
2940 .addr_lsl_slow_14,
2941 .aes,
2942 .alu_lsl_fast,
2943 .cmp_bcc_fusion,
2944 .dotprod,
2945 .enable_select_opt,
2946 .fullfp16,
2947 .fuse_adrp_add,
2948 .fuse_aes,
2949 .perfmon,
2950 .predictable_select_expensive,
2951 .rcpc,
2952 .sha2,
2953 .ssbs,
2954 .v8_2a,
2955 }),
2956 };
2957 pub const cortex_a78: CpuModel = .{
2958 .name = "cortex_a78",
2959 .llvm_name = "cortex-a78",
2960 .features = featureSet(&[_]Feature{
2961 .addr_lsl_slow_14,
2962 .aes,
2963 .alu_lsl_fast,
2964 .cmp_bcc_fusion,
2965 .dotprod,
2966 .enable_select_opt,
2967 .fullfp16,
2968 .fuse_adrp_add,
2969 .fuse_aes,
2970 .perfmon,
2971 .predictable_select_expensive,
2972 .rcpc,
2973 .sha2,
2974 .spe,
2975 .ssbs,
2976 .use_postra_scheduler,
2977 .v8_2a,
2978 }),
2979 };
2980 pub const cortex_a78ae: CpuModel = .{
2981 .name = "cortex_a78ae",
2982 .llvm_name = "cortex-a78ae",
2983 .features = featureSet(&[_]Feature{
2984 .addr_lsl_slow_14,
2985 .aes,
2986 .alu_lsl_fast,
2987 .cmp_bcc_fusion,
2988 .dotprod,
2989 .enable_select_opt,
2990 .fullfp16,
2991 .fuse_adrp_add,
2992 .fuse_aes,
2993 .perfmon,
2994 .predictable_select_expensive,
2995 .rcpc,
2996 .sha2,
2997 .spe,
2998 .ssbs,
2999 .use_postra_scheduler,
3000 .v8_2a,
3001 }),
3002 };
3003 pub const cortex_a78c: CpuModel = .{
3004 .name = "cortex_a78c",
3005 .llvm_name = "cortex-a78c",
3006 .features = featureSet(&[_]Feature{
3007 .addr_lsl_slow_14,
3008 .aes,
3009 .alu_lsl_fast,
3010 .cmp_bcc_fusion,
3011 .dotprod,
3012 .enable_select_opt,
3013 .flagm,
3014 .fullfp16,
3015 .fuse_adrp_add,
3016 .fuse_aes,
3017 .pauth,
3018 .perfmon,
3019 .predictable_select_expensive,
3020 .rcpc,
3021 .sha2,
3022 .spe,
3023 .ssbs,
3024 .use_postra_scheduler,
3025 .v8_2a,
3026 }),
3027 };
3028 pub const cortex_r82: CpuModel = .{
3029 .name = "cortex_r82",
3030 .llvm_name = "cortex-r82",
3031 .features = featureSet(&[_]Feature{
3032 .ccdp,
3033 .fpac,
3034 .perfmon,
3035 .predres,
3036 .use_postra_scheduler,
3037 .v8r,
3038 }),
3039 };
3040 pub const cortex_r82ae: CpuModel = .{
3041 .name = "cortex_r82ae",
3042 .llvm_name = "cortex-r82ae",
3043 .features = featureSet(&[_]Feature{
3044 .ccdp,
3045 .fpac,
3046 .perfmon,
3047 .predres,
3048 .use_postra_scheduler,
3049 .v8r,
3050 }),
3051 };
3052 pub const cortex_x1: CpuModel = .{
3053 .name = "cortex_x1",
3054 .llvm_name = "cortex-x1",
3055 .features = featureSet(&[_]Feature{
3056 .addr_lsl_slow_14,
3057 .aes,
3058 .alu_lsl_fast,
3059 .cmp_bcc_fusion,
3060 .dotprod,
3061 .enable_select_opt,
3062 .fullfp16,
3063 .fuse_adrp_add,
3064 .fuse_aes,
3065 .perfmon,
3066 .predictable_select_expensive,
3067 .rcpc,
3068 .sha2,
3069 .spe,
3070 .ssbs,
3071 .use_postra_scheduler,
3072 .v8_2a,
3073 }),
3074 };
3075 pub const cortex_x1c: CpuModel = .{
3076 .name = "cortex_x1c",
3077 .llvm_name = "cortex-x1c",
3078 .features = featureSet(&[_]Feature{
3079 .addr_lsl_slow_14,
3080 .aes,
3081 .alu_lsl_fast,
3082 .cmp_bcc_fusion,
3083 .dotprod,
3084 .enable_select_opt,
3085 .flagm,
3086 .fullfp16,
3087 .fuse_adrp_add,
3088 .fuse_aes,
3089 .lse2,
3090 .pauth,
3091 .perfmon,
3092 .predictable_select_expensive,
3093 .rcpc_immo,
3094 .sha2,
3095 .spe,
3096 .ssbs,
3097 .use_postra_scheduler,
3098 .v8_2a,
3099 }),
3100 };
3101 pub const cortex_x2: CpuModel = .{
3102 .name = "cortex_x2",
3103 .llvm_name = "cortex-x2",
3104 .features = featureSet(&[_]Feature{
3105 .alu_lsl_fast,
3106 .bf16,
3107 .cmp_bcc_fusion,
3108 .enable_select_opt,
3109 .ete,
3110 .fp16fml,
3111 .fpac,
3112 .fuse_adrp_add,
3113 .fuse_aes,
3114 .i8mm,
3115 .mte,
3116 .perfmon,
3117 .predictable_select_expensive,
3118 .sve_bitperm,
3119 .use_fixed_over_scalable_if_equal_cost,
3120 .use_postra_scheduler,
3121 .v9a,
3122 }),
3123 };
3124 pub const cortex_x3: CpuModel = .{
3125 .name = "cortex_x3",
3126 .llvm_name = "cortex-x3",
3127 .features = featureSet(&[_]Feature{
3128 .alu_lsl_fast,
3129 .avoid_ldapur,
3130 .bf16,
3131 .enable_select_opt,
3132 .ete,
3133 .fp16fml,
3134 .fpac,
3135 .fuse_adrp_add,
3136 .fuse_aes,
3137 .i8mm,
3138 .mte,
3139 .perfmon,
3140 .predictable_select_expensive,
3141 .spe,
3142 .sve_bitperm,
3143 .use_fixed_over_scalable_if_equal_cost,
3144 .use_postra_scheduler,
3145 .v9a,
3146 }),
3147 };
3148 pub const cortex_x4: CpuModel = .{
3149 .name = "cortex_x4",
3150 .llvm_name = "cortex-x4",
3151 .features = featureSet(&[_]Feature{
3152 .alu_lsl_fast,
3153 .avoid_ldapur,
3154 .enable_select_opt,
3155 .ete,
3156 .fp16fml,
3157 .fpac,
3158 .fuse_adrp_add,
3159 .fuse_aes,
3160 .mte,
3161 .perfmon,
3162 .predictable_select_expensive,
3163 .spe,
3164 .sve_bitperm,
3165 .use_fixed_over_scalable_if_equal_cost,
3166 .use_postra_scheduler,
3167 .v9_2a,
3168 }),
3169 };
3170 pub const cortex_x925: CpuModel = .{
3171 .name = "cortex_x925",
3172 .llvm_name = "cortex-x925",
3173 .features = featureSet(&[_]Feature{
3174 .alu_lsl_fast,
3175 .avoid_ldapur,
3176 .enable_select_opt,
3177 .ete,
3178 .fp16fml,
3179 .fpac,
3180 .fuse_adrp_add,
3181 .fuse_aes,
3182 .mte,
3183 .perfmon,
3184 .predictable_select_expensive,
3185 .spe,
3186 .sve_bitperm,
3187 .use_fixed_over_scalable_if_equal_cost,
3188 .use_postra_scheduler,
3189 .v9_2a,
3190 }),
3191 };
3192 pub const cyclone: CpuModel = .{
3193 .name = "cyclone",
3194 .llvm_name = "cyclone",
3195 .features = featureSet(&[_]Feature{
3196 .aes,
3197 .alternate_sextload_cvt_f32_pattern,
3198 .arith_bcc_fusion,
3199 .arith_cbz_fusion,
3200 .disable_latency_sched_heuristic,
3201 .fuse_aes,
3202 .fuse_crypto_eor,
3203 .perfmon,
3204 .sha2,
3205 .store_pair_suppress,
3206 .v8a,
3207 .zcm_fpr64,
3208 .zcm_gpr64,
3209 .zcz,
3210 .zcz_fp_workaround,
3211 }),
3212 };
3213 pub const emag: CpuModel = .{
3214 .name = "emag",
3215 .llvm_name = null,
3216 .features = featureSet(&[_]Feature{
3217 .crc,
3218 .crypto,
3219 .perfmon,
3220 .v8a,
3221 }),
3222 };
3223 pub const exynos_m1: CpuModel = .{
3224 .name = "exynos_m1",
3225 .llvm_name = null,
3226 .features = featureSet(&[_]Feature{
3227 .crc,
3228 .crypto,
3229 .exynos_cheap_as_move,
3230 .force_32bit_jump_tables,
3231 .fuse_aes,
3232 .perfmon,
3233 .slow_misaligned_128store,
3234 .slow_paired_128,
3235 .use_postra_scheduler,
3236 .use_reciprocal_square_root,
3237 .v8a,
3238 }),
3239 };
3240 pub const exynos_m2: CpuModel = .{
3241 .name = "exynos_m2",
3242 .llvm_name = null,
3243 .features = featureSet(&[_]Feature{
3244 .crc,
3245 .crypto,
3246 .exynos_cheap_as_move,
3247 .force_32bit_jump_tables,
3248 .fuse_aes,
3249 .perfmon,
3250 .slow_misaligned_128store,
3251 .slow_paired_128,
3252 .use_postra_scheduler,
3253 .v8a,
3254 }),
3255 };
3256 pub const exynos_m3: CpuModel = .{
3257 .name = "exynos_m3",
3258 .llvm_name = "exynos-m3",
3259 .features = featureSet(&[_]Feature{
3260 .aes,
3261 .alu_lsl_fast,
3262 .crc,
3263 .exynos_cheap_as_move,
3264 .force_32bit_jump_tables,
3265 .fuse_address,
3266 .fuse_adrp_add,
3267 .fuse_aes,
3268 .fuse_csel,
3269 .fuse_literals,
3270 .perfmon,
3271 .predictable_select_expensive,
3272 .sha2,
3273 .store_pair_suppress,
3274 .use_postra_scheduler,
3275 .v8a,
3276 }),
3277 };
3278 pub const exynos_m4: CpuModel = .{
3279 .name = "exynos_m4",
3280 .llvm_name = "exynos-m4",
3281 .features = featureSet(&[_]Feature{
3282 .aes,
3283 .alu_lsl_fast,
3284 .arith_bcc_fusion,
3285 .arith_cbz_fusion,
3286 .dotprod,
3287 .exynos_cheap_as_move,
3288 .force_32bit_jump_tables,
3289 .fullfp16,
3290 .fuse_address,
3291 .fuse_adrp_add,
3292 .fuse_aes,
3293 .fuse_arith_logic,
3294 .fuse_csel,
3295 .fuse_literals,
3296 .perfmon,
3297 .sha2,
3298 .store_pair_suppress,
3299 .use_postra_scheduler,
3300 .v8_2a,
3301 .zcz,
3302 }),
3303 };
3304 pub const exynos_m5: CpuModel = .{
3305 .name = "exynos_m5",
3306 .llvm_name = "exynos-m5",
3307 .features = featureSet(&[_]Feature{
3308 .aes,
3309 .alu_lsl_fast,
3310 .arith_bcc_fusion,
3311 .arith_cbz_fusion,
3312 .dotprod,
3313 .exynos_cheap_as_move,
3314 .force_32bit_jump_tables,
3315 .fullfp16,
3316 .fuse_address,
3317 .fuse_adrp_add,
3318 .fuse_aes,
3319 .fuse_arith_logic,
3320 .fuse_csel,
3321 .fuse_literals,
3322 .perfmon,
3323 .sha2,
3324 .store_pair_suppress,
3325 .use_postra_scheduler,
3326 .v8_2a,
3327 .zcz,
3328 }),
3329 };
3330 pub const falkor: CpuModel = .{
3331 .name = "falkor",
3332 .llvm_name = "falkor",
3333 .features = featureSet(&[_]Feature{
3334 .aes,
3335 .alu_lsl_fast,
3336 .crc,
3337 .perfmon,
3338 .predictable_select_expensive,
3339 .rdm,
3340 .sha2,
3341 .slow_strqro_store,
3342 .store_pair_suppress,
3343 .use_postra_scheduler,
3344 .v8a,
3345 .zcz,
3346 }),
3347 };
3348 pub const fujitsu_monaka: CpuModel = .{
3349 .name = "fujitsu_monaka",
3350 .llvm_name = "fujitsu-monaka",
3351 .features = featureSet(&[_]Feature{
3352 .clrbhb,
3353 .ete,
3354 .faminmax,
3355 .fp16fml,
3356 .fp8dot2,
3357 .fp8dot4,
3358 .fp8fma,
3359 .fpac,
3360 .fujitsu_monaka,
3361 .ls64,
3362 .lut,
3363 .perfmon,
3364 .rand,
3365 .specres2,
3366 .sve_aes,
3367 .sve_bitperm,
3368 .sve_sha3,
3369 .sve_sm4,
3370 .v9_3a,
3371 }),
3372 };
3373 pub const gb10: CpuModel = .{
3374 .name = "gb10",
3375 .llvm_name = "gb10",
3376 .features = featureSet(&[_]Feature{
3377 .alu_lsl_fast,
3378 .avoid_ldapur,
3379 .enable_select_opt,
3380 .ete,
3381 .fp16fml,
3382 .fpac,
3383 .fuse_adrp_add,
3384 .fuse_aes,
3385 .mte,
3386 .perfmon,
3387 .predictable_select_expensive,
3388 .spe,
3389 .sve_aes,
3390 .sve_bitperm,
3391 .sve_sha3,
3392 .sve_sm4,
3393 .use_fixed_over_scalable_if_equal_cost,
3394 .use_postra_scheduler,
3395 .v9_2a,
3396 }),
3397 };
3398 pub const generic: CpuModel = .{
3399 .name = "generic",
3400 .llvm_name = "generic",
3401 .features = featureSet(&[_]Feature{
3402 .enable_select_opt,
3403 .ete,
3404 .fuse_adrp_add,
3405 .fuse_aes,
3406 .neon,
3407 .use_postra_scheduler,
3408 }),
3409 };
3410 pub const grace: CpuModel = .{
3411 .name = "grace",
3412 .llvm_name = "grace",
3413 .features = featureSet(&[_]Feature{
3414 .alu_lsl_fast,
3415 .avoid_ldapur,
3416 .bf16,
3417 .cmp_bcc_fusion,
3418 .disable_latency_sched_heuristic,
3419 .enable_select_opt,
3420 .ete,
3421 .fp16fml,
3422 .fpac,
3423 .fuse_adrp_add,
3424 .fuse_aes,
3425 .i8mm,
3426 .mte,
3427 .perfmon,
3428 .predictable_select_expensive,
3429 .rand,
3430 .spe,
3431 .sve_aes,
3432 .sve_bitperm,
3433 .sve_sha3,
3434 .sve_sm4,
3435 .use_fixed_over_scalable_if_equal_cost,
3436 .use_postra_scheduler,
3437 .v9a,
3438 }),
3439 };
3440 pub const kryo: CpuModel = .{
3441 .name = "kryo",
3442 .llvm_name = "kryo",
3443 .features = featureSet(&[_]Feature{
3444 .aes,
3445 .alu_lsl_fast,
3446 .crc,
3447 .perfmon,
3448 .predictable_select_expensive,
3449 .sha2,
3450 .store_pair_suppress,
3451 .use_postra_scheduler,
3452 .v8a,
3453 .zcz,
3454 }),
3455 };
3456 pub const neoverse_512tvb: CpuModel = .{
3457 .name = "neoverse_512tvb",
3458 .llvm_name = "neoverse-512tvb",
3459 .features = featureSet(&[_]Feature{
3460 .aes,
3461 .alu_lsl_fast,
3462 .bf16,
3463 .ccdp,
3464 .enable_select_opt,
3465 .fp16fml,
3466 .fpac,
3467 .fuse_adrp_add,
3468 .fuse_aes,
3469 .i8mm,
3470 .perfmon,
3471 .predictable_select_expensive,
3472 .rand,
3473 .sha3,
3474 .sm4,
3475 .spe,
3476 .ssbs,
3477 .sve,
3478 .use_postra_scheduler,
3479 .v8_4a,
3480 }),
3481 };
3482 pub const neoverse_e1: CpuModel = .{
3483 .name = "neoverse_e1",
3484 .llvm_name = "neoverse-e1",
3485 .features = featureSet(&[_]Feature{
3486 .aes,
3487 .dotprod,
3488 .fullfp16,
3489 .fuse_adrp_add,
3490 .fuse_aes,
3491 .perfmon,
3492 .rcpc,
3493 .sha2,
3494 .ssbs,
3495 .use_postra_scheduler,
3496 .v8_2a,
3497 }),
3498 };
3499 pub const neoverse_n1: CpuModel = .{
3500 .name = "neoverse_n1",
3501 .llvm_name = "neoverse-n1",
3502 .features = featureSet(&[_]Feature{
3503 .addr_lsl_slow_14,
3504 .aes,
3505 .alu_lsl_fast,
3506 .dotprod,
3507 .enable_select_opt,
3508 .fullfp16,
3509 .fuse_adrp_add,
3510 .fuse_aes,
3511 .perfmon,
3512 .predictable_select_expensive,
3513 .rcpc,
3514 .sha2,
3515 .spe,
3516 .ssbs,
3517 .use_postra_scheduler,
3518 .v8_2a,
3519 }),
3520 };
3521 pub const neoverse_n2: CpuModel = .{
3522 .name = "neoverse_n2",
3523 .llvm_name = "neoverse-n2",
3524 .features = featureSet(&[_]Feature{
3525 .alu_lsl_fast,
3526 .bf16,
3527 .enable_select_opt,
3528 .ete,
3529 .fp16fml,
3530 .fpac,
3531 .fuse_adrp_add,
3532 .fuse_aes,
3533 .i8mm,
3534 .mte,
3535 .perfmon,
3536 .predictable_select_expensive,
3537 .sve_bitperm,
3538 .use_postra_scheduler,
3539 .v9a,
3540 }),
3541 };
3542 pub const neoverse_n3: CpuModel = .{
3543 .name = "neoverse_n3",
3544 .llvm_name = "neoverse-n3",
3545 .features = featureSet(&[_]Feature{
3546 .alu_lsl_fast,
3547 .enable_select_opt,
3548 .ete,
3549 .fp16fml,
3550 .fpac,
3551 .fuse_adrp_add,
3552 .fuse_aes,
3553 .mte,
3554 .perfmon,
3555 .predictable_select_expensive,
3556 .rand,
3557 .spe,
3558 .sve_bitperm,
3559 .use_postra_scheduler,
3560 .v9_2a,
3561 }),
3562 };
3563 pub const neoverse_v1: CpuModel = .{
3564 .name = "neoverse_v1",
3565 .llvm_name = "neoverse-v1",
3566 .features = featureSet(&[_]Feature{
3567 .addr_lsl_slow_14,
3568 .aes,
3569 .alu_lsl_fast,
3570 .bf16,
3571 .ccdp,
3572 .enable_select_opt,
3573 .fp16fml,
3574 .fuse_adrp_add,
3575 .fuse_aes,
3576 .i8mm,
3577 .no_sve_fp_ld1r,
3578 .perfmon,
3579 .predictable_select_expensive,
3580 .rand,
3581 .sha3,
3582 .sm4,
3583 .spe,
3584 .ssbs,
3585 .sve,
3586 .use_postra_scheduler,
3587 .v8_4a,
3588 }),
3589 };
3590 pub const neoverse_v2: CpuModel = .{
3591 .name = "neoverse_v2",
3592 .llvm_name = "neoverse-v2",
3593 .features = featureSet(&[_]Feature{
3594 .alu_lsl_fast,
3595 .avoid_ldapur,
3596 .bf16,
3597 .cmp_bcc_fusion,
3598 .disable_latency_sched_heuristic,
3599 .enable_select_opt,
3600 .ete,
3601 .fp16fml,
3602 .fpac,
3603 .fuse_adrp_add,
3604 .fuse_aes,
3605 .i8mm,
3606 .mte,
3607 .perfmon,
3608 .predictable_select_expensive,
3609 .rand,
3610 .spe,
3611 .sve_bitperm,
3612 .use_fixed_over_scalable_if_equal_cost,
3613 .use_postra_scheduler,
3614 .v9a,
3615 }),
3616 };
3617 pub const neoverse_v3: CpuModel = .{
3618 .name = "neoverse_v3",
3619 .llvm_name = "neoverse-v3",
3620 .features = featureSet(&[_]Feature{
3621 .alu_lsl_fast,
3622 .avoid_ldapur,
3623 .brbe,
3624 .enable_select_opt,
3625 .ete,
3626 .fp16fml,
3627 .fpac,
3628 .fuse_adrp_add,
3629 .fuse_aes,
3630 .ls64,
3631 .mte,
3632 .perfmon,
3633 .predictable_select_expensive,
3634 .rand,
3635 .spe,
3636 .sve_bitperm,
3637 .use_postra_scheduler,
3638 .v9_2a,
3639 }),
3640 };
3641 pub const neoverse_v3ae: CpuModel = .{
3642 .name = "neoverse_v3ae",
3643 .llvm_name = "neoverse-v3ae",
3644 .features = featureSet(&[_]Feature{
3645 .alu_lsl_fast,
3646 .avoid_ldapur,
3647 .brbe,
3648 .enable_select_opt,
3649 .ete,
3650 .fp16fml,
3651 .fpac,
3652 .fuse_adrp_add,
3653 .fuse_aes,
3654 .ls64,
3655 .mte,
3656 .perfmon,
3657 .predictable_select_expensive,
3658 .rand,
3659 .spe,
3660 .sve_bitperm,
3661 .use_postra_scheduler,
3662 .v9_2a,
3663 }),
3664 };
3665 pub const olympus: CpuModel = .{
3666 .name = "olympus",
3667 .llvm_name = "olympus",
3668 .features = featureSet(&[_]Feature{
3669 .brbe,
3670 .chk,
3671 .ete,
3672 .faminmax,
3673 .fp16fml,
3674 .fp8dot2,
3675 .fp8dot4,
3676 .fp8fma,
3677 .fpac,
3678 .ls64,
3679 .lut,
3680 .mte,
3681 .olympus,
3682 .perfmon,
3683 .rand,
3684 .spe,
3685 .sve_aes,
3686 .sve_bitperm,
3687 .sve_sha3,
3688 .sve_sm4,
3689 .v9_2a,
3690 }),
3691 };
3692 pub const oryon_1: CpuModel = .{
3693 .name = "oryon_1",
3694 .llvm_name = "oryon-1",
3695 .features = featureSet(&[_]Feature{
3696 .aes,
3697 .enable_select_opt,
3698 .fp16fml,
3699 .fuse_address,
3700 .fuse_adrp_add,
3701 .fuse_aes,
3702 .fuse_crypto_eor,
3703 .perfmon,
3704 .rand,
3705 .sha3,
3706 .sm4,
3707 .spe,
3708 .use_postra_scheduler,
3709 .v8_6a,
3710 }),
3711 };
3712 pub const saphira: CpuModel = .{
3713 .name = "saphira",
3714 .llvm_name = "saphira",
3715 .features = featureSet(&[_]Feature{
3716 .aes,
3717 .alu_lsl_fast,
3718 .perfmon,
3719 .predictable_select_expensive,
3720 .sha2,
3721 .spe,
3722 .store_pair_suppress,
3723 .use_postra_scheduler,
3724 .v8_4a,
3725 .zcz,
3726 }),
3727 };
3728 pub const thunderx: CpuModel = .{
3729 .name = "thunderx",
3730 .llvm_name = "thunderx",
3731 .features = featureSet(&[_]Feature{
3732 .aes,
3733 .crc,
3734 .perfmon,
3735 .predictable_select_expensive,
3736 .sha2,
3737 .store_pair_suppress,
3738 .use_postra_scheduler,
3739 .v8a,
3740 }),
3741 };
3742 pub const thunderx2t99: CpuModel = .{
3743 .name = "thunderx2t99",
3744 .llvm_name = "thunderx2t99",
3745 .features = featureSet(&[_]Feature{
3746 .aes,
3747 .aggressive_fma,
3748 .arith_bcc_fusion,
3749 .predictable_select_expensive,
3750 .sha2,
3751 .store_pair_suppress,
3752 .use_postra_scheduler,
3753 .v8_1a,
3754 }),
3755 };
3756 pub const thunderx3t110: CpuModel = .{
3757 .name = "thunderx3t110",
3758 .llvm_name = "thunderx3t110",
3759 .features = featureSet(&[_]Feature{
3760 .aes,
3761 .aggressive_fma,
3762 .arith_bcc_fusion,
3763 .balance_fp_ops,
3764 .perfmon,
3765 .predictable_select_expensive,
3766 .sha2,
3767 .store_pair_suppress,
3768 .strict_align,
3769 .use_postra_scheduler,
3770 .v8_3a,
3771 }),
3772 };
3773 pub const thunderxt81: CpuModel = .{
3774 .name = "thunderxt81",
3775 .llvm_name = "thunderxt81",
3776 .features = featureSet(&[_]Feature{
3777 .aes,
3778 .crc,
3779 .perfmon,
3780 .predictable_select_expensive,
3781 .sha2,
3782 .store_pair_suppress,
3783 .use_postra_scheduler,
3784 .v8a,
3785 }),
3786 };
3787 pub const thunderxt83: CpuModel = .{
3788 .name = "thunderxt83",
3789 .llvm_name = "thunderxt83",
3790 .features = featureSet(&[_]Feature{
3791 .aes,
3792 .crc,
3793 .perfmon,
3794 .predictable_select_expensive,
3795 .sha2,
3796 .store_pair_suppress,
3797 .use_postra_scheduler,
3798 .v8a,
3799 }),
3800 };
3801 pub const thunderxt88: CpuModel = .{
3802 .name = "thunderxt88",
3803 .llvm_name = "thunderxt88",
3804 .features = featureSet(&[_]Feature{
3805 .aes,
3806 .crc,
3807 .perfmon,
3808 .predictable_select_expensive,
3809 .sha2,
3810 .store_pair_suppress,
3811 .use_postra_scheduler,
3812 .v8a,
3813 }),
3814 };
3815 pub const tsv110: CpuModel = .{
3816 .name = "tsv110",
3817 .llvm_name = "tsv110",
3818 .features = featureSet(&[_]Feature{
3819 .aes,
3820 .complxnum,
3821 .dotprod,
3822 .fp16fml,
3823 .fuse_aes,
3824 .jsconv,
3825 .perfmon,
3826 .sha2,
3827 .spe,
3828 .store_pair_suppress,
3829 .use_postra_scheduler,
3830 .v8_2a,
3831 }),
3832 };
3833 pub const xgene1: CpuModel = .{
3834 .name = "xgene1",
3835 .llvm_name = null,
3836 .features = featureSet(&[_]Feature{
3837 .perfmon,
3838 .v8a,
3839 }),
3840 };
3841};