master
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) Peter Wemm <peter@netplex.com.au>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#ifdef __i386__
30#include <i386/pcpu.h>
31#else /* !__i386__ */
32
33#ifndef _MACHINE_PCPU_H_
34#define _MACHINE_PCPU_H_
35
36#include <machine/_pmap.h>
37#include <machine/segments.h>
38#include <machine/tss.h>
39
40#define PC_PTI_STACK_SZ 16
41
42struct monitorbuf {
43 int idle_state; /* Used by cpu_idle_mwait. */
44 int stop_state; /* Used by cpustop_handler. */
45 char padding[128 - (2 * sizeof(int))];
46};
47_Static_assert(sizeof(struct monitorbuf) == 128, "2x cache line");
48
49/*
50 * The SMP parts are setup in pmap.c and locore.s for the BSP, and
51 * mp_machdep.c sets up the data for the AP's to "see" when they awake.
52 * The reason for doing it via a struct is so that an array of pointers
53 * to each CPU's data can be set up for things like "check curproc on all
54 * other processors"
55 */
56#define PCPU_MD_FIELDS \
57 struct monitorbuf pc_monitorbuf __aligned(128); /* cache line */\
58 struct pcpu *pc_prvspace; /* Self-reference */ \
59 struct pmap *pc_curpmap; \
60 struct amd64tss *pc_tssp; /* TSS segment active on CPU */ \
61 void *pc_pad0; \
62 uint64_t pc_kcr3; \
63 uint64_t pc_ucr3; \
64 uint64_t pc_saved_ucr3; \
65 register_t pc_rsp0; \
66 register_t pc_scratch_rsp; /* User %rsp in syscall */ \
67 register_t pc_scratch_rax; \
68 u_int pc_apic_id; \
69 u_int pc_acpi_id; /* ACPI CPU id */ \
70 /* Pointer to the CPU %fs descriptor */ \
71 struct user_segment_descriptor *pc_fs32p; \
72 /* Pointer to the CPU %gs descriptor */ \
73 struct user_segment_descriptor *pc_gs32p; \
74 /* Pointer to the CPU LDT descriptor */ \
75 struct system_segment_descriptor *pc_ldt; \
76 /* Pointer to the CPU TSS descriptor */ \
77 struct system_segment_descriptor *pc_tss; \
78 u_int pc_cmci_mask; /* MCx banks for CMCI */ \
79 uint64_t pc_dbreg[16]; /* ddb debugging regs */ \
80 uint64_t pc_pti_stack[PC_PTI_STACK_SZ]; \
81 register_t pc_pti_rsp0; \
82 int pc_dbreg_cmd; /* ddb debugging reg cmd */ \
83 u_int pc_vcpu_id; /* Xen vCPU ID */ \
84 uint32_t pc_pcid_next; \
85 uint32_t pc_pcid_gen; \
86 uint32_t pc_unused; \
87 uint32_t pc_ibpb_set; \
88 void *pc_mds_buf; \
89 void *pc_mds_buf64; \
90 uint32_t pc_pad[4]; \
91 uint8_t pc_mds_tmp[64]; \
92 u_int pc_ipi_bitmap; \
93 struct amd64tss pc_common_tss; \
94 struct user_segment_descriptor pc_gdt[NGDT]; \
95 void *pc_smp_tlb_pmap; \
96 uint64_t pc_smp_tlb_addr1; \
97 uint64_t pc_smp_tlb_addr2; \
98 uint32_t pc_smp_tlb_gen; \
99 u_int pc_smp_tlb_op; \
100 uint64_t pc_ucr3_load_mask; \
101 u_int pc_small_core; \
102 u_int pc_pcid_invlpg_workaround; \
103 struct pmap_pcid pc_kpmap_store; \
104 char __pad[2900] /* pad to UMA_PCPU_ALLOC_SIZE */
105
106#define PC_DBREG_CMD_NONE 0
107#define PC_DBREG_CMD_LOAD 1
108
109#ifdef _KERNEL
110
111#define MONITOR_STOPSTATE_RUNNING 0
112#define MONITOR_STOPSTATE_STOPPED 1
113
114/*
115 * Evaluates to the type of the per-cpu variable name.
116 */
117#define __pcpu_type(name) \
118 __typeof(((struct pcpu *)0)->name)
119
120#ifdef __SEG_GS
121#define get_pcpu() __extension__ ({ \
122 static struct pcpu __seg_gs *__pc = 0; \
123 \
124 __pc->pc_prvspace; \
125})
126
127/*
128 * Evaluates to the address of the per-cpu variable name.
129 */
130#define __PCPU_PTR(name) __extension__ ({ \
131 struct pcpu *__pc = get_pcpu(); \
132 \
133 &__pc->name; \
134})
135
136/*
137 * Evaluates to the value of the per-cpu variable name.
138 */
139#define __PCPU_GET(name) __extension__ ({ \
140 static struct pcpu __seg_gs *__pc = 0; \
141 \
142 __pc->name; \
143})
144
145/*
146 * Adds the value to the per-cpu counter name. The implementation
147 * must be atomic with respect to interrupts.
148 */
149#define __PCPU_ADD(name, val) do { \
150 static struct pcpu __seg_gs *__pc = 0; \
151 __pcpu_type(name) __val; \
152 \
153 __val = (val); \
154 if (sizeof(__val) == 1 || sizeof(__val) == 2 || \
155 sizeof(__val) == 4 || sizeof(__val) == 8) { \
156 __pc->name += __val; \
157 } else \
158 *__PCPU_PTR(name) += __val; \
159} while (0)
160
161/*
162 * Sets the value of the per-cpu variable name to value val.
163 */
164#define __PCPU_SET(name, val) do { \
165 static struct pcpu __seg_gs *__pc = 0; \
166 __pcpu_type(name) __val; \
167 \
168 __val = (val); \
169 if (sizeof(__val) == 1 || sizeof(__val) == 2 || \
170 sizeof(__val) == 4 || sizeof(__val) == 8) { \
171 __pc->name = __val; \
172 } else \
173 *__PCPU_PTR(name) = __val; \
174} while (0)
175#else /* !__SEG_GS */
176/*
177 * Evaluates to the byte offset of the per-cpu variable name.
178 */
179#define __pcpu_offset(name) \
180 __offsetof(struct pcpu, name)
181
182/*
183 * Evaluates to the address of the per-cpu variable name.
184 */
185#define __PCPU_PTR(name) __extension__ ({ \
186 __pcpu_type(name) *__p; \
187 \
188 __asm __volatile("movq %%gs:%1,%0; addq %2,%0" \
189 : "=r" (__p) \
190 : "m" (*(struct pcpu *)(__pcpu_offset(pc_prvspace))), \
191 "i" (__pcpu_offset(name))); \
192 \
193 __p; \
194})
195
196/*
197 * Evaluates to the value of the per-cpu variable name.
198 */
199#define __PCPU_GET(name) __extension__ ({ \
200 __pcpu_type(name) __res; \
201 struct __s { \
202 u_char __b[MIN(sizeof(__pcpu_type(name)), 8)]; \
203 } __s; \
204 \
205 if (sizeof(__res) == 1 || sizeof(__res) == 2 || \
206 sizeof(__res) == 4 || sizeof(__res) == 8) { \
207 __asm __volatile("mov %%gs:%1,%0" \
208 : "=r" (__s) \
209 : "m" (*(struct __s *)(__pcpu_offset(name)))); \
210 *(struct __s *)(void *)&__res = __s; \
211 } else { \
212 __res = *__PCPU_PTR(name); \
213 } \
214 __res; \
215})
216
217/*
218 * Adds the value to the per-cpu counter name. The implementation
219 * must be atomic with respect to interrupts.
220 */
221#define __PCPU_ADD(name, val) do { \
222 __pcpu_type(name) __val; \
223 struct __s { \
224 u_char __b[MIN(sizeof(__pcpu_type(name)), 8)]; \
225 } __s; \
226 \
227 __val = (val); \
228 if (sizeof(__val) == 1 || sizeof(__val) == 2 || \
229 sizeof(__val) == 4 || sizeof(__val) == 8) { \
230 __s = *(struct __s *)(void *)&__val; \
231 __asm __volatile("add %1,%%gs:%0" \
232 : "=m" (*(struct __s *)(__pcpu_offset(name))) \
233 : "r" (__s)); \
234 } else \
235 *__PCPU_PTR(name) += __val; \
236} while (0)
237
238/*
239 * Sets the value of the per-cpu variable name to value val.
240 */
241#define __PCPU_SET(name, val) { \
242 __pcpu_type(name) __val; \
243 struct __s { \
244 u_char __b[MIN(sizeof(__pcpu_type(name)), 8)]; \
245 } __s; \
246 \
247 __val = (val); \
248 if (sizeof(__val) == 1 || sizeof(__val) == 2 || \
249 sizeof(__val) == 4 || sizeof(__val) == 8) { \
250 __s = *(struct __s *)(void *)&__val; \
251 __asm __volatile("mov %1,%%gs:%0" \
252 : "=m" (*(struct __s *)(__pcpu_offset(name))) \
253 : "r" (__s)); \
254 } else { \
255 *__PCPU_PTR(name) = __val; \
256 } \
257}
258
259#define get_pcpu() __extension__ ({ \
260 struct pcpu *__pc; \
261 \
262 __asm __volatile("movq %%gs:%1,%0" \
263 : "=r" (__pc) \
264 : "m" (*(struct pcpu *)(__pcpu_offset(pc_prvspace)))); \
265 __pc; \
266})
267#endif /* !__SEG_GS */
268
269#define PCPU_GET(member) __PCPU_GET(pc_ ## member)
270#define PCPU_ADD(member, val) __PCPU_ADD(pc_ ## member, val)
271#define PCPU_PTR(member) __PCPU_PTR(pc_ ## member)
272#define PCPU_SET(member, val) __PCPU_SET(pc_ ## member, val)
273
274#define IS_BSP() (PCPU_GET(cpuid) == 0)
275
276#define zpcpu_offset_cpu(cpu) ((uintptr_t)&__pcpu[0] + UMA_PCPU_ALLOC_SIZE * cpu)
277#define zpcpu_base_to_offset(base) (void *)((uintptr_t)(base) - (uintptr_t)&__pcpu[0])
278#define zpcpu_offset_to_base(base) (void *)((uintptr_t)(base) + (uintptr_t)&__pcpu[0])
279
280#define zpcpu_sub_protected(base, n) do { \
281 ZPCPU_ASSERT_PROTECTED(); \
282 zpcpu_sub(base, n); \
283} while (0)
284
285#define zpcpu_set_protected(base, n) do { \
286 __typeof(*base) __n = (n); \
287 ZPCPU_ASSERT_PROTECTED(); \
288 switch (sizeof(*base)) { \
289 case 4: \
290 __asm __volatile("movl\t%1,%%gs:(%0)" \
291 : : "r" (base), "ri" (__n) : "memory", "cc"); \
292 break; \
293 case 8: \
294 __asm __volatile("movq\t%1,%%gs:(%0)" \
295 : : "r" (base), "ri" (__n) : "memory", "cc"); \
296 break; \
297 default: \
298 *zpcpu_get(base) = __n; \
299 } \
300} while (0);
301
302#define zpcpu_add(base, n) do { \
303 __typeof(*base) __n = (n); \
304 CTASSERT(sizeof(*base) == 4 || sizeof(*base) == 8); \
305 switch (sizeof(*base)) { \
306 case 4: \
307 __asm __volatile("addl\t%1,%%gs:(%0)" \
308 : : "r" (base), "ri" (__n) : "memory", "cc"); \
309 break; \
310 case 8: \
311 __asm __volatile("addq\t%1,%%gs:(%0)" \
312 : : "r" (base), "ri" (__n) : "memory", "cc"); \
313 break; \
314 } \
315} while (0)
316
317#define zpcpu_add_protected(base, n) do { \
318 ZPCPU_ASSERT_PROTECTED(); \
319 zpcpu_add(base, n); \
320} while (0)
321
322#define zpcpu_sub(base, n) do { \
323 __typeof(*base) __n = (n); \
324 CTASSERT(sizeof(*base) == 4 || sizeof(*base) == 8); \
325 switch (sizeof(*base)) { \
326 case 4: \
327 __asm __volatile("subl\t%1,%%gs:(%0)" \
328 : : "r" (base), "ri" (__n) : "memory", "cc"); \
329 break; \
330 case 8: \
331 __asm __volatile("subq\t%1,%%gs:(%0)" \
332 : : "r" (base), "ri" (__n) : "memory", "cc"); \
333 break; \
334 } \
335} while (0);
336
337#endif /* _KERNEL */
338
339#endif /* !_MACHINE_PCPU_H_ */
340
341#endif /* __i386__ */