master
1/*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2002 David E. O'Brien. All rights reserved.
5 * Copyright (c) 1992, 1993
6 * The Regents of the University of California. All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer
10 * Science Department and Ralph Campbell.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 * @(#)param.h 8.1 (Berkeley) 6/10/93
41 */
42
43#ifndef _AMD64_INCLUDE_PARAM_H_
44#define _AMD64_INCLUDE_PARAM_H_
45
46#include <machine/_align.h>
47
48/*
49 * Machine dependent constants for AMD64.
50 */
51
52#define __HAVE_ACPI
53#define __PCI_REROUTE_INTERRUPT
54
55#ifndef MACHINE
56#define MACHINE "amd64"
57#endif
58#ifndef MACHINE_ARCH
59#define MACHINE_ARCH "amd64"
60#endif
61#ifndef MACHINE_ARCH32
62#define MACHINE_ARCH32 "i386"
63#endif
64
65#ifdef SMP
66#ifndef MAXCPU
67#define MAXCPU 1024
68#endif
69#else
70#define MAXCPU 1
71#endif
72
73#ifndef MAXMEMDOM
74#define MAXMEMDOM 8
75#endif
76
77#define ALIGNBYTES _ALIGNBYTES
78#define ALIGN(p) _ALIGN(p)
79/*
80 * ALIGNED_POINTER is a boolean macro that checks whether an address
81 * is valid to fetch data elements of type t from on this architecture.
82 * This does not reflect the optimal alignment, just the possibility
83 * (within reasonable limits).
84 */
85#define ALIGNED_POINTER(p, t) 1
86
87/*
88 * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
89 * architecture. It should be used with appropriate caution.
90 */
91#define CACHE_LINE_SHIFT 6
92#define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT)
93
94/* Size of the level 1 page table units */
95#define NPTEPG (PAGE_SIZE/(sizeof (pt_entry_t)))
96#define NPTEPGSHIFT 9 /* LOG2(NPTEPG) */
97#define PAGE_SHIFT 12 /* LOG2(PAGE_SIZE) */
98#define PAGE_SIZE (1<<PAGE_SHIFT) /* bytes/page */
99#define PAGE_MASK (PAGE_SIZE-1)
100/* Size of the level 2 page directory units */
101#define NPDEPG (PAGE_SIZE/(sizeof (pd_entry_t)))
102#define NPDEPGSHIFT 9 /* LOG2(NPDEPG) */
103#define PDRSHIFT 21 /* LOG2(NBPDR) */
104#define NBPDR (1<<PDRSHIFT) /* bytes/page dir */
105#define PDRMASK (NBPDR-1)
106/* Size of the level 3 page directory pointer table units */
107#define NPDPEPG (PAGE_SIZE/(sizeof (pdp_entry_t)))
108#define NPDPEPGSHIFT 9 /* LOG2(NPDPEPG) */
109#define PDPSHIFT 30 /* LOG2(NBPDP) */
110#define NBPDP (1<<PDPSHIFT) /* bytes/page dir ptr table */
111#define PDPMASK (NBPDP-1)
112/* Size of the level 4 page-map level-4 table units */
113#define NPML4EPG (PAGE_SIZE/(sizeof (pml4_entry_t)))
114#define NPML4EPGSHIFT 9 /* LOG2(NPML4EPG) */
115#define PML4SHIFT 39 /* LOG2(NBPML4) */
116#define NBPML4 (1UL<<PML4SHIFT)/* bytes/page map lev4 table */
117#define PML4MASK (NBPML4-1)
118/* Size of the level 5 page-map level-5 table units */
119#define NPML5EPG (PAGE_SIZE/(sizeof (pml5_entry_t)))
120#define NPML5EPGSHIFT 9 /* LOG2(NPML5EPG) */
121#define PML5SHIFT 48 /* LOG2(NBPML5) */
122#define NBPML5 (1UL<<PML5SHIFT)/* bytes/page map lev5 table */
123#define PML5MASK (NBPML5-1)
124
125#define MAXPAGESIZES 3 /* maximum number of supported page sizes */
126
127#define IOPAGES 2 /* pages of i/o permission bitmap */
128/*
129 * I/O permission bitmap has a bit for each I/O port plus an additional
130 * byte at the end with all bits set. See section "I/O Permission Bit Map"
131 * in the Intel SDM for more details.
132 */
133#define IOPERM_BITMAP_SIZE (IOPAGES * PAGE_SIZE + 1)
134
135#ifndef KSTACK_PAGES
136#if defined(KASAN) || defined(KMSAN)
137#define KSTACK_PAGES 6
138#else
139#define KSTACK_PAGES 4 /* pages of kstack (with pcb) */
140#endif
141#endif
142#define KSTACK_GUARD_PAGES 1 /* pages of kstack guard; 0 disables */
143
144/*
145 * Mach derived conversion macros
146 */
147#define round_page(x) ((((unsigned long)(x)) + PAGE_MASK) & ~(PAGE_MASK))
148#define trunc_page(x) ((unsigned long)(x) & ~(PAGE_MASK))
149#define trunc_2mpage(x) ((unsigned long)(x) & ~PDRMASK)
150#define round_2mpage(x) ((((unsigned long)(x)) + PDRMASK) & ~PDRMASK)
151#define trunc_1gpage(x) ((unsigned long)(x) & ~PDPMASK)
152
153#define atop(x) ((unsigned long)(x) >> PAGE_SHIFT)
154#define ptoa(x) ((unsigned long)(x) << PAGE_SHIFT)
155
156#define amd64_btop(x) ((unsigned long)(x) >> PAGE_SHIFT)
157#define amd64_ptob(x) ((unsigned long)(x) << PAGE_SHIFT)
158
159#define pgtok(x) ((unsigned long)(x) * (PAGE_SIZE / 1024))
160
161#define INKERNEL(va) (((va) >= DMAP_MIN_ADDRESS && (va) < DMAP_MAX_ADDRESS) \
162 || ((va) >= VM_MIN_KERNEL_ADDRESS && (va) < VM_MAX_KERNEL_ADDRESS))
163
164#ifdef SMP
165#define SC_TABLESIZE 1024 /* Must be power of 2. */
166#endif
167
168#endif /* !_AMD64_INCLUDE_PARAM_H_ */