master
1/*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 1993 The Regents of the University of California.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of the University nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
32
33/*
34 * Functions to provide access to special i386 instructions.
35 * This in included in sys/systm.h, and that file should be
36 * used in preference to this.
37 */
38
39#ifdef __i386__
40#include <i386/cpufunc.h>
41#else /* !__i386__ */
42
43#ifndef _MACHINE_CPUFUNC_H_
44#define _MACHINE_CPUFUNC_H_
45
46struct region_descriptor;
47
48#define readb(va) (*(volatile uint8_t *) (va))
49#define readw(va) (*(volatile uint16_t *) (va))
50#define readl(va) (*(volatile uint32_t *) (va))
51#define readq(va) (*(volatile uint64_t *) (va))
52
53#define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
54#define writew(va, d) (*(volatile uint16_t *) (va) = (d))
55#define writel(va, d) (*(volatile uint32_t *) (va) = (d))
56#define writeq(va, d) (*(volatile uint64_t *) (va) = (d))
57
58static __inline void
59breakpoint(void)
60{
61 __asm __volatile("int $3");
62}
63
64#define bsfl(mask) __builtin_ctz(mask)
65
66#define bsfq(mask) __builtin_ctzl(mask)
67
68#define bsrl(mask) (__builtin_clz(mask) ^ 0x1f)
69
70#define bsrq(mask) (__builtin_clzl(mask) ^ 0x3f)
71
72static __inline void
73clflush(u_long addr)
74{
75
76 __asm __volatile("clflush %0" : : "m" (*(char *)addr));
77}
78
79static __inline void
80clflushopt(u_long addr)
81{
82
83 __asm __volatile(".byte 0x66;clflush %0" : : "m" (*(char *)addr));
84}
85
86static __inline void
87clwb(u_long addr)
88{
89
90 __asm __volatile("clwb %0" : : "m" (*(char *)addr));
91}
92
93static __inline void
94clts(void)
95{
96
97 __asm __volatile("clts");
98}
99
100static __inline void
101disable_intr(void)
102{
103 __asm __volatile("cli" : : : "memory");
104}
105
106static __inline void
107do_cpuid(u_int ax, u_int *p)
108{
109 __asm __volatile("cpuid"
110 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
111 : "0" (ax));
112}
113
114static __inline void
115cpuid_count(u_int ax, u_int cx, u_int *p)
116{
117 __asm __volatile("cpuid"
118 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
119 : "0" (ax), "c" (cx));
120}
121
122static __inline void
123enable_intr(void)
124{
125 __asm __volatile("sti");
126}
127
128static __inline void
129halt(void)
130{
131 __asm __volatile("hlt");
132}
133
134static __inline u_char
135inb(u_int port)
136{
137 u_char data;
138
139 __asm __volatile("inb %w1, %0" : "=a" (data) : "Nd" (port));
140 return (data);
141}
142
143static __inline u_int
144inl(u_int port)
145{
146 u_int data;
147
148 __asm __volatile("inl %w1, %0" : "=a" (data) : "Nd" (port));
149 return (data);
150}
151
152static __inline void
153insb(u_int port, void *addr, size_t count)
154{
155 __asm __volatile("rep; insb"
156 : "+D" (addr), "+c" (count)
157 : "d" (port)
158 : "memory");
159}
160
161static __inline void
162insw(u_int port, void *addr, size_t count)
163{
164 __asm __volatile("rep; insw"
165 : "+D" (addr), "+c" (count)
166 : "d" (port)
167 : "memory");
168}
169
170static __inline void
171insl(u_int port, void *addr, size_t count)
172{
173 __asm __volatile("rep; insl"
174 : "+D" (addr), "+c" (count)
175 : "d" (port)
176 : "memory");
177}
178
179static __inline void
180invd(void)
181{
182 __asm __volatile("invd");
183}
184
185static __inline u_short
186inw(u_int port)
187{
188 u_short data;
189
190 __asm __volatile("inw %w1, %0" : "=a" (data) : "Nd" (port));
191 return (data);
192}
193
194static __inline void
195outb(u_int port, u_char data)
196{
197 __asm __volatile("outb %0, %w1" : : "a" (data), "Nd" (port));
198}
199
200static __inline void
201outl(u_int port, u_int data)
202{
203 __asm __volatile("outl %0, %w1" : : "a" (data), "Nd" (port));
204}
205
206static __inline void
207outsb(u_int port, const void *addr, size_t count)
208{
209 __asm __volatile("rep; outsb"
210 : "+S" (addr), "+c" (count)
211 : "d" (port));
212}
213
214static __inline void
215outsw(u_int port, const void *addr, size_t count)
216{
217 __asm __volatile("rep; outsw"
218 : "+S" (addr), "+c" (count)
219 : "d" (port));
220}
221
222static __inline void
223outsl(u_int port, const void *addr, size_t count)
224{
225 __asm __volatile("rep; outsl"
226 : "+S" (addr), "+c" (count)
227 : "d" (port));
228}
229
230static __inline void
231outw(u_int port, u_short data)
232{
233 __asm __volatile("outw %0, %w1" : : "a" (data), "Nd" (port));
234}
235
236static __inline u_long
237popcntq(u_long mask)
238{
239 u_long result;
240
241 __asm __volatile("popcntq %1,%0" : "=r" (result) : "rm" (mask));
242 return (result);
243}
244
245static __inline void
246lfence(void)
247{
248
249 __asm __volatile("lfence" : : : "memory");
250}
251
252static __inline void
253mfence(void)
254{
255
256 __asm __volatile("mfence" : : : "memory");
257}
258
259static __inline void
260sfence(void)
261{
262
263 __asm __volatile("sfence" : : : "memory");
264}
265
266static __inline void
267ia32_pause(void)
268{
269 __asm __volatile("pause");
270}
271
272static __inline u_long
273read_rflags(void)
274{
275 u_long rf;
276
277 __asm __volatile("pushfq; popq %0" : "=r" (rf));
278 return (rf);
279}
280
281static __inline uint64_t
282rdmsr(u_int msr)
283{
284 uint32_t low, high;
285
286 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
287 return (low | ((uint64_t)high << 32));
288}
289
290static __inline uint32_t
291rdmsr32(u_int msr)
292{
293 uint32_t low;
294
295 __asm __volatile("rdmsr" : "=a" (low) : "c" (msr) : "rdx");
296 return (low);
297}
298
299static __inline uint64_t
300rdpmc(u_int pmc)
301{
302 uint32_t low, high;
303
304 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
305 return (low | ((uint64_t)high << 32));
306}
307
308static __inline uint64_t
309rdtsc(void)
310{
311 uint32_t low, high;
312
313 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
314 return (low | ((uint64_t)high << 32));
315}
316
317static __inline uint64_t
318rdtsc_ordered_lfence(void)
319{
320 lfence();
321 return (rdtsc());
322}
323
324static __inline uint64_t
325rdtsc_ordered_mfence(void)
326{
327 mfence();
328 return (rdtsc());
329}
330
331static __inline uint64_t
332rdtscp(void)
333{
334 uint32_t low, high;
335
336 __asm __volatile("rdtscp" : "=a" (low), "=d" (high) : : "ecx");
337 return (low | ((uint64_t)high << 32));
338}
339
340static __inline uint64_t
341rdtscp_aux(uint32_t *aux)
342{
343 uint32_t low, high;
344
345 __asm __volatile("rdtscp" : "=a" (low), "=d" (high), "=c" (*aux));
346 return (low | ((uint64_t)high << 32));
347}
348
349static __inline uint32_t
350rdtsc32(void)
351{
352 uint32_t rv;
353
354 __asm __volatile("rdtsc" : "=a" (rv) : : "edx");
355 return (rv);
356}
357
358static __inline uint32_t
359rdtscp32(void)
360{
361 uint32_t rv;
362
363 __asm __volatile("rdtscp" : "=a" (rv) : : "ecx", "edx");
364 return (rv);
365}
366
367static __inline void
368wbinvd(void)
369{
370 __asm __volatile("wbinvd");
371}
372
373static __inline void
374write_rflags(u_long rf)
375{
376 __asm __volatile("pushq %0; popfq" : : "r" (rf));
377}
378
379static __inline void
380wrmsr(u_int msr, uint64_t newval)
381{
382 uint32_t low, high;
383
384 low = newval;
385 high = newval >> 32;
386 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
387}
388
389static __inline void
390load_cr0(u_long data)
391{
392
393 __asm __volatile("movq %0,%%cr0" : : "r" (data));
394}
395
396static __inline u_long
397rcr0(void)
398{
399 u_long data;
400
401 __asm __volatile("movq %%cr0,%0" : "=r" (data));
402 return (data);
403}
404
405static __inline u_long
406rcr2(void)
407{
408 u_long data;
409
410 __asm __volatile("movq %%cr2,%0" : "=r" (data));
411 return (data);
412}
413
414static __inline void
415load_cr3(u_long data)
416{
417
418 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
419}
420
421static __inline u_long
422rcr3(void)
423{
424 u_long data;
425
426 __asm __volatile("movq %%cr3,%0" : "=r" (data));
427 return (data);
428}
429
430static __inline void
431load_cr4(u_long data)
432{
433 __asm __volatile("movq %0,%%cr4" : : "r" (data));
434}
435
436static __inline u_long
437rcr4(void)
438{
439 u_long data;
440
441 __asm __volatile("movq %%cr4,%0" : "=r" (data));
442 return (data);
443}
444
445static __inline u_long
446rxcr(u_int reg)
447{
448 u_int low, high;
449
450 __asm __volatile("xgetbv" : "=a" (low), "=d" (high) : "c" (reg));
451 return (low | ((uint64_t)high << 32));
452}
453
454static __inline void
455load_xcr(u_int reg, u_long val)
456{
457 u_int low, high;
458
459 low = val;
460 high = val >> 32;
461 __asm __volatile("xsetbv" : : "c" (reg), "a" (low), "d" (high));
462}
463
464/*
465 * Global TLB flush (except for thise for pages marked PG_G)
466 */
467static __inline void
468invltlb(void)
469{
470
471 load_cr3(rcr3());
472}
473
474#ifndef CR4_PGE
475#define CR4_PGE 0x00000080 /* Page global enable */
476#endif
477
478/*
479 * Perform the guaranteed invalidation of all TLB entries. This
480 * includes the global entries, and entries in all PCIDs, not only the
481 * current context. The function works both on non-PCID CPUs and CPUs
482 * with the PCID turned off or on. See IA-32 SDM Vol. 3a 4.10.4.1
483 * Operations that Invalidate TLBs and Paging-Structure Caches.
484 */
485static __inline void
486invltlb_glob(void)
487{
488 uint64_t cr4;
489
490 cr4 = rcr4();
491 load_cr4(cr4 & ~CR4_PGE);
492 /*
493 * Although preemption at this point could be detrimental to
494 * performance, it would not lead to an error. PG_G is simply
495 * ignored if CR4.PGE is clear. Moreover, in case this block
496 * is re-entered, the load_cr4() either above or below will
497 * modify CR4.PGE flushing the TLB.
498 */
499 load_cr4(cr4 | CR4_PGE);
500}
501
502/*
503 * TLB flush for an individual page (even if it has PG_G).
504 * Only works on 486+ CPUs (i386 does not have PG_G).
505 */
506static __inline void
507invlpg(u_long addr)
508{
509
510 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
511}
512
513#define INVPCID_ADDR 0
514#define INVPCID_CTX 1
515#define INVPCID_CTXGLOB 2
516#define INVPCID_ALLCTX 3
517
518struct invpcid_descr {
519 uint64_t pcid:12 __packed;
520 uint64_t pad:52 __packed;
521 uint64_t addr;
522} __packed;
523
524static __inline void
525invpcid(struct invpcid_descr *d, int type)
526{
527
528 __asm __volatile("invpcid (%0),%1"
529 : : "r" (d), "r" ((u_long)type) : "memory");
530}
531
532#define INVLPGB_VA 0x0001
533#define INVLPGB_PCID 0x0002
534#define INVLPGB_ASID 0x0004
535#define INVLPGB_GLOB 0x0008
536#define INVLPGB_FIN 0x0010
537#define INVLPGB_NEST 0x0020
538
539#define INVLPGB_DESCR(asid, pcid) (((pcid) << 16) | (asid))
540
541#define INVLPGB_2M_CNT (1u << 31)
542
543static __inline void
544invlpgb(uint64_t rax, uint32_t edx, uint32_t ecx)
545{
546 __asm __volatile("invlpgb" : : "a" (rax), "d" (edx), "c" (ecx));
547}
548
549static __inline void
550tlbsync(void)
551{
552 __asm __volatile("tlbsync");
553}
554
555static __inline u_short
556rfs(void)
557{
558 u_short sel;
559 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
560 return (sel);
561}
562
563static __inline u_short
564rgs(void)
565{
566 u_short sel;
567 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
568 return (sel);
569}
570
571static __inline u_short
572rss(void)
573{
574 u_short sel;
575 __asm __volatile("movw %%ss,%0" : "=rm" (sel));
576 return (sel);
577}
578
579static __inline void
580load_ds(u_short sel)
581{
582 __asm __volatile("movw %0,%%ds" : : "rm" (sel));
583}
584
585static __inline void
586load_es(u_short sel)
587{
588 __asm __volatile("movw %0,%%es" : : "rm" (sel));
589}
590
591static __inline void
592cpu_monitor(const void *addr, u_long extensions, u_int hints)
593{
594
595 __asm __volatile("monitor"
596 : : "a" (addr), "c" (extensions), "d" (hints));
597}
598
599static __inline void
600cpu_mwait(u_long extensions, u_int hints)
601{
602
603 __asm __volatile("mwait" : : "a" (hints), "c" (extensions));
604}
605
606static __inline uint32_t
607rdpkru(void)
608{
609 uint32_t res;
610
611 __asm __volatile("rdpkru" : "=a" (res) : "c" (0) : "edx");
612 return (res);
613}
614
615static __inline void
616wrpkru(uint32_t mask)
617{
618
619 __asm __volatile("wrpkru" : : "a" (mask), "c" (0), "d" (0));
620}
621
622#ifdef _KERNEL
623/* This is defined in <machine/specialreg.h> but is too painful to get to */
624#ifndef MSR_FSBASE
625#define MSR_FSBASE 0xc0000100
626#endif
627static __inline void
628load_fs(u_short sel)
629{
630 /* Preserve the fsbase value across the selector load */
631 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr"
632 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
633}
634
635#ifndef MSR_GSBASE
636#define MSR_GSBASE 0xc0000101
637#endif
638static __inline void
639load_gs(u_short sel)
640{
641 /*
642 * Preserve the gsbase value across the selector load.
643 * Note that we have to disable interrupts because the gsbase
644 * being trashed happens to be the kernel gsbase at the time.
645 */
646 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
647 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
648}
649#else
650/* Usable by userland */
651static __inline void
652load_fs(u_short sel)
653{
654 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
655}
656
657static __inline void
658load_gs(u_short sel)
659{
660 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
661}
662#endif
663
664static __inline uint64_t
665rdfsbase(void)
666{
667 uint64_t x;
668
669 __asm __volatile("rdfsbase %0" : "=r" (x));
670 return (x);
671}
672
673static __inline void
674wrfsbase(uint64_t x)
675{
676
677 __asm __volatile("wrfsbase %0" : : "r" (x));
678}
679
680static __inline uint64_t
681rdgsbase(void)
682{
683 uint64_t x;
684
685 __asm __volatile("rdgsbase %0" : "=r" (x));
686 return (x);
687}
688
689static __inline void
690wrgsbase(uint64_t x)
691{
692
693 __asm __volatile("wrgsbase %0" : : "r" (x));
694}
695
696static __inline void
697bare_lgdt(struct region_descriptor *addr)
698{
699 __asm __volatile("lgdt (%0)" : : "r" (addr));
700}
701
702static __inline void
703sgdt(struct region_descriptor *addr)
704{
705 char *loc;
706
707 loc = (char *)addr;
708 __asm __volatile("sgdt %0" : "=m" (*loc) : : "memory");
709}
710
711static __inline void
712lidt(struct region_descriptor *addr)
713{
714 __asm __volatile("lidt (%0)" : : "r" (addr));
715}
716
717static __inline void
718sidt(struct region_descriptor *addr)
719{
720 char *loc;
721
722 loc = (char *)addr;
723 __asm __volatile("sidt %0" : "=m" (*loc) : : "memory");
724}
725
726static __inline void
727lldt(u_short sel)
728{
729 __asm __volatile("lldt %0" : : "r" (sel));
730}
731
732static __inline u_short
733sldt(void)
734{
735 u_short sel;
736
737 __asm __volatile("sldt %0" : "=r" (sel));
738 return (sel);
739}
740
741static __inline void
742ltr(u_short sel)
743{
744 __asm __volatile("ltr %0" : : "r" (sel));
745}
746
747static __inline uint32_t
748read_tr(void)
749{
750 u_short sel;
751
752 __asm __volatile("str %0" : "=r" (sel));
753 return (sel);
754}
755
756static __inline uint64_t
757rdr0(void)
758{
759 uint64_t data;
760 __asm __volatile("movq %%dr0,%0" : "=r" (data));
761 return (data);
762}
763
764static __inline void
765load_dr0(uint64_t dr0)
766{
767 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
768}
769
770static __inline uint64_t
771rdr1(void)
772{
773 uint64_t data;
774 __asm __volatile("movq %%dr1,%0" : "=r" (data));
775 return (data);
776}
777
778static __inline void
779load_dr1(uint64_t dr1)
780{
781 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
782}
783
784static __inline uint64_t
785rdr2(void)
786{
787 uint64_t data;
788 __asm __volatile("movq %%dr2,%0" : "=r" (data));
789 return (data);
790}
791
792static __inline void
793load_dr2(uint64_t dr2)
794{
795 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
796}
797
798static __inline uint64_t
799rdr3(void)
800{
801 uint64_t data;
802 __asm __volatile("movq %%dr3,%0" : "=r" (data));
803 return (data);
804}
805
806static __inline void
807load_dr3(uint64_t dr3)
808{
809 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
810}
811
812static __inline uint64_t
813rdr6(void)
814{
815 uint64_t data;
816 __asm __volatile("movq %%dr6,%0" : "=r" (data));
817 return (data);
818}
819
820static __inline void
821load_dr6(uint64_t dr6)
822{
823 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
824}
825
826static __inline uint64_t
827rdr7(void)
828{
829 uint64_t data;
830 __asm __volatile("movq %%dr7,%0" : "=r" (data));
831 return (data);
832}
833
834static __inline void
835load_dr7(uint64_t dr7)
836{
837 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
838}
839
840static __inline register_t
841intr_disable(void)
842{
843 register_t rflags;
844
845 rflags = read_rflags();
846 disable_intr();
847 return (rflags);
848}
849
850static __inline void
851intr_restore(register_t rflags)
852{
853 write_rflags(rflags);
854}
855
856static __inline void
857stac(void)
858{
859
860 __asm __volatile("stac" : : : "cc");
861}
862
863static __inline void
864clac(void)
865{
866
867 __asm __volatile("clac" : : : "cc");
868}
869
870enum {
871 SGX_ECREATE = 0x0,
872 SGX_EADD = 0x1,
873 SGX_EINIT = 0x2,
874 SGX_EREMOVE = 0x3,
875 SGX_EDGBRD = 0x4,
876 SGX_EDGBWR = 0x5,
877 SGX_EEXTEND = 0x6,
878 SGX_ELDU = 0x8,
879 SGX_EBLOCK = 0x9,
880 SGX_EPA = 0xA,
881 SGX_EWB = 0xB,
882 SGX_ETRACK = 0xC,
883};
884
885enum {
886 SGX_PT_SECS = 0x00,
887 SGX_PT_TCS = 0x01,
888 SGX_PT_REG = 0x02,
889 SGX_PT_VA = 0x03,
890 SGX_PT_TRIM = 0x04,
891};
892
893int sgx_encls(uint32_t eax, uint64_t rbx, uint64_t rcx, uint64_t rdx);
894
895static __inline int
896sgx_ecreate(void *pginfo, void *secs)
897{
898
899 return (sgx_encls(SGX_ECREATE, (uint64_t)pginfo,
900 (uint64_t)secs, 0));
901}
902
903static __inline int
904sgx_eadd(void *pginfo, void *epc)
905{
906
907 return (sgx_encls(SGX_EADD, (uint64_t)pginfo,
908 (uint64_t)epc, 0));
909}
910
911static __inline int
912sgx_einit(void *sigstruct, void *secs, void *einittoken)
913{
914
915 return (sgx_encls(SGX_EINIT, (uint64_t)sigstruct,
916 (uint64_t)secs, (uint64_t)einittoken));
917}
918
919static __inline int
920sgx_eextend(void *secs, void *epc)
921{
922
923 return (sgx_encls(SGX_EEXTEND, (uint64_t)secs,
924 (uint64_t)epc, 0));
925}
926
927static __inline int
928sgx_epa(void *epc)
929{
930
931 return (sgx_encls(SGX_EPA, SGX_PT_VA, (uint64_t)epc, 0));
932}
933
934static __inline int
935sgx_eldu(uint64_t rbx, uint64_t rcx,
936 uint64_t rdx)
937{
938
939 return (sgx_encls(SGX_ELDU, rbx, rcx, rdx));
940}
941
942static __inline int
943sgx_eremove(void *epc)
944{
945
946 return (sgx_encls(SGX_EREMOVE, 0, (uint64_t)epc, 0));
947}
948
949void reset_dbregs(void);
950
951#ifdef _KERNEL
952int rdmsr_safe(u_int msr, uint64_t *val);
953int wrmsr_safe(u_int msr, uint64_t newval);
954#endif
955
956#endif /* !_MACHINE_CPUFUNC_H_ */
957
958#endif /* __i386__ */