1/*-
 2 * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
 3 * All rights reserved.
 4 *
 5 * Portions of this software were developed by SRI International and the
 6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
 7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
 8 *
 9 * Portions of this software were developed by the University of Cambridge
10 * Computer Laboratory as part of the CTSRD Project, with support from the
11 * UK Higher Education Innovation Fund (HEIF).
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 *    notice, this list of conditions and the following disclaimer in the
20 *    documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35#ifndef	_MACHINE_DB_MACHDEP_H_
36#define	_MACHINE_DB_MACHDEP_H_
37
38#include <machine/riscvreg.h>
39#include <machine/frame.h>
40#include <machine/trap.h>
41
42#define	T_BREAKPOINT	(SCAUSE_BREAKPOINT)
43#define	T_WATCHPOINT	(0)
44
45typedef vm_offset_t	db_addr_t;
46typedef long		db_expr_t;
47
48#define	PC_REGS()	((db_addr_t)kdb_frame->tf_sepc)
49
50#define	BKPT_INST	(0x00100073)
51#define	BKPT_SIZE	(INSN_SIZE)
52#define	BKPT_SET(inst)	(BKPT_INST)
53
54#define	BKPT_SKIP do {							\
55	uint32_t _instr;						\
56									\
57	_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE);	\
58	if ((_instr & 0x3) == 0x3)					\
59		kdb_frame->tf_sepc += 4;	/* ebreak */		\
60	else								\
61		kdb_frame->tf_sepc += 2;	/* c.ebreak */		\
62} while (0)
63
64#define	db_clear_single_step	kdb_cpu_clear_singlestep
65#define	db_set_single_step	kdb_cpu_set_singlestep
66
67#define	IS_BREAKPOINT_TRAP(type, code)	(type == T_BREAKPOINT)
68#define	IS_WATCHPOINT_TRAP(type, code)	(type == T_WATCHPOINT)
69
70#define	inst_trap_return(ins)	(ins == 0x10000073)	/* eret */
71#define	inst_return(ins)	(ins == 0x00008067)	/* ret */
72#define	inst_call(ins)		(((ins) & 0x7f) == 111 || \
73				 ((ins) & 0x7f) == 103) /* jal, jalr */
74
75#define	inst_load(ins) ({							\
76	uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE);	\
77	is_load_instr(tmp_instr);						\
78})
79
80#define	inst_store(ins) ({							\
81	uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE);	\
82	is_store_instr(tmp_instr);						\
83})
84
85#define	is_load_instr(ins)	(((ins) & 0x7f) == 3)
86#define	is_store_instr(ins)	(((ins) & 0x7f) == 35)
87
88#define	next_instr_address(pc, bd)	((bd) ? (pc) : ((pc) + 4))
89
90#define	DB_ELFSIZE		64
91
92#endif /* !_MACHINE_DB_MACHDEP_H_ */