1/*-
  2 * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
  3 * All rights reserved.
  4 *
  5 * Portions of this software were developed by SRI International and the
  6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
  7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
  8 *
  9 * Portions of this software were developed by the University of Cambridge
 10 * Computer Laboratory as part of the CTSRD Project, with support from the
 11 * UK Higher Education Innovation Fund (HEIF).
 12 *
 13 * Redistribution and use in source and binary forms, with or without
 14 * modification, are permitted provided that the following conditions
 15 * are met:
 16 * 1. Redistributions of source code must retain the above copyright
 17 *    notice, this list of conditions and the following disclaimer.
 18 * 2. Redistributions in binary form must reproduce the above copyright
 19 *    notice, this list of conditions and the following disclaimer in the
 20 *    documentation and/or other materials provided with the distribution.
 21 *
 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 25 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 32 * SUCH DAMAGE.
 33 */
 34
 35#ifndef _MACHINE_CPUFUNC_H_
 36#define	_MACHINE_CPUFUNC_H_
 37
 38static __inline void
 39breakpoint(void)
 40{
 41
 42	__asm("ebreak");
 43}
 44
 45#ifdef _KERNEL
 46
 47#include <machine/riscvreg.h>
 48
 49static __inline register_t
 50intr_disable(void)
 51{
 52	uint64_t ret;
 53
 54	__asm __volatile(
 55		"csrrci %0, sstatus, %1"
 56		: "=&r" (ret) : "i" (SSTATUS_SIE)
 57	);
 58
 59	return (ret & (SSTATUS_SIE));
 60}
 61
 62static __inline void
 63intr_restore(register_t s)
 64{
 65
 66	__asm __volatile(
 67		"csrs sstatus, %0"
 68		:: "r" (s)
 69	);
 70}
 71
 72static __inline void
 73intr_enable(void)
 74{
 75
 76	__asm __volatile(
 77		"csrsi sstatus, %0"
 78		:: "i" (SSTATUS_SIE)
 79	);
 80}
 81
 82/* NB: fence() is defined as a macro in <machine/atomic.h>. */
 83
 84static __inline void
 85fence_i(void)
 86{
 87
 88	__asm __volatile("fence.i" ::: "memory");
 89}
 90
 91static __inline void
 92sfence_vma(void)
 93{
 94
 95	__asm __volatile("sfence.vma" ::: "memory");
 96}
 97
 98static __inline void
 99sfence_vma_page(uintptr_t addr)
100{
101
102	__asm __volatile("sfence.vma %0" :: "r" (addr) : "memory");
103}
104
105#define	rdcycle()			csr_read64(cycle)
106#define	rdtime()			csr_read64(time)
107#define	rdinstret()			csr_read64(instret)
108#define	rdhpmcounter(n)			csr_read64(hpmcounter##n)
109
110extern int64_t dcache_line_size;
111extern int64_t icache_line_size;
112
113#define	cpu_dcache_wbinv_range(a, s)
114#define	cpu_dcache_inv_range(a, s)
115#define	cpu_dcache_wb_range(a, s)
116
117#define	cpu_idcache_wbinv_range(a, s)
118#define	cpu_icache_sync_range(a, s)
119#define	cpu_icache_sync_range_checked(a, s)
120
121#define	cpufunc_nullop()		riscv_nullop()
122
123void riscv_nullop(void);
124
125#endif	/* _KERNEL */
126#endif	/* _MACHINE_CPUFUNC_H_ */