1/*-
  2 * Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com>
  3 * All rights reserved.
  4 *
  5 * Portions of this software were developed by SRI International and the
  6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
  7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
  8 *
  9 * Portions of this software were developed by the University of Cambridge
 10 * Computer Laboratory as part of the CTSRD Project, with support from the
 11 * UK Higher Education Innovation Fund (HEIF).
 12 *
 13 * Redistribution and use in source and binary forms, with or without
 14 * modification, are permitted provided that the following conditions
 15 * are met:
 16 * 1. Redistributions of source code must retain the above copyright
 17 *    notice, this list of conditions and the following disclaimer.
 18 * 2. Redistributions in binary form must reproduce the above copyright
 19 *    notice, this list of conditions and the following disclaimer in the
 20 *    documentation and/or other materials provided with the distribution.
 21 *
 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 25 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 32 * SUCH DAMAGE.
 33 */
 34
 35#ifndef _MACHINE_CPU_H_
 36#define	_MACHINE_CPU_H_
 37
 38#include <machine/atomic.h>
 39#include <machine/cpufunc.h>
 40#include <machine/frame.h>
 41
 42#define	TRAPF_PC(tfp)		((tfp)->tf_sepc)
 43#define	TRAPF_USERMODE(tfp)	(((tfp)->tf_sstatus & SSTATUS_SPP) == 0)
 44
 45#define	cpu_getstack(td)	((td)->td_frame->tf_sp)
 46#define	cpu_setstack(td, sp)	((td)->td_frame->tf_sp = (sp))
 47#define	cpu_spinwait()		/* nothing */
 48#define	cpu_lock_delay()	DELAY(1)
 49
 50#ifdef _KERNEL
 51
 52/*
 53 * Core manufacturer IDs, as reported by the mvendorid CSR.
 54 */
 55#define	MVENDORID_UNIMPL	0x0
 56#define	MVENDORID_SIFIVE	0x489
 57#define	MVENDORID_THEAD		0x5b7
 58
 59/*
 60 * Micro-architecture ID register, marchid.
 61 *
 62 * IDs for open-source implementations are allocated globally. Commercial IDs
 63 * will have the most-significant bit set.
 64 */
 65#define	MARCHID_UNIMPL		0x0
 66#define	MARCHID_MSB		(1ul << (XLEN - 1))
 67#define	MARCHID_OPENSOURCE(v)	(v)
 68#define	MARCHID_COMMERCIAL(v)	(MARCHID_MSB | (v))
 69#define	MARCHID_IS_OPENSOURCE(m) (((m) & MARCHID_MSB) == 0)
 70
 71/*
 72 * Open-source marchid values.
 73 *
 74 * https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md
 75 */
 76#define	MARCHID_UCB_ROCKET	MARCHID_OPENSOURCE(1)
 77#define	MARCHID_UCB_BOOM	MARCHID_OPENSOURCE(2)
 78#define	MARCHID_UCB_SPIKE	MARCHID_OPENSOURCE(5)
 79#define	MARCHID_UCAM_RVBS	MARCHID_OPENSOURCE(10)
 80
 81/* SiFive marchid values */
 82#define	MARCHID_SIFIVE_U7	MARCHID_COMMERCIAL(7)
 83
 84/*
 85 * MMU virtual-addressing modes. Support for each level implies the previous,
 86 * so Sv48-enabled systems MUST support Sv39, etc.
 87 */
 88#define	MMU_SV39	0x1	/* 3-level paging */
 89#define	MMU_SV48	0x2	/* 4-level paging */
 90#define	MMU_SV57	0x4	/* 5-level paging */
 91
 92extern char btext[];
 93extern char etext[];
 94
 95void	cpu_halt(void) __dead2;
 96void	cpu_reset(void) __dead2;
 97void	fork_trampoline(void);
 98void	identify_cpu(u_int cpu);
 99void	printcpuinfo(u_int cpu);
100
101static __inline uint64_t
102get_cyclecount(void)
103{
104
105	return (rdcycle());
106}
107
108#endif
109
110#endif /* !_MACHINE_CPU_H_ */