1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
 2#ifndef _ASM_POWERPC_PERF_REGS_H
 3#define _ASM_POWERPC_PERF_REGS_H
 4
 5enum perf_event_powerpc_regs {
 6	PERF_REG_POWERPC_R0,
 7	PERF_REG_POWERPC_R1,
 8	PERF_REG_POWERPC_R2,
 9	PERF_REG_POWERPC_R3,
10	PERF_REG_POWERPC_R4,
11	PERF_REG_POWERPC_R5,
12	PERF_REG_POWERPC_R6,
13	PERF_REG_POWERPC_R7,
14	PERF_REG_POWERPC_R8,
15	PERF_REG_POWERPC_R9,
16	PERF_REG_POWERPC_R10,
17	PERF_REG_POWERPC_R11,
18	PERF_REG_POWERPC_R12,
19	PERF_REG_POWERPC_R13,
20	PERF_REG_POWERPC_R14,
21	PERF_REG_POWERPC_R15,
22	PERF_REG_POWERPC_R16,
23	PERF_REG_POWERPC_R17,
24	PERF_REG_POWERPC_R18,
25	PERF_REG_POWERPC_R19,
26	PERF_REG_POWERPC_R20,
27	PERF_REG_POWERPC_R21,
28	PERF_REG_POWERPC_R22,
29	PERF_REG_POWERPC_R23,
30	PERF_REG_POWERPC_R24,
31	PERF_REG_POWERPC_R25,
32	PERF_REG_POWERPC_R26,
33	PERF_REG_POWERPC_R27,
34	PERF_REG_POWERPC_R28,
35	PERF_REG_POWERPC_R29,
36	PERF_REG_POWERPC_R30,
37	PERF_REG_POWERPC_R31,
38	PERF_REG_POWERPC_NIP,
39	PERF_REG_POWERPC_MSR,
40	PERF_REG_POWERPC_ORIG_R3,
41	PERF_REG_POWERPC_CTR,
42	PERF_REG_POWERPC_LINK,
43	PERF_REG_POWERPC_XER,
44	PERF_REG_POWERPC_CCR,
45	PERF_REG_POWERPC_SOFTE,
46	PERF_REG_POWERPC_TRAP,
47	PERF_REG_POWERPC_DAR,
48	PERF_REG_POWERPC_DSISR,
49	PERF_REG_POWERPC_SIER,
50	PERF_REG_POWERPC_MMCRA,
51	/* Extended registers */
52	PERF_REG_POWERPC_MMCR0,
53	PERF_REG_POWERPC_MMCR1,
54	PERF_REG_POWERPC_MMCR2,
55	PERF_REG_POWERPC_MMCR3,
56	PERF_REG_POWERPC_SIER2,
57	PERF_REG_POWERPC_SIER3,
58	PERF_REG_POWERPC_PMC1,
59	PERF_REG_POWERPC_PMC2,
60	PERF_REG_POWERPC_PMC3,
61	PERF_REG_POWERPC_PMC4,
62	PERF_REG_POWERPC_PMC5,
63	PERF_REG_POWERPC_PMC6,
64	PERF_REG_POWERPC_SDAR,
65	PERF_REG_POWERPC_SIAR,
66	/* Max mask value for interrupt regs w/o extended regs */
67	PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1,
68	/* Max mask value for interrupt regs including extended regs */
69	PERF_REG_EXTENDED_MAX = PERF_REG_POWERPC_SIAR + 1,
70};
71
72#define PERF_REG_PMU_MASK	((1ULL << PERF_REG_POWERPC_MAX) - 1)
73
74/*
75 * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300
76 * includes 11 SPRS from MMCR0 to SIAR excluding the
77 * unsupported SPRS MMCR3, SIER2 and SIER3.
78 */
79#define PERF_REG_PMU_MASK_300	\
80	((1ULL << PERF_REG_POWERPC_MMCR0) | (1ULL << PERF_REG_POWERPC_MMCR1) | \
81	(1ULL << PERF_REG_POWERPC_MMCR2) | (1ULL << PERF_REG_POWERPC_PMC1) | \
82	(1ULL << PERF_REG_POWERPC_PMC2) | (1ULL << PERF_REG_POWERPC_PMC3) | \
83	(1ULL << PERF_REG_POWERPC_PMC4) | (1ULL << PERF_REG_POWERPC_PMC5) | \
84	(1ULL << PERF_REG_POWERPC_PMC6) | (1ULL << PERF_REG_POWERPC_SDAR) | \
85	(1ULL << PERF_REG_POWERPC_SIAR))
86
87/*
88 * PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31
89 * includes 14 SPRs from MMCR0 to SIAR.
90 */
91#define PERF_REG_PMU_MASK_31	\
92	(PERF_REG_PMU_MASK_300 | (1ULL << PERF_REG_POWERPC_MMCR3) | \
93	(1ULL << PERF_REG_POWERPC_SIER2) | (1ULL << PERF_REG_POWERPC_SIER3))
94
95#endif /* _ASM_POWERPC_PERF_REGS_H */