master
1/* $NetBSD: specialreg.h,v 1.198.2.6 2024/10/03 12:00:57 martin Exp $ */
2
3/*
4 * Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * Copyright (c) 1991 The Regents of the University of California.
31 * All rights reserved.
32 *
33 * Redistribution and use in source and binary forms, with or without
34 * modification, are permitted provided that the following conditions
35 * are met:
36 * 1. Redistributions of source code must retain the above copyright
37 * notice, this list of conditions and the following disclaimer.
38 * 2. Redistributions in binary form must reproduce the above copyright
39 * notice, this list of conditions and the following disclaimer in the
40 * documentation and/or other materials provided with the distribution.
41 * 3. Neither the name of the University nor the names of its contributors
42 * may be used to endorse or promote products derived from this software
43 * without specific prior written permission.
44 *
45 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
48 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 * SUCH DAMAGE.
56 *
57 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91
58 */
59
60/*
61 * CR0
62 */
63#define CR0_PE 0x00000001 /* Protected mode Enable */
64#define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */
65#define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */
66#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
67#define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */
68#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
69#define CR0_WP 0x00010000 /* Write Protect (honor PTE_W in all modes) */
70#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
71#define CR0_NW 0x20000000 /* Not Write-through */
72#define CR0_CD 0x40000000 /* Cache Disable */
73#define CR0_PG 0x80000000 /* PaGing enable */
74
75/*
76 * Cyrix 486 DLC special registers, accessible as IO ports
77 */
78#define CCR0 0xc0 /* configuration control register 0 */
79#define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */
80#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
81#define CCR0_A20M 0x04 /* enables A20M# input pin */
82#define CCR0_KEN 0x08 /* enables KEN# input pin */
83#define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */
84#define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */
85#define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */
86#define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */
87#define CCR1 0xc1 /* configuration control register 1 */
88#define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */
89
90/*
91 * CR3
92 */
93#define CR3_PCID __BITS(11,0)
94#define CR3_PA __BITS(62,12)
95#define CR3_NO_TLB_FLUSH __BIT(63)
96
97/*
98 * CR4
99 */
100#define CR4_VME 0x00000001 /* Virtual 8086 mode extension enable */
101#define CR4_PVI 0x00000002 /* Protected mode virtual interrupt enable */
102#define CR4_TSD 0x00000004 /* Restrict RDTSC instruction to cpl 0 */
103#define CR4_DE 0x00000008 /* Debugging extension */
104#define CR4_PSE 0x00000010 /* Large (4MB) page size enable */
105#define CR4_PAE 0x00000020 /* Physical address extension enable */
106#define CR4_MCE 0x00000040 /* Machine check enable */
107#define CR4_PGE 0x00000080 /* Page global enable */
108#define CR4_PCE 0x00000100 /* Enable RDPMC instruction for all cpls */
109#define CR4_OSFXSR 0x00000200 /* Enable fxsave/fxrestor and SSE */
110#define CR4_OSXMMEXCPT 0x00000400 /* Enable unmasked SSE exceptions */
111#define CR4_UMIP 0x00000800 /* User Mode Instruction Prevention */
112#define CR4_LA57 0x00001000 /* 57-bit linear addresses */
113#define CR4_VMXE 0x00002000 /* Enable VMX operations */
114#define CR4_SMXE 0x00004000 /* Enable SMX operations */
115#define CR4_FSGSBASE 0x00010000 /* Enable *FSBASE and *GSBASE instructions */
116#define CR4_PCIDE 0x00020000 /* Enable Process Context IDentifiers */
117#define CR4_OSXSAVE 0x00040000 /* Enable xsave and xrestore */
118#define CR4_SMEP 0x00100000 /* Enable SMEP support */
119#define CR4_SMAP 0x00200000 /* Enable SMAP support */
120#define CR4_PKE 0x00400000 /* Enable Protection Keys for user pages */
121#define CR4_CET 0x00800000 /* Enable CET */
122#define CR4_PKS 0x01000000 /* Enable Protection Keys for kern pages */
123
124/*
125 * Extended Control Register XCR0
126 */
127#define XCR0_X87 __BIT(0) /* x87 FPU/MMX state */
128#define XCR0_SSE __BIT(1) /* SSE state */
129#define XCR0_YMM_Hi128 __BIT(2) /* AVX-256 (ymmn registers) */
130#define XCR0_BNDREGS __BIT(3) /* Memory protection ext bounds */
131#define XCR0_BNDCSR __BIT(4) /* Memory protection ext state */
132#define XCR0_Opmask __BIT(5) /* AVX-512 Opmask */
133#define XCR0_ZMM_Hi256 __BIT(6) /* AVX-512 upper 256 bits low regs */
134#define XCR0_Hi16_ZMM __BIT(7) /* AVX-512 512 bits upper registers */
135#define XCR0_PT __BIT(8) /* Processor Trace state */
136#define XCR0_PKRU __BIT(9) /* Protection Key state */
137#define XCR0_CET_U __BIT(11) /* User CET state */
138#define XCR0_CET_S __BIT(12) /* Kern CET state */
139#define XCR0_HDC __BIT(13) /* Hardware Duty Cycle state */
140#define XCR0_LBR __BIT(15) /* Last Branch Record */
141#define XCR0_HWP __BIT(16) /* Hardware P-states */
142
143#define XCR0_FLAGS1 "\20" \
144 "\1" "x87" "\2" "SSE" "\3" "AVX" "\4" "BNDREGS" \
145 "\5" "BNDCSR" "\6" "Opmask" "\7" "ZMM_Hi256" "\10" "Hi16_ZMM" \
146 "\11" "PT" "\12" "PKRU" "\14" "CET_U" \
147 "\15" "CET_S" "\16" "HDC" "\20" "LBR" \
148 "\21" "HWP"
149
150/*
151 * Known FPU bits, only these get enabled. The save area is sized for all the
152 * fields below.
153 */
154#define XCR0_FPU (XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \
155 XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM)
156
157/*
158 * XSAVE component indices, internal to NetBSD.
159 */
160#define XSAVE_X87 0
161#define XSAVE_SSE 1
162#define XSAVE_YMM_Hi128 2
163#define XSAVE_BNDREGS 3
164#define XSAVE_BNDCSR 4
165#define XSAVE_Opmask 5
166#define XSAVE_ZMM_Hi256 6
167#define XSAVE_Hi16_ZMM 7
168
169/*
170 * Highest XSAVE component enabled by XCR0_FPU.
171 */
172#define XSAVE_MAX_COMPONENT XSAVE_Hi16_ZMM
173
174/*
175 * "features" bits.
176 * CPUID Fn00000001
177 */
178/* %edx */
179#define CPUID_FPU 0x00000001 /* processor has an FPU? */
180#define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */
181#define CPUID_DE 0x00000004 /* has debugging extension */
182#define CPUID_PSE 0x00000008 /* has 4MB page size extension */
183#define CPUID_TSC 0x00000010 /* has time stamp counter */
184#define CPUID_MSR 0x00000020 /* has model specific registers */
185#define CPUID_PAE 0x00000040 /* has physical address extension */
186#define CPUID_MCE 0x00000080 /* has machine check exception */
187#define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */
188#define CPUID_APIC 0x00000200 /* has enabled APIC */
189#define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */
190#define CPUID_MTRR 0x00001000 /* has memory type range register */
191#define CPUID_PGE 0x00002000 /* has page global extension */
192#define CPUID_MCA 0x00004000 /* has machine check architecture */
193#define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */
194#define CPUID_PAT 0x00010000 /* Page Attribute Table */
195#define CPUID_PSE36 0x00020000 /* 36-bit PSE */
196#define CPUID_PSN 0x00040000 /* Processor Serial Number */
197#define CPUID_CLFSH 0x00080000 /* CLFLUSH instruction supported */
198#define CPUID_DS 0x00200000 /* Debug Store */
199#define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */
200#define CPUID_MMX 0x00800000 /* MMX supported */
201#define CPUID_FXSR 0x01000000 /* Fast FP/MMX Save/Restore */
202#define CPUID_SSE 0x02000000 /* Streaming SIMD Extensions */
203#define CPUID_SSE2 0x04000000 /* Streaming SIMD Extensions #2 */
204#define CPUID_SS 0x08000000 /* Self-Snoop */
205#define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */
206#define CPUID_TM 0x20000000 /* Thermal Monitor (TCC) */
207#define CPUID_PBE 0x80000000 /* Pending Break Enable */
208
209#define CPUID_FLAGS1 "\20" \
210 "\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \
211 "\5" "TSC" "\6" "MSR" "\7" "PAE" "\10" "MCE" \
212 "\11" "CX8" "\12" "APIC" "\13" "B10" "\14" "SEP" \
213 "\15" "MTRR" "\16" "PGE" "\17" "MCA" "\20" "CMOV" \
214 "\21" "PAT" "\22" "PSE36" "\23" "PN" "\24" "CLFSH" \
215 "\25" "B20" "\26" "DS" "\27" "ACPI" "\30" "MMX" \
216 "\31" "FXSR" "\32" "SSE" "\33" "SSE2" "\34" "SS" \
217 "\35" "HTT" "\36" "TM" "\37" "IA64" "\40" "PBE"
218
219/* Blacklists of CPUID flags - used to mask certain features */
220#ifdef XENPV
221#define CPUID_FEAT_BLACKLIST (CPUID_PGE|CPUID_PSE|CPUID_MTRR)
222#else
223#define CPUID_FEAT_BLACKLIST 0
224#endif
225
226/* %ecx */
227#define CPUID2_SSE3 __BIT(0) /* Streaming SIMD Extensions 3 */
228#define CPUID2_PCLMULQDQ __BIT(1) /* PCLMULQDQ instructions */
229#define CPUID2_DTES64 __BIT(2) /* 64-bit Debug Trace */
230#define CPUID2_MONITOR __BIT(3) /* MONITOR/MWAIT instructions */
231#define CPUID2_DS_CPL __BIT(4) /* CPL Qualified Debug Store */
232#define CPUID2_VMX __BIT(5) /* Virtual Machine eXtensions */
233#define CPUID2_SMX __BIT(6) /* Safer Mode eXtensions */
234#define CPUID2_EST __BIT(7) /* Enhanced SpeedStep Technology */
235#define CPUID2_TM2 __BIT(8) /* Thermal Monitor 2 */
236#define CPUID2_SSSE3 __BIT(9) /* Supplemental SSE3 */
237#define CPUID2_CNXTID __BIT(10) /* Context ID */
238#define CPUID2_SDBG __BIT(11) /* Silicon Debug */
239#define CPUID2_FMA __BIT(12) /* Fused Multiply Add */
240#define CPUID2_CX16 __BIT(13) /* CMPXCHG16B instruction */
241#define CPUID2_XTPR __BIT(14) /* Task Priority Messages disabled? */
242#define CPUID2_PDCM __BIT(15) /* Perf/Debug Capability MSR */
243/* bit 16 unused __BIT(16) */
244#define CPUID2_PCID __BIT(17) /* Process Context ID */
245#define CPUID2_DCA __BIT(18) /* Direct Cache Access */
246#define CPUID2_SSE41 __BIT(19) /* Streaming SIMD Extensions 4.1 */
247#define CPUID2_SSE42 __BIT(20) /* Streaming SIMD Extensions 4.2 */
248#define CPUID2_X2APIC __BIT(21) /* xAPIC Extensions */
249#define CPUID2_MOVBE __BIT(22) /* MOVBE (move after byteswap) */
250#define CPUID2_POPCNT __BIT(23) /* POPCNT instruction available */
251#define CPUID2_DEADLINE __BIT(24) /* APIC Timer supports TSC Deadline */
252#define CPUID2_AESNI __BIT(25) /* AES instructions */
253#define CPUID2_XSAVE __BIT(26) /* XSAVE instructions */
254#define CPUID2_OSXSAVE __BIT(27) /* XGETBV/XSETBV instructions */
255#define CPUID2_AVX __BIT(28) /* AVX instructions */
256#define CPUID2_F16C __BIT(29) /* half precision conversion */
257#define CPUID2_RDRAND __BIT(30) /* RDRAND (hardware random number) */
258#define CPUID2_RAZ __BIT(31) /* RAZ. Indicates guest state. */
259
260#define CPUID2_FLAGS1 "\20" \
261 "\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \
262 "\5" "DS-CPL" "\6" "VMX" "\7" "SMX" "\10" "EST" \
263 "\11" "TM2" "\12" "SSSE3" "\13" "CID" "\14" "SDBG" \
264 "\15" "FMA" "\16" "CX16" "\17" "xTPR" "\20" "PDCM" \
265 "\21" "B16" "\22" "PCID" "\23" "DCA" "\24" "SSE41" \
266 "\25" "SSE42" "\26" "X2APIC" "\27" "MOVBE" "\30" "POPCNT" \
267 "\31" "DEADLINE" "\32" "AES" "\33" "XSAVE" "\34" "OSXSAVE" \
268 "\35" "AVX" "\36" "F16C" "\37" "RDRAND" "\40" "RAZ"
269
270/* %eax */
271#define CPUID_TO_BASEFAMILY(cpuid) (((cpuid) >> 8) & 0xf)
272#define CPUID_TO_BASEMODEL(cpuid) (((cpuid) >> 4) & 0xf)
273#define CPUID_TO_STEPPING(cpuid) ((cpuid) & 0xf)
274
275/*
276 * The Extended family bits should only be inspected when CPUID_TO_BASEFAMILY()
277 * returns 15. They are use to encode family value 16 to 270 (add 15).
278 * The Extended model bits are the high 4 bits of the model.
279 * They are only valid for family >= 15 or family 6 (intel, but all amd
280 * family 6 are documented to return zero bits for them).
281 */
282#define CPUID_TO_EXTFAMILY(cpuid) (((cpuid) >> 20) & 0xff)
283#define CPUID_TO_EXTMODEL(cpuid) (((cpuid) >> 16) & 0xf)
284
285/* The macros for the Display Family and the Display Model */
286#define CPUID_TO_FAMILY(cpuid) (CPUID_TO_BASEFAMILY(cpuid) \
287 + ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \
288 ? 0 : CPUID_TO_EXTFAMILY(cpuid)))
289#define CPUID_TO_MODEL(cpuid) (CPUID_TO_BASEMODEL(cpuid) \
290 | ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f) \
291 && (CPUID_TO_BASEFAMILY(cpuid) != 0x06) \
292 ? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4)))
293
294/* %ebx */
295#define CPUID_BRAND_INDEX __BITS(7,0)
296#define CPUID_CLFLUSH_SIZE __BITS(15,8)
297#define CPUID_HTT_CORES __BITS(23,16)
298#define CPUID_LOCAL_APIC_ID __BITS(31,24)
299
300/*
301 * Intel Deterministic Cache Parameter.
302 * CPUID Fn0000_0004
303 */
304
305/* %eax */
306#define CPUID_DCP_CACHETYPE __BITS(4, 0) /* Cache type */
307#define CPUID_DCP_CACHETYPE_N 0 /* NULL */
308#define CPUID_DCP_CACHETYPE_D 1 /* Data cache */
309#define CPUID_DCP_CACHETYPE_I 2 /* Instruction cache */
310#define CPUID_DCP_CACHETYPE_U 3 /* Unified cache */
311#define CPUID_DCP_CACHELEVEL __BITS(7, 5) /* Cache level (start at 1) */
312#define CPUID_DCP_SELFINITCL __BIT(8) /* Self initializing cachelvl*/
313#define CPUID_DCP_FULLASSOC __BIT(9) /* Full associative */
314#define CPUID_DCP_SHARING __BITS(25, 14) /* sharing */
315#define CPUID_DCP_CORE_P_PKG __BITS(31, 26) /* Cores/package */
316
317/* %ebx */
318#define CPUID_DCP_LINESIZE __BITS(11, 0) /* System coherency linesize */
319#define CPUID_DCP_PARTITIONS __BITS(21, 12) /* Physical line partitions */
320#define CPUID_DCP_WAYS __BITS(31, 22) /* Ways of associativity */
321
322/* %ecx: Number of sets */
323
324/* %edx */
325#define CPUID_DCP_INVALIDATE __BIT(0) /* WB invalidate/invalidate */
326#define CPUID_DCP_INCLUSIVE __BIT(1) /* Cache inclusiveness */
327#define CPUID_DCP_COMPLEX __BIT(2) /* Complex cache indexing */
328
329/*
330 * Intel/AMD MONITOR/MWAIT.
331 * CPUID Fn0000_0005
332 */
333/* %eax */
334#define CPUID_MON_MINSIZE __BITS(15, 0) /* Smallest monitor-line size */
335/* %ebx */
336#define CPUID_MON_MAXSIZE __BITS(15, 0) /* Largest monitor-line size */
337/* %ecx */
338#define CPUID_MON_EMX __BIT(0) /* MONITOR/MWAIT Extensions */
339#define CPUID_MON_IBE __BIT(1) /* Interrupt as Break Event */
340
341#define CPUID_MON_FLAGS "\20" \
342 "\1" "EMX" "\2" "IBE"
343
344/* %edx: number of substates for specific C-state */
345#define CPUID_MON_SUBSTATE(edx, cstate) (((edx) >> (cstate * 4)) & 0x0000000f)
346
347/*
348 * Intel/AMD Digital Thermal Sensor and Power Management.
349 * CPUID Fn0000_0006
350 */
351/* %eax */
352#define CPUID_DSPM_DTS __BIT(0) /* Digital Thermal Sensor */
353#define CPUID_DSPM_IDA __BIT(1) /* Intel Dynamic Acceleration */
354#define CPUID_DSPM_ARAT __BIT(2) /* Always Running APIC Timer */
355#define CPUID_DSPM_PLN __BIT(4) /* Power Limit Notification */
356#define CPUID_DSPM_ECMD __BIT(5) /* Clock Modulation Extension */
357#define CPUID_DSPM_PTM __BIT(6) /* Package Level Thermal Management */
358#define CPUID_DSPM_HWP __BIT(7) /* HWP */
359#define CPUID_DSPM_HWP_NOTIFY __BIT(8) /* HWP Notification */
360#define CPUID_DSPM_HWP_ACTWIN __BIT(9) /* HWP Activity Window */
361#define CPUID_DSPM_HWP_EPP __BIT(10) /* HWP Energy Performance Preference */
362#define CPUID_DSPM_HWP_PLR __BIT(11) /* HWP Package Level Request */
363#define CPUID_DSPM_HDC __BIT(13) /* Hardware Duty Cycling */
364#define CPUID_DSPM_TBMT3 __BIT(14) /* Turbo Boost Max Technology 3.0 */
365#define CPUID_DSPM_HWP_CAP __BIT(15) /* HWP Capabilities */
366#define CPUID_DSPM_HWP_PECI __BIT(16) /* HWP PECI override */
367#define CPUID_DSPM_HWP_FLEX __BIT(17) /* Flexible HWP */
368#define CPUID_DSPM_HWP_FAST __BIT(18) /* Fast access for IA32_HWP_REQUEST */
369#define CPUID_DSPM_HFI __BIT(19) /* Hardware Feedback Interface */
370#define CPUID_DSPM_HWP_IGNIDL __BIT(20) /* Ignore Idle Logical Processor HWP */
371#define CPUID_DSPM_TD __BIT(23) /* Thread Director */
372#define CPUID_DSPM_THERMI_HFN __BIT(24) /* THERM_INTERRUPT MSR HFN bit */
373
374#define CPUID_DSPM_FLAGS "\20" \
375 "\1" "DTS" "\2" "IDA" "\3" "ARAT" \
376 "\5" "PLN" "\6" "ECMD" "\7" "PTM" "\10" "HWP" \
377 "\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \
378 "\16" "HDC" "\17" "TBM3" "\20" "HWP_CAP" \
379 "\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST" "\24HFI" \
380 "\25" "HWP_IGNIDL" "\30" "TD" \
381 "\31" "THERMI_HFN"
382
383/* %ecx */
384#define CPUID_DSPM_HWF __BIT(0) /* MSR_APERF/MSR_MPERF available */
385#define CPUID_DSPM_EPB __BIT(3) /* Energy Performance Bias */
386#define CPUID_DSPM_NTDC __BITS(15, 8) /* Number of Thread Director Classes */
387
388#define CPUID_DSPM_FLAGS1 "\177\20" \
389 "b\0HWF\0" "b\3EPB\0" \
390 "f\10\10NTDC\0"
391
392/*
393 * Intel/AMD Structured Extended Feature.
394 * CPUID Fn0000_0007
395 * %ecx == 0: Subleaf 0
396 * %eax: The Maximum input value for supported subleaf.
397 * %ebx: Feature bits.
398 * %ecx: Feature bits.
399 * %edx: Feature bits.
400 *
401 * %ecx == 1: Structure Extendede Feature Enumeration Sub-leaf
402 * %eax: See below.
403 */
404
405/* %ecx = 0, %ebx */
406#define CPUID_SEF_FSGSBASE __BIT(0) /* {RD,WR}{FS,GS}BASE */
407#define CPUID_SEF_TSC_ADJUST __BIT(1) /* IA32_TSC_ADJUST MSR support */
408#define CPUID_SEF_SGX __BIT(2) /* Software Guard Extensions */
409#define CPUID_SEF_BMI1 __BIT(3) /* Advanced bit manipulation ext. 1st grp */
410#define CPUID_SEF_HLE __BIT(4) /* Hardware Lock Elision */
411#define CPUID_SEF_AVX2 __BIT(5) /* Advanced Vector Extensions 2 */
412#define CPUID_SEF_FDPEXONLY __BIT(6) /* x87FPU Data ptr updated only on x87exp */
413#define CPUID_SEF_SMEP __BIT(7) /* Supervisor-Mode Execution Prevention */
414#define CPUID_SEF_BMI2 __BIT(8) /* Advanced bit manipulation ext. 2nd grp */
415#define CPUID_SEF_ERMS __BIT(9) /* Enhanced REP MOVSB/STOSB */
416#define CPUID_SEF_INVPCID __BIT(10) /* INVPCID instruction */
417#define CPUID_SEF_RTM __BIT(11) /* Restricted Transactional Memory */
418#define CPUID_SEF_QM __BIT(12) /* Resource Director Technology Monitoring */
419#define CPUID_SEF_FPUCSDS __BIT(13) /* Deprecate FPU CS and FPU DS values */
420#define CPUID_SEF_MPX __BIT(14) /* Memory Protection Extensions */
421#define CPUID_SEF_PQE __BIT(15) /* Resource Director Technology Allocation */
422#define CPUID_SEF_AVX512F __BIT(16) /* AVX-512 Foundation */
423#define CPUID_SEF_AVX512DQ __BIT(17) /* AVX-512 Double/Quadword */
424#define CPUID_SEF_RDSEED __BIT(18) /* RDSEED instruction */
425#define CPUID_SEF_ADX __BIT(19) /* ADCX/ADOX instructions */
426#define CPUID_SEF_SMAP __BIT(20) /* Supervisor-Mode Access Prevention */
427#define CPUID_SEF_AVX512_IFMA __BIT(21) /* AVX-512 Integer Fused Multiply Add */
428/* Bit 22 was PCOMMIT */
429#define CPUID_SEF_CLFLUSHOPT __BIT(23) /* Cache Line FLUSH OPTimized */
430#define CPUID_SEF_CLWB __BIT(24) /* Cache Line Write Back */
431#define CPUID_SEF_PT __BIT(25) /* Processor Trace */
432#define CPUID_SEF_AVX512PF __BIT(26) /* AVX-512 PreFetch */
433#define CPUID_SEF_AVX512ER __BIT(27) /* AVX-512 Exponential and Reciprocal */
434#define CPUID_SEF_AVX512CD __BIT(28) /* AVX-512 Conflict Detection */
435#define CPUID_SEF_SHA __BIT(29) /* SHA Extensions */
436#define CPUID_SEF_AVX512BW __BIT(30) /* AVX-512 Byte and Word */
437#define CPUID_SEF_AVX512VL __BIT(31) /* AVX-512 Vector Length */
438
439#define CPUID_SEF_FLAGS "\20" \
440 "\1" "FSGSBASE" "\2" "TSCADJUST" "\3" "SGX" "\4" "BMI1" \
441 "\5" "HLE" "\6" "AVX2" "\7" "FDPEXONLY" "\10" "SMEP" \
442 "\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \
443 "\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \
444 "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \
445 "\25" "SMAP" "\26" "AVX512_IFMA" "\30" "CLFLUSHOPT" \
446 "\31" "CLWB" "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \
447 "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\40" "AVX512VL"
448
449/* %ecx = 0, %ecx */
450#define CPUID_SEF_PREFETCHWT1 __BIT(0) /* PREFETCHWT1 instruction */
451#define CPUID_SEF_AVX512_VBMI __BIT(1) /* AVX-512 Vector Byte Manipulation */
452#define CPUID_SEF_UMIP __BIT(2) /* User-Mode Instruction prevention */
453#define CPUID_SEF_PKU __BIT(3) /* Protection Keys for User-mode pages */
454#define CPUID_SEF_OSPKE __BIT(4) /* OS has set CR4.PKE to ena. protec. keys */
455#define CPUID_SEF_WAITPKG __BIT(5) /* TPAUSE,UMONITOR,UMWAIT */
456#define CPUID_SEF_AVX512_VBMI2 __BIT(6) /* AVX-512 Vector Byte Manipulation 2 */
457#define CPUID_SEF_CET_SS __BIT(7) /* CET Shadow Stack */
458#define CPUID_SEF_GFNI __BIT(8) /* Galois Field instructions */
459#define CPUID_SEF_VAES __BIT(9) /* Vector AES instruction set */
460#define CPUID_SEF_VPCLMULQDQ __BIT(10) /* CLMUL instruction set */
461#define CPUID_SEF_AVX512_VNNI __BIT(11) /* Vector Neural Network Instruction */
462#define CPUID_SEF_AVX512_BITALG __BIT(12) /* BITALG instructions */
463#define CPUID_SEF_TME_EN __BIT(13) /* Total Memory Encryption */
464#define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14) /* Vector Population Count D/Q */
465#define CPUID_SEF_LA57 __BIT(16) /* 57bit linear addr & 5LVL paging */
466#define CPUID_SEF_MAWAU __BITS(21, 17) /* MAWAU for BND{LD,ST}X */
467#define CPUID_SEF_RDPID __BIT(22) /* RDPID and IA32_TSC_AUX */
468#define CPUID_SEF_KL __BIT(23) /* Key Locker */
469#define CPUID_SEF_BUS_LOCK_DETECT __BIT(24) /* OS bus-lock detection */
470#define CPUID_SEF_CLDEMOTE __BIT(25) /* Cache line demote */
471#define CPUID_SEF_MOVDIRI __BIT(27) /* MOVDIRI instruction */
472#define CPUID_SEF_MOVDIR64B __BIT(28) /* MOVDIR64B instruction */
473#define CPUID_SEF_ENQCMD __BIT(29) /* Enqueue Stores */
474#define CPUID_SEF_SGXLC __BIT(30) /* SGX Launch Configuration */
475#define CPUID_SEF_PKS __BIT(31) /* Protection Keys for kern-mode pages */
476
477#define CPUID_SEF_FLAGS1 "\177\20" \
478 "b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0" \
479 "b\4OSPKE\0" "b\5WAITPKG\0" "b\6AVX512_VBMI2\0" "b\7CET_SS\0" \
480 "b\10GFNI\0" "b\11VAES\0" "b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\
481 "b\14AVX512_BITALG\0" "b\15TME_EN\0" "b\16AVX512_VPOPCNTDQ\0" \
482 "b\20LA57\0" \
483 "f\21\5MAWAU\0" "b\26RDPID\0" "b\27KL\0" \
484 "b\30BUS_LOCK_DETECT\0" "b\31CLDEMOTE\0" "b\33MOVDIRI\0" \
485 "b\34MOVDIR64B\0" "b\35ENQCMD\0" "b\36SGXLC\0" "b\37PKS\0"
486
487/* %ecx = 0, %edx */
488#define CPUID_SEF_SGX_KEYS __BIT(1) /* Attestation support for SGX */
489#define CPUID_SEF_AVX512_4VNNIW __BIT(2) /* AVX512 4-reg Neural Network ins */
490#define CPUID_SEF_AVX512_4FMAPS __BIT(3) /* AVX512 4-reg Mult Accum Single precision */
491#define CPUID_SEF_FSRM __BIT(4) /* Fast Short Rep Move */
492#define CPUID_SEF_UINTR __BIT(5) /* User Interrupts */
493#define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8) /* AVX512 VP2INTERSECT */
494#define CPUID_SEF_SRBDS_CTRL __BIT(9) /* IA32_MCU_OPT_CTRL */
495#define CPUID_SEF_MD_CLEAR __BIT(10) /* VERW clears CPU buffers */
496#define CPUID_SEF_RTM_ALWAYS_ABORT __BIT(11) /* XBEGIN immediately abort */
497#define CPUID_SEF_RTM_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */
498#define CPUID_SEF_SERIALIZE __BIT(14) /* SERIALIZE instruction */
499#define CPUID_SEF_HYBRID __BIT(15) /* Hybrid part */
500#define CPUID_SEF_TSXLDTRK __BIT(16) /* TSX suspend load addr tracking */
501#define CPUID_SEF_PCONFIG __BIT(18) /* Platform CONFIGuration */
502#define CPUID_SEF_ARCH_LBR __BIT(19) /* Architectural LBR */
503#define CPUID_SEF_CET_IBT __BIT(20) /* CET Indirect Branch Tracking */
504#define CPUID_SEF_AMX_BF16 __BIT(22) /* AMX bfloat16 */
505#define CPUID_SEF_AVX512_FP16 __BIT(23) /* AVX512 FP16 */
506#define CPUID_SEF_AMX_TILE __BIT(24) /* Tile architecture */
507#define CPUID_SEF_AMX_INT8 __BIT(25) /* AMX 8bit interger */
508#define CPUID_SEF_IBRS __BIT(26) /* IBRS / IBPB Speculation Control */
509#define CPUID_SEF_STIBP __BIT(27) /* STIBP Speculation Control */
510#define CPUID_SEF_L1D_FLUSH __BIT(28) /* IA32_FLUSH_CMD MSR */
511#define CPUID_SEF_ARCH_CAP __BIT(29) /* IA32_ARCH_CAPABILITIES */
512#define CPUID_SEF_CORE_CAP __BIT(30) /* IA32_CORE_CAPABILITIES */
513#define CPUID_SEF_SSBD __BIT(31) /* Speculative Store Bypass Disable */
514
515#define CPUID_SEF_FLAGS2 "\20" \
516 "\2SGX_KEYS" "\3AVX512_4VNNIW" "\4AVX512_4FMAPS" \
517 "\5FSRM" "\6UINTR" \
518 "\11VP2INTERSECT" "\12SRBDS_CTRL" "\13MD_CLEAR" "\14RTM_ALWAYS_ABORT" \
519 "\16RTM_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID" \
520 "\21" "TSXLDTRK" "\23" "PCONFIG" "\24" "ARCH_LBR" \
521 "\25CET_IBT" "\27AMX_BF16" "\30AVX512_FP16" \
522 "\31AMX_TILE" "\32AMX_INT8" "\33IBRS" "\34STIBP" \
523 "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP" "\40" "SSBD"
524
525/* %ecx = 1, %eax */
526#define CPUID_SEF_AVXVNNI __BIT(4) /* AVX version of VNNI */
527#define CPUID_SEF_AVX512_BF16 __BIT(5)
528#define CPUID_SEF_FZLRMS __BIT(10) /* fast zero-length REP MOVSB */
529#define CPUID_SEF_FSRSB __BIT(11) /* fast short REP STOSB */
530#define CPUID_SEF_FSRCS __BIT(12) /* fast short REP CMPSB, REP SCASB */
531#define CPUID_SEF_HRESET __BIT(22) /* HREST & IA32_HRESET_ENABLE MSR */
532#define CPUID_SEF_LAM __BIT(26) /* Linear Address Masking */
533
534#define CPUID_SEF1_FLAGS_A "\20" \
535 "\5" "AVXVNNI" "\6" "AVX512_BF16" \
536 "\13" "FZLRMS" "\14" "FSRSB" \
537 "\15" "FSRCS" "\27" "HRESET" \
538 "\31" "LAM"
539
540/* %ecx = 1, %ebx */
541#define CPUID_SEF_INTEL_PPIN __BIT(0) /* IA32_PPIN & IA32_PPIN_CTL MSRs */
542
543#define CPUID_SEF1_FLAGS_B "\20" \
544 "\1" "PPIN"
545
546/* %ecx = 1, %edx */
547#define CPUID_SEF_CET_SSS __BIT(18) /* CET Supervisor Shadow Stack */
548
549#define CPUID_SEF1_FLAGS_D "\20" \
550 "\23CET_SSS"
551
552/* %ecx = 2, %edx */
553#define CPUID_SEF_PSFD __BIT(0) /* Fast Forwarding Predictor Dis. */
554#define CPUID_SEF_IPRED_CTRL __BIT(1) /* IPRED_DIS */
555#define CPUID_SEF_RRSBA_CTRL __BIT(2) /* RRSBA for CPL3 */
556#define CPUID_SEF_DDPD_U __BIT(3) /* Data Dependent Prefetcher */
557#define CPUID_SEF_BHI_CTRL __BIT(4) /* BHI_DIS_S */
558#define CPUID_SEF_MCDT_NO __BIT(5) /* !MXCSR Config Dependent Timing */
559
560#define CPUID_SEF2_FLAGS_D "\20" \
561 "\1PSFD" "\2IPRED_CTRL" "\3RRSBA_CTRL" "\4DDPD_U" \
562 "\5BHI_CTRL" "\6MCDT_NO"
563
564/*
565 * Intel CPUID Architectural Performance Monitoring.
566 * CPUID Fn0000000a
567 *
568 * See also src/usr.sbin/tprof/arch/tprof_x86.c
569 */
570
571/* %eax */
572#define CPUID_PERF_VERSION __BITS(7, 0) /* Version ID */
573#define CPUID_PERF_NGPPC __BITS(15, 8) /* Num of G.P. perf counter */
574#define CPUID_PERF_NBWGPPC __BITS(23, 16) /* Bit width of G.P. perfcnt */
575#define CPUID_PERF_BVECLEN __BITS(31, 24) /* Length of EBX bit vector */
576
577#define CPUID_PERF_FLAGS0 "\177\20" \
578 "f\0\10VERSION\0" "f\10\10GPCounter\0" \
579 "f\20\10GPBitwidth\0" "f\30\10Vectorlen\0"
580
581/* %ebx */
582#define CPUID_PERF_CORECYCL __BIT(0) /* No core cycle */
583#define CPUID_PERF_INSTRETRY __BIT(1) /* No instruction retried */
584#define CPUID_PERF_REFCYCL __BIT(2) /* No reference cycles */
585#define CPUID_PERF_LLCREF __BIT(3) /* No LLCache reference */
586#define CPUID_PERF_LLCMISS __BIT(4) /* No LLCache miss */
587#define CPUID_PERF_BRINSRETR __BIT(5) /* No branch inst. retried */
588#define CPUID_PERF_BRMISPRRETR __BIT(6) /* No branch mispredict retry */
589#define CPUID_PERF_TOPDOWNSLOT __BIT(7) /* No top-down slots */
590
591#define CPUID_PERF_FLAGS1 "\177\20" \
592 "b\0CORECYCL\0" "b\1INST\0" "b\2REFCYCL\0" "b\3LLCREF\0" \
593 "b\4LLCMISS\0" "b\5BRINST\0" "b\6BRMISPR\0" "b\7TOPDOWNSLOT\0"
594
595/* %ecx */
596
597#define CPUID_PERF_FLAGS2 "\177\20" \
598 "b\0INST\0" "b\1CLK_CORETHREAD\0" "b\2CLK_REF_TSC\0" "b\3TOPDOWNSLOT\0"
599
600/* %edx */
601#define CPUID_PERF_NFFPC __BITS(4, 0) /* Num of fixed-funct perfcnt */
602#define CPUID_PERF_NBWFFPC __BITS(12, 5) /* Bit width of fixed-func pc */
603#define CPUID_PERF_ANYTHREADDEPR __BIT(15) /* Any Thread deprecation */
604
605#define CPUID_PERF_FLAGS3 "\177\20" \
606 "f\0\5FixedFunc\0" "f\5\10FFBitwidth\0" "b\17ANYTHREADDEPR\0"
607
608/*
609 * Intel/AMD CPUID Extended Topology Enumeration.
610 * CPUID Fn0000000b
611 * %ecx == level number
612 * %eax: See below.
613 * %ebx: Number of logical processors at this level.
614 * %ecx: See below.
615 * %edx: x2APIC ID of the current logical processor.
616 */
617/* %eax */
618#define CPUID_TOP_SHIFTNUM __BITS(4, 0) /* Topology ID shift value */
619/* %ecx */
620#define CPUID_TOP_LVLNUM __BITS(7, 0) /* Level number */
621#define CPUID_TOP_LVLTYPE __BITS(15, 8) /* Level type */
622#define CPUID_TOP_LVLTYPE_INVAL 0 /* Invalid */
623#define CPUID_TOP_LVLTYPE_SMT 1 /* SMT */
624#define CPUID_TOP_LVLTYPE_CORE 2 /* Core */
625
626/*
627 * Intel/AMD CPUID Processor extended state Enumeration.
628 * CPUID Fn0000000d
629 *
630 * %ecx == 0: supported features info:
631 * %eax: Valid bits of lower 32bits of XCR0
632 * %ebx: Maximum save area size for features enabled in XCR0
633 * %ecx: Maximum save area size for all cpu features
634 * %edx: Valid bits of upper 32bits of XCR0
635 *
636 * %ecx == 1:
637 * %eax: See below
638 * %ebx: Save area size for features enabled by XCR0 | IA32_XSS
639 * %ecx: Valid bits of lower 32bits of IA32_XSS
640 * %edx: Valid bits of upper 32bits of IA32_XSS
641 *
642 * %ecx >= 2: Save area details for XCR0 bit n
643 * %eax: size of save area for this feature
644 * %ebx: offset of save area for this feature
645 * %ecx, %edx: reserved
646 * All of %eax, %ebx, %ecx and %edx are zero for unsupported features.
647 */
648
649/* %ecx = 1, %eax */
650#define CPUID_PES1_XSAVEOPT __BIT(0) /* xsaveopt instruction */
651#define CPUID_PES1_XSAVEC __BIT(1) /* xsavec & compacted XRSTOR */
652#define CPUID_PES1_XGETBV __BIT(2) /* xgetbv with ECX = 1 */
653#define CPUID_PES1_XSAVES __BIT(3) /* xsaves/xrstors, IA32_XSS */
654#define CPUID_PES1_XFD __BIT(4) /* eXtened Feature Disable */
655
656#define CPUID_PES1_FLAGS "\20" \
657 "\1XSAVEOPT" "\2XSAVEC" "\3XGETBV" "\4XSAVES" \
658 "\5XFD"
659
660/*
661 * Intel Deterministic Address Translation Parameter.
662 * CPUID Fn0000_0018
663 */
664
665/* %ecx=0 %eax __BITS(31, 0): the maximum input value of supported sub-leaf */
666
667/* %ebx */
668#define CPUID_DATP_PGSIZE __BITS(3, 0) /* page size */
669#define CPUID_DATP_PGSIZE_4KB __BIT(0) /* 4KB page support */
670#define CPUID_DATP_PGSIZE_2MB __BIT(1) /* 2MB page support */
671#define CPUID_DATP_PGSIZE_4MB __BIT(2) /* 4MB page support */
672#define CPUID_DATP_PGSIZE_1GB __BIT(3) /* 1GB page support */
673#define CPUID_DATP_PARTITIONING __BITS(10, 8) /* Partitioning */
674#define CPUID_DATP_WAYS __BITS(31, 16) /* Ways of associativity */
675
676/* Number of sets: %ecx */
677
678/* %edx */
679#define CPUID_DATP_TCTYPE __BITS(4, 0) /* Translation Cache type */
680#define CPUID_DATP_TCTYPE_N 0 /* NULL (not valid) */
681#define CPUID_DATP_TCTYPE_D 1 /* Data TLB */
682#define CPUID_DATP_TCTYPE_I 2 /* Instruction TLB */
683#define CPUID_DATP_TCTYPE_U 3 /* Unified TLB */
684#define CPUID_DATP_TCTYPE_L 4 /* Load only TLB */
685#define CPUID_DATP_TCTYPE_S 5 /* Store only TLB */
686#define CPUID_DATP_TCLEVEL __BITS(7, 5) /* TLB level (start at 1) */
687#define CPUID_DATP_FULLASSOC __BIT(8) /* Full associative */
688#define CPUID_DATP_SHARING __BITS(25, 14) /* sharing */
689
690/*
691 * Intel Native Model ID Information Enumeration.
692 * CPUID Fn0000_001a
693 */
694/* %eax */
695#define CPUID_HYBRID_NATIVEID __BITS(23, 0) /* Native model ID */
696#define CPUID_HYBRID_CORETYPE __BITS(31, 24) /* Core type */
697#define CPUID_HYBRID_CORETYPE_ATOM 0x20 /* Atom */
698#define CPUID_HYBRID_CORETYPE_CORE 0x40 /* Core */
699
700/*
701 * Intel Tile Information
702 * CPUID Fn0000_001d
703 * %ecx == 0: Main leaf
704 * %eax: max_palette
705 * %ecx == 1: Tile Palette1 Sub-leaf
706 * Tile palette 1
707 */
708
709/* %ecx */
710#define CPUID_TILE_P1_TOTAL_B __BITS(15, 0)
711#define CPUID_TILE_P1_B_PERTILE __BITS(31, 16)
712#define CPUID_TILE_P1_B_PERLOW __BITS(15, 0)
713#define CPUID_TILE_P1_MAXNAMES __BITS(31, 16)
714#define CPUID_TILE_P1_MAXROWS __BITS(15, 0)
715
716/*
717 * Intel TMUL Information
718 * CPUID Fn0000_001e
719 */
720
721/* %ebx */
722#define CPUID_TMUL_MAXK __BITS(7, 0) /* Rows or columns */
723#define CPUID_TMUL_MAXN __BITS(23, 8) /* Column bytes */
724
725/*
726 * Intel extended features.
727 * CPUID Fn80000001
728 */
729/* %edx */
730#define CPUID_SYSCALL __BIT(11) /* SYSCALL/SYSRET */
731#define CPUID_XD __BIT(20) /* Execute Disable (like CPUID_NOX) */
732#define CPUID_PAGE1GB __BIT(26) /* 1GB Large Page Support */
733#define CPUID_RDTSCP __BIT(27) /* Read TSC Pair Instruction */
734#define CPUID_EM64T __BIT(29) /* Intel EM64T */
735
736#define CPUID_INTEL_EXT_FLAGS "\20" \
737 "\14" "SYSCALL/SYSRET" "\25" "XD" "\33" "P1GB" \
738 "\34" "RDTSCP" "\36" "EM64T"
739
740/* %ecx */
741#define CPUID_LAHF __BIT(0) /* LAHF/SAHF in IA-32e mode, 64bit sub*/
742 /* __BIT(5) */ /* LZCNT. Same as AMD's CPUID_ABM */
743#define CPUID_PREFETCHW __BIT(8) /* PREFETCHW */
744
745#define CPUID_INTEL_FLAGS4 "\20" \
746 "\1" "LAHF" "\02" "B01" "\03" "B02" \
747 "\06" "LZCNT" \
748 "\11" "PREFETCHW"
749
750
751/*
752 * AMD/VIA extended features.
753 * CPUID Fn80000001
754 */
755/* %edx */
756/* CPUID_SYSCALL SYSCALL/SYSRET */
757#define CPUID_MPC 0x00080000 /* Multiprocessing Capable */
758#define CPUID_NOX 0x00100000 /* No Execute Page Protection */
759#define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */
760/* CPUID_MMX MMX supported */
761/* CPUID_FXSR fast FP/MMX save/restore */
762#define CPUID_FFXSR 0x02000000 /* FXSAVE/FXSTOR Extensions */
763/* CPUID_PAGE1GB 1GB Large Page Support */
764/* CPUID_RDTSCP Read TSC Pair Instruction */
765/* CPUID_EM64T Long mode */
766#define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */
767#define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */
768
769#define CPUID_EXT_FLAGS "\20" \
770 "\14" "SYSCALL/SYSRET" \
771 "\24" "MPC" \
772 "\25" "NOX" "\27" "MMXX" "\30" "MMX" \
773 "\31" "FXSR" "\32" "FFXSR" "\33" "P1GB" "\34" "RDTSCP" \
774 "\36" "LONG" "\37" "3DNOW2" "\40" "3DNOW"
775
776/* %ecx (AMD) */
777/* CPUID_LAHF LAHF/SAHF instruction */
778#define CPUID_CMPLEGACY __BIT(1) /* Compare Legacy */
779#define CPUID_SVM __BIT(2) /* Secure Virtual Machine */
780#define CPUID_EAPIC __BIT(3) /* Extended APIC space */
781#define CPUID_ALTMOVCR0 __BIT(4) /* Lock Mov Cr0 */
782#define CPUID_ABM __BIT(5) /* LZCNT instruction */
783#define CPUID_SSE4A __BIT(6) /* SSE4A instruction set */
784#define CPUID_MISALIGNSSE __BIT(7) /* Misaligned SSE */
785#define CPUID_3DNOWPF __BIT(8) /* 3DNow Prefetch */
786#define CPUID_OSVW __BIT(9) /* OS visible workarounds */
787#define CPUID_IBS __BIT(10) /* Instruction Based Sampling */
788#define CPUID_XOP __BIT(11) /* XOP instruction set */
789#define CPUID_SKINIT __BIT(12) /* SKINIT */
790#define CPUID_WDT __BIT(13) /* watchdog timer support */
791#define CPUID_LWP __BIT(15) /* Light Weight Profiling */
792#define CPUID_FMA4 __BIT(16) /* FMA4 instructions */
793#define CPUID_TCE __BIT(17) /* Translation cache Extension */
794#define CPUID_NODEID __BIT(19) /* NodeID MSR available */
795#define CPUID_TBM __BIT(21) /* TBM instructions */
796#define CPUID_TOPOEXT __BIT(22) /* cpuid Topology Extension */
797#define CPUID_PCEC __BIT(23) /* Perf Ctr Ext Core */
798#define CPUID_PCENB __BIT(24) /* Perf Ctr Ext NB */
799#define CPUID_SPM __BIT(25) /* Stream Perf Mon */
800#define CPUID_DBE __BIT(26) /* Data Breakpoint Extension */
801#define CPUID_PTSC __BIT(27) /* PerfTsc */
802#define CPUID_L2IPERFC __BIT(28) /* L2I performance counter Extension */
803#define CPUID_MWAITX __BIT(29) /* MWAITX/MONITORX support */
804#define CPUID_ADDRMASKEXT __BIT(30) /* Breakpoint Addressing Mask ext. */
805
806#define CPUID_AMD_FLAGS4 "\20" \
807 "\1" "LAHF" "\2" "CMPLEGACY" "\3" "SVM" "\4" "EAPIC" \
808 "\5" "ALTMOVCR0" "\6" "LZCNT" "\7" "SSE4A" "\10" "MISALIGNSSE" \
809 "\11" "3DNOWPREFETCH" \
810 "\12" "OSVW" "\13" "IBS" "\14" "XOP" \
811 "\15" "SKINIT" "\16" "WDT" "\17" "B14" "\20" "LWP" \
812 "\21" "FMA4" "\22" "TCE" "\23" "B18" "\24" "NodeID" \
813 "\25" "B20" "\26" "TBM" "\27" "TopoExt" "\30" "PCExtC" \
814 "\31" "PCExtNB" "\32" "StrmPM" "\33" "DBExt" "\34" "PerfTsc" \
815 "\35" "L2IPERFC" "\36" "MWAITX" "\37" "AddrMaskExt" "\40" "B31"
816
817/*
818 * Advanced Power Management and RAS.
819 * CPUID Fn8000_0007
820 *
821 * Only ITSC is for both Intel and AMD. Others are only for AMD.
822 *
823 * %ebx: RAS capabilities. See below.
824 * %ecx: Processor Power Monitoring Interface.
825 * %edx: See below.
826 *
827 */
828/* %ebx */
829#define CPUID_RAS_OVFL_RECOV __BIT(0) /* MCA Overflow Recovery */
830#define CPUID_RAS_SUCCOR __BIT(1) /* Sw UnCorr. err. COntainment & Recovery */
831#define CPUID_RAS_MCAX __BIT(3) /* MCA Extension */
832
833#define CPUID_RAS_FLAGS "\20" \
834 "\1OVFL_RECOV" "\2SUCCOR" "\4" "MCAX"
835
836/* %edx */
837#define CPUID_APM_TS __BIT(0) /* Temperature Sensor */
838#define CPUID_APM_FID __BIT(1) /* Frequency ID control */
839#define CPUID_APM_VID __BIT(2) /* Voltage ID control */
840#define CPUID_APM_TTP __BIT(3) /* THERMTRIP (PCI F3xE4 register) */
841#define CPUID_APM_HTC __BIT(4) /* Hardware thermal control (HTC) */
842#define CPUID_APM_STC __BIT(5) /* Software thermal control (STC) */
843#define CPUID_APM_100 __BIT(6) /* 100MHz multiplier control */
844#define CPUID_APM_HWP __BIT(7) /* HW P-State control */
845#define CPUID_APM_ITSC __BIT(8) /* Invariant TSC */
846#define CPUID_APM_CPB __BIT(9) /* Core Performance Boost */
847#define CPUID_APM_EFF __BIT(10) /* Effective Frequency (read-only) */
848#define CPUID_APM_PROCFI __BIT(11) /* Processor Feedback Interface */
849#define CPUID_APM_PROCPR __BIT(12) /* Processor Power Reporting */
850#define CPUID_APM_CONNSTBY __BIT(13) /* Connected Standby */
851#define CPUID_APM_RAPL __BIT(14) /* Running Average Power Limit */
852
853#define CPUID_APM_FLAGS "\20" \
854 "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \
855 "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \
856 "\11" "ITSC" "\12" "CPB" "\13" "EffFreq" "\14" "PROCFI" \
857 "\15" "PROCPR" "\16" "CONNSTBY" "\17" "RAPL"
858
859/*
860 * AMD Processor Capacity Parameters and Extended Features.
861 * CPUID Fn8000_0008
862 * %eax: Long Mode Size Identifiers
863 * %ebx: Extended Feature Identifiers
864 * %ecx: Size Identifiers
865 * %edx: RDPRU Register Identifier Range
866 */
867
868/* %ebx */
869#define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */
870#define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */
871#define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */
872#define CPUID_CAPEX_INVLPGB __BIT(3) /* INVLPGB instruction */
873#define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */
874#define CPUID_CAPEX_MBE __BIT(6) /* Memory Bandwidth Enforcement */
875#define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */
876#define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */
877#define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */
878#define CPUID_CAPEX_INT_WBINVD __BIT(13) /* Interruptable WB[NO]INVD */
879#define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */
880#define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */
881#define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */
882#define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */
883#define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */
884#define CPUID_CAPEX_IBRS_SAMEMODE __BIT(19) /* IBRS same speculation limits */
885#define CPUID_CAPEX_EFER_LSMSLE_UN __BIT(20) /* EFER.LMSLE is unsupported */
886#define CPUID_CAPEX_AMD_PPIN __BIT(23) /* Protected Processor Inventory Number */
887#define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */
888#define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */
889#define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */
890#define CPUID_CAPEX_CPPC __BIT(27) /* Collaborative Processor Perf. Control */
891#define CPUID_CAPEX_PSFD __BIT(28) /* Predictive Store Forward Dis */
892#define CPUID_CAPEX_BTC_NO __BIT(29) /* Branch Type Confusion NO */
893#define CPUID_CAPEX_IBPB_RET __BIT(30) /* Clear RET address predictor */
894
895#define CPUID_CAPEX_FLAGS "\20" \
896 "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" "\4INVLPGB" \
897 "\5RDPRU" "\7MBE" \
898 "\11MCOMMIT" "\12WBNOINVD" "\13B10" \
899 "\15IBPB" "\16INT_WBINVD" "\17IBRS" "\20STIBP" \
900 "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" \
901 "\24IBRS_SAMEMODE" \
902 "\25EFER_LSMSLE_UN" "\30PPIN" \
903 "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO" "\34CPPC" \
904 "\35PSFD" "\36BTC_NO" "\37IBPB_RET"
905
906/* %ecx */
907#define CPUID_CAPEX_PerfTscSize __BITS(17,16) /* Perf. tstamp counter size */
908#define CPUID_CAPEX_ApicIdSize __BITS(15,12) /* APIC ID Size */
909#define CPUID_CAPEX_NC __BITS(7,0) /* Number of threads - 1 */
910
911/*
912 * AMD SVM Revision and Feature.
913 * CPUID Fn8000_000a
914 */
915
916/* %eax: SVM revision */
917#define CPUID_AMD_SVM_REV __BITS(7,0)
918
919/* %edx: SVM features */
920#define CPUID_AMD_SVM_NP __BIT(0) /* Nested Paging */
921#define CPUID_AMD_SVM_LbrVirt __BIT(1) /* LBR virtualization */
922#define CPUID_AMD_SVM_SVML __BIT(2) /* SVM Lock */
923#define CPUID_AMD_SVM_NRIPS __BIT(3) /* NRIP Save on #VMEXIT */
924#define CPUID_AMD_SVM_TSCRateCtrl __BIT(4) /* MSR-based TSC rate ctrl */
925#define CPUID_AMD_SVM_VMCBCleanBits __BIT(5) /* VMCB Clean Bits support */
926#define CPUID_AMD_SVM_FlushByASID __BIT(6) /* Flush by ASID */
927#define CPUID_AMD_SVM_DecodeAssist __BIT(7) /* Decode Assists support */
928#define CPUID_AMD_SVM_PauseFilter __BIT(10) /* PAUSE intercept filter */
929#define CPUID_AMD_SVM_PFThreshold __BIT(12) /* PAUSE filter threshold */
930#define CPUID_AMD_SVM_AVIC __BIT(13) /* Advanced Virt. Intr. Ctrl */
931#define CPUID_AMD_SVM_V_VMSAVE_VMLOAD __BIT(15) /* Virtual VM{SAVE/LOAD} */
932#define CPUID_AMD_SVM_vGIF __BIT(16) /* Virtualized GIF */
933#define CPUID_AMD_SVM_GMET __BIT(17) /* Guest Mode Execution Trap */
934#define CPUID_AMD_SVM_X2AVIC __BIT(18) /* Virt. Intr. Ctrl 4 x2APIC */
935#define CPUID_AMD_SVM_SSSCHECK __BIT(19) /* Shadow Stack restrictions */
936#define CPUID_AMD_SVM_SPEC_CTRL __BIT(20) /* SPEC_CTRL virtualization */
937#define CPUID_AMD_SVM_ROGPT __BIT(21) /* Read-Only Guest PTable */
938#define CPUID_AMD_SVM_HOST_MCE_OVERRIDE __BIT(23) /* #MC intercept */
939#define CPUID_AMD_SVM_TLBICTL __BIT(24) /* TLB Intercept Control */
940#define CPUID_AMD_SVM_VNMI __BIT(25) /* NMI Virtualization */
941#define CPUID_AMD_SVM_IBSVIRT __BIT(26) /* IBS Virtualization */
942#define CPUID_AMD_SVM_XLVTOFFFLTCHG __BIT(27) /* Ext LVToffset FLT changed */
943#define CPUID_AMD_SVM_VMCBADRCHKCHG __BIT(28) /* VMCB addr check changed */
944#define CPUID_AMD_SVM_BUSLOCKTHRESH __BIT(29) /* Bus Lock Threshold */
945
946
947#define CPUID_AMD_SVM_FLAGS "\20" \
948 "\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \
949 "\5" "TSCRate" "\6" "VMCBCleanBits" \
950 "\7" "FlushByASID" "\10" "DecodeAssist" \
951 "\11" "B08" "\12" "B09" "\13" "PauseFilter" "\14" "B11" \
952 "\15" "PFThreshold" "\16" "AVIC" "\17" "B14" \
953 "\20" "V_VMSAVE_VMLOAD" \
954 "\21" "VGIF" "\22" "GMET" "\23x2AVIC" "\24SSSCHECK" \
955 "\25" "SPEC_CTRL" "\26" "ROGPT" "\30HOST_MCE_OVERRIDE" \
956 "\31" "TLBICTL" "\32VNMI" "\33IBSVIRT" "\34ExtLvtOffsetFaultChg" \
957 "\35VmcbAddrChkChg" "\36BusLockThreshold"
958
959/*
960 * AMD Instruction-Based Sampling Capabilities.
961 * CPUID Fn8000_001b
962 */
963/* %eax */
964#define CPUID_IBS_FFV __BIT(0) /* Feature Flags Valid */
965#define CPUID_IBS_FETCHSUM __BIT(1) /* Fetch Sampling */
966#define CPUID_IBS_OPSAM __BIT(2) /* execution SAMpling */
967#define CPUID_IBS_RDWROPCNT __BIT(3) /* Read Write of Op Counter */
968#define CPUID_IBS_OPCNT __BIT(4) /* OP CouNTing mode */
969#define CPUID_IBS_BRNTRGT __BIT(5) /* Branch Target */
970#define CPUID_IBS_OPCNTEXT __BIT(6) /* OpCurCnt and OpMaxCnt extended */
971#define CPUID_IBS_RIPINVALIDCHK __BIT(7) /* Invalid RIP indication */
972#define CPUID_IBS_OPBRNFUSE __BIT(8) /* Fused branch micro-op indicate */
973#define CPUID_IBS_FETCHCTLEXTD __BIT(9) /* IC_IBS_EXTD_CTL MSR */
974#define CPUID_IBS_OPDATA4 __BIT(10) /* IBS op data 4 MSR */
975#define CPUID_IBS_L3MISSFILT __BIT(11) /* L3 Miss Filtering */
976
977#define CPUID_IBS_FLAGS "\20" \
978 "\1IBSFFV" "\2FetchSam" "\3OpSam" "\4RdWrOpCnt" \
979 "\5OpCnt" "\6BrnTrgt" "\7OpCntExt" "\10RipInvalidChk" \
980 "\11OpBrnFuse" "\12IbsFetchCtlExtd" "\13IbsOpData4" \
981 "\14IbsL3MissFiltering"
982
983/*
984 * AMD Cache Topology Information.
985 * CPUID Fn8000_001d
986 * It's almost the same as Intel Deterministic Cache Parameter Leaf(0x04)
987 * except the following:
988 * No Cores/package (%eax bit 31..26)
989 * No Complex cache indexing (%edx bit 2)
990 */
991
992/*
993 * AMD Processor Topology Information.
994 * CPUID Fn8000_001e
995 * %eax: Extended APIC ID.
996 * %ebx: Core Identifiers.
997 * %ecx: Node Identifiers.
998 */
999
1000/* %ebx */
1001#define CPUID_AMD_PROCT_COREID __BITS(7,0) /* Core ID */
1002#define CPUID_AMD_PROCT_THREADS_PER_CORE __BITS(15,8) /* Threads/Core - 1 */
1003
1004/* %ecx */
1005#define CPUID_AMD_PROCT_NODEID __BITS(7,0) /* Node ID */
1006#define CPUID_AMD_PROCT_NODE_PER_PROCESSOR __BITS(10,8) /* Node/Processor -1 */
1007
1008/*
1009 * AMD Encrypted Memory Capabilities.
1010 * CPUID Fn8000_001f
1011 * %eax: flags
1012 * %ebx: 5-0: Cbit Position
1013 * 11-6: PhysAddrReduction
1014 * 15-12: NumVMPL
1015 * %ecx: 31-0: NumEncryptedGuests
1016 * %edx: 31-0: MinSevNoEsAsid
1017 */
1018#define CPUID_AMD_ENCMEM_SME __BIT(0) /* Secure Memory Encryption */
1019#define CPUID_AMD_ENCMEM_SEV __BIT(1) /* Secure Encrypted Virtualiz. */
1020#define CPUID_AMD_ENCMEM_PGFLMSR __BIT(2) /* Page Flush MSR */
1021#define CPUID_AMD_ENCMEM_SEVES __BIT(3) /* SEV Encrypted State */
1022#define CPUID_AMD_ENCMEM_SEV_SNP __BIT(4) /* Secure Nested Paging */
1023#define CPUID_AMD_ENCMEM_VMPL __BIT(5) /* Virtual Machine Privilege Lvl */
1024#define CPUID_AMD_ENCMEM_RMPQUERY __BIT(6) /* RMPQUERY instruction */
1025#define CPUID_AMD_ENCMEM_VMPLSSS __BIT(7) /* VMPL Secure Shadow Stack */
1026#define CPUID_AMD_ENCMEM_SECTSC __BIT(8) /* Secure TSC */
1027#define CPUID_AMD_ENCMEM_TSCAUX_V __BIT(9) /* TSC AUX Virtualization */
1028#define CPUID_AMD_ENCMEM_HECC __BIT(10) /* HW Enf Cache Coh across enc dom */
1029#define CPUID_AMD_ENCMEM_64BH __BIT(11) /* 64Bit Host */
1030#define CPUID_AMD_ENCMEM_RSTRINJ __BIT(12) /* Restricted Injection */
1031#define CPUID_AMD_ENCMEM_ALTINJ __BIT(13) /* Alternate Injection */
1032#define CPUID_AMD_ENCMEM_DBGSWAP __BIT(14) /* Debug Swap */
1033#define CPUID_AMD_ENCMEM_PREVHOSTIBS __BIT(15) /* Prevent Host IBS */
1034#define CPUID_AMD_ENCMEM_VTE __BIT(16) /* Virtual Transparent Encryption */
1035
1036#define CPUID_AMD_ENCMEM_VMGEXITP __BIT(17) /* VMGEXIT Parameter */
1037#define CPUID_AMD_ENCMEM_VIRTTOM __BIT(18) /* Virtual TOM MSR */
1038#define CPUID_AMD_ENCMEM_IBSVGUEST __BIT(19) /* IBS Virt. for SEV-ES guest */
1039#define CPUID_AMD_ENCMEM_VMSA_REGPROT __BIT(24) /* VmsaRegProt */
1040#define CPUID_AMD_ENCMEM_SMTPROTECT __BIT(25) /* SMT Protection */
1041#define CPUID_AMD_ENCMEM_SVSM_COMMPAGE __BIT(28) /* SVSM Communication Page */
1042#define CPUID_AMD_ENCMEM_NESTED_VSMP __BIT(29) /* VIRT_{RMPUPDATE,PSMASH} */
1043
1044#define CPUID_AMD_ENCMEM_FLAGS "\20" \
1045 "\1" "SME" "\2" "SEV" "\3" "PageFlushMsr" "\4" "SEV-ES" \
1046 "\5" "SEV-SNP" "\6" "VMPL" "\7RMPQUERY" "\10VmplSSS" \
1047 "\11SecureTSC" "\12TscAuxVirt" "\13HwEnfCacheCoh" "\14" "64BitHost" \
1048 "\15" "RSTRINJ" "\16" "ALTINJ" "\17" "DebugSwap" "\20PreventHostIbs" \
1049 "\21VTE" "\22VmgexitParam" "\23VirtualTomMsr" "\24IbsVirtGuest" \
1050 "\31VmsaRegProt" "\32SmtProtection" \
1051 "\35SvsmCommPageMSR" "\36NestedVirtSnpMsr"
1052
1053/*
1054 * AMD Extended Features 2.
1055 * CPUID Fn8000_0021
1056 */
1057
1058/* %eax */
1059#define CPUID_AMDEXT2_NONESTEDDBP __BIT(0) /* No nested data breakpoints */
1060#define CPUID_AMDEXT2_FGKBNOSERIAL __BIT(1) /* {FS,GS,K}BASE WRMSR !serializ */
1061#define CPUID_AMDEXT2_LFENCESERIAL __BIT(2) /* LFENCE always serializing */
1062#define CPUID_AMDEXT2_SMMPGCFGLCK __BIT(3) /* SMM Paging configuration lock */
1063#define CPUID_AMDEXT2_NULLSELCLRB __BIT(6) /* Null segment selector clr base */
1064#define CPUID_AMDEXT2_UPADDRIGN __BIT(7) /* Upper Address Ignore */
1065#define CPUID_AMDEXT2_AUTOIBRS __BIT(8) /* Automatic IBRS */
1066#define CPUID_AMDEXT2_NOSMMCTL __BIT(9) /* SMM_CTL MSR is not supported */
1067#define CPUID_AMDEXT2_FSRS __BIT(10) /* Fast Short Rep Stosb */
1068#define CPUID_AMDEXT2_FSRC __BIT(11) /* Fast Short Rep Cmpsb */
1069#define CPUID_AMDEXT2_PREFETCHCTL __BIT(13) /* Prefetch control MSR */
1070#define CPUID_AMDEXT2_CPUIDUSRDIS __BIT(17) /* CPUID dis. for non-priv. soft */
1071#define CPUID_AMDEXT2_EPSF __BIT(18) /* Enhanced Predictive Store Fwd */
1072
1073#define CPUID_AMDEXT2_FLAGS "\20" \
1074 "\1NoNestedDataBp" "\2FsGsKernelGsBaseNonSerializing" \
1075 "\3LfenceAlwaysSerialize" "\4SmmPgCfgLock" \
1076 "\7NullSelectClearsBase" "\10UpperAddressIgnore" \
1077 "\11AutomaticIBRS" "\12NoSmmCtlMSR" "\13FSRS" "\14FSRC" \
1078 "\16PrefetchCtlMSR" \
1079 "\22CpuidUserDis" "\23EPSF"
1080
1081/*
1082 * AMD Extended Performance Monitoring and Debug
1083 * CPUID Fn8000_0022
1084 */
1085
1086/* %eax */
1087#define CPUID_AXPERF_PERFMONV2 __BIT(0) /* Version 2 */
1088#define CPUID_AXPERF_LBRSTACK __BIT(1) /* Last Branch Record Stack */
1089#define CPUID_AXPERF_LBRPMCFREEZE __BIT(2) /* Freezing LBR and PMC */
1090
1091#define CPUID_AXPERF_FLAGS "\20" \
1092 "\1PerfMonV2" "\2LbrStack" "\3LbrAndPmcFreeze"
1093
1094/* %ebx */
1095#define CPUID_AXPERF_NCPC __BITS(3, 0) /* Num of Core PMC counters */
1096#define CPUID_AXPERF_NLBRSTACK __BITS(9, 4) /* Num of LBR Stack entries */
1097#define CPUID_AXPERF_NNBPC __BITS(15, 10) /* Num of NorthBridge PMCs */
1098#define CPUID_AXPERF_NUMCPC __BITS(21, 16) /* Num of UMC PMCs */
1099
1100/*
1101 * Centaur Extended Feature flags.
1102 * CPUID FnC000_0001 (VIA "Nehemiah" or later)
1103 */
1104#define CPUID_VIA_HAS_AIS __BIT(0) /* Alternate Instruction Set supported */
1105 /* (VIA "Nehemiah" only) */
1106#define CPUID_VIA_DO_AIS __BIT(1) /* Alternate Instruction Set enabled */
1107 /* (VIA "Nehemiah" only) */
1108#define CPUID_VIA_HAS_RNG __BIT(2) /* Random number generator */
1109#define CPUID_VIA_DO_RNG __BIT(3)
1110#define CPUID_VIA_HAS_ACE __BIT(6) /* AES Encryption */
1111#define CPUID_VIA_DO_ACE __BIT(7)
1112#define CPUID_VIA_HAS_ACE2 __BIT(8) /* AES+CTR instructions */
1113#define CPUID_VIA_DO_ACE2 __BIT(9)
1114#define CPUID_VIA_HAS_PHE __BIT(10) /* SHA1+SHA256 HMAC */
1115#define CPUID_VIA_DO_PHE __BIT(11)
1116#define CPUID_VIA_HAS_PMM __BIT(12) /* RSA Instructions */
1117#define CPUID_VIA_DO_PMM __BIT(13)
1118
1119#define CPUID_FLAGS_PADLOCK "\20" \
1120 "\3" "RNG" "\7" "AES" "\11" "AES/CTR" "\13" "SHA1/SHA256" \
1121 "\15" "RSA"
1122
1123/*
1124 * Model-Specific Registers
1125 */
1126#define MSR_TSC 0x010
1127#define MSR_IA32_PLATFORM_ID 0x017
1128#define MSR_APICBASE 0x01b
1129#define APICBASE_BSP 0x00000100 /* boot processor */
1130#define APICBASE_EXTD 0x00000400 /* x2APIC mode */
1131#define APICBASE_EN 0x00000800 /* software enable */
1132/*
1133 * APICBASE_PHYSADDR is actually variable-sized on some CPUs. But we're
1134 * only interested in the initial value, which is guaranteed to fit the
1135 * first 32 bits. So this macro is fine.
1136 */
1137#define APICBASE_PHYSADDR 0xfffff000 /* physical address */
1138#define MSR_EBL_CR_POWERON 0x02a
1139#define MSR_EBC_FREQUENCY_ID 0x02c /* PIV only */
1140#define MSR_IA32_SPEC_CTRL 0x048
1141#define IA32_SPEC_CTRL_IBRS 0x01
1142#define IA32_SPEC_CTRL_STIBP 0x02
1143#define IA32_SPEC_CTRL_SSBD 0x04
1144#define MSR_IA32_PRED_CMD 0x049
1145#define IA32_PRED_CMD_IBPB 0x01
1146#define MSR_BIOS_UPDT_TRIG 0x079
1147#define MSR_BIOS_SIGN 0x08b
1148#define MSR_PERFCTR0 0x0c1
1149#define MSR_PERFCTR1 0x0c2
1150#define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */
1151#define MSR_MPERF 0x0e7
1152#define MSR_APERF 0x0e8
1153#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
1154#define MSR_MTRRcap 0x0fe
1155#define MSR_IA32_ARCH_CAPABILITIES 0x10a
1156#define IA32_ARCH_RDCL_NO 0x01
1157#define IA32_ARCH_IBRS_ALL 0x02
1158#define IA32_ARCH_RSBA 0x04
1159#define IA32_ARCH_SKIP_L1DFL_VMENTRY 0x08
1160#define IA32_ARCH_SSB_NO 0x10
1161#define IA32_ARCH_MDS_NO 0x20
1162#define IA32_ARCH_IF_PSCHANGE_MC_NO 0x40
1163#define IA32_ARCH_TSX_CTRL 0x80
1164#define IA32_ARCH_TAA_NO 0x100
1165#define MSR_IA32_FLUSH_CMD 0x10b
1166#define IA32_FLUSH_CMD_L1D_FLUSH 0x01
1167#define MSR_TSX_FORCE_ABORT 0x10f
1168#define MSR_IA32_TSX_CTRL 0x122
1169#define IA32_TSX_CTRL_RTM_DISABLE __BIT(0)
1170#define IA32_TSX_CTRL_TSX_CPUID_CLEAR __BIT(1)
1171#define MSR_SYSENTER_CS 0x174 /* PII+ only */
1172#define MSR_SYSENTER_ESP 0x175 /* PII+ only */
1173#define MSR_SYSENTER_EIP 0x176 /* PII+ only */
1174#define MSR_MCG_CAP 0x179
1175#define MSR_MCG_STATUS 0x17a
1176#define MSR_MCG_CTL 0x17b
1177#define MSR_EVNTSEL0 0x186
1178#define MSR_EVNTSEL1 0x187
1179#define MSR_PERF_STATUS 0x198 /* Pentium M */
1180#define MSR_PERF_CTL 0x199 /* Pentium M */
1181#define MSR_THERM_CONTROL 0x19a
1182#define MSR_THERM_INTERRUPT 0x19b
1183#define MSR_THERM_STATUS 0x19c
1184#define MSR_THERM2_CTL 0x19d /* Pentium M */
1185#define MSR_MISC_ENABLE 0x1a0
1186#define IA32_MISC_FAST_STR_EN __BIT(0)
1187#define IA32_MISC_ATCC_EN __BIT(3)
1188#define IA32_MISC_PERFMON_EN __BIT(7)
1189#define IA32_MISC_BTS_UNAVAIL __BIT(11)
1190#define IA32_MISC_PEBS_UNAVAIL __BIT(12)
1191#define IA32_MISC_EISST_EN __BIT(16)
1192#define IA32_MISC_MWAIT_EN __BIT(18)
1193#define IA32_MISC_LIMIT_CPUID __BIT(22)
1194#define IA32_MISC_XTPR_DIS __BIT(23)
1195#define IA32_MISC_XD_DIS __BIT(34)
1196#define MSR_TEMPERATURE_TARGET 0x1a2
1197#define MSR_DEBUGCTLMSR 0x1d9
1198#define MSR_LASTBRANCHFROMIP 0x1db
1199#define MSR_LASTBRANCHTOIP 0x1dc
1200#define MSR_LASTINTFROMIP 0x1dd
1201#define MSR_LASTINTTOIP 0x1de
1202#define MSR_ROB_CR_BKUPTMPDR6 0x1e0
1203#define MSR_MTRRphysBase0 0x200
1204#define MSR_MTRRphysMask0 0x201
1205#define MSR_MTRRphysBase1 0x202
1206#define MSR_MTRRphysMask1 0x203
1207#define MSR_MTRRphysBase2 0x204
1208#define MSR_MTRRphysMask2 0x205
1209#define MSR_MTRRphysBase3 0x206
1210#define MSR_MTRRphysMask3 0x207
1211#define MSR_MTRRphysBase4 0x208
1212#define MSR_MTRRphysMask4 0x209
1213#define MSR_MTRRphysBase5 0x20a
1214#define MSR_MTRRphysMask5 0x20b
1215#define MSR_MTRRphysBase6 0x20c
1216#define MSR_MTRRphysMask6 0x20d
1217#define MSR_MTRRphysBase7 0x20e
1218#define MSR_MTRRphysMask7 0x20f
1219#define MSR_MTRRphysBase8 0x210
1220#define MSR_MTRRphysMask8 0x211
1221#define MSR_MTRRphysBase9 0x212
1222#define MSR_MTRRphysMask9 0x213
1223#define MSR_MTRRphysBase10 0x214
1224#define MSR_MTRRphysMask10 0x215
1225#define MSR_MTRRphysBase11 0x216
1226#define MSR_MTRRphysMask11 0x217
1227#define MSR_MTRRphysBase12 0x218
1228#define MSR_MTRRphysMask12 0x219
1229#define MSR_MTRRphysBase13 0x21a
1230#define MSR_MTRRphysMask13 0x21b
1231#define MSR_MTRRphysBase14 0x21c
1232#define MSR_MTRRphysMask14 0x21d
1233#define MSR_MTRRphysBase15 0x21e
1234#define MSR_MTRRphysMask15 0x21f
1235#define MSR_MTRRfix64K_00000 0x250
1236#define MSR_MTRRfix16K_80000 0x258
1237#define MSR_MTRRfix16K_A0000 0x259
1238#define MSR_MTRRfix4K_C0000 0x268
1239#define MSR_MTRRfix4K_C8000 0x269
1240#define MSR_MTRRfix4K_D0000 0x26a
1241#define MSR_MTRRfix4K_D8000 0x26b
1242#define MSR_MTRRfix4K_E0000 0x26c
1243#define MSR_MTRRfix4K_E8000 0x26d
1244#define MSR_MTRRfix4K_F0000 0x26e
1245#define MSR_MTRRfix4K_F8000 0x26f
1246#define MSR_CR_PAT 0x277
1247#define MSR_MTRRdefType 0x2ff
1248#define MSR_MC0_CTL 0x400
1249#define MSR_MC0_STATUS 0x401
1250#define MSR_MC0_ADDR 0x402
1251#define MSR_MC0_MISC 0x403
1252#define MSR_MC1_CTL 0x404
1253#define MSR_MC1_STATUS 0x405
1254#define MSR_MC1_ADDR 0x406
1255#define MSR_MC1_MISC 0x407
1256#define MSR_MC2_CTL 0x408
1257#define MSR_MC2_STATUS 0x409
1258#define MSR_MC2_ADDR 0x40a
1259#define MSR_MC2_MISC 0x40b
1260#define MSR_MC3_CTL 0x40c
1261#define MSR_MC3_STATUS 0x40d
1262#define MSR_MC3_ADDR 0x40e
1263#define MSR_MC3_MISC 0x40f
1264#define MSR_MC4_CTL 0x410
1265#define MSR_MC4_STATUS 0x411
1266#define MSR_MC4_ADDR 0x412
1267#define MSR_MC4_MISC 0x413
1268 /* 0x480 - 0x490 VMX */
1269#define MSR_X2APIC_BASE 0x800 /* 0x800 - 0xBFF */
1270#define MSR_X2APIC_ID 0x002 /* x2APIC ID. (RO) */
1271#define MSR_X2APIC_VERS 0x003 /* Version. (RO) */
1272#define MSR_X2APIC_TPRI 0x008 /* Task Prio. (RW) */
1273#define MSR_X2APIC_PPRI 0x00a /* Processor prio. (RO) */
1274#define MSR_X2APIC_EOI 0x00b /* End Int. (W) */
1275#define MSR_X2APIC_LDR 0x00d /* Logical dest. (RO) */
1276#define MSR_X2APIC_SVR 0x00f /* Spurious intvec (RW) */
1277#define MSR_X2APIC_ISR 0x010 /* In-Service Status (RO) */
1278#define MSR_X2APIC_TMR 0x018 /* Trigger Mode (RO) */
1279#define MSR_X2APIC_IRR 0x020 /* Interrupt Req (RO) */
1280#define MSR_X2APIC_ESR 0x028 /* Err status. (RW) */
1281#define MSR_X2APIC_LVT_CMCI 0x02f /* LVT CMCI (RW) */
1282#define MSR_X2APIC_ICRLO 0x030 /* Int. cmd. (RW64) */
1283#define MSR_X2APIC_LVTT 0x032 /* Loc.vec.(timer) (RW) */
1284#define MSR_X2APIC_TMINT 0x033 /* Loc.vec (Thermal) (RW) */
1285#define MSR_X2APIC_PCINT 0x034 /* Loc.vec (Perf Mon) (RW) */
1286#define MSR_X2APIC_LVINT0 0x035 /* Loc.vec (LINT0) (RW) */
1287#define MSR_X2APIC_LVINT1 0x036 /* Loc.vec (LINT1) (RW) */
1288#define MSR_X2APIC_LVERR 0x037 /* Loc.vec (ERROR) (RW) */
1289#define MSR_X2APIC_ICR_TIMER 0x038 /* Initial count (RW) */
1290#define MSR_X2APIC_CCR_TIMER 0x039 /* Current count (RO) */
1291#define MSR_X2APIC_DCR_TIMER 0x03e /* Divisor config (RW) */
1292#define MSR_X2APIC_SELF_IPI 0x03f /* SELF IPI (W) */
1293
1294/*
1295 * VIA "Nehemiah" or later MSRs
1296 */
1297#define MSR_VIA_RNG 0x0000110b
1298#define MSR_VIA_RNG_ENABLE 0x00000040
1299#define MSR_VIA_RNG_NOISE_MASK 0x00000300
1300#define MSR_VIA_RNG_NOISE_A 0x00000000
1301#define MSR_VIA_RNG_NOISE_B 0x00000100
1302#define MSR_VIA_RNG_2NOISE 0x00000300
1303#define MSR_VIA_FCR 0x00001107 /* Feature Control Register */
1304#define VIA_FCR_ACE_ENABLE 0x10000000 /* Enable PadLock (ex. RNG) */
1305#define VIA_FCR_CX8_REPORT 0x00000002 /* Enable CX8 CPUID reporting */
1306#define VIA_FCR_ALTINST_ENABLE 0x00000001 /* Enable ALTINST (C3 only) */
1307
1308/*
1309 * AMD K6/K7 MSRs.
1310 */
1311#define MSR_K6_UWCCR 0xc0000085
1312#define MSR_K7_EVNTSEL0 0xc0010000
1313#define MSR_K7_EVNTSEL1 0xc0010001
1314#define MSR_K7_EVNTSEL2 0xc0010002
1315#define MSR_K7_EVNTSEL3 0xc0010003
1316#define MSR_K7_PERFCTR0 0xc0010004
1317#define MSR_K7_PERFCTR1 0xc0010005
1318#define MSR_K7_PERFCTR2 0xc0010006
1319#define MSR_K7_PERFCTR3 0xc0010007
1320
1321/*
1322 * AMD K8 (Opteron) MSRs.
1323 */
1324#define MSR_SYSCFG 0xc0010010
1325
1326#define MSR_EFER 0xc0000080 /* Extended feature enable */
1327#define EFER_SCE 0x00000001 /* SYSCALL extension */
1328#define EFER_LME 0x00000100 /* Long Mode Enable */
1329#define EFER_LMA 0x00000400 /* Long Mode Active */
1330#define EFER_NXE 0x00000800 /* No-Execute Enabled */
1331#define EFER_SVME 0x00001000 /* Secure Virtual Machine En. */
1332#define EFER_LMSLE 0x00002000 /* Long Mode Segment Limit E. */
1333#define EFER_FFXSR 0x00004000 /* Fast FXSAVE/FXRSTOR En. */
1334#define EFER_TCE 0x00008000 /* Translation Cache Ext. */
1335
1336#define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */
1337#define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */
1338#define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */
1339#define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */
1340
1341#define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */
1342#define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */
1343#define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */
1344
1345#define MSR_VMCR 0xc0010114 /* Virtual Machine Control Register */
1346#define VMCR_DPD 0x00000001 /* Debug port disable */
1347#define VMCR_RINIT 0x00000002 /* intercept init */
1348#define VMCR_DISA20 0x00000004 /* Disable A20 masking */
1349#define VMCR_LOCK 0x00000008 /* SVM Lock */
1350#define VMCR_SVMED 0x00000010 /* SVME Disable */
1351#define MSR_SVMLOCK 0xc0010118 /* SVM Lock key */
1352
1353/*
1354 * These require a 'passcode' for access. See cpufunc.h.
1355 */
1356#define MSR_HWCR 0xc0010015
1357#define HWCR_TLBCACHEDIS 0x00000008
1358#define HWCR_FFDIS 0x00000040
1359
1360#define MSR_NB_CFG 0xc001001f
1361#define NB_CFG_DISIOREQLOCK 0x0000000000000008ULL
1362#define NB_CFG_DISDATMSK 0x0000001000000000ULL
1363#define NB_CFG_INITAPICCPUIDLO (1ULL << 54)
1364
1365/* AMD Errata 1474. */
1366#define MSR_CC6_CFG 0xc0010296
1367#define CC6_CFG_DISABLE_BITS (__BIT(22) | __BIT(14) | __BIT(6))
1368
1369#define MSR_LS_CFG 0xc0011020
1370#define LS_CFG_ERRATA_1033 __BIT(4)
1371#define LS_CFG_ERRATA_793 __BIT(15)
1372#define LS_CFG_ERRATA_1095 __BIT(57)
1373#define LS_CFG_DIS_LS2_SQUISH 0x02000000
1374#define LS_CFG_DIS_SSB_F15H 0x0040000000000000ULL
1375#define LS_CFG_DIS_SSB_F16H 0x0000000200000000ULL
1376#define LS_CFG_DIS_SSB_F17H 0x0000000000000400ULL
1377
1378#define MSR_IC_CFG 0xc0011021
1379#define IC_CFG_DIS_SEQ_PREFETCH 0x00000800
1380#define IC_CFG_DIS_IND 0x00004000
1381#define IC_CFG_ERRATA_776 __BIT(26)
1382
1383#define MSR_DC_CFG 0xc0011022
1384#define DC_CFG_DIS_CNV_WC_SSO 0x00000008
1385#define DC_CFG_DIS_SMC_CHK_BUF 0x00000400
1386#define DC_CFG_ERRATA_261 0x01000000
1387
1388#define MSR_BU_CFG 0xc0011023
1389#define BU_CFG_ERRATA_298 0x0000000000000002ULL
1390#define BU_CFG_ERRATA_254 0x0000000000200000ULL
1391#define BU_CFG_ERRATA_309 0x0000000000800000ULL
1392#define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL
1393#define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL
1394#define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL
1395
1396#define MSR_FP_CFG 0xc0011028
1397#define FP_CFG_ERRATA_1049 __BIT(4)
1398
1399#define MSR_DE_CFG 0xc0011029
1400#define DE_CFG_ERRATA_721 0x00000001
1401#define DE_CFG_LFENCE_SERIALIZE __BIT(1)
1402#define DE_CFG_ERRATA_ZENBLEED __BIT(9)
1403#define DE_CFG_ERRATA_1021 __BIT(13)
1404
1405#define MSR_BU_CFG2 0xc001102a
1406#define BU_CFG2_CWPLUS_DIS __BIT(24)
1407
1408#define MSR_LS_CFG2 0xc001102d
1409#define LS_CFG2_ERRATA_1091 __BIT(34)
1410
1411/* AMD Family10h MSRs */
1412#define MSR_OSVW_ID_LENGTH 0xc0010140
1413#define MSR_OSVW_STATUS 0xc0010141
1414#define MSR_UCODE_AMD_PATCHLEVEL 0x0000008b
1415#define MSR_UCODE_AMD_PATCHLOADER 0xc0010020
1416
1417/* X86 MSRs */
1418#define MSR_RDTSCP_AUX 0xc0000103
1419
1420/*
1421 * Constants related to MTRRs
1422 */
1423#define MTRR_N64K 8 /* numbers of fixed-size entries */
1424#define MTRR_N16K 16
1425#define MTRR_N4K 64
1426
1427/*
1428 * the following four 3-byte registers control the non-cacheable regions.
1429 * These registers must be written as three separate bytes.
1430 *
1431 * NCRx+0: A31-A24 of starting address
1432 * NCRx+1: A23-A16 of starting address
1433 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
1434 *
1435 * The non-cacheable region's starting address must be aligned to the
1436 * size indicated by the NCR_SIZE_xx field.
1437 */
1438#define NCR1 0xc4
1439#define NCR2 0xc7
1440#define NCR3 0xca
1441#define NCR4 0xcd
1442
1443#define NCR_SIZE_0K 0
1444#define NCR_SIZE_4K 1
1445#define NCR_SIZE_8K 2
1446#define NCR_SIZE_16K 3
1447#define NCR_SIZE_32K 4
1448#define NCR_SIZE_64K 5
1449#define NCR_SIZE_128K 6
1450#define NCR_SIZE_256K 7
1451#define NCR_SIZE_512K 8
1452#define NCR_SIZE_1M 9
1453#define NCR_SIZE_2M 10
1454#define NCR_SIZE_4M 11
1455#define NCR_SIZE_8M 12
1456#define NCR_SIZE_16M 13
1457#define NCR_SIZE_32M 14
1458#define NCR_SIZE_4G 15