master
1/* $NetBSD: asm.h,v 1.22 2015/10/17 19:29:48 nakayama Exp $ */
2
3#include <sparc/asm.h>
4
5/*
6 * Here are some defines to try to maintain consistency but still
7 * support 32-and 64-bit compilers.
8 */
9#ifdef _LP64
10/* reg that points to base of data/text segment */
11#define BASEREG %g4
12/* first constants for storage allocation */
13#define LNGSZ 8
14#define LNGSHFT 3
15#define PTRSZ 8
16#define PTRSHFT 3
17#define POINTER .xword
18#define ULONG .xword
19/* Now instructions to load/store pointers & long ints */
20#define LDLNG ldx
21#define LDULNG ldx
22#define STLNG stx
23#define STULNG stx
24#define LDPTR ldx
25#define LDPTRA ldxa
26#define STPTR stx
27#define STPTRA stxa
28#define CASPTR casx
29#define CASPTRA casxa
30/* Now something to calculate the stack bias */
31#define STKB BIAS
32#define CCCR %xcc
33#else
34#define BASEREG %g0
35#define LNGSZ 4
36#define LNGSHFT 2
37#define PTRSZ 4
38#define PTRSHFT 2
39#define POINTER .word
40#define ULONG .word
41/* Instructions to load/store pointers & long ints */
42#define LDLNG ldsw
43#define LDULNG lduw
44#define STLNG stw
45#define STULNG stw
46#define LDPTR lduw
47#define LDPTRA lduwa
48#define STPTR stw
49#define STPTRA stwa
50#define CASPTR cas
51#define CASPTRA casa
52#define STKB 0
53#define CCCR %icc
54#endif
55
56#if defined(_KERNEL) || defined(_RUMPKERNEL)
57/* Give this real authority: reset the machine */
58#define NOTREACHED sir
59#else
60#define NOTREACHED
61#endif
62
63/* if < 32, copy by bytes, memcpy, kcopy, ... */
64#define BCOPY_SMALL 32
65
66/* use as needed to align things on longword boundaries */
67#define _ALIGN .align 8
68#define ICACHE_ALIGN .align 32
69
70/*
71 * Combine 2 regs -- used to convert 64-bit ILP32
72 * values to LP64.
73 */
74#define COMBINE(r1, r2, d) \
75 clruw r2; \
76 sllx r1, 32, d; \
77 or d, r2, d
78
79/*
80 * Split 64-bit value in 1 reg into high and low halves.
81 * Used for ILP32 return values.
82 */
83#define SPLIT(s, r0, r1) \
84 srl s, 0, r1; \
85 srlx s, 32, r0
86
87#define SPLIT_RETL(s, r0, r1) \
88 srl s, 0, r1; \
89 retl; \
90 srlx s, 32, r0