1/*	$NetBSD: hid_601.h,v 1.2 2008/04/28 20:23:32 martin Exp $	*/
  2
  3/*-
  4 * Copyright (c) 1999 The NetBSD Foundation, Inc.
  5 * All rights reserved.
  6 *
  7 * This code is derived from software contributed to The NetBSD Foundation
  8 * by Jason R. Thorpe.
  9 *
 10 * Redistribution and use in source and binary forms, with or without
 11 * modification, are permitted provided that the following conditions
 12 * are met:
 13 * 1. Redistributions of source code must retain the above copyright
 14 *    notice, this list of conditions and the following disclaimer.
 15 * 2. Redistributions in binary form must reproduce the above copyright
 16 *    notice, this list of conditions and the following disclaimer in the
 17 *    documentation and/or other materials provided with the distribution.
 18 *
 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 29 * POSSIBILITY OF SUCH DAMAGE.
 30 */
 31
 32#ifndef _POWERPC_OEA_HID_601_H_
 33#define _POWERPC_OEA_HID_601_H_
 34/*
 35 * Hardware Implementation Dependent registers for the PowerPC 601.
 36 */
 37
 38/*
 39 * HID0 (SPR 1008) -- Checkstop Enable/Disable and Status register
 40 */
 41/*	v- feature bits -v						*/
 42#define	HID0_601_EHP	0x00000001	/* enable HP_SNP_REQ# */
 43#define	HID0_601_EMC	0x00000002	/* main cache error */
 44#define	HID0_601_PAR	0x00000004	/* precharge of ARTRY#/SHD# disabled */
 45#define	HID0_601_LM	0x00000008	/* little endian mode */
 46#define	HID0_601_DRL	0x00000010	/* alt sec rld of load/store miss */
 47#define	HID0_601_DRF	0x00000020	/* alt sec rld of insn fetch miss */
 48/*	v- checkstop enable/disable bits -v				*/
 49#define	HID0_601_EPP	0x00000040	/* i/o protocol checkstop */
 50#define	HID0_601_EIU	0x00000080	/* invalid uCode checkstop */
 51#define	HID0_601_ECP	0x00000100	/* cache parity checkstop */
 52#define	HID0_601_EBD	0x00000200	/* data bus parity checkstop */
 53#define	HID0_601_EBA	0x00000400	/* address bus parity checkstop */
 54#define	HID0_601_EDT	0x00000800	/* dispatch timeout checkstop */
 55#define	HID0_601_ESH	0x00001000	/* sequencer timeout checkstop */
 56#define	HID0_601_ECD	0x00002000	/* cache checkstop */
 57#define	HID0_601_ETD	0x00004000	/* TLB checkstop */
 58#define	HID0_601_EM	0x00008000	/* machine checkstop */
 59#define	HID0_601_ES	0x00010000	/* uCode checkstop */
 60		/*	0x00020000	   reserved */
 61		/*	0x00040000	   reserved */
 62		/*	0x00080000	   reserved */
 63/*	v- status bits -- correspond to enable bits above -v		*/
 64#define	HID0_601_PP	0x00100000
 65#define	HID0_601_IU	0x00200000
 66#define	HID0_601_CP	0x00400000
 67#define	HID0_601_BD	0x00800000
 68#define	HID0_601_BA	0x01000000
 69#define	HID0_601_DT	0x02000000
 70#define	HID0_601_SH	0x04000000
 71#define	HID0_601_CD	0x08000000
 72#define	HID0_601_TD	0x10000000
 73#define	HID0_601_M	0x20000000
 74#define	HID0_601_S	0x40000000
 75
 76#define	HID0_601_CE	0x80000000	/* master checkstop enable */
 77
 78#define HID0_601_BITMASK "\020" \
 79    "\040CE\037S\036M\035TD\034CD\033SH\032DT\031BA" \
 80    "\030BD\027CP\026IU\025PP\021ES" \
 81    "\020EM\017ETC\016ECD\015ESH\014EDT\013EBA\012EBD\011ECP" \
 82    "\010EIU\007EPP\006DRF\005DRL\004LM\003PAR\002EMC\001EHP"
 83
 84
 85/*
 86 * HID1 (SPR 1009) -- Debug Modes register
 87 */
 88	/* XXX */
 89
 90
 91/*
 92 * HID2 (SPR 1010) -- Instruction Address Breakpoint Register
 93 */
 94
 95
 96/*
 97 * HID5 (SPR 1013) -- Data Address Breakpoint Register
 98 */
 99
100
101/*
102 * HID15 (SPR 1023) -- Processor ID Register
103 */
104#define	HID15_601_PID	0x0000000f	/* processor ID mask */
105
106#endif /* _POWERPC_OEA_HID_601_H_ */