master
1/* $NetBSD: mcontext.h,v 1.24 2020/10/03 09:56:00 martin Exp $ */
2
3/*-
4 * Copyright (c) 1999, 2002 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Klaus Klein, and by Jason R. Thorpe of Wasabi Systems, Inc.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _MIPS_MCONTEXT_H_
33#define _MIPS_MCONTEXT_H_
34
35/*
36 * General register state
37 */
38#define _NGREG 37 /* R0-R31, MDLO, MDHI, CAUSE, PC, SR */
39
40#define _REG_R0 0
41#define _REG_AT 1
42#define _REG_V0 2
43#define _REG_V1 3
44#define _REG_A0 4
45#define _REG_A1 5
46#define _REG_A2 6
47#define _REG_A3 7
48#define _REG_T0 8
49#define _REG_T1 9
50#define _REG_T2 10
51#define _REG_T3 11
52#define _REG_T4 12
53#define _REG_T5 13
54#define _REG_T6 14
55#define _REG_T7 15
56#define _REG_S0 16
57#define _REG_S1 17
58#define _REG_S2 18
59#define _REG_S3 19
60#define _REG_S4 20
61#define _REG_S5 21
62#define _REG_S6 22
63#define _REG_S7 23
64#define _REG_T8 24
65#define _REG_T9 25
66#define _REG_K0 26
67#define _REG_K1 27
68#define _REG_GP 28
69#define _REG_SP 29
70#define _REG_S8 30
71#define _REG_RA 31
72
73/* XXX: The following conflict with <mips/regnum.h> */
74#define _REG_MDLO 32
75#define _REG_MDHI 33
76#define _REG_CAUSE 34
77#define _REG_EPC 35
78#define _REG_SR 36
79
80#ifndef __ASSEMBLER__
81
82/* Make sure this is signed; we need pointers to be sign-extended. */
83#if defined(__mips_n32)
84typedef long long __greg_t;
85#else
86typedef long __greg_t;
87#endif /* __mips_n32 */
88
89typedef __greg_t __gregset_t[_NGREG];
90
91/*
92 * For the O32/O64 ABI, there are 16 doubles, one at each even FP reg
93 * number. The FP registers themselves are 32-bits.
94 *
95 * For 64-bit ABIs (include N32), each FP register is a 64-bit double.
96 */
97typedef __greg_t __freg_t;
98
99/*
100 * Floating point register state
101 */
102struct __fpregset_nabi {
103 union {
104 double __fp64_dregs[32];
105 __freg_t __fp_regs[32];
106 } __fp_r;
107 __greg_t __fp_csr;
108};
109struct __fpregset_oabi {
110 union {
111 double __fp_dregs[16];
112 float __fp_fregs[32];
113 __int32_t __fp_regs[32];
114 } __fp_r;
115 unsigned int __fp_csr;
116 unsigned int __fp_pad;
117};
118
119#if __mips_n32 || __mips_n64
120typedef struct __fpregset_nabi __fpregset_t;
121#else
122typedef struct __fpregset_oabi __fpregset_t;
123#endif
124
125typedef struct {
126 __gregset_t __gregs;
127 __fpregset_t __fpregs;
128 __greg_t _mc_tlsbase;
129#if !__mips_n32
130 __greg_t __mc_unused;
131#endif
132} mcontext_t;
133
134#if defined(_KERNEL) && !defined(__mips_o32)
135typedef __int32_t __greg32_t;
136typedef __greg32_t __gregset32_t[_NGREG];
137
138typedef struct {
139 __gregset32_t __gregs;
140 struct __fpregset_oabi __fpregs;
141 __greg32_t _mc_tlsbase;
142 __greg32_t __mc_unused;
143} mcontext_o32_t;
144
145typedef struct {
146 __gregset_t __gregs;
147 struct __fpregset_nabi __fpregs;
148 __greg_t _mc_tlsbase;
149} mcontext32_t;
150
151#endif /* _KERNEL && _LP64 */
152
153#endif /* !__ASSEMBLER__ */
154
155#define _UC_MACHINE_PAD 14 /* Padding appended to ucontext_t */
156
157#define _UC_SETSTACK 0x00010000
158#define _UC_CLRSTACK 0x00020000
159#define _UC_TLSBASE 0x00040000
160
161#define _UC_MACHINE_SP(uc) ((uc)->uc_mcontext.__gregs[_REG_SP])
162#define _UC_MACHINE_FP(uc) ((uc)->uc_mcontext.__gregs[_REG_S8])
163#define _UC_MACHINE_PC(uc) ((uc)->uc_mcontext.__gregs[_REG_EPC])
164#define _UC_MACHINE_INTRV(uc) ((uc)->uc_mcontext.__gregs[_REG_V0])
165
166#define _UC_MACHINE_SET_PC(uc, pc) _UC_MACHINE_PC(uc) = (pc)
167
168#define _UC_MACHINE32_SP(uc) _UC_MACHINE_SP(uc)
169#define _UC_MACHINE32_PC(uc) _UC_MACHINE_PC(uc)
170#define _UC_MACHINE32_INTRV(uc) _UC_MACHINE_INTRV(uc)
171#define _UC_MACHINE32_PAD 14 /* Padding appended to ucontext32_t */
172
173#define _UC_MACHINE32_SET_PC(uc, pc) _UC_MACHINE_PC((uc), (pc))
174
175#define __UCONTEXT_SIZE_O32 (40 + 296 + 56) /* 392 */
176#define __UCONTEXT_SIZE_N32 (40 + 568 + 56) /* 664 */
177#define __UCONTEXT_SIZE_N64 (56 + 576 + 112) /* 774 */
178
179#ifdef __mips_o32
180#define __UCONTEXT_SIZE __UCONTEXT_SIZE_O32
181#elif __mips_n32
182#define __UCONTEXT_SIZE __UCONTEXT_SIZE_N32
183#elif __mips_n64
184#define __UCONTEXT_SIZE __UCONTEXT_SIZE_N64
185#define __UCONTEXT32_SIZE __UCONTEXT_SIZE_N32
186#else
187#error O64 is not supported
188#endif
189
190#if defined(_LIBC_SOURCE) || defined(_RTLD_SOURCE) || defined(__LIBPTHREAD_SOURCE__)
191#define TLS_TP_OFFSET 0x7000
192#define TLS_DTV_OFFSET 0x8000
193
194#include <sys/tls.h>
195
196__CTASSERT(TLS_TP_OFFSET + sizeof(struct tls_tcb) < 0x8000);
197__CTASSERT(TLS_TP_OFFSET % sizeof(struct tls_tcb) == 0);
198
199__BEGIN_DECLS
200
201static __inline struct tls_tcb *
202__lwp_gettcb_fast(void)
203{
204 struct tls_tcb *__tcb;
205
206 /*
207 * Only emit a rdhwr $3, $29 so the kernel can quickly emulate it.
208 */
209 __asm __volatile(
210#if 1
211 // For some reason the syscall is much faster than
212 // emulating rdhwr $3,$29 on a CN50xx
213 "addiu $2,$0,316; syscall; nop; move %[__tcb],$2"
214#else
215 ".set push"
216 ";.set mips32r2"
217 ";.p2align 4"
218 ";ssnop"
219 ";rdhwr $3,$29"
220 ";ssnop"
221 ";move %0,$3"
222 ";.set pop"
223#endif
224 : [__tcb]"=r"(__tcb)
225 :
226 : "v0", "v1", "a3");
227 return __tcb - (TLS_TP_OFFSET / sizeof(*__tcb) + 1);
228}
229
230void _lwp_setprivate(void *);
231
232static inline void
233__lwp_settcb(struct tls_tcb *__tcb)
234{
235 __tcb += TLS_TP_OFFSET / sizeof(*__tcb) + 1;
236 _lwp_setprivate(__tcb);
237}
238__END_DECLS
239#endif
240
241#endif /* _MIPS_MCONTEXT_H_ */