master
1/* $NetBSD: twereg.h,v 1.16 2018/11/08 06:34:40 msaitoh Exp $ */
2
3/*-
4 * Copyright (c) 2000 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Andrew Doran.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/*-
33 * Copyright (c) 2000 Michael Smith
34 * Copyright (c) 2000 BSDi
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 * 1. Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * 2. Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in the
44 * documentation and/or other materials provided with the distribution.
45 *
46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
49 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
56 * SUCH DAMAGE.
57 *
58 * from FreeBSD: twereg.h,v 1.1 2000/05/24 23:35:23 msmith Exp
59 */
60
61#ifndef _PCI_TWEREG_H_
62#define _PCI_TWEREG_H_
63
64/* Board registers. */
65#define TWE_REG_CTL 0x00
66#define TWE_REG_STS 0x04
67#define TWE_REG_CMD_QUEUE 0x08
68#define TWE_REG_RESP_QUEUE 0x0c
69
70/* Control register bit definitions. */
71#define TWE_CTL_CLEAR_HOST_INTR 0x00080000
72#define TWE_CTL_CLEAR_ATTN_INTR 0x00040000
73#define TWE_CTL_MASK_CMD_INTR 0x00020000
74#define TWE_CTL_MASK_RESP_INTR 0x00010000
75#define TWE_CTL_UNMASK_CMD_INTR 0x00008000
76#define TWE_CTL_UNMASK_RESP_INTR 0x00004000
77#define TWE_CTL_CLEAR_ERROR_STS 0x00000200
78#define TWE_CTL_ISSUE_SOFT_RESET 0x00000100
79#define TWE_CTL_ENABLE_INTRS 0x00000080
80#define TWE_CTL_DISABLE_INTRS 0x00000040
81#define TWE_CTL_ISSUE_HOST_INTR 0x00000020
82#define TWE_CTL_CLEAR_PARITY_ERROR 0x00800000
83#define TWE_CTL_CLEAR_PCI_ABORT 0x00100000
84
85/* Status register bit definitions. */
86#define TWE_STS_MAJOR_VERSION_MASK 0xf0000000
87#define TWE_STS_MINOR_VERSION_MASK 0x0f000000
88#define TWE_STS_PCI_PARITY_ERROR 0x00800000
89#define TWE_STS_QUEUE_ERROR 0x00400000
90#define TWE_STS_MICROCONTROLLER_ERROR 0x00200000
91#define TWE_STS_PCI_ABORT 0x00100000
92#define TWE_STS_HOST_INTR 0x00080000
93#define TWE_STS_ATTN_INTR 0x00040000
94#define TWE_STS_CMD_INTR 0x00020000
95#define TWE_STS_RESP_INTR 0x00010000
96#define TWE_STS_CMD_QUEUE_FULL 0x00008000
97#define TWE_STS_RESP_QUEUE_EMPTY 0x00004000
98#define TWE_STS_MICROCONTROLLER_READY 0x00002000
99#define TWE_STS_CMD_QUEUE_EMPTY 0x00001000
100
101#define TWE_STS_ALL_INTRS 0x000f0000
102#define TWE_STS_CLEARABLE_BITS 0x00d00000
103#define TWE_STS_EXPECTED_BITS 0x00002000
104#define TWE_STS_UNEXPECTED_BITS 0x00f80000
105
106/* Command packet opcodes. */
107#define TWE_OP_NOP 0x00
108#define TWE_OP_INIT_CONNECTION 0x01
109#define TWE_OP_READ 0x02
110#define TWE_OP_WRITE 0x03
111#define TWE_OP_READVERIFY 0x04
112#define TWE_OP_VERIFY 0x05
113#define TWE_OP_PROBE 0x06
114#define TWE_OP_PROBEUNIT 0x07
115#define TWE_OP_ZEROUNIT 0x08
116#define TWE_OP_REPLACEUNIT 0x09
117#define TWE_OP_HOTSWAP 0x0a
118#define TWE_OP_SETATAFEATURE 0x0c
119#define TWE_OP_FLUSH 0x0e
120#define TWE_OP_ABORT 0x0f
121#define TWE_OP_CHECKSTATUS 0x10
122#define TWE_OP_ATA_PASSTHROUGH 0x11
123#define TWE_OP_GET_PARAM 0x12
124#define TWE_OP_SET_PARAM 0x13
125#define TWE_OP_CREATEUNIT 0x14
126#define TWE_OP_DELETEUNIT 0x15
127#define TWE_OP_REBUILDUNIT 0x17
128#define TWE_OP_SECTOR_INFO 0x1a
129#define TWE_OP_AEN_LISTEN 0x1c
130#define TWE_OP_CMD_PACKET 0x1d
131#define TWE_OP_CMD_WITH_DATA 0x1f
132
133/* Response queue entries. Masking and shifting yields request ID. */
134#define TWE_RESP_MASK 0x00000ff0
135#define TWE_RESP_SHIFT 4
136
137/* Miscellenous constants. */
138#define TWE_ALIGNMENT 512
139#define TWE_MAX_UNITS 16
140#define TWE_INIT_CMD_PACKET_SIZE 0x3
141#define TWE_SG_SIZE 62
142#define TWE_MAX_CMDS 255
143#define TWE_Q_START 0
144#define TWE_UNIT_INFORMATION_TABLE_BASE 0x300
145#define TWE_IOCTL 0x80
146#define TWE_SECTOR_SIZE 512
147
148/* Scatter/gather block. */
149struct twe_sgb {
150 u_int32_t tsg_address;
151 u_int32_t tsg_length;
152} __packed;
153
154/*
155 * Command block. This is 512 (really 508) bytes in size, and must be
156 * aligned on a 512 byte boundary.
157 */
158struct twe_cmd {
159 u_int8_t tc_opcode; /* high 3 bits is S/G list offset */
160 u_int8_t tc_size;
161 u_int8_t tc_cmdid;
162 u_int8_t tc_unit; /* high nybble is host ID */
163 u_int8_t tc_status;
164 u_int8_t tc_flags;
165 u_int16_t tc_count; /* block & param count, msg credits */
166 union {
167 struct {
168 u_int32_t lba;
169 struct twe_sgb sgl[TWE_SG_SIZE];
170 } io __packed;
171 struct {
172 struct twe_sgb sgl[TWE_SG_SIZE];
173 } param;
174 struct {
175 u_int32_t response_queue_pointer;
176 } init_connection __packed;
177 } tc_args;
178 int32_t tc_pad;
179} __packed;
180
181/* Get/set parameter block. */
182struct twe_param {
183 u_int16_t tp_table_id;
184 u_int8_t tp_param_id;
185 u_int8_t tp_param_size;
186 u_int8_t tp_data[1];
187} __packed;
188
189/*
190 * From 3ware's documentation:
191 *
192 * All parameters maintained by the controller are grouped into related
193 * tables. Tables are accessed indirectly via get and set parameter
194 * commands. To access a specific parameter in a table, the table ID and
195 * parameter index are used to uniquely identify a parameter. Table
196 * 0xffff is the directory table and provides a list of the table IDs and
197 * sizes of all other tables. Index zero in each table specifies the
198 * entire table, and index one specifies the size of the table. An entire
199 * table can be read or set by using index zero.
200 */
201
202#define TWE_PARAM_PARAM_ALL 0
203#define TWE_PARAM_PARAM_SIZE 1
204
205#define TWE_PARAM_DIRECTORY 0xffff /* size is 4 * number of tables */
206#define TWE_PARAM_DIRECTORY_TABLES 2 /* 16 bits * number of tables */
207#define TWE_PARAM_DIRECTORY_SIZES 3 /* 16 bits * number of tables */
208
209#define TWE_PARAM_DRIVESUMMARY 0x0002
210#define TWE_PARAM_DRIVESUMMARY_Num 2 /* number of physical drives [2] */
211#define TWE_PARAM_DRIVESUMMARY_Status 3 /* array giving drive status per aport */
212#define TWE_PARAM_DRIVESTATUS_Missing 0x00
213#define TWE_PARAM_DRIVESTATUS_NotSupp 0xfe
214#define TWE_PARAM_DRIVESTATUS_Present 0xff
215
216#define TWE_PARAM_UNITSUMMARY 0x0003
217#define TWE_PARAM_UNITSUMMARY_Num 2 /* number of logical units [2] */
218#define TWE_PARAM_UNITSUMMARY_Status 3 /* array giving unit status [16] */
219#define TWE_PARAM_UNITSTATUS_Online (1<<0)
220#define TWE_PARAM_UNITSTATUS_Complete (1<<1)
221#define TWE_PARAM_UNITSTATUS_MASK 0xfc
222#define TWE_PARAM_UNITSTATUS_Normal 0xfc
223#define TWE_PARAM_UNITSTATUS_Initialising 0xf4 /* cannot be incomplete */
224#define TWE_PARAM_UNITSTATUS_Degraded 0xec
225#define TWE_PARAM_UNITSTATUS_Rebuilding 0xdc /* cannot be incomplete */
226#define TWE_PARAM_UNITSTATUS_Verifying 0xcc /* cannot be incomplete */
227#define TWE_PARAM_UNITSTATUS_Corrupt 0xbc /* cannot be complete */
228#define TWE_PARAM_UNITSTATUS_Missing 0x00 /* cannot be complete or online */
229
230#define TWE_PARAM_DRIVEINFO 0x0200 /* add drive number 0x00-0x0f XXX docco confused 0x0100 vs 0x0200 */
231#define TWE_PARAM_DRIVEINFO_Size 2 /* size in blocks [4] */
232#define TWE_PARAM_DRIVEINFO_Model 3 /* drive model string [40] */
233#define TWE_PARAM_DRIVEINFO_Serial 4 /* drive serial number [20] */
234#define TWE_PARAM_DRIVEINFO_PhysCylNum 5 /* physical geometry [2] */
235#define TWE_PARAM_DRIVEINFO_PhysHeadNum 6 /* [2] */
236#define TWE_PARAM_DRIVEINFO_PhysSectorNum 7 /* [2] */
237#define TWE_PARAM_DRIVEINFO_LogCylNum 8 /* logical geometry [2] */
238#define TWE_PARAM_DRIVEINFO_LogHeadNum 9 /* [2] */
239#define TWE_PARAM_DRIVEINFO_LogSectorNum 10 /* [2] */
240#define TWE_PARAM_DRIVEINFO_UnitNum 11 /* unit number this drive is associated with or 0xff [1] */
241#define TWE_PARAM_DRIVEINFO_DriveFlags 12 /* N/A [1] */
242
243#define TWE_PARAM_APORTTIMEOUT 0x02c0 /* add (aport_number * 3) to parameter index */
244#define TWE_PARAM_APORTTIMEOUT_READ 2 /* read timeouts last 24hrs [2] */
245#define TWE_PARAM_APORTTIMEOUT_WRITE 3 /* write timeouts last 24hrs [2] */
246#define TWE_PARAM_APORTTIMEOUT_DEGRADE 4 /* degrade threshold [2] */
247
248#define TWE_PARAM_UNITINFO 0x0300 /* add unit number 0x00-0x0f */
249#define TWE_PARAM_UNITINFO_Number 2 /* unit number [1] */
250#define TWE_PARAM_UNITINFO_Status 3 /* unit status [1] */
251#define TWE_PARAM_UNITINFO_Capacity 4 /* unit capacity in blocks [4] */
252#define TWE_PARAM_UNITINFO_DescriptorSize 5 /* unit descriptor size + 3 bytes [2] */
253#define TWE_PARAM_UNITINFO_Descriptor 6 /* unit descriptor, TWE_UnitDescriptor or TWE_Array_Descriptor */
254#define TWE_PARAM_UNITINFO_Flags 7 /* unit flags [1] */
255#define TWE_PARAM_UNITFLAGS_WCE (1<<0)
256
257#define TWE_PARAM_AEN 0x0401
258#define TWE_PARAM_AEN_UnitCode 2 /* (unit number << 8) | AEN code [2] */
259#define TWE_AEN_QUEUE_EMPTY 0x00
260#define TWE_AEN_SOFT_RESET 0x01
261#define TWE_AEN_DEGRADED_MIRROR 0x02 /* reports unit */
262#define TWE_AEN_CONTROLLER_ERROR 0x03
263#define TWE_AEN_REBUILD_FAIL 0x04 /* reports unit */
264#define TWE_AEN_REBUILD_DONE 0x05 /* reports unit */
265#define TWE_AEN_INCOMP_UNIT 0x06 /* reports unit */
266#define TWE_AEN_INIT_DONE 0x07 /* reports unit */
267#define TWE_AEN_UNCLEAN_SHUTDOWN 0x08 /* reports unit */
268#define TWE_AEN_APORT_TIMEOUT 0x09 /* reports unit, rate limited to 1 per 2^16 errors */
269#define TWE_AEN_DRIVE_ERROR 0x0a /* reports unit */
270#define TWE_AEN_REBUILD_STARTED 0x0b /* reports unit */
271#define TWE_AEN_QUEUE_FULL 0xff
272#define TWE_AEN_TABLE_UNDEFINED 0x15
273#define TWE_AEN_CODE(x) ((x) & 0xff)
274#define TWE_AEN_UNIT(x) ((x) >> 8)
275
276#define TWE_PARAM_VERSION 0x0402
277#define TWE_PARAM_VERSION_Mon 2 /* monitor version [16] */
278#define TWE_PARAM_VERSION_FW 3 /* firmware version [16] */
279#define TWE_PARAM_VERSION_BIOS 4 /* BIOSs version [16] */
280#define TWE_PARAM_VERSION_PCB 5 /* PCB version [8] */
281#define TWE_PARAM_VERSION_ATA 6 /* A-chip version [8] */
282#define TWE_PARAM_VERSION_PCI 7 /* P-chip version [8] */
283#define TWE_PARAM_VERSION_CtrlModel 8 /* N/A */
284#define TWE_PARAM_VERSION_CtrlSerial 9 /* N/A */
285#define TWE_PARAM_VERSION_SBufSize 10 /* N/A */
286#define TWE_PARAM_VERSION_CompCode 11 /* compatibility code [4] */
287
288#define TWE_PARAM_CONTROLLER 0x0403
289#define TWE_PARAM_CONTROLLER_DCBSectors 2 /* # sectors reserved for DCB per drive [2] */
290#define TWE_PARAM_CONTROLLER_PortCount 3 /* number of drive ports [1] */
291
292#define TWE_PARAM_FEATURES 0x404
293#define TWE_PARAM_FEATURES_DriverShutdown 2 /* set to 1 if driver supports shutdown notification [1] */
294
295#define TWE_PARAM_PROC 0x406
296#define TWE_PARAM_PROC_PERCENT 2 /* Per-sub-unit % complete of init/verify/rebuild or 0xff [16] */
297
298struct twe_unit_descriptor {
299 u_int8_t num_subunits; /* must be zero */
300 u_int8_t configuration;
301#define TWE_UD_CONFIG_CBOD 0x0c /* JBOD with DCB, used for mirrors */
302#define TWE_UD_CONFIG_SPARE 0x0d /* same as CBOD, but firmware will use as spare */
303#define TWE_UD_CONFIG_SUBUNIT 0x0e /* drive is a subunit in an array */
304#define TWE_UD_CONFIG_JBOD 0x0f /* plain drive */
305 u_int8_t phys_drv_num; /* may be 0xff if port can't be determined at runtime */
306 u_int8_t log_drv_num; /* must be zero for configuration == 0x0f */
307 u_int32_t start_lba;
308 u_int32_t block_count; /* actual drive size if configuration == 0x0f, otherwise less DCB size */
309} __packed;
310
311struct twe_mirror_descriptor {
312 u_int8_t flag; /* must be 0xff */
313 u_int8_t res1;
314 u_int8_t mirunit_status[4]; /* bitmap of functional subunits in each mirror */
315 u_int8_t res2[6];
316} __packed;
317
318struct twe_array_descriptor {
319 u_int8_t num_subunits; /* number of subunits, or number of mirror units in RAID10 */
320 u_int8_t configuration;
321#define TWE_AD_CONFIG_RAID0 0x00
322#define TWE_AD_CONFIG_RAID1 0x01
323#define TWE_AD_CONFIG_TwinStor 0x02
324#define TWE_AD_CONFIG_RAID5 0x05
325#define TWE_AD_CONFIG_RAID10 0x06
326 u_int8_t stripe_size;
327#define TWE_AD_STRIPE_4k 0x03
328#define TWE_AD_STRIPE_8k 0x04
329#define TWE_AD_STRIPE_16k 0x05
330#define TWE_AD_STRIPE_32k 0x06
331#define TWE_AD_STRIPE_64k 0x07
332#define TWE_AD_STRIPE_128k 0x08
333#define TWE_AD_STRIPE_256k 0x09
334#define TWE_AD_STRIPE_512k 0x0a
335#define TWE_AD_STRIPE_1024k 0x0b
336 u_int8_t log_drv_status; /* bitmap of functional subunits, or mirror units in RAID10 */
337 u_int32_t start_lba;
338 u_int32_t block_count; /* actual drive size if configuration == 0x0f, otherwise less DCB size */
339 struct twe_unit_descriptor subunit[1];
340} __packed;
341
342#endif /* !_PCI_TWEREG_H_ */