master
1/* $NetBSD: i2o.h,v 1.17 2022/05/30 09:56:04 andvar Exp $ */
2
3/*-
4 * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Andrew Doran.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/*
33 * Structures and constants, as presented by the I2O specification revision
34 * 1.5 (obtainable from http://www.intelligent-io.com/). Currently, only
35 * what's useful to us is defined in this file.
36 */
37
38#ifndef _I2O_I2O_H_
39#define _I2O_I2O_H_
40
41#include <sys/cdefs.h>
42#include <sys/types.h>
43
44/*
45 * ================= Miscellaneous definitions =================
46 */
47
48/* Organisation IDs */
49#define I2O_ORG_DPT 0x001b
50#define I2O_ORG_INTEL 0x0028
51#define I2O_ORG_AMI 0x1000
52
53/* Macros to assist in building message headers */
54#define I2O_MSGFLAGS(s) (I2O_VERSION_11 | (sizeof(struct s) << 14))
55#define I2O_MSGFUNC(t, f) ((t) | (I2O_TID_HOST << 12) | ((f) << 24))
56#define I2O_MSGPRIV(o, f) ((f) | ((o) << 16))
57
58/* Common message function codes with no payload or an undefined payload */
59#define I2O_UTIL_NOP 0x00
60#define I2O_EXEC_IOP_CLEAR 0xbe
61#define I2O_EXEC_SYS_QUIESCE 0xc3
62#define I2O_EXEC_SYS_ENABLE 0xd1
63#define I2O_PRIVATE_MESSAGE 0xff
64
65/* Device class codes */
66#define I2O_CLASS_EXECUTIVE 0x00
67#define I2O_CLASS_DDM 0x01
68#define I2O_CLASS_RANDOM_BLOCK_STORAGE 0x10
69#define I2O_CLASS_SEQUENTIAL_STORAGE 0x11
70#define I2O_CLASS_LAN 0x20
71#define I2O_CLASS_WAN 0x30
72#define I2O_CLASS_FIBRE_CHANNEL_PORT 0x40
73#define I2O_CLASS_FIBRE_CHANNEL_PERIPHERAL 0x41
74#define I2O_CLASS_SCSI_PERIPHERAL 0x51
75#define I2O_CLASS_ATE_PORT 0x60
76#define I2O_CLASS_ATE_PERIPHERAL 0x61
77#define I2O_CLASS_FLOPPY_CONTROLLER 0x70
78#define I2O_CLASS_FLOPPY_DEVICE 0x71
79#define I2O_CLASS_BUS_ADAPTER_PORT 0x80
80
81#define I2O_CLASS_ANY 0xffffffff
82
83/* Reply status codes */
84#define I2O_STATUS_SUCCESS 0x00
85#define I2O_STATUS_ABORT_DIRTY 0x01
86#define I2O_STATUS_ABORT_NO_DATA_XFER 0x02
87#define I2O_STATUS_ABORT_PARTIAL_XFER 0x03
88#define I2O_STATUS_ERROR_DIRTY 0x04
89#define I2O_STATUS_ERROR_NO_DATA_XFER 0x05
90#define I2O_STATUS_ERROR_PARTIAL_XFER 0x06
91#define I2O_STATUS_PROCESS_ABORT_DIRTY 0x08
92#define I2O_STATUS_PROCESS_ABORT_NO_DATA_XFER 0x09
93#define I2O_STATUS_PROCESS_ABORT_PARTIAL_XFER 0x0a
94#define I2O_STATUS_TRANSACTION_ERROR 0x0b
95#define I2O_STATUS_PROGRESS_REPORT 0x80
96
97/* Detailed status codes */
98#define I2O_DSC_SUCCESS 0x00
99#define I2O_DSC_BAD_KEY 0x02
100#define I2O_DSC_TCL_ERROR 0x03
101#define I2O_DSC_REPLY_BUFFER_FULL 0x04
102#define I2O_DSC_NO_SUCH_PAGE 0x05
103#define I2O_DSC_INSUFFICIENT_RESOURCE_SOFT 0x06
104#define I2O_DSC_INSUFFICIENT_RESOURCE_HARD 0x07
105#define I2O_DSC_CHAIN_BUFFER_TOO_LARGE 0x09
106#define I2O_DSC_UNSUPPORTED_FUNCTION 0x0a
107#define I2O_DSC_DEVICE_LOCKED 0x0b
108#define I2O_DSC_DEVICE_RESET 0x0c
109#define I2O_DSC_INAPPROPRIATE_FUNCTION 0x0d
110#define I2O_DSC_INVALID_INITIATOR_ADDRESS 0x0e
111#define I2O_DSC_INVALID_MESSAGE_FLAGS 0x0f
112#define I2O_DSC_INVALID_OFFSET 0x10
113#define I2O_DSC_INVALID_PARAMETER 0x11
114#define I2O_DSC_INVALID_REQUEST 0x12
115#define I2O_DSC_INVALID_TARGET_ADDRESS 0x13
116#define I2O_DSC_MESSAGE_TOO_LARGE 0x14
117#define I2O_DSC_MESSAGE_TOO_SMALL 0x15
118#define I2O_DSC_MISSING_PARAMETER 0x16
119#define I2O_DSC_TIMEOUT 0x17
120#define I2O_DSC_UNKNOWN_ERROR 0x18
121#define I2O_DSC_UNKNOWN_FUNCTION 0x19
122#define I2O_DSC_UNSUPPORTED_VERSION 0x1a
123#define I2O_DSC_DEVICE_BUSY 0x1b
124#define I2O_DSC_DEVICE_NOT_AVAILABLE 0x1c
125
126/* Message versions */
127#define I2O_VERSION_10 0x00
128#define I2O_VERSION_11 0x01
129#define I2O_VERSION_20 0x02
130
131/* Commonly used TIDs */
132#define I2O_TID_IOP 0
133#define I2O_TID_HOST 1
134#define I2O_TID_NONE 4095
135
136/* SGL flags. This list covers only a fraction of the possibilities. */
137#define I2O_SGL_IGNORE 0x00000000
138#define I2O_SGL_SIMPLE 0x10000000
139#define I2O_SGL_PAGE_LIST 0x20000000
140
141#define I2O_SGL_BC_32BIT 0x01000000
142#define I2O_SGL_BC_64BIT 0x02000000
143#define I2O_SGL_BC_96BIT 0x03000000
144#define I2O_SGL_DATA_OUT 0x04000000
145#define I2O_SGL_END_BUFFER 0x40000000
146#define I2O_SGL_END 0x80000000
147
148/* Serial number formats */
149#define I2O_SNFMT_UNKNOWN 0
150#define I2O_SNFMT_BINARY 1
151#define I2O_SNFMT_ASCII 2
152#define I2O_SNFMT_UNICODE 3
153#define I2O_SNFMT_LAN_MAC 4
154#define I2O_SNFMT_WAN_MAC 5
155
156/*
157 * ================= Common structures =================
158 */
159
160/*
161 * Standard I2O message frame. All message frames begin with this.
162 *
163 * Bits Field Meaning
164 * ---- ------------- ----------------------------------------------------
165 * 0-2 msgflags Message header version. Must be 001 (little endian).
166 * 3 msgflags Reserved.
167 * 4-7 msgflags Offset to SGLs expressed as # of 32-bit words.
168 * 8-15 msgflags Control flags.
169 * 16-31 msgflags Message frame size expressed as # of 32-bit words.
170 * 0-11 msgfunc TID of target.
171 * 12-23 msgfunc TID of initiator.
172 * 24-31 msgfunc Function (i.e., type of message).
173 */
174struct i2o_msg {
175 u_int32_t msgflags;
176 u_int32_t msgfunc;
177 u_int32_t msgictx; /* Initiator context */
178 u_int32_t msgtctx; /* Transaction context */
179
180 /* Message payload */
181
182} __packed;
183
184#define I2O_MSGFLAGS_STATICMF 0x0100
185#define I2O_MSGFLAGS_64BIT 0x0200
186#define I2O_MSGFLAGS_MULTI 0x1000
187#define I2O_MSGFLAGS_FAIL 0x2000
188#define I2O_MSGFLAGS_LAST_REPLY 0x4000
189#define I2O_MSGFLAGS_REPLY 0x8000
190
191/*
192 * Standard reply frame. msgflags, msgfunc, msgictx and msgtctx have the
193 * same meaning as in `struct i2o_msg'.
194 */
195struct i2o_reply {
196 u_int32_t msgflags;
197 u_int32_t msgfunc;
198 u_int32_t msgictx;
199 u_int32_t msgtctx;
200 u_int16_t detail; /* Detailed status code */
201 u_int8_t reserved;
202 u_int8_t reqstatus; /* Request status code */
203
204 /* Reply payload */
205
206} __packed;
207
208/*
209 * Fault notification reply, returned when a message frame can not be
210 * processed (i.e I2O_MSGFLAGS_FAIL is set in the reply).
211 */
212struct i2o_fault_notify {
213 u_int32_t msgflags;
214 u_int32_t msgfunc;
215 u_int32_t msgictx;
216 u_int32_t msgtctx; /* Not valid! */
217 u_int8_t lowestver;
218 u_int8_t highestver;
219 u_int8_t severity;
220 u_int8_t failurecode;
221 u_int16_t failingiop; /* Bits 0-12 only */
222 u_int16_t failinghostunit;
223 u_int32_t agelimit;
224 u_int32_t lowmfa;
225 u_int32_t highmfa;
226};
227
228/*
229 * Hardware resource table. Not documented here.
230 */
231struct i2o_hrt_entry {
232 u_int32_t adapterid;
233 u_int16_t controllingtid;
234 u_int8_t busnumber;
235 u_int8_t bustype;
236 u_int8_t businfo[8];
237} __packed;
238
239struct i2o_hrt {
240 u_int16_t numentries;
241 u_int8_t entrysize;
242 u_int8_t hrtversion;
243 u_int32_t changeindicator;
244 struct i2o_hrt_entry entry[1];
245} __packed;
246
247/*
248 * Logical configuration table entry. Bitfields are broken down as follows:
249 *
250 * Bits Field Meaning
251 * ----- -------------- ---------------------------------------------------
252 * 0-11 classid Class ID.
253 * 12-15 classid Class version.
254 * 0-11 usertid User TID
255 * 12-23 usertid Parent TID.
256 * 24-31 usertid BIOS info.
257 */
258struct i2o_lct_entry {
259 u_int16_t entrysize;
260 u_int16_t localtid; /* Bits 0-12 only */
261 u_int32_t changeindicator;
262 u_int32_t deviceflags;
263 u_int16_t classid;
264 u_int16_t orgid;
265 u_int32_t subclassinfo;
266 u_int32_t usertid;
267 u_int8_t identitytag[8];
268 u_int32_t eventcaps;
269} __packed;
270
271/*
272 * Logical configuration table header.
273 */
274struct i2o_lct {
275 u_int16_t tablesize;
276 u_int16_t flags;
277 u_int32_t iopflags;
278 u_int32_t changeindicator;
279 struct i2o_lct_entry entry[1];
280} __packed;
281
282/*
283 * IOP system table. Bitfields are broken down as follows:
284 *
285 * Bits Field Meaning
286 * ----- -------------- ---------------------------------------------------
287 * 0-11 iopid IOP ID.
288 * 12-31 iopid Reserved.
289 * 0-11 segnumber Segment number.
290 * 12-15 segnumber I2O version.
291 * 16-23 segnumber IOP state.
292 * 24-31 segnumber Messenger type.
293 */
294struct i2o_systab_entry {
295 u_int16_t orgid;
296 u_int16_t reserved0;
297 u_int32_t iopid;
298 u_int32_t segnumber;
299 u_int16_t inboundmsgframesize;
300 u_int16_t reserved1;
301 u_int32_t lastchanged;
302 u_int32_t iopcaps;
303 u_int32_t inboundmsgportaddresslow;
304 u_int32_t inboundmsgportaddresshigh;
305} __packed;
306
307struct i2o_systab {
308 u_int8_t numentries;
309 u_int8_t version;
310 u_int16_t reserved0;
311 u_int32_t changeindicator;
312 u_int32_t reserved1[2];
313 struct i2o_systab_entry entry[1];
314} __packed;
315
316/*
317 * IOP status record. Bitfields are broken down as follows:
318 *
319 * Bits Field Meaning
320 * ----- -------------- ---------------------------------------------------
321 * 0-11 iopid IOP ID.
322 * 12-15 iopid Reserved.
323 * 16-31 iopid Host unit ID.
324 * 0-11 segnumber Segment number.
325 * 12-15 segnumber I2O version.
326 * 16-23 segnumber IOP state.
327 * 24-31 segnumber Messenger type.
328 */
329struct i2o_status {
330 u_int16_t orgid;
331 u_int16_t reserved0;
332 u_int32_t iopid;
333 u_int32_t segnumber;
334 u_int16_t inboundmframesize;
335 u_int8_t initcode;
336 u_int8_t reserved1;
337 u_int32_t maxinboundmframes;
338 u_int32_t currentinboundmframes;
339 u_int32_t maxoutboundmframes;
340 u_int8_t productid[24];
341 u_int32_t expectedlctsize;
342 u_int32_t iopcaps;
343 u_int32_t desiredprivmemsize;
344 u_int32_t currentprivmemsize;
345 u_int32_t currentprivmembase;
346 u_int32_t desiredpriviosize;
347 u_int32_t currentpriviosize;
348 u_int32_t currentpriviobase;
349 u_int8_t reserved2[3];
350 u_int8_t syncbyte;
351} __packed;
352
353#define I2O_IOP_STATE_INITIALIZING 0x01
354#define I2O_IOP_STATE_RESET 0x02
355#define I2O_IOP_STATE_HOLD 0x04
356#define I2O_IOP_STATE_READY 0x05
357#define I2O_IOP_STATE_OPERATIONAL 0x08
358#define I2O_IOP_STATE_FAILED 0x10
359#define I2O_IOP_STATE_FAULTED 0x11
360
361/*
362 * ================= Executive class messages =================
363 */
364
365#define I2O_EXEC_STATUS_GET 0xa0
366struct i2o_exec_status_get {
367 u_int32_t msgflags;
368 u_int32_t msgfunc;
369 u_int32_t reserved[4];
370 u_int32_t addrlow;
371 u_int32_t addrhigh;
372 u_int32_t length;
373} __packed;
374
375#define I2O_EXEC_OUTBOUND_INIT 0xa1
376struct i2o_exec_outbound_init {
377 u_int32_t msgflags;
378 u_int32_t msgfunc;
379 u_int32_t msgictx;
380 u_int32_t msgtctx;
381 u_int32_t pagesize;
382 u_int32_t flags; /* init code, outbound msg size */
383} __packed;
384
385#define I2O_EXEC_OUTBOUND_INIT_IN_PROGRESS 1
386#define I2O_EXEC_OUTBOUND_INIT_REJECTED 2
387#define I2O_EXEC_OUTBOUND_INIT_FAILED 3
388#define I2O_EXEC_OUTBOUND_INIT_COMPLETE 4
389
390#define I2O_EXEC_LCT_NOTIFY 0xa2
391struct i2o_exec_lct_notify {
392 u_int32_t msgflags;
393 u_int32_t msgfunc;
394 u_int32_t msgictx;
395 u_int32_t msgtctx;
396 u_int32_t classid;
397 u_int32_t changeindicator;
398} __packed;
399
400#define I2O_EXEC_SYS_TAB_SET 0xa3
401struct i2o_exec_sys_tab_set {
402 u_int32_t msgflags;
403 u_int32_t msgfunc;
404 u_int32_t msgictx;
405 u_int32_t msgtctx;
406 u_int32_t iopid;
407 u_int32_t segnumber;
408} __packed;
409
410#define I2O_EXEC_HRT_GET 0xa8
411struct i2o_exec_hrt_get {
412 u_int32_t msgflags;
413 u_int32_t msgfunc;
414 u_int32_t msgictx;
415 u_int32_t msgtctx;
416} __packed;
417
418#define I2O_EXEC_IOP_RESET 0xbd
419struct i2o_exec_iop_reset {
420 u_int32_t msgflags;
421 u_int32_t msgfunc;
422 u_int32_t reserved[4];
423 u_int32_t statuslow;
424 u_int32_t statushigh;
425} __packed;
426
427#define I2O_RESET_IN_PROGRESS 0x01
428#define I2O_RESET_REJECTED 0x02
429
430/*
431 * ================= Executive class parameter groups =================
432 */
433
434#define I2O_PARAM_EXEC_LCT_SCALAR 0x0101
435#define I2O_PARAM_EXEC_LCT_TABLE 0x0102
436
437/*
438 * ================= HBA class messages =================
439 */
440
441#define I2O_HBA_BUS_SCAN 0x89
442struct i2o_hba_bus_scan {
443 u_int32_t msgflags;
444 u_int32_t msgfunc;
445 u_int32_t msgictx;
446 u_int32_t msgtctx;
447} __packed;
448
449/*
450 * ================= HBA class parameter groups =================
451 */
452
453#define I2O_PARAM_HBA_CTLR_INFO 0x0000
454struct i2o_param_hba_ctlr_info {
455 u_int8_t bustype;
456 u_int8_t busstate;
457 u_int16_t reserved;
458 u_int8_t busname[12];
459} __packed;
460
461#define I2O_HBA_BUS_GENERIC 0x00
462#define I2O_HBA_BUS_SCSI 0x01
463#define I2O_HBA_BUS_FCA 0x10
464
465#define I2O_PARAM_HBA_SCSI_PORT_INFO 0x0001
466struct i2o_param_hba_scsi_port_info {
467 u_int8_t physicalif;
468 u_int8_t electricalif;
469 u_int8_t isosynchonrous;
470 u_int8_t connectortype;
471 u_int8_t connectorgender;
472 u_int8_t reserved1;
473 u_int16_t reserved2;
474 u_int32_t maxnumberofdevices;
475} __packed;
476
477#define I2O_PARAM_HBA_SCSI_PORT_GENERIC 0x01
478#define I2O_PARAM_HBA_SCSI_PORT_UNKNOWN 0x02
479#define I2O_PARAM_HBA_SCSI_PORT_PARINTF 0x03
480#define I2O_PARAM_HBA_SCSI_PORT_FCL 0x04
481#define I2O_PARAM_HBA_SCSI_PORT_1394 0x05
482#define I2O_PARAM_HBA_SCSI_PORT_SSA 0x06
483
484#define I2O_PARAM_HBA_SCSI_PORT_SE 0x03
485#define I2O_PARAM_HBA_SCSI_PORT_DIFF 0x04
486#define I2O_PARAM_HBA_SCSI_PORT_LVD 0x05
487#define I2O_PARAM_HBA_SCSI_PORT_OPTCL 0x06
488
489#define I2O_PARAM_HBA_SCSI_PORT_HDBS50 0x04
490#define I2O_PARAM_HBA_SCSI_PORT_HDBU50 0x05
491#define I2O_PARAM_HBA_SCSI_PORT_DBS50 0x06
492#define I2O_PARAM_HBA_SCSI_PORT_DBU50 0x07
493#define I2O_PARAM_HBA_SCSI_PORT_HDBS68 0x08
494#define I2O_PARAM_HBA_SCSI_PORT_HDBU68 0x09
495#define I2O_PARAM_HBA_SCSI_PORT_SCA1 0x0a
496#define I2O_PARAM_HBA_SCSI_PORT_SCA2 0x0b
497#define I2O_PARAM_HBA_SCSI_PORT_FCDB9 0x0c
498#define I2O_PARAM_HBA_SCSI_PORT_FC 0x0d
499#define I2O_PARAM_HBA_SCSI_PORT_FCSCA40 0x0e
500#define I2O_PARAM_HBA_SCSI_PORT_FCSCA20 0x0f
501#define I2O_PARAM_HBA_SCSI_PORT_FCBNC 0x10
502
503#define I2O_PARAM_HBA_SCSI_PORT_FEMALE 0x03
504#define I2O_PARAM_HBA_SCSI_PORT_MALE 0x04
505
506#define I2O_PARAM_HBA_SCSI_CTLR_INFO 0x0200
507struct i2o_param_hba_scsi_ctlr_info {
508 u_int8_t scsitype;
509 u_int8_t protection;
510 u_int8_t settings;
511 u_int8_t reserved;
512 u_int32_t initiatorid;
513 u_int64_t scanlun0only;
514 u_int16_t disabledevice;
515 u_int8_t maxoffset;
516 u_int8_t maxdatawidth;
517 u_int64_t maxsyncrate;
518} __packed;
519
520/*
521 * ================= Utility messages =================
522 */
523
524#define I2O_UTIL_ABORT 0x01
525struct i2o_util_abort {
526 u_int32_t msgflags;
527 u_int32_t msgfunc;
528 u_int32_t msgictx;
529 u_int32_t msgtctx;
530 u_int32_t flags; /* abort type and function type */
531 u_int32_t tctxabort;
532} __packed;
533
534#define I2O_UTIL_ABORT_EXACT 0x00000000
535#define I2O_UTIL_ABORT_FUNCTION 0x00010000
536#define I2O_UTIL_ABORT_TRANSACTION 0x00020000
537#define I2O_UTIL_ABORT_WILD 0x00030000
538
539#define I2O_UTIL_ABORT_CLEAN 0x00040000
540
541struct i2o_util_abort_reply {
542 u_int32_t msgflags;
543 u_int32_t msgfunc;
544 u_int32_t msgictx;
545 u_int32_t msgtctx;
546 u_int32_t count;
547} __packed;
548
549#define I2O_UTIL_PARAMS_SET 0x05
550#define I2O_UTIL_PARAMS_GET 0x06
551struct i2o_util_params_op {
552 u_int32_t msgflags;
553 u_int32_t msgfunc;
554 u_int32_t msgictx;
555 u_int32_t msgtctx;
556 u_int32_t flags;
557} __packed;
558
559#define I2O_PARAMS_OP_FIELD_GET 1
560#define I2O_PARAMS_OP_LIST_GET 2
561#define I2O_PARAMS_OP_MORE_GET 3
562#define I2O_PARAMS_OP_SIZE_GET 4
563#define I2O_PARAMS_OP_TABLE_GET 5
564#define I2O_PARAMS_OP_FIELD_SET 6
565#define I2O_PARAMS_OP_LIST_SET 7
566#define I2O_PARAMS_OP_ROW_ADD 8
567#define I2O_PARAMS_OP_ROW_DELETE 9
568#define I2O_PARAMS_OP_TABLE_CLEAR 10
569
570struct i2o_param_op_list_header {
571 u_int16_t count;
572 u_int16_t reserved;
573} __packed;
574
575struct i2o_param_op_all_template {
576 u_int16_t operation;
577 u_int16_t group;
578 u_int16_t fieldcount;
579 u_int16_t fields[1];
580} __packed;
581
582struct i2o_param_op_results {
583 u_int16_t count;
584 u_int16_t reserved;
585} __packed;
586
587struct i2o_param_read_results {
588 u_int16_t blocksize;
589 u_int8_t blockstatus;
590 u_int8_t errorinfosize;
591} __packed;
592
593struct i2o_param_table_results {
594 u_int16_t blocksize;
595 u_int8_t blockstatus;
596 u_int8_t errorinfosize;
597 u_int16_t rowcount;
598 u_int16_t moreflag;
599} __packed;
600
601#define I2O_UTIL_CLAIM 0x09
602struct i2o_util_claim {
603 u_int32_t msgflags;
604 u_int32_t msgfunc;
605 u_int32_t msgictx;
606 u_int32_t msgtctx;
607 u_int32_t flags;
608} __packed;
609
610#define I2O_UTIL_CLAIM_RESET_SENSITIVE 0x00000002
611#define I2O_UTIL_CLAIM_STATE_SENSITIVE 0x00000004
612#define I2O_UTIL_CLAIM_CAPACITY_SENSITIVE 0x00000008
613#define I2O_UTIL_CLAIM_NO_PEER_SERVICE 0x00000010
614#define I2O_UTIL_CLAIM_NO_MANAGEMENT_SERVICE 0x00000020
615
616#define I2O_UTIL_CLAIM_PRIMARY_USER 0x01000000
617#define I2O_UTIL_CLAIM_AUTHORIZED_USER 0x02000000
618#define I2O_UTIL_CLAIM_SECONDARY_USER 0x03000000
619#define I2O_UTIL_CLAIM_MANAGEMENT_USER 0x04000000
620
621#define I2O_UTIL_CLAIM_RELEASE 0x0b
622struct i2o_util_claim_release {
623 u_int32_t msgflags;
624 u_int32_t msgfunc;
625 u_int32_t msgictx;
626 u_int32_t msgtctx;
627 u_int32_t flags; /* User flags as per I2O_UTIL_CLAIM */
628} __packed;
629
630#define I2O_UTIL_CLAIM_RELEASE_CONDITIONAL 0x00000001
631
632#define I2O_UTIL_CONFIG_DIALOG 0x10
633struct i2o_util_config_dialog {
634 u_int32_t msgflags;
635 u_int32_t msgfunc;
636 u_int32_t msgictx;
637 u_int32_t msgtctx;
638 u_int32_t pageno;
639} __packed;
640
641#define I2O_UTIL_EVENT_REGISTER 0x13
642struct i2o_util_event_register {
643 u_int32_t msgflags;
644 u_int32_t msgfunc;
645 u_int32_t msgictx;
646 u_int32_t msgtctx;
647 u_int32_t eventmask;
648} __packed;
649
650struct i2o_util_event_register_reply {
651 u_int32_t msgflags;
652 u_int32_t msgfunc;
653 u_int32_t msgictx;
654 u_int32_t msgtctx;
655 u_int32_t event;
656 u_int32_t eventdata[1];
657} __packed;
658
659/* Generic events. */
660#define I2O_EVENT_GEN_DEVICE_STATE 0x00400000
661#define I2O_EVENT_GEN_VENDOR_EVENT 0x00800000
662#define I2O_EVENT_GEN_FIELD_MODIFIED 0x01000000
663#define I2O_EVENT_GEN_EVENT_MASK_MODIFIED 0x02000000
664#define I2O_EVENT_GEN_DEVICE_RESET 0x04000000
665#define I2O_EVENT_GEN_CAPABILITY_CHANGE 0x08000000
666#define I2O_EVENT_GEN_LOCK_RELEASE 0x10000000
667#define I2O_EVENT_GEN_NEED_CONFIGURATION 0x20000000
668#define I2O_EVENT_GEN_GENERAL_WARNING 0x40000000
669#define I2O_EVENT_GEN_STATE_CHANGE 0x80000000
670
671/* Executive class events. */
672#define I2O_EVENT_EXEC_RESOURCE_LIMITS 0x00000001
673#define I2O_EVENT_EXEC_CONNECTION_FAIL 0x00000002
674#define I2O_EVENT_EXEC_ADAPTER_FAULT 0x00000004
675#define I2O_EVENT_EXEC_POWER_FAIL 0x00000008
676#define I2O_EVENT_EXEC_RESET_PENDING 0x00000010
677#define I2O_EVENT_EXEC_RESET_IMMINENT 0x00000020
678#define I2O_EVENT_EXEC_HARDWARE_FAIL 0x00000040
679#define I2O_EVENT_EXEC_XCT_CHANGE 0x00000080
680#define I2O_EVENT_EXEC_NEW_LCT_ENTRY 0x00000100
681#define I2O_EVENT_EXEC_MODIFIED_LCT 0x00000200
682#define I2O_EVENT_EXEC_DDM_AVAILIBILITY 0x00000400
683
684/* LAN class events. */
685#define I2O_EVENT_LAN_LINK_DOWN 0x00000001
686#define I2O_EVENT_LAN_LINK_UP 0x00000002
687#define I2O_EVENT_LAN_MEDIA_CHANGE 0x00000004
688
689/*
690 * ================= Utility parameter groups =================
691 */
692
693#define I2O_PARAM_DEVICE_IDENTITY 0xf100
694struct i2o_param_device_identity {
695 u_int32_t classid;
696 u_int16_t ownertid;
697 u_int16_t parenttid;
698 u_int8_t vendorinfo[16];
699 u_int8_t productinfo[16];
700 u_int8_t description[16];
701 u_int8_t revlevel[8];
702 u_int8_t snformat;
703 u_int8_t serialnumber[1];
704} __packed;
705
706#define I2O_PARAM_DDM_IDENTITY 0xf101
707struct i2o_param_ddm_identity {
708 u_int16_t ddmtid;
709 u_int8_t name[24];
710 u_int8_t revlevel[8];
711 u_int8_t snformat;
712 u_int8_t serialnumber[12];
713} __packed;
714
715/*
716 * ================= Block storage class messages =================
717 */
718
719#define I2O_RBS_BLOCK_READ 0x30
720struct i2o_rbs_block_read {
721 u_int32_t msgflags;
722 u_int32_t msgfunc;
723 u_int32_t msgictx;
724 u_int32_t msgtctx;
725 u_int32_t flags; /* flags, time multiplier, read ahead */
726 u_int32_t datasize;
727 u_int32_t lowoffset;
728 u_int32_t highoffset;
729} __packed;
730
731#define I2O_RBS_BLOCK_READ_NO_RETRY 0x01
732#define I2O_RBS_BLOCK_READ_SOLO 0x02
733#define I2O_RBS_BLOCK_READ_CACHE_READ 0x04
734#define I2O_RBS_BLOCK_READ_PREFETCH 0x08
735#define I2O_RBS_BLOCK_READ_CACHE_ONLY 0x10
736
737#define I2O_RBS_BLOCK_WRITE 0x31
738struct i2o_rbs_block_write {
739 u_int32_t msgflags;
740 u_int32_t msgfunc;
741 u_int32_t msgictx;
742 u_int32_t msgtctx;
743 u_int32_t flags; /* flags, time multiplier */
744 u_int32_t datasize;
745 u_int32_t lowoffset;
746 u_int32_t highoffset;
747} __packed;
748
749#define I2O_RBS_BLOCK_WRITE_NO_RETRY 0x01
750#define I2O_RBS_BLOCK_WRITE_SOLO 0x02
751#define I2O_RBS_BLOCK_WRITE_CACHE_NONE 0x04
752#define I2O_RBS_BLOCK_WRITE_CACHE_WT 0x08
753#define I2O_RBS_BLOCK_WRITE_CACHE_WB 0x10
754
755#define I2O_RBS_CACHE_FLUSH 0x37
756struct i2o_rbs_cache_flush {
757 u_int32_t msgflags;
758 u_int32_t msgfunc;
759 u_int32_t msgictx;
760 u_int32_t msgtctx;
761 u_int32_t flags; /* flags, time multiplier */
762} __packed;
763
764#define I2O_RBS_MEDIA_MOUNT 0x41
765struct i2o_rbs_media_mount {
766 u_int32_t msgflags;
767 u_int32_t msgfunc;
768 u_int32_t msgictx;
769 u_int32_t msgtctx;
770 u_int32_t mediaid;
771 u_int32_t loadflags;
772} __packed;
773
774#define I2O_RBS_MEDIA_EJECT 0x43
775struct i2o_rbs_media_eject {
776 u_int32_t msgflags;
777 u_int32_t msgfunc;
778 u_int32_t msgictx;
779 u_int32_t msgtctx;
780 u_int32_t mediaid;
781} __packed;
782
783#define I2O_RBS_MEDIA_LOCK 0x49
784struct i2o_rbs_media_lock {
785 u_int32_t msgflags;
786 u_int32_t msgfunc;
787 u_int32_t msgictx;
788 u_int32_t msgtctx;
789 u_int32_t mediaid;
790} __packed;
791
792#define I2O_RBS_MEDIA_UNLOCK 0x4b
793struct i2o_rbs_media_unlock {
794 u_int32_t msgflags;
795 u_int32_t msgfunc;
796 u_int32_t msgictx;
797 u_int32_t msgtctx;
798 u_int32_t mediaid;
799} __packed;
800
801/* Standard RBS reply frame. */
802struct i2o_rbs_reply {
803 u_int32_t msgflags;
804 u_int32_t msgfunc;
805 u_int32_t msgictx;
806 u_int32_t msgtctx;
807 u_int16_t detail;
808 u_int8_t retrycount;
809 u_int8_t reqstatus;
810 u_int32_t transfercount;
811 u_int64_t offset; /* Error replies only */
812} __packed;
813
814/*
815 * ================= Block storage class parameter groups =================
816 */
817
818#define I2O_PARAM_RBS_DEVICE_INFO 0x0000
819struct i2o_param_rbs_device_info {
820 u_int8_t type;
821 u_int8_t npaths;
822 u_int16_t powerstate;
823 u_int32_t blocksize;
824 u_int64_t capacity;
825 u_int32_t capabilities;
826 u_int32_t state;
827} __packed;
828
829#define I2O_RBS_TYPE_DIRECT 0x00
830#define I2O_RBS_TYPE_WORM 0x04
831#define I2O_RBS_TYPE_CDROM 0x05
832#define I2O_RBS_TYPE_OPTICAL 0x07
833
834#define I2O_RBS_CAP_CACHING 0x00000001
835#define I2O_RBS_CAP_MULTI_PATH 0x00000002
836#define I2O_RBS_CAP_DYNAMIC_CAPACITY 0x00000004
837#define I2O_RBS_CAP_REMOVABLE_MEDIA 0x00000008
838#define I2O_RBS_CAP_REMOVABLE_DEVICE 0x00000010
839#define I2O_RBS_CAP_READ_ONLY 0x00000020
840#define I2O_RBS_CAP_LOCKOUT 0x00000040
841#define I2O_RBS_CAP_BOOT_BYPASS 0x00000080
842#define I2O_RBS_CAP_COMPRESSION 0x00000100
843#define I2O_RBS_CAP_DATA_SECURITY 0x00000200
844#define I2O_RBS_CAP_RAID 0x00000400
845
846#define I2O_RBS_STATE_CACHING 0x00000001
847#define I2O_RBS_STATE_POWERED_ON 0x00000002
848#define I2O_RBS_STATE_READY 0x00000004
849#define I2O_RBS_STATE_MEDIA_LOADED 0x00000008
850#define I2O_RBS_STATE_DEVICE_LOADED 0x00000010
851#define I2O_RBS_STATE_READ_ONLY 0x00000020
852#define I2O_RBS_STATE_LOCKOUT 0x00000040
853#define I2O_RBS_STATE_BOOT_BYPASS 0x00000080
854#define I2O_RBS_STATE_COMPRESSION 0x00000100
855#define I2O_RBS_STATE_DATA_SECURITY 0x00000200
856#define I2O_RBS_STATE_RAID 0x00000400
857
858#define I2O_PARAM_RBS_OPERATION 0x0001
859struct i2o_param_rbs_operation {
860 u_int8_t autoreass;
861 u_int8_t reasstolerance;
862 u_int8_t numretries;
863 u_int8_t reserved0;
864 u_int32_t reasssize;
865 u_int32_t expectedtimeout;
866 u_int32_t rwvtimeout;
867 u_int32_t rwvtimeoutbase;
868 u_int32_t timeoutbase;
869 u_int32_t orderedreqdepth;
870 u_int32_t atomicwritesize;
871} __packed;
872
873#define I2O_PARAM_RBS_OPERATION_autoreass 0
874#define I2O_PARAM_RBS_OPERATION_reasstolerance 1
875#define I2O_PARAM_RBS_OPERATION_numretries 2
876#define I2O_PARAM_RBS_OPERATION_reserved0 3
877#define I2O_PARAM_RBS_OPERATION_reasssize 4
878#define I2O_PARAM_RBS_OPERATION_expectedtimeout 5
879#define I2O_PARAM_RBS_OPERATION_rwvtimeout 6
880#define I2O_PARAM_RBS_OPERATION_rwvtimeoutbase 7
881#define I2O_PARAM_RBS_OPERATION_timeoutbase 8
882#define I2O_PARAM_RBS_OPERATION_orderedreqdepth 9
883#define I2O_PARAM_RBS_OPERATION_atomicwritesize 10
884
885#define I2O_PARAM_RBS_CACHE_CONTROL 0x0003
886struct i2o_param_rbs_cache_control {
887 u_int32_t totalcachesize;
888 u_int32_t readcachesize;
889 u_int32_t writecachesize;
890 u_int8_t writepolicy;
891 u_int8_t readpolicy;
892 u_int8_t errorcorrection;
893 u_int8_t reserved;
894} __packed;
895
896/*
897 * ================= SCSI peripheral class messages =================
898 */
899
900#define I2O_SCSI_DEVICE_RESET 0x27
901struct i2o_scsi_device_reset {
902 u_int32_t msgflags;
903 u_int32_t msgfunc;
904 u_int32_t msgictx;
905 u_int32_t msgtctx;
906} __packed;
907
908#define I2O_SCSI_SCB_EXEC 0x81
909struct i2o_scsi_scb_exec {
910 u_int32_t msgflags;
911 u_int32_t msgfunc;
912 u_int32_t msgictx;
913 u_int32_t msgtctx;
914 u_int32_t flags; /* CDB length and flags */
915 u_int8_t cdb[16];
916 u_int32_t datalen;
917} __packed;
918
919#define I2O_SCB_FLAG_SENSE_DATA_IN_MESSAGE 0x00200000
920#define I2O_SCB_FLAG_SENSE_DATA_IN_BUFFER 0x00600000
921#define I2O_SCB_FLAG_SIMPLE_QUEUE_TAG 0x00800000
922#define I2O_SCB_FLAG_HEAD_QUEUE_TAG 0x01000000
923#define I2O_SCB_FLAG_ORDERED_QUEUE_TAG 0x01800000
924#define I2O_SCB_FLAG_ACA_QUEUE_TAG 0x02000000
925#define I2O_SCB_FLAG_ENABLE_DISCONNECT 0x20000000
926#define I2O_SCB_FLAG_XFER_FROM_DEVICE 0x40000000
927#define I2O_SCB_FLAG_XFER_TO_DEVICE 0x80000000
928
929#define I2O_SCSI_SCB_ABORT 0x83
930struct i2o_scsi_scb_abort {
931 u_int32_t msgflags;
932 u_int32_t msgfunc;
933 u_int32_t msgictx;
934 u_int32_t msgtctx;
935 u_int32_t tctxabort;
936} __packed;
937
938struct i2o_scsi_reply {
939 u_int32_t msgflags;
940 u_int32_t msgfunc;
941 u_int32_t msgictx;
942 u_int32_t msgtctx;
943 u_int8_t scsistatus;
944 u_int8_t hbastatus;
945 u_int8_t reserved;
946 u_int8_t reqstatus;
947 u_int32_t datalen;
948 u_int32_t senselen;
949 u_int8_t sense[40];
950} __packed;
951
952#define I2O_SCSI_DSC_SUCCESS 0x00
953#define I2O_SCSI_DSC_REQUEST_ABORTED 0x02
954#define I2O_SCSI_DSC_UNABLE_TO_ABORT 0x03
955#define I2O_SCSI_DSC_COMPLETE_WITH_ERROR 0x04
956#define I2O_SCSI_DSC_ADAPTER_BUSY 0x05
957#define I2O_SCSI_DSC_REQUEST_INVALID 0x06
958#define I2O_SCSI_DSC_PATH_INVALID 0x07
959#define I2O_SCSI_DSC_DEVICE_NOT_PRESENT 0x08
960#define I2O_SCSI_DSC_UNABLE_TO_TERMINATE 0x09
961#define I2O_SCSI_DSC_SELECTION_TIMEOUT 0x0a
962#define I2O_SCSI_DSC_COMMAND_TIMEOUT 0x0b
963#define I2O_SCSI_DSC_MR_MESSAGE_RECEIVED 0x0d
964#define I2O_SCSI_DSC_SCSI_BUS_RESET 0x0e
965#define I2O_SCSI_DSC_PARITY_ERROR_FAILURE 0x0f
966#define I2O_SCSI_DSC_AUTOSENSE_FAILED 0x10
967#define I2O_SCSI_DSC_NO_ADAPTER 0x11
968#define I2O_SCSI_DSC_DATA_OVERRUN 0x12
969#define I2O_SCSI_DSC_UNEXPECTED_BUS_FREE 0x13
970#define I2O_SCSI_DSC_SEQUENCE_FAILURE 0x14
971#define I2O_SCSI_DSC_REQUEST_LENGTH_ERROR 0x15
972#define I2O_SCSI_DSC_PROVIDE_FAILURE 0x16
973#define I2O_SCSI_DSC_BDR_MESSAGE_SENT 0x17
974#define I2O_SCSI_DSC_REQUEST_TERMINATED 0x18
975#define I2O_SCSI_DSC_IDE_MESSAGE_SENT 0x33
976#define I2O_SCSI_DSC_RESOURCE_UNAVAILABLE 0x34
977#define I2O_SCSI_DSC_UNACKNOWLEDGED_EVENT 0x35
978#define I2O_SCSI_DSC_MESSAGE_RECEIVED 0x36
979#define I2O_SCSI_DSC_INVALID_CDB 0x37
980#define I2O_SCSI_DSC_LUN_INVALID 0x38
981#define I2O_SCSI_DSC_SCSI_TID_INVALID 0x39
982#define I2O_SCSI_DSC_FUNCTION_UNAVAILABLE 0x3a
983#define I2O_SCSI_DSC_NO_NEXUS 0x3b
984#define I2O_SCSI_DSC_SCSI_IID_INVALID 0x3c
985#define I2O_SCSI_DSC_CDB_RECEIVED 0x3d
986#define I2O_SCSI_DSC_LUN_ALREADY_ENABLED 0x3e
987#define I2O_SCSI_DSC_BUS_BUSY 0x3f
988#define I2O_SCSI_DSC_QUEUE_FROZEN 0x40
989
990/*
991 * ================= SCSI peripheral class parameter groups =================
992 */
993
994#define I2O_PARAM_SCSI_DEVICE_INFO 0x0000
995struct i2o_param_scsi_device_info {
996 u_int8_t devicetype;
997 u_int8_t flags;
998 u_int16_t reserved0;
999 u_int32_t identifier;
1000 u_int8_t luninfo[8];
1001 u_int32_t queuedepth;
1002 u_int8_t reserved1;
1003 u_int8_t negoffset;
1004 u_int8_t negdatawidth;
1005 u_int8_t reserved2;
1006 u_int64_t negsyncrate;
1007} __packed;
1008
1009/*
1010 * ================= LAN class messages =================
1011 */
1012
1013#define I2O_LAN_PACKET_SEND 0x3b
1014struct i2o_lan_packet_send {
1015 u_int32_t msgflags;
1016 u_int32_t msgfunc;
1017 u_int32_t msgictx;
1018 u_int32_t tcw;
1019
1020 /* SGL follows */
1021} __packed;
1022
1023#define I2O_LAN_TCW_ACCESS_PRI_MASK 0x00000007
1024#define I2O_LAN_TCW_SUPPRESS_CRC 0x00000008
1025#define I2O_LAN_TCW_SUPPRESS_LOOPBACK 0x00000010
1026#define I2O_LAN_TCW_CKSUM_NETWORK 0x00000020
1027#define I2O_LAN_TCW_CKSUM_TRANSPORT 0x00000040
1028#define I2O_LAN_TCW_REPLY_BATCH 0x00000000
1029#define I2O_LAN_TCW_REPLY_IMMEDIATELY 0x40000000
1030#define I2O_LAN_TCW_REPLY_UNSUCCESSFUL 0x80000000
1031#define I2O_LAN_TCW_REPLY_NONE 0xc0000000
1032
1033#define I2O_LAN_SDU_SEND 0x3d
1034struct i2o_lan_sdu_send {
1035 u_int32_t msgflags;
1036 u_int32_t msgfunc;
1037 u_int32_t msgictx;
1038 u_int32_t tcw; /* As per PACKET_SEND. */
1039
1040 /* SGL follows */
1041} __packed;
1042
1043struct i2o_lan_send_reply {
1044 u_int32_t msgflags;
1045 u_int32_t msgfunc;
1046 u_int32_t msgictx;
1047 u_int32_t trl;
1048 u_int16_t detail;
1049 u_int8_t reserved;
1050 u_int8_t reqstatus;
1051 u_int32_t tctx[1];
1052} __packed;
1053
1054#define I2O_LAN_RECEIVE_POST 0x3e
1055struct i2o_lan_receive_post {
1056 u_int32_t msgflags;
1057 u_int32_t msgfunc;
1058 u_int32_t msgictx;
1059 u_int32_t bktcnt;
1060
1061 /* SGL follows */
1062} __packed;
1063
1064struct i2o_lan_receive_reply {
1065 u_int32_t msgflags;
1066 u_int32_t msgfunc;
1067 u_int32_t msgictx;
1068 u_int8_t trlcount;
1069 u_int8_t trlesize;
1070 u_int8_t reserved;
1071 u_int8_t trlflags;
1072 u_int32_t bucketsleft;
1073} __packed;
1074
1075#define I2O_LAN_RECEIVE_REPLY_PDB 0x80
1076
1077#define I2O_LAN_PDB_ERROR_NONE 0x00
1078#define I2O_LAN_PDB_ERROR_BAD_CRC 0x01
1079#define I2O_LAN_PDB_ERROR_ALIGNMENT 0x02
1080#define I2O_LAN_PDB_ERROR_TOO_LONG 0x03
1081#define I2O_LAN_PDB_ERROR_TOO_SHORT 0x04
1082#define I2O_LAN_PDB_ERROR_RX_OVERRUN 0x05
1083#define I2O_LAN_PDB_ERROR_L3_CKSUM_BAD 0x40
1084#define I2O_LAN_PDB_ERROR_L4_CKSUM_BAD 0x80
1085#define I2O_LAN_PDB_ERROR_CKSUM_MASK 0xc0
1086#define I2O_LAN_PDB_ERROR_OTHER 0xff
1087
1088#define I2O_LAN_RESET 0x35
1089struct i2o_lan_reset {
1090 u_int32_t msgflags;
1091 u_int32_t msgfunc;
1092 u_int32_t msgictx;
1093 u_int16_t reserved;
1094 u_int16_t resrcflags;
1095} __packed;
1096
1097#define I2O_LAN_RESRC_RETURN_BUCKETS 0x0001
1098#define I2O_LAN_RESRC_RETURN_XMITS 0x0002
1099
1100#define I2O_LAN_SUSPEND 0x37
1101struct i2o_lan_suspend {
1102 u_int32_t msgflags;
1103 u_int32_t msgfunc;
1104 u_int32_t msgictx;
1105 u_int16_t reserved;
1106 u_int16_t resrcflags; /* As per RESET. */
1107} __packed;
1108
1109#define I2O_LAN_DSC_SUCCESS 0x00
1110#define I2O_LAN_DSC_DEVICE_FAILURE 0x01
1111#define I2O_LAN_DSC_DESTINATION_NOT_FOUND 0x02
1112#define I2O_LAN_DSC_TRANSMIT_ERROR 0x03
1113#define I2O_LAN_DSC_TRANSMIT_ABORTED 0x04
1114#define I2O_LAN_DSC_RECEIVE_ERROR 0x05
1115#define I2O_LAN_DSC_RECEIVE_ABORTED 0x06
1116#define I2O_LAN_DSC_DMA_ERROR 0x07
1117#define I2O_LAN_DSC_BAD_PACKET_DETECTED 0x08
1118#define I2O_LAN_DSC_OUT_OF_MEMORY 0x09
1119#define I2O_LAN_DSC_BUCKET_OVERRUN 0x0a
1120#define I2O_LAN_DSC_IOP_INTERNAL_ERROR 0x0b
1121#define I2O_LAN_DSC_CANCELED 0x0c
1122#define I2O_LAN_DSC_INVALID_TRANSACTION_CONTEXT 0x0d
1123#define I2O_LAN_DSC_DEST_ADDRESS_DETECTED 0x0e
1124#define I2O_LAN_DSC_DEST_ADDRESS_OMITTED 0x0f
1125#define I2O_LAN_DSC_PARTIAL_PACKET_RETURNED 0x10
1126#define I2O_LAN_DSC_TEMP_SUSPENDED_STATE 0x11
1127
1128/*
1129 * ================= LAN class parameter groups =================
1130 */
1131
1132#define I2O_PARAM_LAN_DEVICE_INFO 0x0000
1133struct i2o_param_lan_device_info {
1134 u_int16_t lantype;
1135 u_int16_t flags;
1136 u_int8_t addrfmt;
1137 u_int8_t reserved1;
1138 u_int16_t reserved2;
1139 u_int32_t minpktsize;
1140 u_int32_t maxpktsize;
1141 u_int8_t hwaddr[8];
1142 u_int64_t maxtxbps;
1143 u_int64_t maxrxbps;
1144} __packed;
1145
1146#define I2O_LAN_TYPE_ETHERNET 0x0030
1147#define I2O_LAN_TYPE_100BASEVG 0x0040
1148#define I2O_LAN_TYPE_TOKEN_RING 0x0050
1149#define I2O_LAN_TYPE_FDDI 0x0060
1150#define I2O_LAN_TYPE_FIBRECHANNEL 0x0070
1151
1152#define I2O_PARAM_LAN_MAC_ADDRESS 0x0001
1153struct i2o_param_lan_mac_address {
1154 u_int8_t activeaddr[8];
1155 u_int8_t localaddr[8];
1156 u_int8_t addrmask[8];
1157 u_int32_t filtermask;
1158 u_int32_t hwfiltercaps;
1159 u_int32_t maxmcastaddr;
1160 u_int32_t maxfilterperfect;
1161 u_int32_t maxfilterimperfect;
1162} __packed;
1163
1164#define I2O_PARAM_LAN_MAC_ADDRESS_activeaddr 0
1165#define I2O_PARAM_LAN_MAC_ADDRESS_localaddr 1
1166#define I2O_PARAM_LAN_MAC_ADDRESS_addrmask 2
1167#define I2O_PARAM_LAN_MAC_ADDRESS_filtermask 3
1168#define I2O_PARAM_LAN_MAC_ADDRESS_hwfiltercaps 4
1169#define I2O_PARAM_LAN_MAC_ADDRESS_maxmcastaddr 5
1170#define I2O_PARAM_LAN_MAC_ADDRESS_maxfilterperfect 6
1171#define I2O_PARAM_LAN_MAC_ADDRESS_maxfilterimperfect 7
1172
1173#define I2O_LAN_FILTERMASK_UNICAST_DISABLE 0x0001
1174#define I2O_LAN_FILTERMASK_PROMISC_ENABLE 0x0002
1175#define I2O_LAN_FILTERMASK_PROMISC_MCAST_ENABLE 0x0004
1176#define I2O_LAN_FILTERMASK_BROADCAST_DISABLE 0x0100
1177#define I2O_LAN_FILTERMASK_MCAST_DISABLE 0x0200
1178#define I2O_LAN_FILTERMASK_FUNCADDR_DISABLE 0x0400
1179#define I2O_LAN_FILTERMASK_MACMODE_0 0x0800
1180#define I2O_LAN_FILTERMASK_MACMODE_1 0x1000
1181
1182#define I2O_PARAM_LAN_MCAST_MAC_ADDRESS 0x0002
1183/*
1184 * This one's a table, not a scalar.
1185 */
1186
1187#define I2O_PARAM_LAN_BATCH_CONTROL 0x0003
1188struct i2o_param_lan_batch_control {
1189 u_int32_t batchflags;
1190 u_int32_t risingloaddly; /* 1.5 only */
1191 u_int32_t risingloadthresh; /* 1.5 only */
1192 u_int32_t fallingloaddly; /* 1.5 only */
1193 u_int32_t fallingloadthresh; /* 1.5 only */
1194 u_int32_t maxrxbatchcount;
1195 u_int32_t maxrxbatchdelay;
1196 u_int32_t maxtxbatchdelay; /* 2.0 (conflict with 1.5) */
1197 u_int32_t maxtxbatchcount; /* 2.0 only */
1198} __packed;
1199
1200#define I2O_PARAM_LAN_BATCH_CONTROL_batchflags 0
1201#define I2O_PARAM_LAN_BATCH_CONTROL_risingloaddly 1
1202#define I2O_PARAM_LAN_BATCH_CONTROL_risingloadthresh 2
1203#define I2O_PARAM_LAN_BATCH_CONTROL_fallingloaddly 3
1204#define I2O_PARAM_LAN_BATCH_CONTROL_fallingloadthresh 4
1205#define I2O_PARAM_LAN_BATCH_CONTROL_maxrxbatchcount 5
1206#define I2O_PARAM_LAN_BATCH_CONTROL_maxrxbatchdelay 6
1207#define I2O_PARAM_LAN_BATCH_CONTROL_maxtxbatchdelay 7
1208#define I2O_PARAM_LAN_BATCH_CONTROL_maxtxbatchcount 8
1209
1210#define I2O_PARAM_LAN_OPERATION 0x0004
1211struct i2o_param_lan_operation {
1212 u_int32_t pktprepad;
1213 u_int32_t userflags;
1214 u_int32_t pktorphanlimit;
1215 u_int32_t txmodesenable; /* 2.0 only */
1216 u_int32_t rxmodesenable; /* 2.0 only */
1217} __packed;
1218
1219#define I2O_PARAM_LAN_OPERATION_pktprepad 0
1220#define I2O_PARAM_LAN_OPERATION_userflags 1
1221#define I2O_PARAM_LAN_OPERATION_pktorphanlimit 2
1222#define I2O_PARAM_LAN_OPERATION_txmodesenable 3
1223#define I2O_PARAM_LAN_OPERATION_rxmodesenable 4
1224
1225#define I2O_PARAM_LAN_MEDIA_OPERATION 0x0005
1226struct i2o_param_lan_media_operation {
1227 u_int32_t connectortype;
1228 u_int32_t connectiontype;
1229 u_int32_t curtxbps;
1230 u_int32_t currxbps;
1231 u_int8_t fullduplex;
1232 u_int8_t linkstatus;
1233 u_int8_t badpkthandling; /* v1.5 only */
1234 u_int8_t duplextarget; /* v2.0 only */
1235 u_int32_t connectortarget; /* v2.0 only */
1236 u_int32_t connectiontarget; /* v2.0 only */
1237} __packed;
1238
1239#define I2O_PARAM_LAN_MEDIA_OPERATION_connectortype 0
1240#define I2O_PARAM_LAN_MEDIA_OPERATION_connectiontype 1
1241#define I2O_PARAM_LAN_MEDIA_OPERATION_curtxbps 2
1242#define I2O_PARAM_LAN_MEDIA_OPERATION_currxbps 3
1243#define I2O_PARAM_LAN_MEDIA_OPERATION_fullduplex 4
1244#define I2O_PARAM_LAN_MEDIA_OPERATION_linkstatus 5
1245#define I2O_PARAM_LAN_MEDIA_OPERATION_badpkthandling 6
1246#define I2O_PARAM_LAN_MEDIA_OPERATION_duplextarget 7
1247#define I2O_PARAM_LAN_MEDIA_OPERATION_connectortarget 8
1248#define I2O_PARAM_LAN_MEDIA_OPERATION_connectiontarget 9
1249
1250#define I2O_LAN_CONNECTOR_OTHER 0x00
1251#define I2O_LAN_CONNECTOR_UNKNOWN 0x01
1252#define I2O_LAN_CONNECTOR_AUI 0x02
1253#define I2O_LAN_CONNECTOR_UTP 0x03
1254#define I2O_LAN_CONNECTOR_BNC 0x04
1255#define I2O_LAN_CONNECTOR_RJ45 0x05
1256#define I2O_LAN_CONNECTOR_STP_DB9 0x06
1257#define I2O_LAN_CONNECTOR_FIBER_MIC 0x07
1258#define I2O_LAN_CONNECTOR_APPLE_AUI 0x08
1259#define I2O_LAN_CONNECTOR_MII 0x09
1260#define I2O_LAN_CONNECTOR_COPPER_DB9 0x0a
1261#define I2O_LAN_CONNECTOR_COPPER_AW 0x0b
1262#define I2O_LAN_CONNECTOR_OPTICAL_LW 0x0c
1263#define I2O_LAN_CONNECTOR_SIP 0x0d
1264#define I2O_LAN_CONNECTOR_OPTICAL_SW 0x0e
1265
1266#define I2O_LAN_CONNECTION_UNKNOWN 0x0000
1267
1268#define I2O_LAN_CONNECTION_ETHERNET_AUI 0x0301
1269#define I2O_LAN_CONNECTION_ETHERNET_10BASE5 0x0302
1270#define I2O_LAN_CONNECTION_ETHERNET_FOIRL 0x0303
1271#define I2O_LAN_CONNECTION_ETHERNET_10BASE2 0x0304
1272#define I2O_LAN_CONNECTION_ETHERNET_10BROAD36 0x0305
1273#define I2O_LAN_CONNECTION_ETHERNET_10BASET 0x0306
1274#define I2O_LAN_CONNECTION_ETHERNET_10BASEFP 0x0307
1275#define I2O_LAN_CONNECTION_ETHERNET_10BASEFB 0x0308
1276#define I2O_LAN_CONNECTION_ETHERNET_10BASEFL 0x0309
1277#define I2O_LAN_CONNECTION_ETHERNET_100BASETX 0x030a
1278#define I2O_LAN_CONNECTION_ETHERNET_100BASEFX 0x030b
1279#define I2O_LAN_CONNECTION_ETHERNET_100BASET4 0x030c
1280#define I2O_LAN_CONNECTION_ETHERNET_1000BASESX 0x030d
1281#define I2O_LAN_CONNECTION_ETHERNET_1000BASELX 0x030e
1282#define I2O_LAN_CONNECTION_ETHERNET_1000BASECX 0x030f
1283#define I2O_LAN_CONNECTION_ETHERNET_1000BASET 0x0310
1284
1285#define I2O_LAN_CONNECTION_100BASEVG_ETHERNET 0x0401
1286#define I2O_LAN_CONNECTION_100BASEVG_TOKEN_RING 0x0402
1287
1288#define I2O_LAN_CONNECTION_TOKEN_RING_4MBIT 0x0501
1289#define I2O_LAN_CONNECTION_TOKEN_RING_16MBIT 0x0502
1290
1291#define I2O_LAN_CONNECTION_FDDI_125MBIT 0x0601
1292
1293#define I2O_LAN_CONNECTION_FIBRECHANNEL_P2P 0x0701
1294#define I2O_LAN_CONNECTION_FIBRECHANNEL_AL 0x0702
1295#define I2O_LAN_CONNECTION_FIBRECHANNEL_PL 0x0703
1296#define I2O_LAN_CONNECTION_FIBRECHANNEL_F 0x0704
1297
1298#define I2O_LAN_CONNECTION_OTHER_EMULATED 0x0f00
1299#define I2O_LAN_CONNECTION_OTHER_OTHER 0x0f01
1300
1301#define I2O_LAN_CONNECTION_DEFAULT 0xffffffff
1302
1303#define I2O_PARAM_LAN_TRANSMIT_INFO 0x0007
1304struct i2o_param_lan_transmit_info {
1305 u_int32_t maxpktsg;
1306 u_int32_t maxchainsg;
1307 u_int32_t maxoutstanding;
1308 u_int32_t maxpktsout;
1309 u_int32_t maxpktsreq;
1310 u_int32_t txmodes;
1311} __packed;
1312
1313#define I2O_LAN_MODES_NO_DA_IN_SGL 0x0002
1314#define I2O_LAN_MODES_CRC_SUPPRESSION 0x0004
1315#define I2O_LAN_MODES_LOOPBACK_SUPPRESSION 0x0004 /* 1.5 only */
1316#define I2O_LAN_MODES_FCS_RECEPTION 0x0008 /* 2.0 only */
1317#define I2O_LAN_MODES_MAC_INSERTION 0x0010
1318#define I2O_LAN_MODES_RIF_INSERTION 0x0020
1319#define I2O_LAN_MODES_IPV4_CHECKSUM 0x0100 /* 2.0 only */
1320#define I2O_LAN_MODES_TCP_CHECKSUM 0x0200 /* 2.0 only */
1321#define I2O_LAN_MODES_UDP_CHECKSUM 0x0400 /* 2.0 only */
1322#define I2O_LAN_MODES_RSVP_CHECKSUM 0x0800 /* 2.0 only */
1323#define I2O_LAN_MODES_ICMP_CHECKSUM 0x1000 /* 2.0 only */
1324
1325#define I2O_PARAM_LAN_RECEIVE_INFO 0x0008
1326struct i2o_param_lan_receive_info {
1327 u_int32_t maxchain;
1328 u_int32_t maxbuckets;
1329} __packed;
1330
1331#define I2O_PARAM_LAN_STATS 0x0009
1332struct i2o_param_lan_stats {
1333 u_int64_t opackets;
1334 u_int64_t obytes;
1335 u_int64_t ipackets;
1336 u_int64_t oerrors;
1337 u_int64_t ierrors;
1338 u_int64_t rxnobuffer;
1339 u_int64_t resetcount;
1340} __packed;
1341
1342#define I2O_PARAM_LAN_802_3_STATS 0x0200
1343struct i2o_param_lan_802_3_stats {
1344 u_int64_t alignmenterror;
1345 u_int64_t onecollision;
1346 u_int64_t manycollisions;
1347 u_int64_t deferred;
1348 u_int64_t latecollision;
1349 u_int64_t maxcollisions;
1350 u_int64_t carrierlost;
1351 u_int64_t excessivedeferrals;
1352} __packed;
1353
1354#define I2O_PARAM_LAN_FDDI_STATS 0x0400
1355struct i2o_param_lan_fddi_stats {
1356 u_int64_t configstate;
1357 u_int64_t upstreamnode;
1358 u_int64_t downstreamnode;
1359 u_int64_t frameerrors;
1360 u_int64_t frameslost;
1361 u_int64_t ringmgmtstate;
1362 u_int64_t lctfailures;
1363 u_int64_t lemrejects;
1364 u_int64_t lemcount;
1365 u_int64_t lconnectionstate;
1366} __packed;
1367
1368#endif /* !defined _I2O_I2O_H_ */