1/*	$NetBSD: satareg.h,v 1.7 2022/02/16 22:00:55 andvar Exp $	*/
  2
  3/*-
  4 * Copyright (c) 2003 The NetBSD Foundation, Inc.
  5 * All rights reserved.
  6 *
  7 * This code is derived from software contributed to The NetBSD Foundation
  8 * by Jason R. Thorpe of Wasabi Systems, Inc.
  9 *
 10 * Redistribution and use in source and binary forms, with or without
 11 * modification, are permitted provided that the following conditions
 12 * are met:
 13 * 1. Redistributions of source code must retain the above copyright
 14 *    notice, this list of conditions and the following disclaimer.
 15 * 2. Redistributions in binary form must reproduce the above copyright
 16 *    notice, this list of conditions and the following disclaimer in the
 17 *    documentation and/or other materials provided with the distribution.
 18 *
 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 29 * POSSIBILITY OF SUCH DAMAGE.
 30 */
 31
 32#ifndef _DEV_ATA_SATAREG_H_
 33#define	_DEV_ATA_SATAREG_H_
 34
 35/*
 36 * Serial ATA register definitions.
 37 *
 38 * Reference:
 39 *
 40 *	Serial ATA: High Speed Serialized AT Attachment
 41 *	Revision 1.0 29-August-2001
 42 *	Serial ATA Working Group
 43 */
 44
 45/*
 46 * SStatus (SCR0) --
 47 *	Serial ATA interface status register
 48 */
 49	/*
 50	 * The DET value indicates the interface device detection and
 51	 * PHY state.
 52	 */
 53#define	SStatus_DET_NODEV	(0x0 << 0)	/* no device connected */
 54#define	SStatus_DET_DEV_NE	(0x1 << 0)	/* device, but PHY comm not
 55						   established */
 56#define	SStatus_DET_DEV		(0x3 << 0)	/* device, PHY comm
 57						   established */
 58#define	SStatus_DET_OFFLINE	(0x4 << 0)	/* PHY in offline mode */
 59#define	SStatus_DET_mask	(0xf << 0)
 60#define	SStatus_DET_shift	0
 61	/*
 62	 * The SPD value indicates the negotiated interface communication
 63	 * speed established.
 64	 */
 65#define	SStatus_SPD_NONE	(0x0 << 4)	/* no negotiated speed */
 66#define	SStatus_SPD_G1		(0x1 << 4)	/* Generation 1 (1.5Gb/s) */
 67#define	SStatus_SPD_G2		(0x2 << 4)	/* Generation 2 (3.0Gb/s) */
 68#define	SStatus_SPD_G3		(0x3 << 4)	/* Generation 3 (6.0Gb/s) */
 69#define	SStatus_SPD_mask	(0xf << 4)
 70#define	SStatus_SPD_shift	4
 71	/*
 72	 * The IPM value indicates the current interface power management
 73	 * state.
 74	 */
 75#define	SStatus_IPM_NODEV	(0x0 << 8)	/* no device connected */
 76#define	SStatus_IPM_ACTIVE	(0x1 << 8)	/* ACTIVE state */
 77#define	SStatus_IPM_PARTIAL	(0x2 << 8)	/* PARTIAL pm state */
 78#define	SStatus_IPM_SLUMBER	(0x6 << 8)	/* SLUMBER pm state */
 79#define	SStatus_IPM_DEVSLEEP	(0x8 << 8)	/* DevSleep pm state */
 80#define	SStatus_IPM_mask	(0xf << 8)
 81#define	SStatus_IPM_shift	8
 82
 83/*
 84 * SError (SCR1) --
 85 *	Serial ATA interface error register
 86 */
 87#define	SError_ERR_I		(1U << 0)	/* Recovered data integrity
 88						   error */
 89#define	SError_ERR_M		(1U << 1)	/* Recovered communications
 90						   error */
 91#define	SError_ERR_T		(1U << 8)	/* Non-recovered transient
 92						   data integrity error */
 93#define	SError_ERR_C		(1U << 9)	/* Non-recovered persistent
 94						   communication or data
 95						   integrity error */
 96#define	SError_ERR_P		(1U << 10)	/* Protocol error */
 97#define	SError_ERR_E		(1U << 11)	/* Internal error */
 98#define	SError_DIAG_N		(1U << 16)	/* PhyRdy change */
 99#define	SError_DIAG_I		(1U << 17)	/* PHY internal error */
100#define	SError_DIAG_W		(1U << 18)	/* Comm Wake */
101#define	SError_DIAG_B		(1U << 19)	/* 10b to 8b decode error */
102#define	SError_DIAG_D		(1U << 20)	/* Disparity error */
103#define	SError_DIAG_C		(1U << 21)	/* CRC error */
104#define	SError_DIAG_H		(1U << 22)	/* Handshake error */
105#define	SError_DIAG_S		(1U << 23)	/* Link sequence error */
106#define	SError_DIAG_T		(1U << 24)	/* Transport state transition
107						   error */
108#define	SError_DIAG_F		(1U << 25)	/* Unrecognized FIS type */
109#define	SError_DIAG_X		(1U << 26)	/* Device Exchanged */
110
111/*
112 * SControl (SCR2) --
113 *	Serial ATA interface control register
114 */
115	/*
116	 * The DET field controls the host adapter device detection
117	 * and interface initialization.
118	 */
119#define	SControl_DET_NONE	(0x0 << 0)	/* No device detection or
120						   initialization action
121						   requested */
122#define	SControl_DET_INIT	(0x1 << 0)	/* Initialize interface
123						   communication (equiv
124						   of a hard reset) */
125#define	SControl_DET_DISABLE	(0x4 << 0)	/* disable interface and
126						   take PHY offline */
127	/*
128	 * The SPD field represents the highest allowed communication
129	 * speed the interface is allowed to negotiate when communication
130	 * is established.
131	 */
132#define	SControl_SPD_ANY	(0x0 << 4)	/* No restrictions */
133#define	SControl_SPD_G1		(0x1 << 4)	/* Generation 1 (1.5Gb/s) */
134#define	SControl_SPD_G2		(0x2 << 4)	/* Generation 2 (3.0Gb/s) */
135#define	SControl_SPD_G3		(0x3 << 4)	/* Generation 3 (6.0Gb/s) */
136	/*
137	 * The IPM field represents the enabled interface power management
138	 * states that can be invoked via the Serial ATA interface power
139	 * management capabilities.
140	 */
141#define	SControl_IPM_ANY	(0x0 << 8)	/* No restrictions */
142#define	SControl_IPM_NOPARTIAL	(0x1 << 8)	/* PARTIAL disabled */
143#define	SControl_IPM_NOSLUMBER	(0x2 << 8)	/* SLUMBER disabled */
144#define	SControl_IPM_NODEVSLEEP	(0x4 << 8)	/* DevSleep disabled */
145#define	SControl_IPM_NONE	(0x7 << 8)	/* No power management */
146	/*
147	 * The SPM field selects a power management state.  A non-zero
148	 * value written to this field causes initiation of the selected
149	 * power management state.
150	 */
151#define	SControl_SPM_PARTIAL	(0x1 << 12)	/* transition to PARTIAL */
152#define	SControl_SPM_SLUMBER	(0x2 << 12)	/* transition to SLUBMER */
153#define	SControl_SPM_ComWake	(0x4 << 12)	/* transition from PM */
154	/*
155	 * The PMP field identifies the selected Port Multiplier Port
156	 * for accessing the SActive register.
157	 */
158#define	SControl_PMP(x)		((x) << 16)
159
160#endif /* _DEV_ATA_SATAREG_H_ */